LLVM  10.0.0svn
R600OptimizeVectorRegisters.cpp
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1 //===- R600MergeVectorRegisters.cpp ---------------------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// This pass merges inputs of swizzeable instructions into vector sharing
11 /// common data and/or have enough undef subreg using swizzle abilities.
12 ///
13 /// For instance let's consider the following pseudo code :
14 /// %5 = REG_SEQ %1, sub0, %2, sub1, %3, sub2, undef, sub3
15 /// ...
16 /// %7 = REG_SEQ %1, sub0, %3, sub1, undef, sub2, %4, sub3
17 /// (swizzable Inst) %7, SwizzleMask : sub0, sub1, sub2, sub3
18 ///
19 /// is turned into :
20 /// %5 = REG_SEQ %1, sub0, %2, sub1, %3, sub2, undef, sub3
21 /// ...
22 /// %7 = INSERT_SUBREG %4, sub3
23 /// (swizzable Inst) %7, SwizzleMask : sub0, sub2, sub1, sub3
24 ///
25 /// This allow regalloc to reduce register pressure for vector registers and
26 /// to reduce MOV count.
27 //===----------------------------------------------------------------------===//
28 
29 #include "AMDGPU.h"
30 #include "AMDGPUSubtarget.h"
31 #include "R600Defines.h"
32 #include "R600InstrInfo.h"
34 #include "llvm/ADT/DenseMap.h"
35 #include "llvm/ADT/STLExtras.h"
36 #include "llvm/ADT/StringRef.h"
46 #include "llvm/IR/DebugLoc.h"
47 #include "llvm/Pass.h"
48 #include "llvm/Support/Debug.h"
51 #include <cassert>
52 #include <utility>
53 #include <vector>
54 
55 using namespace llvm;
56 
57 #define DEBUG_TYPE "vec-merger"
58 
59 static bool isImplicitlyDef(MachineRegisterInfo &MRI, unsigned Reg) {
60  assert(MRI.isSSA());
62  return false;
63  const MachineInstr *MI = MRI.getUniqueVRegDef(Reg);
64  return MI && MI->isImplicitDef();
65 }
66 
67 namespace {
68 
69 class RegSeqInfo {
70 public:
71  MachineInstr *Instr;
73  std::vector<unsigned> UndefReg;
74 
75  RegSeqInfo(MachineRegisterInfo &MRI, MachineInstr *MI) : Instr(MI) {
76  assert(MI->getOpcode() == R600::REG_SEQUENCE);
77  for (unsigned i = 1, e = Instr->getNumOperands(); i < e; i+=2) {
78  MachineOperand &MO = Instr->getOperand(i);
79  unsigned Chan = Instr->getOperand(i + 1).getImm();
80  if (isImplicitlyDef(MRI, MO.getReg()))
81  UndefReg.push_back(Chan);
82  else
83  RegToChan[MO.getReg()] = Chan;
84  }
85  }
86 
87  RegSeqInfo() = default;
88 
89  bool operator==(const RegSeqInfo &RSI) const {
90  return RSI.Instr == Instr;
91  }
92 };
93 
94 class R600VectorRegMerger : public MachineFunctionPass {
95 private:
96  using InstructionSetMap = DenseMap<unsigned, std::vector<MachineInstr *>>;
97 
99  const R600InstrInfo *TII = nullptr;
101  InstructionSetMap PreviousRegSeqByReg;
102  InstructionSetMap PreviousRegSeqByUndefCount;
103 
104  bool canSwizzle(const MachineInstr &MI) const;
105  bool areAllUsesSwizzeable(unsigned Reg) const;
106  void SwizzleInput(MachineInstr &,
107  const std::vector<std::pair<unsigned, unsigned>> &RemapChan) const;
108  bool tryMergeVector(const RegSeqInfo *Untouched, RegSeqInfo *ToMerge,
109  std::vector<std::pair<unsigned, unsigned>> &Remap) const;
110  bool tryMergeUsingCommonSlot(RegSeqInfo &RSI, RegSeqInfo &CompatibleRSI,
111  std::vector<std::pair<unsigned, unsigned>> &RemapChan);
112  bool tryMergeUsingFreeSlot(RegSeqInfo &RSI, RegSeqInfo &CompatibleRSI,
113  std::vector<std::pair<unsigned, unsigned>> &RemapChan);
114  MachineInstr *RebuildVector(RegSeqInfo *MI, const RegSeqInfo *BaseVec,
115  const std::vector<std::pair<unsigned, unsigned>> &RemapChan) const;
116  void RemoveMI(MachineInstr *);
117  void trackRSI(const RegSeqInfo &RSI);
118 
119 public:
120  static char ID;
121 
122  R600VectorRegMerger() : MachineFunctionPass(ID) {}
123 
124  void getAnalysisUsage(AnalysisUsage &AU) const override {
125  AU.setPreservesCFG();
131  }
132 
133  StringRef getPassName() const override {
134  return "R600 Vector Registers Merge Pass";
135  }
136 
137  bool runOnMachineFunction(MachineFunction &Fn) override;
138 };
139 
140 } // end anonymous namespace
141 
142 INITIALIZE_PASS_BEGIN(R600VectorRegMerger, DEBUG_TYPE,
143  "R600 Vector Reg Merger", false, false)
144 INITIALIZE_PASS_END(R600VectorRegMerger, DEBUG_TYPE,
145  "R600 Vector Reg Merger", false, false)
146 
147 char R600VectorRegMerger::ID = 0;
148 
149 char &llvm::R600VectorRegMergerID = R600VectorRegMerger::ID;
150 
151 bool R600VectorRegMerger::canSwizzle(const MachineInstr &MI)
152  const {
153  if (TII->get(MI.getOpcode()).TSFlags & R600_InstFlag::TEX_INST)
154  return true;
155  switch (MI.getOpcode()) {
156  case R600::R600_ExportSwz:
157  case R600::EG_ExportSwz:
158  return true;
159  default:
160  return false;
161  }
162 }
163 
164 bool R600VectorRegMerger::tryMergeVector(const RegSeqInfo *Untouched,
165  RegSeqInfo *ToMerge, std::vector< std::pair<unsigned, unsigned>> &Remap)
166  const {
167  unsigned CurrentUndexIdx = 0;
168  for (DenseMap<unsigned, unsigned>::iterator It = ToMerge->RegToChan.begin(),
169  E = ToMerge->RegToChan.end(); It != E; ++It) {
171  Untouched->RegToChan.find((*It).first);
172  if (PosInUntouched != Untouched->RegToChan.end()) {
173  Remap.push_back(std::pair<unsigned, unsigned>
174  ((*It).second, (*PosInUntouched).second));
175  continue;
176  }
177  if (CurrentUndexIdx >= Untouched->UndefReg.size())
178  return false;
179  Remap.push_back(std::pair<unsigned, unsigned>
180  ((*It).second, Untouched->UndefReg[CurrentUndexIdx++]));
181  }
182 
183  return true;
184 }
185 
186 static
188  const std::vector<std::pair<unsigned, unsigned>> &RemapChan,
189  unsigned Chan) {
190  for (unsigned j = 0, je = RemapChan.size(); j < je; j++) {
191  if (RemapChan[j].first == Chan)
192  return RemapChan[j].second;
193  }
194  llvm_unreachable("Chan wasn't reassigned");
195 }
196 
197 MachineInstr *R600VectorRegMerger::RebuildVector(
198  RegSeqInfo *RSI, const RegSeqInfo *BaseRSI,
199  const std::vector<std::pair<unsigned, unsigned>> &RemapChan) const {
200  Register Reg = RSI->Instr->getOperand(0).getReg();
201  MachineBasicBlock::iterator Pos = RSI->Instr;
202  MachineBasicBlock &MBB = *Pos->getParent();
203  DebugLoc DL = Pos->getDebugLoc();
204 
205  Register SrcVec = BaseRSI->Instr->getOperand(0).getReg();
206  DenseMap<unsigned, unsigned> UpdatedRegToChan = BaseRSI->RegToChan;
207  std::vector<unsigned> UpdatedUndef = BaseRSI->UndefReg;
208  for (DenseMap<unsigned, unsigned>::iterator It = RSI->RegToChan.begin(),
209  E = RSI->RegToChan.end(); It != E; ++It) {
210  Register DstReg = MRI->createVirtualRegister(&R600::R600_Reg128RegClass);
211  unsigned SubReg = (*It).first;
212  unsigned Swizzle = (*It).second;
213  unsigned Chan = getReassignedChan(RemapChan, Swizzle);
214 
215  MachineInstr *Tmp = BuildMI(MBB, Pos, DL, TII->get(R600::INSERT_SUBREG),
216  DstReg)
217  .addReg(SrcVec)
218  .addReg(SubReg)
219  .addImm(Chan);
220  UpdatedRegToChan[SubReg] = Chan;
221  std::vector<unsigned>::iterator ChanPos = llvm::find(UpdatedUndef, Chan);
222  if (ChanPos != UpdatedUndef.end())
223  UpdatedUndef.erase(ChanPos);
224  assert(!is_contained(UpdatedUndef, Chan) &&
225  "UpdatedUndef shouldn't contain Chan more than once!");
226  LLVM_DEBUG(dbgs() << " ->"; Tmp->dump(););
227  (void)Tmp;
228  SrcVec = DstReg;
229  }
230  MachineInstr *NewMI =
231  BuildMI(MBB, Pos, DL, TII->get(R600::COPY), Reg).addReg(SrcVec);
232  LLVM_DEBUG(dbgs() << " ->"; NewMI->dump(););
233 
234  LLVM_DEBUG(dbgs() << " Updating Swizzle:\n");
235  for (MachineRegisterInfo::use_instr_iterator It = MRI->use_instr_begin(Reg),
236  E = MRI->use_instr_end(); It != E; ++It) {
237  LLVM_DEBUG(dbgs() << " "; (*It).dump(); dbgs() << " ->");
238  SwizzleInput(*It, RemapChan);
239  LLVM_DEBUG((*It).dump());
240  }
241  RSI->Instr->eraseFromParent();
242 
243  // Update RSI
244  RSI->Instr = NewMI;
245  RSI->RegToChan = UpdatedRegToChan;
246  RSI->UndefReg = UpdatedUndef;
247 
248  return NewMI;
249 }
250 
251 void R600VectorRegMerger::RemoveMI(MachineInstr *MI) {
252  for (InstructionSetMap::iterator It = PreviousRegSeqByReg.begin(),
253  E = PreviousRegSeqByReg.end(); It != E; ++It) {
254  std::vector<MachineInstr *> &MIs = (*It).second;
255  MIs.erase(llvm::find(MIs, MI), MIs.end());
256  }
257  for (InstructionSetMap::iterator It = PreviousRegSeqByUndefCount.begin(),
258  E = PreviousRegSeqByUndefCount.end(); It != E; ++It) {
259  std::vector<MachineInstr *> &MIs = (*It).second;
260  MIs.erase(llvm::find(MIs, MI), MIs.end());
261  }
262 }
263 
264 void R600VectorRegMerger::SwizzleInput(MachineInstr &MI,
265  const std::vector<std::pair<unsigned, unsigned>> &RemapChan) const {
266  unsigned Offset;
267  if (TII->get(MI.getOpcode()).TSFlags & R600_InstFlag::TEX_INST)
268  Offset = 2;
269  else
270  Offset = 3;
271  for (unsigned i = 0; i < 4; i++) {
272  unsigned Swizzle = MI.getOperand(i + Offset).getImm() + 1;
273  for (unsigned j = 0, e = RemapChan.size(); j < e; j++) {
274  if (RemapChan[j].first == Swizzle) {
275  MI.getOperand(i + Offset).setImm(RemapChan[j].second - 1);
276  break;
277  }
278  }
279  }
280 }
281 
282 bool R600VectorRegMerger::areAllUsesSwizzeable(unsigned Reg) const {
283  for (MachineRegisterInfo::use_instr_iterator It = MRI->use_instr_begin(Reg),
284  E = MRI->use_instr_end(); It != E; ++It) {
285  if (!canSwizzle(*It))
286  return false;
287  }
288  return true;
289 }
290 
291 bool R600VectorRegMerger::tryMergeUsingCommonSlot(RegSeqInfo &RSI,
292  RegSeqInfo &CompatibleRSI,
293  std::vector<std::pair<unsigned, unsigned>> &RemapChan) {
294  for (MachineInstr::mop_iterator MOp = RSI.Instr->operands_begin(),
295  MOE = RSI.Instr->operands_end(); MOp != MOE; ++MOp) {
296  if (!MOp->isReg())
297  continue;
298  if (PreviousRegSeqByReg[MOp->getReg()].empty())
299  continue;
300  for (MachineInstr *MI : PreviousRegSeqByReg[MOp->getReg()]) {
301  CompatibleRSI = PreviousRegSeq[MI];
302  if (RSI == CompatibleRSI)
303  continue;
304  if (tryMergeVector(&CompatibleRSI, &RSI, RemapChan))
305  return true;
306  }
307  }
308  return false;
309 }
310 
311 bool R600VectorRegMerger::tryMergeUsingFreeSlot(RegSeqInfo &RSI,
312  RegSeqInfo &CompatibleRSI,
313  std::vector<std::pair<unsigned, unsigned>> &RemapChan) {
314  unsigned NeededUndefs = 4 - RSI.UndefReg.size();
315  if (PreviousRegSeqByUndefCount[NeededUndefs].empty())
316  return false;
317  std::vector<MachineInstr *> &MIs =
318  PreviousRegSeqByUndefCount[NeededUndefs];
319  CompatibleRSI = PreviousRegSeq[MIs.back()];
320  tryMergeVector(&CompatibleRSI, &RSI, RemapChan);
321  return true;
322 }
323 
324 void R600VectorRegMerger::trackRSI(const RegSeqInfo &RSI) {
326  It = RSI.RegToChan.begin(), E = RSI.RegToChan.end(); It != E; ++It) {
327  PreviousRegSeqByReg[(*It).first].push_back(RSI.Instr);
328  }
329  PreviousRegSeqByUndefCount[RSI.UndefReg.size()].push_back(RSI.Instr);
330  PreviousRegSeq[RSI.Instr] = RSI;
331 }
332 
333 bool R600VectorRegMerger::runOnMachineFunction(MachineFunction &Fn) {
334  if (skipFunction(Fn.getFunction()))
335  return false;
336 
338  TII = ST.getInstrInfo();
339  MRI = &Fn.getRegInfo();
340 
341  for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
342  MBB != MBBe; ++MBB) {
343  MachineBasicBlock *MB = &*MBB;
344  PreviousRegSeq.clear();
345  PreviousRegSeqByReg.clear();
346  PreviousRegSeqByUndefCount.clear();
347 
348  for (MachineBasicBlock::iterator MII = MB->begin(), MIIE = MB->end();
349  MII != MIIE; ++MII) {
350  MachineInstr &MI = *MII;
351  if (MI.getOpcode() != R600::REG_SEQUENCE) {
352  if (TII->get(MI.getOpcode()).TSFlags & R600_InstFlag::TEX_INST) {
353  Register Reg = MI.getOperand(1).getReg();
355  It = MRI->def_instr_begin(Reg), E = MRI->def_instr_end();
356  It != E; ++It) {
357  RemoveMI(&(*It));
358  }
359  }
360  continue;
361  }
362 
363  RegSeqInfo RSI(*MRI, &MI);
364 
365  // All uses of MI are swizzeable ?
366  Register Reg = MI.getOperand(0).getReg();
367  if (!areAllUsesSwizzeable(Reg))
368  continue;
369 
370  LLVM_DEBUG({
371  dbgs() << "Trying to optimize ";
372  MI.dump();
373  });
374 
375  RegSeqInfo CandidateRSI;
376  std::vector<std::pair<unsigned, unsigned>> RemapChan;
377  LLVM_DEBUG(dbgs() << "Using common slots...\n";);
378  if (tryMergeUsingCommonSlot(RSI, CandidateRSI, RemapChan)) {
379  // Remove CandidateRSI mapping
380  RemoveMI(CandidateRSI.Instr);
381  MII = RebuildVector(&RSI, &CandidateRSI, RemapChan);
382  trackRSI(RSI);
383  continue;
384  }
385  LLVM_DEBUG(dbgs() << "Using free slots...\n";);
386  RemapChan.clear();
387  if (tryMergeUsingFreeSlot(RSI, CandidateRSI, RemapChan)) {
388  RemoveMI(CandidateRSI.Instr);
389  MII = RebuildVector(&RSI, &CandidateRSI, RemapChan);
390  trackRSI(RSI);
391  continue;
392  }
393  //Failed to merge
394  trackRSI(RSI);
395  }
396  }
397  return false;
398 }
399 
401  return new R600VectorRegMerger();
402 }
INITIALIZE_PASS_BEGIN(R600VectorRegMerger, DEBUG_TYPE, "R600 Vector Reg Merger", false, false) INITIALIZE_PASS_END(R600VectorRegMerger
static bool isImplicitlyDef(MachineRegisterInfo &MRI, unsigned Reg)
AnalysisUsage & addPreserved()
Add the specified Pass class to the set of analyses preserved by this pass.
AMDGPU specific subclass of TargetSubtarget.
This class represents lattice values for constants.
Definition: AllocatorList.h:23
Interface definition for R600InstrInfo.
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:63
unsigned Reg
static std::vector< std::pair< int, unsigned > > Swizzle(std::vector< std::pair< int, unsigned >> Src, R600InstrInfo::BankSwizzle Swz)
unsigned second
A debug info location.
Definition: DebugLoc.h:33
static const AMDGPUSubtarget & get(const MachineFunction &MF)
AnalysisUsage & addRequired()
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
const HexagonInstrInfo * TII
unsigned getNumOperands() const
Retuns the total number of operands.
Definition: MachineInstr.h:414
unsigned SubReg
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:411
defusechain_iterator - This class provides iterator support for machine operands in the function that...
FunctionPass * createR600VectorRegMerger()
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
unsigned const MachineRegisterInfo * MRI
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
Represent the analysis usage information of a pass.
R600 Vector Reg Merger
const R600InstrInfo * getInstrInfo() const override
void setImm(int64_t immVal)
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:284
static unsigned getReassignedChan(const std::vector< std::pair< unsigned, unsigned >> &RemapChan, unsigned Chan)
bool isImplicitDef() const
auto find(R &&Range, const T &Val) -> decltype(adl_begin(Range))
Provide wrappers to std::find which take ranges instead of having to pass begin/end explicitly...
Definition: STLExtras.h:1186
INITIALIZE_PASS_END(RegBankSelect, DEBUG_TYPE, "Assign register bank of generic virtual registers", false, false) RegBankSelect
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
unsigned first
constexpr bool empty(const T &RangeOrContainer)
Test whether RangeOrContainer is empty. Similar to C++17 std::empty.
Definition: STLExtras.h:197
Iterator for intrusive lists based on ilist_node.
MachineOperand class - Representation of each machine instruction operand.
void setPreservesCFG()
This function should be called by the pass, iff they do not:
Definition: Pass.cpp:301
int64_t getImm() const
MachineInstr * getUniqueVRegDef(unsigned Reg) const
getUniqueVRegDef - Return the unique machine instr that defines the specified virtual register or nul...
const Function & getFunction() const
Return the LLVM function that this machine code represents.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Provides AMDGPU specific target descriptions.
Representation of each machine instruction.
Definition: MachineInstr.h:64
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
aarch64 promote const
IRTranslator LLVM IR MI
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
bool operator==(uint64_t V1, const APInt &V2)
Definition: APInt.h:1973
Register getReg() const
getReg - Returns the register number.
#define LLVM_DEBUG(X)
Definition: Debug.h:122
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:416
#define DEBUG_TYPE
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
bool is_contained(R &&Range, const E &Element)
Wrapper function around std::find to detect if an element exists in a container.
Definition: STLExtras.h:1224