LLVM  10.0.0svn
RegisterBankInfo.cpp
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1 //===- llvm/CodeGen/GlobalISel/RegisterBankInfo.cpp --------------*- C++ -*-==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 /// This file implements the RegisterBankInfo class.
10 //===----------------------------------------------------------------------===//
11 
13 #include "llvm/ADT/SmallString.h"
14 #include "llvm/ADT/SmallVector.h"
15 #include "llvm/ADT/Statistic.h"
24 #include "llvm/Config/llvm-config.h"
25 #include "llvm/IR/Type.h"
26 #include "llvm/Support/Debug.h"
28 
29 #include <algorithm> // For std::max.
30 
31 #define DEBUG_TYPE "registerbankinfo"
32 
33 using namespace llvm;
34 
35 STATISTIC(NumPartialMappingsCreated,
36  "Number of partial mappings dynamically created");
37 STATISTIC(NumPartialMappingsAccessed,
38  "Number of partial mappings dynamically accessed");
39 STATISTIC(NumValueMappingsCreated,
40  "Number of value mappings dynamically created");
41 STATISTIC(NumValueMappingsAccessed,
42  "Number of value mappings dynamically accessed");
43 STATISTIC(NumOperandsMappingsCreated,
44  "Number of operands mappings dynamically created");
45 STATISTIC(NumOperandsMappingsAccessed,
46  "Number of operands mappings dynamically accessed");
47 STATISTIC(NumInstructionMappingsCreated,
48  "Number of instruction mappings dynamically created");
49 STATISTIC(NumInstructionMappingsAccessed,
50  "Number of instruction mappings dynamically accessed");
51 
52 const unsigned RegisterBankInfo::DefaultMappingID = UINT_MAX;
53 const unsigned RegisterBankInfo::InvalidMappingID = UINT_MAX - 1;
54 
55 //------------------------------------------------------------------------------
56 // RegisterBankInfo implementation.
57 //------------------------------------------------------------------------------
59  unsigned NumRegBanks)
60  : RegBanks(RegBanks), NumRegBanks(NumRegBanks) {
61 #ifndef NDEBUG
62  for (unsigned Idx = 0, End = getNumRegBanks(); Idx != End; ++Idx) {
63  assert(RegBanks[Idx] != nullptr && "Invalid RegisterBank");
64  assert(RegBanks[Idx]->isValid() && "RegisterBank should be valid");
65  }
66 #endif // NDEBUG
67 }
68 
70 #ifndef NDEBUG
71  for (unsigned Idx = 0, End = getNumRegBanks(); Idx != End; ++Idx) {
72  const RegisterBank &RegBank = getRegBank(Idx);
73  assert(Idx == RegBank.getID() &&
74  "ID does not match the index in the array");
75  LLVM_DEBUG(dbgs() << "Verify " << RegBank << '\n');
76  assert(RegBank.verify(TRI) && "RegBank is invalid");
77  }
78 #endif // NDEBUG
79  return true;
80 }
81 
82 const RegisterBank *
84  const TargetRegisterInfo &TRI) const {
87 
88  assert(Reg && "NoRegister does not have a register bank");
89  const RegClassOrRegBank &RegClassOrBank = MRI.getRegClassOrRegBank(Reg);
90  if (auto *RB = RegClassOrBank.dyn_cast<const RegisterBank *>())
91  return RB;
92  if (auto *RC = RegClassOrBank.dyn_cast<const TargetRegisterClass *>())
93  return &getRegBankFromRegClass(*RC);
94  return nullptr;
95 }
96 
97 const TargetRegisterClass &
99  const TargetRegisterInfo &TRI) const {
100  assert(Register::isPhysicalRegister(Reg) && "Reg must be a physreg");
101  const auto &RegRCIt = PhysRegMinimalRCs.find(Reg);
102  if (RegRCIt != PhysRegMinimalRCs.end())
103  return *RegRCIt->second;
104  const TargetRegisterClass *PhysRC = TRI.getMinimalPhysRegClass(Reg);
105  PhysRegMinimalRCs[Reg] = PhysRC;
106  return *PhysRC;
107 }
108 
110  const MachineInstr &MI, unsigned OpIdx, const TargetInstrInfo &TII,
111  const TargetRegisterInfo &TRI) const {
112  // The mapping of the registers may be available via the
113  // register class constraints.
114  const TargetRegisterClass *RC = MI.getRegClassConstraint(OpIdx, &TII, &TRI);
115 
116  if (!RC)
117  return nullptr;
118 
119  const RegisterBank &RegBank = getRegBankFromRegClass(*RC);
120  // Sanity check that the target properly implemented getRegBankFromRegClass.
121  assert(RegBank.covers(*RC) &&
122  "The mapping of the register bank does not make sense");
123  return &RegBank;
124 }
125 
128 
129  // If the register already has a class, fallback to MRI::constrainRegClass.
130  auto &RegClassOrBank = MRI.getRegClassOrRegBank(Reg);
131  if (RegClassOrBank.is<const TargetRegisterClass *>())
132  return MRI.constrainRegClass(Reg, &RC);
133 
134  const RegisterBank *RB = RegClassOrBank.get<const RegisterBank *>();
135  // Otherwise, all we can do is ensure the bank covers the class, and set it.
136  if (RB && !RB->covers(RC))
137  return nullptr;
138 
139  // If nothing was set or the class is simply compatible, set it.
140  MRI.setRegClass(Reg, &RC);
141  return &RC;
142 }
143 
144 /// Check whether or not \p MI should be treated like a copy
145 /// for the mappings.
146 /// Copy like instruction are special for mapping because
147 /// they don't have actual register constraints. Moreover,
148 /// they sometimes have register classes assigned and we can
149 /// just use that instead of failing to provide a generic mapping.
150 static bool isCopyLike(const MachineInstr &MI) {
151  return MI.isCopy() || MI.isPHI() ||
152  MI.getOpcode() == TargetOpcode::REG_SEQUENCE;
153 }
154 
157  // For copies we want to walk over the operands and try to find one
158  // that has a register bank since the instruction itself will not get
159  // us any constraint.
160  bool IsCopyLike = isCopyLike(MI);
161  // For copy like instruction, only the mapping of the definition
162  // is important. The rest is not constrained.
163  unsigned NumOperandsForMapping = IsCopyLike ? 1 : MI.getNumOperands();
164 
165  const MachineFunction &MF = *MI.getMF();
166  const TargetSubtargetInfo &STI = MF.getSubtarget();
167  const TargetRegisterInfo &TRI = *STI.getRegisterInfo();
168  const MachineRegisterInfo &MRI = MF.getRegInfo();
169  // We may need to query the instruction encoding to guess the mapping.
170  const TargetInstrInfo &TII = *STI.getInstrInfo();
171 
172  // Before doing anything complicated check if the mapping is not
173  // directly available.
174  bool CompleteMapping = true;
175 
176  SmallVector<const ValueMapping *, 8> OperandsMapping(NumOperandsForMapping);
177  for (unsigned OpIdx = 0, EndIdx = MI.getNumOperands(); OpIdx != EndIdx;
178  ++OpIdx) {
179  const MachineOperand &MO = MI.getOperand(OpIdx);
180  if (!MO.isReg())
181  continue;
182  Register Reg = MO.getReg();
183  if (!Reg)
184  continue;
185  // The register bank of Reg is just a side effect of the current
186  // excution and in particular, there is no reason to believe this
187  // is the best default mapping for the current instruction. Keep
188  // it as an alternative register bank if we cannot figure out
189  // something.
190  const RegisterBank *AltRegBank = getRegBank(Reg, MRI, TRI);
191  // For copy-like instruction, we want to reuse the register bank
192  // that is already set on Reg, if any, since those instructions do
193  // not have any constraints.
194  const RegisterBank *CurRegBank = IsCopyLike ? AltRegBank : nullptr;
195  if (!CurRegBank) {
196  // If this is a target specific instruction, we can deduce
197  // the register bank from the encoding constraints.
198  CurRegBank = getRegBankFromConstraints(MI, OpIdx, TII, TRI);
199  if (!CurRegBank) {
200  // All our attempts failed, give up.
201  CompleteMapping = false;
202 
203  if (!IsCopyLike)
204  // MI does not carry enough information to guess the mapping.
206  continue;
207  }
208  }
209 
210  unsigned Size = getSizeInBits(Reg, MRI, TRI);
211  const ValueMapping *ValMapping = &getValueMapping(0, Size, *CurRegBank);
212  if (IsCopyLike) {
213  if (!OperandsMapping[0]) {
214  if (MI.isRegSequence()) {
215  // For reg_sequence, the result size does not match the input.
216  unsigned ResultSize = getSizeInBits(MI.getOperand(0).getReg(),
217  MRI, TRI);
218  OperandsMapping[0] = &getValueMapping(0, ResultSize, *CurRegBank);
219  } else {
220  OperandsMapping[0] = ValMapping;
221  }
222  }
223 
224  // The default handling assumes any register bank can be copied to any
225  // other. If this isn't the case, the target should specially deal with
226  // reg_sequence/phi. There may also be unsatisfiable copies.
227  for (; OpIdx != EndIdx; ++OpIdx) {
228  const MachineOperand &MO = MI.getOperand(OpIdx);
229  if (!MO.isReg())
230  continue;
231  Register Reg = MO.getReg();
232  if (!Reg)
233  continue;
234 
235  const RegisterBank *AltRegBank = getRegBank(Reg, MRI, TRI);
236  if (AltRegBank &&
237  cannotCopy(*CurRegBank, *AltRegBank, getSizeInBits(Reg, MRI, TRI)))
239  }
240 
241  CompleteMapping = true;
242  break;
243  }
244 
245  OperandsMapping[OpIdx] = ValMapping;
246  }
247 
248  if (IsCopyLike && !CompleteMapping) {
249  // No way to deduce the type from what we have.
251  }
252 
253  assert(CompleteMapping && "Setting an uncomplete mapping");
254  return getInstructionMapping(
255  DefaultMappingID, /*Cost*/ 1,
256  /*OperandsMapping*/ getOperandsMapping(OperandsMapping),
257  NumOperandsForMapping);
258 }
259 
260 /// Hashing function for PartialMapping.
261 static hash_code hashPartialMapping(unsigned StartIdx, unsigned Length,
262  const RegisterBank *RegBank) {
263  return hash_combine(StartIdx, Length, RegBank ? RegBank->getID() : 0);
264 }
265 
266 /// Overloaded version of hash_value for a PartialMapping.
267 hash_code
269  return hashPartialMapping(PartMapping.StartIdx, PartMapping.Length,
270  PartMapping.RegBank);
271 }
272 
274 RegisterBankInfo::getPartialMapping(unsigned StartIdx, unsigned Length,
275  const RegisterBank &RegBank) const {
276  ++NumPartialMappingsAccessed;
277 
278  hash_code Hash = hashPartialMapping(StartIdx, Length, &RegBank);
279  const auto &It = MapOfPartialMappings.find(Hash);
280  if (It != MapOfPartialMappings.end())
281  return *It->second;
282 
283  ++NumPartialMappingsCreated;
284 
285  auto &PartMapping = MapOfPartialMappings[Hash];
286  PartMapping = std::make_unique<PartialMapping>(StartIdx, Length, RegBank);
287  return *PartMapping;
288 }
289 
291 RegisterBankInfo::getValueMapping(unsigned StartIdx, unsigned Length,
292  const RegisterBank &RegBank) const {
293  return getValueMapping(&getPartialMapping(StartIdx, Length, RegBank), 1);
294 }
295 
296 static hash_code
298  unsigned NumBreakDowns) {
299  if (LLVM_LIKELY(NumBreakDowns == 1))
300  return hash_value(*BreakDown);
301  SmallVector<size_t, 8> Hashes(NumBreakDowns);
302  for (unsigned Idx = 0; Idx != NumBreakDowns; ++Idx)
303  Hashes.push_back(hash_value(BreakDown[Idx]));
304  return hash_combine_range(Hashes.begin(), Hashes.end());
305 }
306 
309  unsigned NumBreakDowns) const {
310  ++NumValueMappingsAccessed;
311 
312  hash_code Hash = hashValueMapping(BreakDown, NumBreakDowns);
313  const auto &It = MapOfValueMappings.find(Hash);
314  if (It != MapOfValueMappings.end())
315  return *It->second;
316 
317  ++NumValueMappingsCreated;
318 
319  auto &ValMapping = MapOfValueMappings[Hash];
320  ValMapping = std::make_unique<ValueMapping>(BreakDown, NumBreakDowns);
321  return *ValMapping;
322 }
323 
324 template <typename Iterator>
326 RegisterBankInfo::getOperandsMapping(Iterator Begin, Iterator End) const {
327 
328  ++NumOperandsMappingsAccessed;
329 
330  // The addresses of the value mapping are unique.
331  // Therefore, we can use them directly to hash the operand mapping.
332  hash_code Hash = hash_combine_range(Begin, End);
333  auto &Res = MapOfOperandsMappings[Hash];
334  if (Res)
335  return Res.get();
336 
337  ++NumOperandsMappingsCreated;
338 
339  // Create the array of ValueMapping.
340  // Note: this array will not hash to this instance of operands
341  // mapping, because we use the pointer of the ValueMapping
342  // to hash and we expect them to uniquely identify an instance
343  // of value mapping.
344  Res = std::make_unique<ValueMapping[]>(std::distance(Begin, End));
345  unsigned Idx = 0;
346  for (Iterator It = Begin; It != End; ++It, ++Idx) {
347  const ValueMapping *ValMap = *It;
348  if (!ValMap)
349  continue;
350  Res[Idx] = *ValMap;
351  }
352  return Res.get();
353 }
354 
357  const {
358  return getOperandsMapping(OpdsMapping.begin(), OpdsMapping.end());
359 }
360 
362  std::initializer_list<const RegisterBankInfo::ValueMapping *> OpdsMapping)
363  const {
364  return getOperandsMapping(OpdsMapping.begin(), OpdsMapping.end());
365 }
366 
367 static hash_code
368 hashInstructionMapping(unsigned ID, unsigned Cost,
369  const RegisterBankInfo::ValueMapping *OperandsMapping,
370  unsigned NumOperands) {
371  return hash_combine(ID, Cost, OperandsMapping, NumOperands);
372 }
373 
375 RegisterBankInfo::getInstructionMappingImpl(
376  bool IsInvalid, unsigned ID, unsigned Cost,
377  const RegisterBankInfo::ValueMapping *OperandsMapping,
378  unsigned NumOperands) const {
379  assert(((IsInvalid && ID == InvalidMappingID && Cost == 0 &&
380  OperandsMapping == nullptr && NumOperands == 0) ||
381  !IsInvalid) &&
382  "Mismatch argument for invalid input");
383  ++NumInstructionMappingsAccessed;
384 
385  hash_code Hash =
386  hashInstructionMapping(ID, Cost, OperandsMapping, NumOperands);
387  const auto &It = MapOfInstructionMappings.find(Hash);
388  if (It != MapOfInstructionMappings.end())
389  return *It->second;
390 
391  ++NumInstructionMappingsCreated;
392 
393  auto &InstrMapping = MapOfInstructionMappings[Hash];
394  InstrMapping = std::make_unique<InstructionMapping>(
395  ID, Cost, OperandsMapping, NumOperands);
396  return *InstrMapping;
397 }
398 
402  if (Mapping.isValid())
403  return Mapping;
404  llvm_unreachable("The target must implement this");
405 }
406 
408 RegisterBankInfo::getInstrPossibleMappings(const MachineInstr &MI) const {
409  InstructionMappings PossibleMappings;
410  const auto &Mapping = getInstrMapping(MI);
411  if (Mapping.isValid()) {
412  // Put the default mapping first.
413  PossibleMappings.push_back(&Mapping);
414  }
415 
416  // Then the alternative mapping, if any.
418  for (const InstructionMapping *AltMapping : AltMappings)
419  PossibleMappings.push_back(AltMapping);
420 #ifndef NDEBUG
421  for (const InstructionMapping *Mapping : PossibleMappings)
422  assert(Mapping->verify(MI) && "Mapping is invalid");
423 #endif
424  return PossibleMappings;
425 }
426 
429  // No alternative for MI.
430  return InstructionMappings();
431 }
432 
434  MachineInstr &MI = OpdMapper.getMI();
435  MachineRegisterInfo &MRI = OpdMapper.getMRI();
436  LLVM_DEBUG(dbgs() << "Applying default-like mapping\n");
437  for (unsigned OpIdx = 0,
438  EndIdx = OpdMapper.getInstrMapping().getNumOperands();
439  OpIdx != EndIdx; ++OpIdx) {
440  LLVM_DEBUG(dbgs() << "OpIdx " << OpIdx);
441  MachineOperand &MO = MI.getOperand(OpIdx);
442  if (!MO.isReg()) {
443  LLVM_DEBUG(dbgs() << " is not a register, nothing to be done\n");
444  continue;
445  }
446  if (!MO.getReg()) {
447  LLVM_DEBUG(dbgs() << " is %%noreg, nothing to be done\n");
448  continue;
449  }
450  assert(OpdMapper.getInstrMapping().getOperandMapping(OpIdx).NumBreakDowns !=
451  0 &&
452  "Invalid mapping");
453  assert(OpdMapper.getInstrMapping().getOperandMapping(OpIdx).NumBreakDowns ==
454  1 &&
455  "This mapping is too complex for this function");
457  OpdMapper.getVRegs(OpIdx);
458  if (empty(NewRegs)) {
459  LLVM_DEBUG(dbgs() << " has not been repaired, nothing to be done\n");
460  continue;
461  }
462  Register OrigReg = MO.getReg();
463  Register NewReg = *NewRegs.begin();
464  LLVM_DEBUG(dbgs() << " changed, replace " << printReg(OrigReg, nullptr));
465  MO.setReg(NewReg);
466  LLVM_DEBUG(dbgs() << " with " << printReg(NewReg, nullptr));
467 
468  // The OperandsMapper creates plain scalar, we may have to fix that.
469  // Check if the types match and if not, fix that.
470  LLT OrigTy = MRI.getType(OrigReg);
471  LLT NewTy = MRI.getType(NewReg);
472  if (OrigTy != NewTy) {
473  // The default mapping is not supposed to change the size of
474  // the storage. However, right now we don't necessarily bump all
475  // the types to storage size. For instance, we can consider
476  // s16 G_AND legal whereas the storage size is going to be 32.
477  assert(OrigTy.getSizeInBits() <= NewTy.getSizeInBits() &&
478  "Types with difference size cannot be handled by the default "
479  "mapping");
480  LLVM_DEBUG(dbgs() << "\nChange type of new opd from " << NewTy << " to "
481  << OrigTy);
482  MRI.setType(NewReg, OrigTy);
483  }
484  LLVM_DEBUG(dbgs() << '\n');
485  }
486 }
487 
489  const MachineRegisterInfo &MRI,
490  const TargetRegisterInfo &TRI) const {
491  if (Register::isPhysicalRegister(Reg)) {
492  // The size is not directly available for physical registers.
493  // Instead, we need to access a register class that contains Reg and
494  // get the size of that register class.
495  // Because this is expensive, we'll cache the register class by calling
496  auto *RC = &getMinimalPhysRegClass(Reg, TRI);
497  assert(RC && "Expecting Register class");
498  return TRI.getRegSizeInBits(*RC);
499  }
500  return TRI.getRegSizeInBits(Reg, MRI);
501 }
502 
503 //------------------------------------------------------------------------------
504 // Helper classes implementation.
505 //------------------------------------------------------------------------------
506 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
508  print(dbgs());
509  dbgs() << '\n';
510 }
511 #endif
512 
514  assert(RegBank && "Register bank not set");
515  assert(Length && "Empty mapping");
516  assert((StartIdx <= getHighBitIdx()) && "Overflow, switch to APInt?");
517  // Check if the minimum width fits into RegBank.
518  assert(RegBank->getSize() >= Length && "Register bank too small for Mask");
519  return true;
520 }
521 
523  OS << "[" << StartIdx << ", " << getHighBitIdx() << "], RegBank = ";
524  if (RegBank)
525  OS << *RegBank;
526  else
527  OS << "nullptr";
528 }
529 
531  if (NumBreakDowns < 2)
532  return true;
533 
534  const PartialMapping *First = begin();
535  for (const PartialMapping *Part = First + 1; Part != end(); ++Part) {
536  if (Part->Length != First->Length || Part->RegBank != First->RegBank)
537  return false;
538  }
539 
540  return true;
541 }
542 
543 bool RegisterBankInfo::ValueMapping::verify(unsigned MeaningfulBitWidth) const {
544  assert(NumBreakDowns && "Value mapped nowhere?!");
545  unsigned OrigValueBitWidth = 0;
546  for (const RegisterBankInfo::PartialMapping &PartMap : *this) {
547  // Check that each register bank is big enough to hold the partial value:
548  // this check is done by PartialMapping::verify
549  assert(PartMap.verify() && "Partial mapping is invalid");
550  // The original value should completely be mapped.
551  // Thus the maximum accessed index + 1 is the size of the original value.
552  OrigValueBitWidth =
553  std::max(OrigValueBitWidth, PartMap.getHighBitIdx() + 1);
554  }
555  assert(OrigValueBitWidth >= MeaningfulBitWidth &&
556  "Meaningful bits not covered by the mapping");
557  APInt ValueMask(OrigValueBitWidth, 0);
558  for (const RegisterBankInfo::PartialMapping &PartMap : *this) {
559  // Check that the union of the partial mappings covers the whole value,
560  // without overlaps.
561  // The high bit is exclusive in the APInt API, thus getHighBitIdx + 1.
562  APInt PartMapMask = APInt::getBitsSet(OrigValueBitWidth, PartMap.StartIdx,
563  PartMap.getHighBitIdx() + 1);
564  ValueMask ^= PartMapMask;
565  assert((ValueMask & PartMapMask) == PartMapMask &&
566  "Some partial mappings overlap");
567  }
568  assert(ValueMask.isAllOnesValue() && "Value is not fully mapped");
569  return true;
570 }
571 
572 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
574  print(dbgs());
575  dbgs() << '\n';
576 }
577 #endif
578 
580  OS << "#BreakDown: " << NumBreakDowns << " ";
581  bool IsFirst = true;
582  for (const PartialMapping &PartMap : *this) {
583  if (!IsFirst)
584  OS << ", ";
585  OS << '[' << PartMap << ']';
586  IsFirst = false;
587  }
588 }
589 
591  const MachineInstr &MI) const {
592  // Check that all the register operands are properly mapped.
593  // Check the constructor invariant.
594  // For PHI, we only care about mapping the definition.
595  assert(NumOperands == (isCopyLike(MI) ? 1 : MI.getNumOperands()) &&
596  "NumOperands must match, see constructor");
597  assert(MI.getParent() && MI.getMF() &&
598  "MI must be connected to a MachineFunction");
599  const MachineFunction &MF = *MI.getMF();
600  const RegisterBankInfo *RBI = MF.getSubtarget().getRegBankInfo();
601  (void)RBI;
602 
603  for (unsigned Idx = 0; Idx < NumOperands; ++Idx) {
604  const MachineOperand &MO = MI.getOperand(Idx);
605  if (!MO.isReg()) {
606  assert(!getOperandMapping(Idx).isValid() &&
607  "We should not care about non-reg mapping");
608  continue;
609  }
610  Register Reg = MO.getReg();
611  if (!Reg)
612  continue;
613  assert(getOperandMapping(Idx).isValid() &&
614  "We must have a mapping for reg operands");
615  const RegisterBankInfo::ValueMapping &MOMapping = getOperandMapping(Idx);
616  (void)MOMapping;
617  // Register size in bits.
618  // This size must match what the mapping expects.
619  assert(MOMapping.verify(RBI->getSizeInBits(
620  Reg, MF.getRegInfo(), *MF.getSubtarget().getRegisterInfo())) &&
621  "Value mapping is invalid");
622  }
623  return true;
624 }
625 
626 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
628  print(dbgs());
629  dbgs() << '\n';
630 }
631 #endif
632 
634  OS << "ID: " << getID() << " Cost: " << getCost() << " Mapping: ";
635 
636  for (unsigned OpIdx = 0; OpIdx != NumOperands; ++OpIdx) {
637  const ValueMapping &ValMapping = getOperandMapping(OpIdx);
638  if (OpIdx)
639  OS << ", ";
640  OS << "{ Idx: " << OpIdx << " Map: " << ValMapping << '}';
641  }
642 }
643 
644 const int RegisterBankInfo::OperandsMapper::DontKnowIdx = -1;
645 
647  MachineInstr &MI, const InstructionMapping &InstrMapping,
648  MachineRegisterInfo &MRI)
649  : MRI(MRI), MI(MI), InstrMapping(InstrMapping) {
650  unsigned NumOpds = InstrMapping.getNumOperands();
651  OpToNewVRegIdx.resize(NumOpds, OperandsMapper::DontKnowIdx);
652  assert(InstrMapping.verify(MI) && "Invalid mapping for MI");
653 }
654 
656 RegisterBankInfo::OperandsMapper::getVRegsMem(unsigned OpIdx) {
657  assert(OpIdx < getInstrMapping().getNumOperands() && "Out-of-bound access");
658  unsigned NumPartialVal =
659  getInstrMapping().getOperandMapping(OpIdx).NumBreakDowns;
660  int StartIdx = OpToNewVRegIdx[OpIdx];
661 
662  if (StartIdx == OperandsMapper::DontKnowIdx) {
663  // This is the first time we try to access OpIdx.
664  // Create the cells that will hold all the partial values at the
665  // end of the list of NewVReg.
666  StartIdx = NewVRegs.size();
667  OpToNewVRegIdx[OpIdx] = StartIdx;
668  for (unsigned i = 0; i < NumPartialVal; ++i)
669  NewVRegs.push_back(0);
670  }
672  getNewVRegsEnd(StartIdx, NumPartialVal);
673 
674  return make_range(&NewVRegs[StartIdx], End);
675 }
676 
678 RegisterBankInfo::OperandsMapper::getNewVRegsEnd(unsigned StartIdx,
679  unsigned NumVal) const {
680  return const_cast<OperandsMapper *>(this)->getNewVRegsEnd(StartIdx, NumVal);
681 }
683 RegisterBankInfo::OperandsMapper::getNewVRegsEnd(unsigned StartIdx,
684  unsigned NumVal) {
685  assert((NewVRegs.size() == StartIdx + NumVal ||
686  NewVRegs.size() > StartIdx + NumVal) &&
687  "NewVRegs too small to contain all the partial mapping");
688  return NewVRegs.size() <= StartIdx + NumVal ? NewVRegs.end()
689  : &NewVRegs[StartIdx + NumVal];
690 }
691 
693  assert(OpIdx < getInstrMapping().getNumOperands() && "Out-of-bound access");
695  getVRegsMem(OpIdx);
696  const ValueMapping &ValMapping = getInstrMapping().getOperandMapping(OpIdx);
697  const PartialMapping *PartMap = ValMapping.begin();
698  for (Register &NewVReg : NewVRegsForOpIdx) {
699  assert(PartMap != ValMapping.end() && "Out-of-bound access");
700  assert(NewVReg == 0 && "Register has already been created");
701  // The new registers are always bound to scalar with the right size.
702  // The actual type has to be set when the target does the mapping
703  // of the instruction.
704  // The rationale is that this generic code cannot guess how the
705  // target plans to split the input type.
706  NewVReg = MRI.createGenericVirtualRegister(LLT::scalar(PartMap->Length));
707  MRI.setRegBank(NewVReg, *PartMap->RegBank);
708  ++PartMap;
709  }
710 }
711 
713  unsigned PartialMapIdx,
714  Register NewVReg) {
715  assert(OpIdx < getInstrMapping().getNumOperands() && "Out-of-bound access");
716  assert(getInstrMapping().getOperandMapping(OpIdx).NumBreakDowns >
717  PartialMapIdx &&
718  "Out-of-bound access for partial mapping");
719  // Make sure the memory is initialized for that operand.
720  (void)getVRegsMem(OpIdx);
721  assert(NewVRegs[OpToNewVRegIdx[OpIdx] + PartialMapIdx] == 0 &&
722  "This value is already set");
723  NewVRegs[OpToNewVRegIdx[OpIdx] + PartialMapIdx] = NewVReg;
724 }
725 
728  bool ForDebug) const {
729  (void)ForDebug;
730  assert(OpIdx < getInstrMapping().getNumOperands() && "Out-of-bound access");
731  int StartIdx = OpToNewVRegIdx[OpIdx];
732 
733  if (StartIdx == OperandsMapper::DontKnowIdx)
734  return make_range(NewVRegs.end(), NewVRegs.end());
735 
736  unsigned PartMapSize =
737  getInstrMapping().getOperandMapping(OpIdx).NumBreakDowns;
739  getNewVRegsEnd(StartIdx, PartMapSize);
741  make_range(&NewVRegs[StartIdx], End);
742 #ifndef NDEBUG
743  for (Register VReg : Res)
744  assert((VReg || ForDebug) && "Some registers are uninitialized");
745 #endif
746  return Res;
747 }
748 
749 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
751  print(dbgs(), true);
752  dbgs() << '\n';
753 }
754 #endif
755 
757  bool ForDebug) const {
758  unsigned NumOpds = getInstrMapping().getNumOperands();
759  if (ForDebug) {
760  OS << "Mapping for " << getMI() << "\nwith " << getInstrMapping() << '\n';
761  // Print out the internal state of the index table.
762  OS << "Populated indices (CellNumber, IndexInNewVRegs): ";
763  bool IsFirst = true;
764  for (unsigned Idx = 0; Idx != NumOpds; ++Idx) {
765  if (OpToNewVRegIdx[Idx] != DontKnowIdx) {
766  if (!IsFirst)
767  OS << ", ";
768  OS << '(' << Idx << ", " << OpToNewVRegIdx[Idx] << ')';
769  IsFirst = false;
770  }
771  }
772  OS << '\n';
773  } else
774  OS << "Mapping ID: " << getInstrMapping().getID() << ' ';
775 
776  OS << "Operand Mapping: ";
777  // If we have a function, we can pretty print the name of the registers.
778  // Otherwise we will print the raw numbers.
779  const TargetRegisterInfo *TRI =
780  getMI().getParent() && getMI().getMF()
782  : nullptr;
783  bool IsFirst = true;
784  for (unsigned Idx = 0; Idx != NumOpds; ++Idx) {
785  if (OpToNewVRegIdx[Idx] == DontKnowIdx)
786  continue;
787  if (!IsFirst)
788  OS << ", ";
789  IsFirst = false;
790  OS << '(' << printReg(getMI().getOperand(Idx).getReg(), TRI) << ", [";
791  bool IsFirstNewVReg = true;
792  for (Register VReg : getVRegs(Idx)) {
793  if (!IsFirstNewVReg)
794  OS << ", ";
795  IsFirstNewVReg = false;
796  OS << printReg(VReg, TRI);
797  }
798  OS << "])";
799  }
800 }
unsigned NumRegBanks
Total number of register banks.
static const unsigned InvalidMappingID
Identifier used when the related instruction mapping instance is generated by the default constructor...
RegisterBank ** RegBanks
Hold the set of supported register banks.
const_iterator end(StringRef path)
Get end iterator over path.
Definition: Path.cpp:233
const ValueMapping * getOperandsMapping(Iterator Begin, Iterator End) const
Get the uniquely generated array of ValueMapping for the elements of between Begin and End...
GCNRegPressure max(const GCNRegPressure &P1, const GCNRegPressure &P2)
const_iterator begin(StringRef path, Style style=Style::native)
Get begin iterator over path.
Definition: Path.cpp:224
typename SuperClass::const_iterator const_iterator
Definition: SmallVector.h:320
const MachineFunction * getMF() const
Return the function that contains the basic block that this instruction belongs to.
This class represents lattice values for constants.
Definition: AllocatorList.h:23
void print(raw_ostream &OS) const
Print this on OS;.
#define LLVM_DUMP_METHOD
Mark debug helper function definitions like dump() that should not be stripped from debug builds...
Definition: Compiler.h:473
const InstructionMapping & getInstructionMapping(unsigned ID, unsigned Cost, const ValueMapping *OperandsMapping, unsigned NumOperands) const
Method to get a uniquely generated InstructionMapping.
#define LLVM_LIKELY(EXPR)
Definition: Compiler.h:198
void setVRegs(unsigned OpIdx, unsigned PartialMapIdx, Register NewVReg)
Set the virtual register of the PartialMapIdx-th partial mapping of the OpIdx-th operand to NewVReg...
DenseMap< unsigned, std::unique_ptr< const PartialMapping > > MapOfPartialMappings
Keep dynamically allocated PartialMapping in a separate map.
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
unsigned getSizeInBits(Register Reg, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI) const
Get the size in bits of Reg.
void dump() const
Print this on dbgs() stream.
Helper class that represents how the value of an instruction may be mapped and what is the related co...
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:63
This provides a very simple, boring adaptor for a begin and end iterator into a range type...
unsigned Reg
unsigned getNumRegBanks() const
Get the total number of register banks.
MachineRegisterInfo & getMRI() const
The MachineRegisterInfo we used to realize the mapping.
bool isRegSequence() const
LLT getType(unsigned Reg) const
Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register...
Helper class used to get/create the virtual registers that will be used to replace the MachineOperand...
STATISTIC(NumFunctions, "Total number of functions")
unsigned const TargetRegisterInfo * TRI
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
void setRegBank(unsigned Reg, const RegisterBank &RegBank)
Set the register bank to RegBank for Reg.
bool isPHI() const
const TargetRegisterClass & getMinimalPhysRegClass(Register Reg, const TargetRegisterInfo &TRI) const
Get the MinimalPhysRegClass for Reg.
static hash_code hashValueMapping(const RegisterBankInfo::PartialMapping *BreakDown, unsigned NumBreakDowns)
void dump() const
Print this partial mapping on dbgs() stream.
bool verify(unsigned MeaningfulBitWidth) const
Verify that this mapping makes sense for a value of MeaningfulBitWidth.
bool covers(const TargetRegisterClass &RC) const
Check whether this register bank covers RC.
T dyn_cast() const
Returns the current pointer if it is of the specified pointer type, otherwises returns null...
Definition: PointerUnion.h:205
Holds all the information related to register banks.
const HexagonInstrInfo * TII
const TargetRegisterClass * getRegClassConstraint(unsigned OpIdx, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const
Compute the static register class constraint for operand OpIdx.
unsigned getNumOperands() const
Retuns the total number of operands.
Definition: MachineInstr.h:414
const InstructionMapping & getInstrMapping() const
The final mapping of the instruction.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:41
unsigned StartIdx
Number of bits at which this partial mapping starts in the original value.
void dump() const
Print this operands mapper on dbgs() stream.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:411
iterator_range< SmallVectorImpl< Register >::const_iterator > getVRegs(unsigned OpIdx, bool ForDebug=false) const
Get all the virtual registers required to map the OpIdx-th operand of the instruction.
bool verify() const
Check that the Mask is compatible with the RegBank.
static int getID(struct InternalInstruction *insn, const void *miiArg)
const RegClassOrRegBank & getRegClassOrRegBank(unsigned Reg) const
Return the register bank or register class of Reg.
hash_code hash_value(const APFloat &Arg)
See friend declarations above.
Definition: APFloat.cpp:4470
const PartialMapping & getPartialMapping(unsigned StartIdx, unsigned Length, const RegisterBank &RegBank) const
Get the uniquely generated PartialMapping for the given arguments.
void setReg(Register Reg)
Change the register this operand corresponds to.
virtual const TargetInstrInfo * getInstrInfo() const
static LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
const TargetRegisterClass * constrainRegClass(unsigned Reg, const TargetRegisterClass *RC, unsigned MinNumRegs=0)
constrainRegClass - Constrain the register class of the specified virtual register to be a common sub...
const RegisterBank * RegBank
Register bank where the partial value lives.
TargetInstrInfo - Interface to description of machine instruction set.
bool isAllOnesValue() const
Determine if all bits are set.
Definition: APInt.h:395
unsigned const MachineRegisterInfo * MRI
const InstructionMapping & getInvalidInstructionMapping() const
Method to get a uniquely generated invalid InstructionMapping.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
virtual const InstructionMapping & getInstrMapping(const MachineInstr &MI) const
Get the mapping of the different operands of MI on the register bank.
Helper struct that represents how a value is partially mapped into a register.
unsigned Length
Length of this mapping in bits.
void setType(unsigned VReg, LLT Ty)
Set the low-level type of VReg to Ty.
static bool isCopyLike(const MachineInstr &MI)
Check whether or not MI should be treated like a copy for the mappings.
static void print(raw_ostream &Out, object::Archive::Kind Kind, T Val)
static const unsigned DefaultMappingID
Identifier used when the related instruction mapping instance is generated by target independent code...
bool isCopy() const
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
constexpr bool empty(const T &RangeOrContainer)
Test whether RangeOrContainer is empty. Similar to C++17 std::empty.
Definition: STLExtras.h:209
DenseMap< unsigned, const TargetRegisterClass * > PhysRegMinimalRCs
Getting the minimal register class of a physreg is expensive.
bool isValid() const
Check whether this object is valid.
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
bool verify(const MachineInstr &MI) const
Verifiy that this mapping makes sense for MI.
const PartialMapping * end() const
OperandsMapper(MachineInstr &MI, const InstructionMapping &InstrMapping, MachineRegisterInfo &MRI)
Create an OperandsMapper that will hold the information to apply InstrMapping to MI.
static hash_code hashPartialMapping(unsigned StartIdx, unsigned Length, const RegisterBank *RegBank)
Hashing function for PartialMapping.
RegisterBank & getRegBank(unsigned ID)
Get the register bank identified by ID.
MachineOperand class - Representation of each machine instruction operand.
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:837
static void applyDefaultMapping(const OperandsMapper &OpdMapper)
Helper method to apply something that is like the default mapping.
void print(raw_ostream &OS) const
Print this on OS;.
unsigned getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
void print(raw_ostream &OS) const
Print this partial mapping on OS;.
This class implements the register bank concept.
Definition: RegisterBank.h:28
Helper struct that represents how a value is mapped through different register banks.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
A range adaptor for a pair of iterators.
Class for arbitrary precision integers.
Definition: APInt.h:69
hash_code hash_combine(const Ts &...args)
Combine values into a single hash_code.
Definition: Hashing.h:600
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
typename SuperClass::iterator iterator
Definition: SmallVector.h:319
static hash_code hashInstructionMapping(unsigned ID, unsigned Cost, const RegisterBankInfo::ValueMapping *OperandsMapping, unsigned NumOperands)
hash_code hash_combine_range(InputIteratorT first, InputIteratorT last)
Compute a hash_code for a sequence of values.
Definition: Hashing.h:478
An opaque object representing a hash code.
Definition: Hashing.h:71
const PartialMapping * begin() const
Iterators through the PartialMappings.
void createVRegs(unsigned OpIdx)
Create as many new virtual registers as needed for the mapping of the OpIdx-th operand.
static APInt getBitsSet(unsigned numBits, unsigned loBit, unsigned hiBit)
Get a value with a block of bits set.
Definition: APInt.h:606
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:256
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
TargetSubtargetInfo - Generic base class for all target subtargets.
Representation of each machine instruction.
Definition: MachineInstr.h:64
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
virtual InstructionMappings getInstrAlternativeMappings(const MachineInstr &MI) const
Get the alternative mappings for MI.
DenseMap< unsigned, std::unique_ptr< ValueMapping[]> > MapOfOperandsMappings
Keep dynamically allocated array of ValueMapping in a separate map.
const InstructionMapping & getInstrMappingImpl(const MachineInstr &MI) const
Try to get the mapping of MI.
uint32_t Size
Definition: Profile.cpp:46
const TargetRegisterClass * getMinimalPhysRegClass(unsigned Reg, MVT VT=MVT::Other) const
Returns the Register Class of a physical register of the given type, picking the most sub register cl...
bool isReg() const
isReg - Tests if this is a MO_Register operand.
bool cannotCopy(const RegisterBank &Dst, const RegisterBank &Src, unsigned Size) const
bool verify(const TargetRegisterInfo &TRI) const
Check if this register bank is valid.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
unsigned NumBreakDowns
Number of partial mapping to break down this value.
const RegisterBank * getRegBankFromConstraints(const MachineInstr &MI, unsigned OpIdx, const TargetInstrInfo &TII, const TargetRegisterInfo &TRI) const
Get the register bank for the OpIdx-th operand of MI form the encoding constraints, if any.
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:45
DenseMap< unsigned, std::unique_ptr< const InstructionMapping > > MapOfInstructionMappings
Keep dynamically allocated InstructionMapping in a separate map.
IRTranslator LLVM IR MI
void setRegClass(unsigned Reg, const TargetRegisterClass *RC)
setRegClass - Set the register class of the specified virtual register.
RegisterBankInfo()
This constructor is meaningless.
unsigned getRegSizeInBits(const TargetRegisterClass &RC) const
Return the size in bits of a register from class RC.
ppc ctr loops verify
Register createGenericVirtualRegister(LLT Ty, StringRef Name="")
Create and return a new generic virtual register with low-level type Ty.
DenseMap< unsigned, std::unique_ptr< const ValueMapping > > MapOfValueMappings
Keep dynamically allocated ValueMapping in a separate map.
Register getReg() const
getReg - Returns the register number.
void print(raw_ostream &OS, bool ForDebug=false) const
Print this operands mapper on OS stream.
void dump() const
Print this on dbgs() stream.
unsigned getNumOperands() const
Get the number of operands.
#define LLVM_DEBUG(X)
Definition: Debug.h:122
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:416
const ValueMapping & getValueMapping(unsigned StartIdx, unsigned Length, const RegisterBank &RegBank) const
The most common ValueMapping consists of a single PartialMapping.
SmallVector< const InstructionMapping *, 4 > InstructionMappings
Convenient type to represent the alternatives for mapping an instruction.
static const TargetRegisterClass * constrainGenericRegister(Register Reg, const TargetRegisterClass &RC, MachineRegisterInfo &MRI)
Constrain the (possibly generic) virtual register Reg to RC.
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
unsigned getID() const
Get the identifier of this register bank.
Definition: RegisterBank.h:47
A discriminated union of two or more pointer types, with the discriminator in the low bit of the poin...
Definition: PointerUnion.h:156
virtual const RegisterBank & getRegBankFromRegClass(const TargetRegisterClass &RC) const
Get a register bank that covers RC.
void resize(size_type N)
Definition: SmallVector.h:344