LLVM  10.0.0svn
Thumb2ITBlockPass.cpp
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1 //===-- Thumb2ITBlockPass.cpp - Insert Thumb-2 IT blocks ------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #include "ARM.h"
10 #include "ARMMachineFunctionInfo.h"
11 #include "ARMSubtarget.h"
13 #include "Thumb2InstrInfo.h"
14 #include "llvm/ADT/SmallSet.h"
15 #include "llvm/ADT/SmallVector.h"
16 #include "llvm/ADT/Statistic.h"
17 #include "llvm/ADT/StringRef.h"
25 #include "llvm/IR/DebugLoc.h"
26 #include "llvm/MC/MCInstrDesc.h"
27 #include "llvm/MC/MCRegisterInfo.h"
28 #include <cassert>
29 #include <new>
30 
31 using namespace llvm;
32 
33 #define DEBUG_TYPE "thumb2-it"
34 #define PASS_NAME "Thumb IT blocks insertion pass"
35 
36 STATISTIC(NumITs, "Number of IT blocks inserted");
37 STATISTIC(NumMovedInsts, "Number of predicated instructions moved");
38 
40 
41 namespace {
42 
43  class Thumb2ITBlock : public MachineFunctionPass {
44  public:
45  static char ID;
46 
47  bool restrictIT;
48  const Thumb2InstrInfo *TII;
49  const TargetRegisterInfo *TRI;
50  ARMFunctionInfo *AFI;
51 
52  Thumb2ITBlock() : MachineFunctionPass(ID) {}
53 
54  bool runOnMachineFunction(MachineFunction &Fn) override;
55 
56  MachineFunctionProperties getRequiredProperties() const override {
59  }
60 
61  StringRef getPassName() const override {
62  return PASS_NAME;
63  }
64 
65  private:
66  bool MoveCopyOutOfITBlock(MachineInstr *MI,
68  RegisterSet &Defs, RegisterSet &Uses);
69  bool InsertITInstructions(MachineBasicBlock &Block);
70  };
71 
72  char Thumb2ITBlock::ID = 0;
73 
74 } // end anonymous namespace
75 
76 INITIALIZE_PASS(Thumb2ITBlock, DEBUG_TYPE, PASS_NAME, false, false)
77 
78 /// TrackDefUses - Tracking what registers are being defined and used by
79 /// instructions in the IT block. This also tracks "dependencies", i.e. uses
80 /// in the IT block that are defined before the IT instruction.
81 static void TrackDefUses(MachineInstr *MI, RegisterSet &Defs, RegisterSet &Uses,
83  using RegList = SmallVector<unsigned, 4>;
84  RegList LocalDefs;
85  RegList LocalUses;
86 
87  for (auto &MO : MI->operands()) {
88  if (!MO.isReg())
89  continue;
90  Register Reg = MO.getReg();
91  if (!Reg || Reg == ARM::ITSTATE || Reg == ARM::SP)
92  continue;
93  if (MO.isUse())
94  LocalUses.push_back(Reg);
95  else
96  LocalDefs.push_back(Reg);
97  }
98 
99  auto InsertUsesDefs = [&](RegList &Regs, RegisterSet &UsesDefs) {
100  for (unsigned Reg : Regs)
101  for (MCSubRegIterator Subreg(Reg, TRI, /*IncludeSelf=*/true);
102  Subreg.isValid(); ++Subreg)
103  UsesDefs.insert(*Subreg);
104  };
105 
106  InsertUsesDefs(LocalDefs, Defs);
107  InsertUsesDefs(LocalUses, Uses);
108 }
109 
110 /// Clear kill flags for any uses in the given set. This will likely
111 /// conservatively remove more kill flags than are necessary, but removing them
112 /// is safer than incorrect kill flags remaining on instructions.
114  for (MachineOperand &MO : MI->operands()) {
115  if (!MO.isReg() || MO.isDef() || !MO.isKill())
116  continue;
117  if (!Uses.count(MO.getReg()))
118  continue;
119  MO.setIsKill(false);
120  }
121 }
122 
123 static bool isCopy(MachineInstr *MI) {
124  switch (MI->getOpcode()) {
125  default:
126  return false;
127  case ARM::MOVr:
128  case ARM::MOVr_TC:
129  case ARM::tMOVr:
130  case ARM::t2MOVr:
131  return true;
132  }
133 }
134 
135 bool
136 Thumb2ITBlock::MoveCopyOutOfITBlock(MachineInstr *MI,
138  RegisterSet &Defs, RegisterSet &Uses) {
139  if (!isCopy(MI))
140  return false;
141  // llvm models select's as two-address instructions. That means a copy
142  // is inserted before a t2MOVccr, etc. If the copy is scheduled in
143  // between selects we would end up creating multiple IT blocks.
144  assert(MI->getOperand(0).getSubReg() == 0 &&
145  MI->getOperand(1).getSubReg() == 0 &&
146  "Sub-register indices still around?");
147 
148  Register DstReg = MI->getOperand(0).getReg();
149  Register SrcReg = MI->getOperand(1).getReg();
150 
151  // First check if it's safe to move it.
152  if (Uses.count(DstReg) || Defs.count(SrcReg))
153  return false;
154 
155  // If the CPSR is defined by this copy, then we don't want to move it. E.g.,
156  // if we have:
157  //
158  // movs r1, r1
159  // rsb r1, 0
160  // movs r2, r2
161  // rsb r2, 0
162  //
163  // we don't want this to be converted to:
164  //
165  // movs r1, r1
166  // movs r2, r2
167  // itt mi
168  // rsb r1, 0
169  // rsb r2, 0
170  //
171  const MCInstrDesc &MCID = MI->getDesc();
172  if (MI->hasOptionalDef() &&
173  MI->getOperand(MCID.getNumOperands() - 1).getReg() == ARM::CPSR)
174  return false;
175 
176  // Then peek at the next instruction to see if it's predicated on CC or OCC.
177  // If not, then there is nothing to be gained by moving the copy.
179  ++I;
181 
182  while (I != E && I->isDebugInstr())
183  ++I;
184 
185  if (I != E) {
186  unsigned NPredReg = 0;
187  ARMCC::CondCodes NCC = getITInstrPredicate(*I, NPredReg);
188  if (NCC == CC || NCC == OCC)
189  return true;
190  }
191  return false;
192 }
193 
194 bool Thumb2ITBlock::InsertITInstructions(MachineBasicBlock &MBB) {
195  bool Modified = false;
196  RegisterSet Defs, Uses;
197  MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
198 
199  while (MBBI != E) {
200  MachineInstr *MI = &*MBBI;
201  DebugLoc dl = MI->getDebugLoc();
202  unsigned PredReg = 0;
203  ARMCC::CondCodes CC = getITInstrPredicate(*MI, PredReg);
204  if (CC == ARMCC::AL) {
205  ++MBBI;
206  continue;
207  }
208 
209  Defs.clear();
210  Uses.clear();
211  TrackDefUses(MI, Defs, Uses, TRI);
212 
213  // Insert an IT instruction.
214  MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII->get(ARM::t2IT))
215  .addImm(CC);
216 
217  // Add implicit use of ITSTATE to IT block instructions.
218  MI->addOperand(MachineOperand::CreateReg(ARM::ITSTATE, false/*ifDef*/,
219  true/*isImp*/, false/*isKill*/));
220 
221  MachineInstr *LastITMI = MI;
222  MachineBasicBlock::iterator InsertPos = MIB.getInstr();
223  ++MBBI;
224 
225  // Form IT block.
227  unsigned Mask = 0, Pos = 3;
228 
229  // v8 IT blocks are limited to one conditional op unless -arm-no-restrict-it
230  // is set: skip the loop
231  if (!restrictIT) {
232  // Branches, including tricky ones like LDM_RET, need to end an IT
233  // block so check the instruction we just put in the block.
234  for (; MBBI != E && Pos &&
235  (!MI->isBranch() && !MI->isReturn()) ; ++MBBI) {
236  if (MBBI->isDebugInstr())
237  continue;
238 
239  MachineInstr *NMI = &*MBBI;
240  MI = NMI;
241 
242  unsigned NPredReg = 0;
243  ARMCC::CondCodes NCC = getITInstrPredicate(*NMI, NPredReg);
244  if (NCC == CC || NCC == OCC) {
245  Mask |= ((NCC ^ CC) & 1) << Pos;
246  // Add implicit use of ITSTATE.
247  NMI->addOperand(MachineOperand::CreateReg(ARM::ITSTATE, false/*ifDef*/,
248  true/*isImp*/, false/*isKill*/));
249  LastITMI = NMI;
250  } else {
251  if (NCC == ARMCC::AL &&
252  MoveCopyOutOfITBlock(NMI, CC, OCC, Defs, Uses)) {
253  --MBBI;
254  MBB.remove(NMI);
255  MBB.insert(InsertPos, NMI);
256  ClearKillFlags(MI, Uses);
257  ++NumMovedInsts;
258  continue;
259  }
260  break;
261  }
262  TrackDefUses(NMI, Defs, Uses, TRI);
263  --Pos;
264  }
265  }
266 
267  // Finalize IT mask.
268  Mask |= (1 << Pos);
269  MIB.addImm(Mask);
270 
271  // Last instruction in IT block kills ITSTATE.
272  LastITMI->findRegisterUseOperand(ARM::ITSTATE)->setIsKill();
273 
274  // Finalize the bundle.
275  finalizeBundle(MBB, InsertPos.getInstrIterator(),
276  ++LastITMI->getIterator());
277 
278  Modified = true;
279  ++NumITs;
280  }
281 
282  return Modified;
283 }
284 
285 bool Thumb2ITBlock::runOnMachineFunction(MachineFunction &Fn) {
286  const ARMSubtarget &STI =
287  static_cast<const ARMSubtarget &>(Fn.getSubtarget());
288  if (!STI.isThumb2())
289  return false;
290  AFI = Fn.getInfo<ARMFunctionInfo>();
291  TII = static_cast<const Thumb2InstrInfo *>(STI.getInstrInfo());
292  TRI = STI.getRegisterInfo();
293  restrictIT = STI.restrictIT();
294 
295  if (!AFI->isThumbFunction())
296  return false;
297 
298  bool Modified = false;
299  for (auto &MBB : Fn )
300  Modified |= InsertITInstructions(MBB);
301 
302  if (Modified)
303  AFI->setHasITBlocks(true);
304 
305  return Modified;
306 }
307 
308 /// createThumb2ITBlockPass - Returns an instance of the Thumb2 IT blocks
309 /// insertion pass.
310 FunctionPass *llvm::createThumb2ITBlockPass() { return new Thumb2ITBlock(); }
MachineOperand * findRegisterUseOperand(Register Reg, bool isKill=false, const TargetRegisterInfo *TRI=nullptr)
Wrapper for findRegisterUseOperandIdx, it returns a pointer to the MachineOperand rather than an inde...
static bool isCopy(MachineInstr *MI)
This class represents lattice values for constants.
Definition: AllocatorList.h:23
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:385
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:178
unsigned Reg
unsigned getSubReg() const
STATISTIC(NumFunctions, "Total number of functions")
unsigned const TargetRegisterInfo * TRI
A debug info location.
Definition: DebugLoc.h:33
iterator_range< mop_iterator > operands()
Definition: MachineInstr.h:477
#define PASS_NAME
const ARMBaseInstrInfo * getInstrInfo() const override
Definition: ARMSubtarget.h:525
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
Definition: MCInstrDesc.h:225
const HexagonInstrInfo * TII
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:411
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:408
SmallSet< unsigned, 4 > RegisterSet
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
bool isBranch(QueryType Type=AnyInBundle) const
Returns true if this is a conditional, unconditional, or indirect branch.
Definition: MachineInstr.h:675
bool isReturn(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:641
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
bool restrictIT() const
Definition: ARMSubtarget.h:789
static void ClearKillFlags(MachineInstr *MI, RegisterSet &Uses)
Clear kill flags for any uses in the given set.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
Definition: SmallSet.h:134
static void TrackDefUses(MachineInstr *MI, RegisterSet &Defs, RegisterSet &Uses, const TargetRegisterInfo *TRI)
TrackDefUses - Tracking what registers are being defined and used by instructions in the IT block...
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:284
self_iterator getIterator()
Definition: ilist_node.h:81
static MachineOperand CreateReg(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
MCSubRegIterator enumerates all sub-registers of Reg.
void setIsKill(bool Val=true)
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:33
#define DEBUG_TYPE
void addOperand(MachineFunction &MF, const MachineOperand &Op)
Add the specified operand to the instruction.
ARMCC::CondCodes getITInstrPredicate(const MachineInstr &MI, unsigned &PredReg)
getITInstrPredicate - Valid only in Thumb2 mode.
MachineOperand class - Representation of each machine instruction operand.
MachineInstr * getInstr() const
If conversion operators fail, use this method to get the MachineInstr explicitly. ...
MachineInstr * remove(MachineInstr *I)
Remove the unbundled instruction from the instruction list without deleting it.
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:256
MachineFunctionProperties & set(Property P)
bool isThumb2() const
Definition: ARMSubtarget.h:756
Representation of each machine instruction.
Definition: MachineInstr.h:64
static CondCodes getOppositeCondition(CondCodes CC)
Definition: ARMBaseInfo.h:48
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
ARMFunctionInfo - This class is derived from MachineFunctionInfo and contains private ARM-specific in...
#define I(x, y, z)
Definition: MD5.cpp:58
const ARMBaseRegisterInfo * getRegisterInfo() const override
Definition: ARMSubtarget.h:537
bool hasOptionalDef(QueryType Type=IgnoreBundle) const
Set if this instruction has an optional definition, e.g.
Definition: MachineInstr.h:631
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
aarch64 promote const
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:80
IRTranslator LLVM IR MI
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
FunctionPass * createThumb2ITBlockPass()
createThumb2ITBlockPass - Returns an instance of the Thumb2 IT blocks insertion pass.
Register getReg() const
getReg - Returns the register number.
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:416
void finalizeBundle(MachineBasicBlock &MBB, MachineBasicBlock::instr_iterator FirstMI, MachineBasicBlock::instr_iterator LastMI)
finalizeBundle - Finalize a machine instruction bundle which includes a sequence of instructions star...
Properties which a MachineFunction may have at a given point in time.
Wrapper class representing virtual and physical registers.
Definition: Register.h:19