14#ifndef LLVM_TARGETPARSER_ARMTARGETPARSER_H
15#define LLVM_TARGETPARSER_ARMTARGETPARSER_H
81#define ARM_ARCH_EXT_NAME(NAME, ID, FEATURE, NEGFEATURE) \
82 {NAME, ID, FEATURE, NEGFEATURE},
83#include "ARMTargetParser.def"
92#define ARM_HW_DIV_NAME(NAME, ID) {NAME, ID},
93#include "ARMTargetParser.def"
98#define ARM_ARCH(NAME, ID, CPU_ATTR, ARCH_FEATURE, ARCH_ATTR, ARCH_FPU, \
101#include "ARMTargetParser.def"
116#define ARM_CPU_NAME(NAME, ID, DEFAULT_FPU, IS_DEFAULT, DEFAULT_EXT) \
117 {NAME, ARM::ArchKind::ID, IS_DEFAULT, DEFAULT_EXT},
118#include "ARMTargetParser.def"
123#define ARM_FPU(NAME, KIND, VERSION, NEON_SUPPORT, RESTRICTION) KIND,
124#include "ARMTargetParser.def"
169#define ARM_FPU(NAME, KIND, VERSION, NEON_SUPPORT, RESTRICTION) \
170 {NAME, KIND, VERSION, NEON_SUPPORT, RESTRICTION},
171#include "llvm/TargetParser/ARMTargetParser.def"
195#define ARM_ARCH(NAME, ID, CPU_ATTR, ARCH_FEATURE, ARCH_ATTR, ARCH_FPU, \
197 {NAME, CPU_ATTR, ARCH_FEATURE, ARCH_FPU, \
198 ARCH_BASE_EXT, ArchKind::ID, ARCH_ATTR},
199#include "llvm/TargetParser/ARMTargetParser.def"
203 assert((Kind >= ArchKind::ARMV8A && Kind <= ArchKind::ARMV9_3A) &&
204 "We only expect operator-- to be called with ARMV8/V9");
205 if (Kind == ArchKind::INVALID || Kind == ArchKind::ARMV8A ||
206 Kind == ArchKind::ARMV8_1A || Kind == ArchKind::ARMV9A ||
207 Kind == ArchKind::ARMV8R)
208 Kind = ArchKind::INVALID;
210 unsigned KindAsInteger =
static_cast<unsigned>(Kind);
211 Kind =
static_cast<ArchKind>(--KindAsInteger);
225 std::vector<StringRef> &Features);
234 std::vector<StringRef> &Features,
This file defines the StringMap class.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
cl::list< SPIRV::Extension::Extension > Extensions("spirv-extensions", cl::desc("SPIR-V extensions"), cl::ZeroOrMore, cl::Hidden, cl::values(clEnumValN(SPIRV::Extension::SPV_INTEL_arbitrary_precision_integers, "SPV_INTEL_arbitrary_precision_integers", "Allows generating arbitrary width integer types"), clEnumValN(SPIRV::Extension::SPV_INTEL_optnone, "SPV_INTEL_optnone", "Adds OptNoneINTEL value for Function Control mask that " "indicates a request to not optimize the function"), clEnumValN(SPIRV::Extension::SPV_KHR_no_integer_wrap_decoration, "SPV_KHR_no_integer_wrap_decoration", "Adds decorations to indicate that a given instruction does " "not cause integer wrapping"), clEnumValN(SPIRV::Extension::SPV_KHR_bit_instructions, "SPV_KHR_bit_instructions", "This enables bit instructions to be used by SPIR-V modules " "without requiring the Shader capability")))
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
StringRef - Represent a constant reference to a string, i.e.
constexpr StringRef substr(size_t Start, size_t N=npos) const
Return a reference to the substring from [Start, Start + N).
Triple - Helper class for working with autoconf configuration names.
StringRef getArchExtName(uint64_t ArchExtKind)
StringRef getFPUSynonym(StringRef FPU)
bool getFPUFeatures(FPUKind FPUKind, std::vector< StringRef > &Features)
StringRef getCanonicalArchName(StringRef Arch)
MArch is expected to be of the form (arm|thumb)?(eb)?(v.
uint64_t parseHWDiv(StringRef HWDiv)
StringRef getCPUAttr(ArchKind AK)
StringRef getArchName(ArchKind AK)
StringRef computeDefaultTargetABI(const Triple &TT, StringRef CPU)
void fillValidCPUArchList(SmallVectorImpl< StringRef > &Values)
static const FPUName FPUNames[]
uint64_t parseArchExt(StringRef ArchExt)
ArchKind convertV9toV8(ArchKind AK)
@ Crypto
Neon with Crypto.
ArchKind parseArch(StringRef Arch)
FPURestriction getFPURestriction(FPUKind FPUKind)
bool appendArchExtFeatures(StringRef CPU, ARM::ArchKind AK, StringRef ArchExt, std::vector< StringRef > &Features, FPUKind &ArgFPUKind)
const struct llvm::ARM::@411 HWDivNames[]
StringRef getDefaultCPU(StringRef Arch)
StringRef getArchExtFeature(StringRef ArchExt)
const CpuNames CPUNames[]
ProfileKind parseArchProfile(StringRef Arch)
FPUKind parseFPU(StringRef FPU)
StringRef getSubArch(ArchKind AK)
static const ArchNames ARMArchNames[]
StringRef getARMCPUForArch(const llvm::Triple &Triple, StringRef MArch={})
Get the (LLVM) name of the minimum ARM CPU for the arch we are targeting.
unsigned parseArchVersion(StringRef Arch)
const ExtName ARCHExtNames[]
NeonSupportLevel getFPUNeonSupportLevel(FPUKind FPUKind)
ArchKind parseCPUArch(StringRef CPU)
unsigned getArchAttr(ArchKind AK)
StringRef getFPUName(FPUKind FPUKind)
FPUVersion getFPUVersion(FPUKind FPUKind)
ArchKind & operator--(ArchKind &Kind)
bool getHWDivFeatures(uint64_t HWDivKind, std::vector< StringRef > &Features)
@ SP_D16
Only single-precision instructions, with 16 D registers.
@ D16
Only 16 D registers.
uint64_t getDefaultExtensions(StringRef CPU, ArchKind AK)
FPUKind getDefaultFPU(StringRef CPU, ArchKind AK)
bool getExtensionFeatures(uint64_t Extensions, std::vector< StringRef > &Features)
void PrintSupportedExtensions(StringMap< StringRef > DescMap)
This is an optimization pass for GlobalISel generic memory operations.
StringRef getSubArch() const
uint64_t ArchBaseExtensions
ARMBuildAttrs::CPUArch ArchAttr
uint64_t DefaultExtensions
FPURestriction Restriction
NeonSupportLevel NeonSupport