LLVM 19.0.0git
ARMTargetParser.h
Go to the documentation of this file.
1//===-- ARMTargetParser - Parser for ARM target features --------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements a target parser to recognise ARM hardware features
10// such as FPU/CPU/ARCH/extensions and specific support such as HWDIV.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_TARGETPARSER_ARMTARGETPARSER_H
15#define LLVM_TARGETPARSER_ARMTARGETPARSER_H
16
17#include "llvm/ADT/StringMap.h"
18#include "llvm/ADT/StringRef.h"
21#include <vector>
22
23namespace llvm {
24
25class Triple;
26
27namespace ARM {
28
29// Arch extension modifiers for CPUs.
30// Note that this is not the same as the AArch64 list
34 AEK_CRC = 1 << 1,
35 AEK_CRYPTO = 1 << 2,
36 AEK_FP = 1 << 3,
38 AEK_HWDIVARM = 1 << 5,
39 AEK_MP = 1 << 6,
40 AEK_SIMD = 1 << 7,
41 AEK_SEC = 1 << 8,
42 AEK_VIRT = 1 << 9,
43 AEK_DSP = 1 << 10,
44 AEK_FP16 = 1 << 11,
45 AEK_RAS = 1 << 12,
46 AEK_DOTPROD = 1 << 13,
47 AEK_SHA2 = 1 << 14,
48 AEK_AES = 1 << 15,
49 AEK_FP16FML = 1 << 16,
50 AEK_SB = 1 << 17,
51 AEK_FP_DP = 1 << 18,
52 AEK_LOB = 1 << 19,
53 AEK_BF16 = 1 << 20,
54 AEK_I8MM = 1 << 21,
55 AEK_CDECP0 = 1 << 22,
56 AEK_CDECP1 = 1 << 23,
57 AEK_CDECP2 = 1 << 24,
58 AEK_CDECP3 = 1 << 25,
59 AEK_CDECP4 = 1 << 26,
60 AEK_CDECP5 = 1 << 27,
61 AEK_CDECP6 = 1 << 28,
62 AEK_CDECP7 = 1 << 29,
63 AEK_PACBTI = 1 << 30,
64 // Unsupported extensions.
65 AEK_OS = 1ULL << 59,
66 AEK_IWMMXT = 1ULL << 60,
67 AEK_IWMMXT2 = 1ULL << 61,
68 AEK_MAVERICK = 1ULL << 62,
69 AEK_XSCALE = 1ULL << 63,
70};
71
72// List of Arch Extension names.
73struct ExtName {
78};
79
81#define ARM_ARCH_EXT_NAME(NAME, ID, FEATURE, NEGFEATURE) \
82 {NAME, ID, FEATURE, NEGFEATURE},
83#include "ARMTargetParser.def"
84};
85
86// List of HWDiv names (use getHWDivSynonym) and which architectural
87// features they correspond to (use getHWDivFeatures).
88const struct {
91} HWDivNames[] = {
92#define ARM_HW_DIV_NAME(NAME, ID) {NAME, ID},
93#include "ARMTargetParser.def"
94};
95
96// Arch names.
97enum class ArchKind {
98#define ARM_ARCH(NAME, ID, CPU_ATTR, ARCH_FEATURE, ARCH_ATTR, ARCH_FPU, \
99 ARCH_BASE_EXT) \
100 ID,
101#include "ARMTargetParser.def"
102};
103
104// List of CPU names and their arches.
105// The same CPU can have multiple arches and can be default on multiple arches.
106// When finding the Arch for a CPU, first-found prevails. Sort them accordingly.
107// When this becomes table-generated, we'd probably need two tables.
108struct CpuNames {
111 bool Default; // is $Name the default CPU for $ArchID ?
113};
114
116#define ARM_CPU_NAME(NAME, ID, DEFAULT_FPU, IS_DEFAULT, DEFAULT_EXT) \
117 {NAME, ARM::ArchKind::ID, IS_DEFAULT, DEFAULT_EXT},
118#include "ARMTargetParser.def"
119};
120
121// FPU names.
123#define ARM_FPU(NAME, KIND, VERSION, NEON_SUPPORT, RESTRICTION) KIND,
124#include "ARMTargetParser.def"
125 FK_LAST
127
128// FPU Version
129enum class FPUVersion {
130 NONE,
131 VFPV2,
132 VFPV3,
134 VFPV4,
135 VFPV5,
137};
138
139// An FPU name restricts the FPU in one of three ways:
140enum class FPURestriction {
141 None = 0, ///< No restriction
142 D16, ///< Only 16 D registers
143 SP_D16 ///< Only single-precision instructions, with 16 D registers
144};
145
146inline bool isDoublePrecision(const FPURestriction restriction) {
147 return restriction != FPURestriction::SP_D16;
148}
149
150inline bool has32Regs(const FPURestriction restriction) {
151 return restriction == FPURestriction::None;
152}
153
154// An FPU name implies one of three levels of Neon support:
156 None = 0, ///< No Neon
157 Neon, ///< Neon
158 Crypto ///< Neon with Crypto
159};
160
161// v6/v7/v8 Profile
162enum class ProfileKind { INVALID = 0, A, R, M };
163
164// List of canonical FPU names (use getFPUSynonym) and which architectural
165// features they correspond to (use getFPUFeatures).
166// The entries must appear in the order listed in ARM::FPUKind for correct
167// indexing
168struct FPUName {
174};
175
176static const FPUName FPUNames[] = {
177#define ARM_FPU(NAME, KIND, VERSION, NEON_SUPPORT, RESTRICTION) \
178 {NAME, KIND, VERSION, NEON_SUPPORT, RESTRICTION},
179#include "llvm/TargetParser/ARMTargetParser.def"
180};
181
182// List of canonical arch names (use getArchSynonym).
183// This table also provides the build attribute fields for CPU arch
184// and Arch ID, according to the Addenda to the ARM ABI, chapters
185// 2.4 and 2.3.5.2 respectively.
186// FIXME: SubArch values were simplified to fit into the expectations
187// of the triples and are not conforming with their official names.
188// Check to see if the expectation should be changed.
189struct ArchNames {
191 StringRef CPUAttr; // CPU class in build attributes.
196 ARMBuildAttrs::CPUArch ArchAttr; // Arch ID in build attributes.
197
198 // Return ArchFeature without the leading "+".
199 StringRef getSubArch() const { return ArchFeature.substr(1); }
200};
201
202static const ArchNames ARMArchNames[] = {
203#define ARM_ARCH(NAME, ID, CPU_ATTR, ARCH_FEATURE, ARCH_ATTR, ARCH_FPU, \
204 ARCH_BASE_EXT) \
205 {NAME, CPU_ATTR, ARCH_FEATURE, ARCH_FPU, \
206 ARCH_BASE_EXT, ArchKind::ID, ARCH_ATTR},
207#include "llvm/TargetParser/ARMTargetParser.def"
208};
209
211 assert((Kind >= ArchKind::ARMV8A && Kind <= ArchKind::ARMV9_3A) &&
212 "We only expect operator-- to be called with ARMV8/V9");
213 if (Kind == ArchKind::INVALID || Kind == ArchKind::ARMV8A ||
214 Kind == ArchKind::ARMV8_1A || Kind == ArchKind::ARMV9A ||
215 Kind == ArchKind::ARMV8R)
216 Kind = ArchKind::INVALID;
217 else {
218 unsigned KindAsInteger = static_cast<unsigned>(Kind);
219 Kind = static_cast<ArchKind>(--KindAsInteger);
220 }
221 return Kind;
222}
223
224// Information by ID
229
230bool getFPUFeatures(FPUKind FPUKind, std::vector<StringRef> &Features);
231bool getHWDivFeatures(uint64_t HWDivKind, std::vector<StringRef> &Features);
233 std::vector<StringRef> &Features);
234
236unsigned getArchAttr(ArchKind AK);
242 std::vector<StringRef> &Features,
243 FPUKind &ArgFPUKind);
245
246// Information by Name
252
253// Parser
260unsigned parseArchVersion(StringRef Arch);
261
264
265/// Get the (LLVM) name of the minimum ARM CPU for the arch we are targeting.
266///
267/// \param Arch the architecture name (e.g., "armv7s"). If it is an empty
268/// string then the triple's arch name is used.
270
271void PrintSupportedExtensions(StringMap<StringRef> DescMap);
272
273} // namespace ARM
274} // namespace llvm
275
276#endif
This file defines the StringMap class.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static cl::opt< std::set< SPIRV::Extension::Extension >, false, SPIRVExtensionsParser > Extensions("spirv-ext", cl::desc("Specify list of enabled SPIR-V extensions"))
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:586
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
constexpr StringRef substr(size_t Start, size_t N=npos) const
Return a reference to the substring from [Start, Start + N).
Definition: StringRef.h:556
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
StringRef getArchExtName(uint64_t ArchExtKind)
StringRef getFPUSynonym(StringRef FPU)
bool getFPUFeatures(FPUKind FPUKind, std::vector< StringRef > &Features)
StringRef getCanonicalArchName(StringRef Arch)
MArch is expected to be of the form (arm|thumb)?(eb)?(v.
uint64_t parseHWDiv(StringRef HWDiv)
StringRef getCPUAttr(ArchKind AK)
StringRef getArchName(ArchKind AK)
StringRef computeDefaultTargetABI(const Triple &TT, StringRef CPU)
void fillValidCPUArchList(SmallVectorImpl< StringRef > &Values)
static const FPUName FPUNames[]
uint64_t parseArchExt(StringRef ArchExt)
ArchKind convertV9toV8(ArchKind AK)
@ Crypto
Neon with Crypto.
ArchKind parseArch(StringRef Arch)
FPURestriction getFPURestriction(FPUKind FPUKind)
bool appendArchExtFeatures(StringRef CPU, ARM::ArchKind AK, StringRef ArchExt, std::vector< StringRef > &Features, FPUKind &ArgFPUKind)
StringRef getDefaultCPU(StringRef Arch)
StringRef getArchExtFeature(StringRef ArchExt)
const CpuNames CPUNames[]
ProfileKind parseArchProfile(StringRef Arch)
FPUKind parseFPU(StringRef FPU)
StringRef getSubArch(ArchKind AK)
const struct llvm::ARM::@423 HWDivNames[]
static const ArchNames ARMArchNames[]
uint64_t ID
StringRef getARMCPUForArch(const llvm::Triple &Triple, StringRef MArch={})
Get the (LLVM) name of the minimum ARM CPU for the arch we are targeting.
unsigned parseArchVersion(StringRef Arch)
const ExtName ARCHExtNames[]
bool has32Regs(const FPURestriction restriction)
NeonSupportLevel getFPUNeonSupportLevel(FPUKind FPUKind)
ArchKind parseCPUArch(StringRef CPU)
bool isDoublePrecision(const FPURestriction restriction)
StringRef Name
unsigned getArchAttr(ArchKind AK)
StringRef getFPUName(FPUKind FPUKind)
FPUVersion getFPUVersion(FPUKind FPUKind)
ArchKind & operator--(ArchKind &Kind)
bool getHWDivFeatures(uint64_t HWDivKind, std::vector< StringRef > &Features)
@ SP_D16
Only single-precision instructions, with 16 D registers.
@ None
No restriction.
@ D16
Only 16 D registers.
uint64_t getDefaultExtensions(StringRef CPU, ArchKind AK)
FPUKind getDefaultFPU(StringRef CPU, ArchKind AK)
bool getExtensionFeatures(uint64_t Extensions, std::vector< StringRef > &Features)
void PrintSupportedExtensions(StringMap< StringRef > DescMap)
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
StringRef getSubArch() const
ARMBuildAttrs::CPUArch ArchAttr
FPURestriction Restriction
NeonSupportLevel NeonSupport