LLVM 19.0.0git
ARMTargetParser.cpp
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1//===-- ARMTargetParser - Parser for ARM target features --------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements a target parser to recognise ARM hardware features
10// such as FPU/CPU/ARCH/extensions and specific support such as HWDIV.
11//
12//===----------------------------------------------------------------------===//
13
16#include "llvm/Support/Format.h"
20#include <cctype>
21
22using namespace llvm;
23
25 return StringSwitch<StringRef>(HWDiv)
26 .Case("thumb,arm", "arm,thumb")
27 .Default(HWDiv);
28}
29
30// Allows partial match, ex. "v7a" matches "armv7a".
32 Arch = getCanonicalArchName(Arch);
33 StringRef Syn = getArchSynonym(Arch);
34 for (const auto &A : ARMArchNames) {
35 if (A.Name.ends_with(Syn))
36 return A.ID;
37 }
38 return ArchKind::INVALID;
39}
40
41// Version number (ex. v7 = 7).
43 Arch = getCanonicalArchName(Arch);
44 switch (parseArch(Arch)) {
45 case ArchKind::ARMV4:
46 case ArchKind::ARMV4T:
47 return 4;
48 case ArchKind::ARMV5T:
49 case ArchKind::ARMV5TE:
50 case ArchKind::IWMMXT:
51 case ArchKind::IWMMXT2:
52 case ArchKind::XSCALE:
53 case ArchKind::ARMV5TEJ:
54 return 5;
55 case ArchKind::ARMV6:
56 case ArchKind::ARMV6K:
57 case ArchKind::ARMV6T2:
58 case ArchKind::ARMV6KZ:
59 case ArchKind::ARMV6M:
60 return 6;
61 case ArchKind::ARMV7A:
62 case ArchKind::ARMV7VE:
63 case ArchKind::ARMV7R:
64 case ArchKind::ARMV7M:
65 case ArchKind::ARMV7S:
66 case ArchKind::ARMV7EM:
67 case ArchKind::ARMV7K:
68 return 7;
69 case ArchKind::ARMV8A:
70 case ArchKind::ARMV8_1A:
71 case ArchKind::ARMV8_2A:
72 case ArchKind::ARMV8_3A:
73 case ArchKind::ARMV8_4A:
74 case ArchKind::ARMV8_5A:
75 case ArchKind::ARMV8_6A:
76 case ArchKind::ARMV8_7A:
77 case ArchKind::ARMV8_8A:
78 case ArchKind::ARMV8_9A:
79 case ArchKind::ARMV8R:
80 case ArchKind::ARMV8MBaseline:
81 case ArchKind::ARMV8MMainline:
82 case ArchKind::ARMV8_1MMainline:
83 return 8;
84 case ArchKind::ARMV9A:
85 case ArchKind::ARMV9_1A:
86 case ArchKind::ARMV9_2A:
87 case ArchKind::ARMV9_3A:
88 case ArchKind::ARMV9_4A:
89 case ArchKind::ARMV9_5A:
90 return 9;
91 case ArchKind::INVALID:
92 return 0;
93 }
94 llvm_unreachable("Unhandled architecture");
95}
96
98 switch (AK) {
99 case ARM::ArchKind::ARMV6M:
100 case ARM::ArchKind::ARMV7M:
101 case ARM::ArchKind::ARMV7EM:
102 case ARM::ArchKind::ARMV8MMainline:
103 case ARM::ArchKind::ARMV8MBaseline:
104 case ARM::ArchKind::ARMV8_1MMainline:
105 return ARM::ProfileKind::M;
106 case ARM::ArchKind::ARMV7R:
107 case ARM::ArchKind::ARMV8R:
108 return ARM::ProfileKind::R;
109 case ARM::ArchKind::ARMV7A:
110 case ARM::ArchKind::ARMV7VE:
111 case ARM::ArchKind::ARMV7K:
112 case ARM::ArchKind::ARMV8A:
113 case ARM::ArchKind::ARMV8_1A:
114 case ARM::ArchKind::ARMV8_2A:
115 case ARM::ArchKind::ARMV8_3A:
116 case ARM::ArchKind::ARMV8_4A:
117 case ARM::ArchKind::ARMV8_5A:
118 case ARM::ArchKind::ARMV8_6A:
119 case ARM::ArchKind::ARMV8_7A:
120 case ARM::ArchKind::ARMV8_8A:
121 case ARM::ArchKind::ARMV8_9A:
122 case ARM::ArchKind::ARMV9A:
123 case ARM::ArchKind::ARMV9_1A:
124 case ARM::ArchKind::ARMV9_2A:
125 case ARM::ArchKind::ARMV9_3A:
126 case ARM::ArchKind::ARMV9_4A:
127 case ARM::ArchKind::ARMV9_5A:
128 return ARM::ProfileKind::A;
129 case ARM::ArchKind::ARMV4:
130 case ARM::ArchKind::ARMV4T:
131 case ARM::ArchKind::ARMV5T:
132 case ARM::ArchKind::ARMV5TE:
133 case ARM::ArchKind::ARMV5TEJ:
134 case ARM::ArchKind::ARMV6:
135 case ARM::ArchKind::ARMV6K:
136 case ARM::ArchKind::ARMV6T2:
137 case ARM::ArchKind::ARMV6KZ:
138 case ARM::ArchKind::ARMV7S:
139 case ARM::ArchKind::IWMMXT:
140 case ARM::ArchKind::IWMMXT2:
141 case ARM::ArchKind::XSCALE:
142 case ARM::ArchKind::INVALID:
143 return ARM::ProfileKind::INVALID;
144 }
145 llvm_unreachable("Unhandled architecture");
146}
147
148// Profile A/R/M
150 Arch = getCanonicalArchName(Arch);
151 return getProfileKind(parseArch(Arch));
152}
153
155 std::vector<StringRef> &Features) {
156
157 if (FPUKind >= FK_LAST || FPUKind == FK_INVALID)
158 return false;
159
160 static const struct FPUFeatureNameInfo {
161 const char *PlusName, *MinusName;
162 FPUVersion MinVersion;
163 FPURestriction MaxRestriction;
164 } FPUFeatureInfoList[] = {
165 // We have to specify the + and - versions of the name in full so
166 // that we can return them as static StringRefs.
167 //
168 // Also, the SubtargetFeatures ending in just "sp" are listed here
169 // under FPURestriction::None, which is the only FPURestriction in
170 // which they would be valid (since FPURestriction::SP doesn't
171 // exist).
172 {"+vfp2", "-vfp2", FPUVersion::VFPV2, FPURestriction::D16},
173 {"+vfp2sp", "-vfp2sp", FPUVersion::VFPV2, FPURestriction::SP_D16},
174 {"+vfp3", "-vfp3", FPUVersion::VFPV3, FPURestriction::None},
175 {"+vfp3d16", "-vfp3d16", FPUVersion::VFPV3, FPURestriction::D16},
176 {"+vfp3d16sp", "-vfp3d16sp", FPUVersion::VFPV3, FPURestriction::SP_D16},
177 {"+vfp3sp", "-vfp3sp", FPUVersion::VFPV3, FPURestriction::None},
178 {"+fp16", "-fp16", FPUVersion::VFPV3_FP16, FPURestriction::SP_D16},
179 {"+vfp4", "-vfp4", FPUVersion::VFPV4, FPURestriction::None},
180 {"+vfp4d16", "-vfp4d16", FPUVersion::VFPV4, FPURestriction::D16},
181 {"+vfp4d16sp", "-vfp4d16sp", FPUVersion::VFPV4, FPURestriction::SP_D16},
182 {"+vfp4sp", "-vfp4sp", FPUVersion::VFPV4, FPURestriction::None},
183 {"+fp-armv8", "-fp-armv8", FPUVersion::VFPV5, FPURestriction::None},
184 {"+fp-armv8d16", "-fp-armv8d16", FPUVersion::VFPV5, FPURestriction::D16},
185 {"+fp-armv8d16sp", "-fp-armv8d16sp", FPUVersion::VFPV5, FPURestriction::SP_D16},
186 {"+fp-armv8sp", "-fp-armv8sp", FPUVersion::VFPV5, FPURestriction::None},
187 {"+fullfp16", "-fullfp16", FPUVersion::VFPV5_FULLFP16, FPURestriction::SP_D16},
188 {"+fp64", "-fp64", FPUVersion::VFPV2, FPURestriction::D16},
189 {"+d32", "-d32", FPUVersion::VFPV3, FPURestriction::None},
190 };
191
192 for (const auto &Info: FPUFeatureInfoList) {
193 if (FPUNames[FPUKind].FPUVer >= Info.MinVersion &&
194 FPUNames[FPUKind].Restriction <= Info.MaxRestriction)
195 Features.push_back(Info.PlusName);
196 else
197 Features.push_back(Info.MinusName);
198 }
199
200 static const struct NeonFeatureNameInfo {
201 const char *PlusName, *MinusName;
202 NeonSupportLevel MinSupportLevel;
203 } NeonFeatureInfoList[] = {
204 {"+neon", "-neon", NeonSupportLevel::Neon},
205 {"+sha2", "-sha2", NeonSupportLevel::Crypto},
206 {"+aes", "-aes", NeonSupportLevel::Crypto},
207 };
208
209 for (const auto &Info: NeonFeatureInfoList) {
210 if (FPUNames[FPUKind].NeonSupport >= Info.MinSupportLevel)
211 Features.push_back(Info.PlusName);
212 else
213 Features.push_back(Info.MinusName);
214 }
215
216 return true;
217}
218
220 StringRef Syn = getFPUSynonym(FPU);
221 for (const auto &F : FPUNames) {
222 if (Syn == F.Name)
223 return F.ID;
224 }
225 return FK_INVALID;
226}
227
229 if (FPUKind >= FK_LAST)
230 return NeonSupportLevel::None;
231 return FPUNames[FPUKind].NeonSupport;
232}
233
235 return StringSwitch<StringRef>(FPU)
236 .Cases("fpa", "fpe2", "fpe3", "maverick", "invalid") // Unsupported
237 .Case("vfp2", "vfpv2")
238 .Case("vfp3", "vfpv3")
239 .Case("vfp4", "vfpv4")
240 .Case("vfp3-d16", "vfpv3-d16")
241 .Case("vfp4-d16", "vfpv4-d16")
242 .Cases("fp4-sp-d16", "vfpv4-sp-d16", "fpv4-sp-d16")
243 .Cases("fp4-dp-d16", "fpv4-dp-d16", "vfpv4-d16")
244 .Case("fp5-sp-d16", "fpv5-sp-d16")
245 .Cases("fp5-dp-d16", "fpv5-dp-d16", "fpv5-d16")
246 // FIXME: Clang uses it, but it's bogus, since neon defaults to vfpv3.
247 .Case("neon-vfpv3", "neon")
248 .Default(FPU);
249}
250
252 if (FPUKind >= FK_LAST)
253 return StringRef();
254 return FPUNames[FPUKind].Name;
255}
256
258 if (FPUKind >= FK_LAST)
259 return FPUVersion::NONE;
260 return FPUNames[FPUKind].FPUVer;
261}
262
264 if (FPUKind >= FK_LAST)
265 return FPURestriction::None;
266 return FPUNames[FPUKind].Restriction;
267}
268
270 if (CPU == "generic")
271 return ARM::ARMArchNames[static_cast<unsigned>(AK)].DefaultFPU;
272
274#define ARM_CPU_NAME(NAME, ID, DEFAULT_FPU, IS_DEFAULT, DEFAULT_EXT) \
275 .Case(NAME, DEFAULT_FPU)
276#include "llvm/TargetParser/ARMTargetParser.def"
277 .Default(ARM::FK_INVALID);
278}
279
281 if (CPU == "generic")
282 return ARM::ARMArchNames[static_cast<unsigned>(AK)].ArchBaseExtensions;
283
284 return StringSwitch<uint64_t>(CPU)
285#define ARM_CPU_NAME(NAME, ID, DEFAULT_FPU, IS_DEFAULT, DEFAULT_EXT) \
286 .Case(NAME, \
287 ARMArchNames[static_cast<unsigned>(ArchKind::ID)].ArchBaseExtensions | \
288 DEFAULT_EXT)
289#include "llvm/TargetParser/ARMTargetParser.def"
291}
292
294 std::vector<StringRef> &Features) {
295
296 if (HWDivKind == AEK_INVALID)
297 return false;
298
299 if (HWDivKind & AEK_HWDIVARM)
300 Features.push_back("+hwdiv-arm");
301 else
302 Features.push_back("-hwdiv-arm");
303
304 if (HWDivKind & AEK_HWDIVTHUMB)
305 Features.push_back("+hwdiv");
306 else
307 Features.push_back("-hwdiv");
308
309 return true;
310}
311
313 std::vector<StringRef> &Features) {
314
315 if (Extensions == AEK_INVALID)
316 return false;
317
318 for (const auto &AE : ARCHExtNames) {
319 if ((Extensions & AE.ID) == AE.ID && !AE.Feature.empty())
320 Features.push_back(AE.Feature);
321 else if (!AE.NegFeature.empty())
322 Features.push_back(AE.NegFeature);
323 }
324
325 return getHWDivFeatures(Extensions, Features);
326}
327
329 return ARMArchNames[static_cast<unsigned>(AK)].Name;
330}
331
333 return ARMArchNames[static_cast<unsigned>(AK)].CPUAttr;
334}
335
337 return ARMArchNames[static_cast<unsigned>(AK)].getSubArch();
338}
339
341 return ARMArchNames[static_cast<unsigned>(AK)].ArchAttr;
342}
343
345 for (const auto &AE : ARCHExtNames) {
346 if (ArchExtKind == AE.ID)
347 return AE.Name;
348 }
349 return StringRef();
350}
351
353 return Name.consume_front("no");
354}
355
357 bool Negated = stripNegationPrefix(ArchExt);
358 for (const auto &AE : ARCHExtNames) {
359 if (!AE.Feature.empty() && ArchExt == AE.Name)
360 return StringRef(Negated ? AE.NegFeature : AE.Feature);
361 }
362
363 return StringRef();
364}
365
367 if (InputFPUKind == ARM::FK_INVALID || InputFPUKind == ARM::FK_NONE)
368 return ARM::FK_INVALID;
369
370 const ARM::FPUName &InputFPU = ARM::FPUNames[InputFPUKind];
371
372 // If the input FPU already supports double-precision, then there
373 // isn't any different FPU we can return here.
375 return InputFPUKind;
376
377 // Otherwise, look for an FPU entry with all the same fields, except
378 // that it supports double precision.
379 for (const ARM::FPUName &CandidateFPU : ARM::FPUNames) {
380 if (CandidateFPU.FPUVer == InputFPU.FPUVer &&
381 CandidateFPU.NeonSupport == InputFPU.NeonSupport &&
382 ARM::has32Regs(CandidateFPU.Restriction) ==
383 ARM::has32Regs(InputFPU.Restriction) &&
384 ARM::isDoublePrecision(CandidateFPU.Restriction)) {
385 return CandidateFPU.ID;
386 }
387 }
388
389 // nothing found
390 return ARM::FK_INVALID;
391}
392
394 if (InputFPUKind == ARM::FK_INVALID || InputFPUKind == ARM::FK_NONE)
395 return ARM::FK_INVALID;
396
397 const ARM::FPUName &InputFPU = ARM::FPUNames[InputFPUKind];
398
399 // If the input FPU already is single-precision only, then there
400 // isn't any different FPU we can return here.
401 if (!ARM::isDoublePrecision(InputFPU.Restriction))
402 return InputFPUKind;
403
404 // Otherwise, look for an FPU entry with all the same fields, except
405 // that it does not support double precision.
406 for (const ARM::FPUName &CandidateFPU : ARM::FPUNames) {
407 if (CandidateFPU.FPUVer == InputFPU.FPUVer &&
408 CandidateFPU.NeonSupport == InputFPU.NeonSupport &&
409 ARM::has32Regs(CandidateFPU.Restriction) ==
410 ARM::has32Regs(InputFPU.Restriction) &&
411 !ARM::isDoublePrecision(CandidateFPU.Restriction)) {
412 return CandidateFPU.ID;
413 }
414 }
415
416 // nothing found
417 return ARM::FK_INVALID;
418}
419
421 StringRef ArchExt,
422 std::vector<StringRef> &Features,
423 ARM::FPUKind &ArgFPUKind) {
424
425 size_t StartingNumFeatures = Features.size();
426 const bool Negated = stripNegationPrefix(ArchExt);
427 uint64_t ID = parseArchExt(ArchExt);
428
429 if (ID == AEK_INVALID)
430 return false;
431
432 for (const auto &AE : ARCHExtNames) {
433 if (Negated) {
434 if ((AE.ID & ID) == ID && !AE.NegFeature.empty())
435 Features.push_back(AE.NegFeature);
436 } else {
437 if ((AE.ID & ID) == AE.ID && !AE.Feature.empty())
438 Features.push_back(AE.Feature);
439 }
440 }
441
442 if (CPU == "")
443 CPU = "generic";
444
445 if (ArchExt == "fp" || ArchExt == "fp.dp") {
446 const ARM::FPUKind DefaultFPU = getDefaultFPU(CPU, AK);
448 if (ArchExt == "fp.dp") {
449 const bool IsDP = ArgFPUKind != ARM::FK_INVALID &&
450 ArgFPUKind != ARM::FK_NONE &&
452 if (Negated) {
453 /* If there is no FPU selected yet, we still need to set ArgFPUKind, as
454 * leaving it as FK_INVALID, would cause default FPU to be selected
455 * later and that could be double precision one. */
456 if (ArgFPUKind != ARM::FK_INVALID && !IsDP)
457 return true;
458 FPUKind = findSinglePrecisionFPU(DefaultFPU);
459 if (FPUKind == ARM::FK_INVALID)
460 FPUKind = ARM::FK_NONE;
461 } else {
462 if (IsDP)
463 return true;
464 FPUKind = findDoublePrecisionFPU(DefaultFPU);
465 if (FPUKind == ARM::FK_INVALID)
466 return false;
467 }
468 } else if (Negated) {
469 FPUKind = ARM::FK_NONE;
470 } else {
471 FPUKind = DefaultFPU;
472 }
473 ArgFPUKind = FPUKind;
474 return true;
475 }
476 return StartingNumFeatures != Features.size();
477}
478
480 if (getProfileKind(AK) != ProfileKind::A)
481 return ARM::ArchKind::INVALID;
482 if (AK < ARM::ArchKind::ARMV9A || AK > ARM::ArchKind::ARMV9_3A)
483 return ARM::ArchKind::INVALID;
484 unsigned AK_v8 = static_cast<unsigned>(ARM::ArchKind::ARMV8_5A);
485 AK_v8 += static_cast<unsigned>(AK) -
486 static_cast<unsigned>(ARM::ArchKind::ARMV9A);
487 return static_cast<ARM::ArchKind>(AK_v8);
488}
489
491 ArchKind AK = parseArch(Arch);
492 if (AK == ArchKind::INVALID)
493 return StringRef();
494
495 // Look for multiple AKs to find the default for pair AK+Name.
496 for (const auto &CPU : CPUNames) {
497 if (CPU.ArchID == AK && CPU.Default)
498 return CPU.Name;
499 }
500
501 // If we can't find a default then target the architecture instead
502 return "generic";
503}
504
506 StringRef Syn = getHWDivSynonym(HWDiv);
507 for (const auto &D : HWDivNames) {
508 if (Syn == D.Name)
509 return D.ID;
510 }
511 return AEK_INVALID;
512}
513
515 for (const auto &A : ARCHExtNames) {
516 if (ArchExt == A.Name)
517 return A.ID;
518 }
519 return AEK_INVALID;
520}
521
523 for (const auto &C : CPUNames) {
524 if (CPU == C.Name)
525 return C.ArchID;
526 }
527 return ArchKind::INVALID;
528}
529
531 for (const auto &Arch : CPUNames) {
532 if (Arch.ArchID != ArchKind::INVALID)
533 Values.push_back(Arch.Name);
534 }
535}
536
538 StringRef ArchName =
539 CPU.empty() ? TT.getArchName() : getArchName(parseCPUArch(CPU));
540
541 if (TT.isOSBinFormatMachO()) {
542 if (TT.getEnvironment() == Triple::EABI ||
543 TT.getOS() == Triple::UnknownOS ||
544 parseArchProfile(ArchName) == ProfileKind::M)
545 return "aapcs";
546 if (TT.isWatchABI())
547 return "aapcs16";
548 return "apcs-gnu";
549 } else if (TT.isOSWindows())
550 // FIXME: this is invalid for WindowsCE.
551 return "aapcs";
552
553 // Select the default based on the platform.
554 switch (TT.getEnvironment()) {
555 case Triple::Android:
556 case Triple::GNUEABI:
558 case Triple::MuslEABI:
560 case Triple::OpenHOS:
561 return "aapcs-linux";
562 case Triple::EABIHF:
563 case Triple::EABI:
564 return "aapcs";
565 default:
566 if (TT.isOSNetBSD())
567 return "apcs-gnu";
568 if (TT.isOSFreeBSD() || TT.isOSOpenBSD() || TT.isOSHaiku() ||
569 TT.isOHOSFamily())
570 return "aapcs-linux";
571 return "aapcs";
572 }
573}
574
576 if (MArch.empty())
577 MArch = Triple.getArchName();
578 MArch = llvm::ARM::getCanonicalArchName(MArch);
579
580 // Some defaults are forced.
581 switch (Triple.getOS()) {
586 if (!MArch.empty() && MArch == "v6")
587 return "arm1176jzf-s";
588 if (!MArch.empty() && MArch == "v7")
589 return "cortex-a8";
590 break;
592 // FIXME: this is invalid for WindowsCE
593 if (llvm::ARM::parseArchVersion(MArch) <= 7)
594 return "cortex-a9";
595 break;
602 if (MArch == "v7k")
603 return "cortex-a7";
604 break;
605 default:
606 break;
607 }
608
609 if (MArch.empty())
610 return StringRef();
611
613 if (!CPU.empty() && !CPU.equals("invalid"))
614 return CPU;
615
616 // If no specific architecture version is requested, return the minimum CPU
617 // required by the OS and environment.
618 switch (Triple.getOS()) {
620 return "arm1176jzf-s";
622 switch (Triple.getEnvironment()) {
627 return "arm926ej-s";
628 default:
629 return "strongarm";
630 }
633 return "cortex-a8";
634 default:
635 switch (Triple.getEnvironment()) {
639 return "arm1176jzf-s";
640 default:
641 return "arm7tdmi";
642 }
643 }
644
645 llvm_unreachable("invalid arch name");
646}
647
649 outs() << "All available -march extensions for ARM\n\n"
650 << " " << left_justify("Name", 20)
651 << (DescMap.empty() ? "\n" : "Description\n");
652 for (const auto &Ext : ARCHExtNames) {
653 // Extensions without a feature cannot be used with -march.
654 if (!Ext.Feature.empty()) {
655 std::string Description = DescMap[Ext.Name].str();
656 outs() << " "
657 << format(Description.empty() ? "%s\n" : "%-20s%s\n",
658 Ext.Name.str().c_str(), Description.c_str());
659 }
660 }
661}
static ARM::FPUKind findSinglePrecisionFPU(ARM::FPUKind InputFPUKind)
static StringRef getHWDivSynonym(StringRef HWDiv)
static bool stripNegationPrefix(StringRef &Name)
static ARM::ProfileKind getProfileKind(ARM::ArchKind AK)
static ARM::FPUKind findDoublePrecisionFPU(ARM::FPUKind InputFPUKind)
static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")
static GCRegistry::Add< StatepointGC > D("statepoint-example", "an example strategy for statepoint")
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
std::string Name
#define F(x, y, z)
Definition: MD5.cpp:55
cl::list< SPIRV::Extension::Extension > Extensions("spirv-extensions", cl::desc("SPIR-V extensions"), cl::ZeroOrMore, cl::Hidden, cl::values(clEnumValN(SPIRV::Extension::SPV_EXT_shader_atomic_float_add, "SPV_EXT_shader_atomic_float_add", "Adds atomic add instruction on floating-point numbers."), clEnumValN(SPIRV::Extension::SPV_EXT_shader_atomic_float16_add, "SPV_EXT_shader_atomic_float16_add", "Extends the SPV_EXT_shader_atomic_float_add extension to support " "atomically adding to 16-bit floating-point numbers in memory."), clEnumValN(SPIRV::Extension::SPV_EXT_shader_atomic_float_min_max, "SPV_EXT_shader_atomic_float_min_max", "Adds atomic min and max instruction on floating-point numbers."), clEnumValN(SPIRV::Extension::SPV_INTEL_arbitrary_precision_integers, "SPV_INTEL_arbitrary_precision_integers", "Allows generating arbitrary width integer types."), clEnumValN(SPIRV::Extension::SPV_INTEL_optnone, "SPV_INTEL_optnone", "Adds OptNoneINTEL value for Function Control mask that " "indicates a request to not optimize the function."), clEnumValN(SPIRV::Extension::SPV_INTEL_usm_storage_classes, "SPV_INTEL_usm_storage_classes", "Introduces two new storage classes that are sub classes of " "the CrossWorkgroup storage class " "that provides additional information that can enable " "optimization."), clEnumValN(SPIRV::Extension::SPV_INTEL_subgroups, "SPV_INTEL_subgroups", "Allows work items in a subgroup to share data without the " "use of local memory and work group barriers, and to " "utilize specialized hardware to load and store blocks of " "data from images or buffers."), clEnumValN(SPIRV::Extension::SPV_KHR_uniform_group_instructions, "SPV_KHR_uniform_group_instructions", "Allows support for additional group operations within " "uniform control flow."), clEnumValN(SPIRV::Extension::SPV_KHR_no_integer_wrap_decoration, "SPV_KHR_no_integer_wrap_decoration", "Adds decorations to indicate that a given instruction does " "not cause integer wrapping."), clEnumValN(SPIRV::Extension::SPV_KHR_expect_assume, "SPV_KHR_expect_assume", "Provides additional information to a compiler, similar to " "the llvm.assume and llvm.expect intrinsics."), clEnumValN(SPIRV::Extension::SPV_KHR_bit_instructions, "SPV_KHR_bit_instructions", "This enables bit instructions to be used by SPIR-V modules " "without requiring the Shader capability."), clEnumValN(SPIRV::Extension::SPV_KHR_linkonce_odr, "SPV_KHR_linkonce_odr", "Allows to use the LinkOnceODR linkage type that is to let " "a function or global variable to be merged with other functions " "or global variables of the same name when linkage occurs."), clEnumValN(SPIRV::Extension::SPV_KHR_subgroup_rotate, "SPV_KHR_subgroup_rotate", "Adds a new instruction that enables rotating values across " "invocations within a subgroup."), clEnumValN(SPIRV::Extension::SPV_INTEL_function_pointers, "SPV_INTEL_function_pointers", "Allows translation of function pointers.")))
This file implements the StringSwitch template, which mimics a switch() statement whose cases are str...
static Triple::ArchType parseArch(StringRef ArchName)
Definition: Triple.cpp:502
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:586
void push_back(const T &Elt)
Definition: SmallVector.h:426
bool empty() const
Definition: StringMap.h:103
StringMap - This is an unconventional map that is specialized for handling keys that are "strings",...
Definition: StringMap.h:128
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
constexpr bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:134
bool equals(StringRef RHS) const
equals - Check for string equality, this is more efficient than compare() when the relative ordering ...
Definition: StringRef.h:164
A switch()-like statement whose cases are string literals.
Definition: StringSwitch.h:44
StringSwitch & Case(StringLiteral S, T Value)
Definition: StringSwitch.h:69
R Default(T Value)
Definition: StringSwitch.h:182
StringSwitch & Cases(StringLiteral S0, StringLiteral S1, T Value)
Definition: StringSwitch.h:90
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
@ MuslEABIHF
Definition: Triple.h:251
OSType getOS() const
Get the parsed operating system type of this triple.
Definition: Triple.h:370
EnvironmentType getEnvironment() const
Get the parsed environment type of this triple.
Definition: Triple.h:378
StringRef getArchName() const
Get the architecture (first) component of the triple.
Definition: Triple.cpp:1189
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
StringRef getArchExtName(uint64_t ArchExtKind)
StringRef getFPUSynonym(StringRef FPU)
bool getFPUFeatures(FPUKind FPUKind, std::vector< StringRef > &Features)
StringRef getCanonicalArchName(StringRef Arch)
MArch is expected to be of the form (arm|thumb)?(eb)?(v.
uint64_t parseHWDiv(StringRef HWDiv)
StringRef getCPUAttr(ArchKind AK)
StringRef getArchName(ArchKind AK)
StringRef computeDefaultTargetABI(const Triple &TT, StringRef CPU)
void fillValidCPUArchList(SmallVectorImpl< StringRef > &Values)
const struct llvm::ARM::@414 HWDivNames[]
static const FPUName FPUNames[]
uint64_t parseArchExt(StringRef ArchExt)
ArchKind convertV9toV8(ArchKind AK)
ArchKind parseArch(StringRef Arch)
FPURestriction getFPURestriction(FPUKind FPUKind)
bool appendArchExtFeatures(StringRef CPU, ARM::ArchKind AK, StringRef ArchExt, std::vector< StringRef > &Features, FPUKind &ArgFPUKind)
StringRef getArchSynonym(StringRef Arch)
Converts e.g. "armv8" -> "armv8-a".
StringRef getDefaultCPU(StringRef Arch)
StringRef getArchExtFeature(StringRef ArchExt)
const CpuNames CPUNames[]
ProfileKind parseArchProfile(StringRef Arch)
FPUKind parseFPU(StringRef FPU)
StringRef getSubArch(ArchKind AK)
static const ArchNames ARMArchNames[]
StringRef getARMCPUForArch(const llvm::Triple &Triple, StringRef MArch={})
Get the (LLVM) name of the minimum ARM CPU for the arch we are targeting.
unsigned parseArchVersion(StringRef Arch)
const ExtName ARCHExtNames[]
bool has32Regs(const FPURestriction restriction)
NeonSupportLevel getFPUNeonSupportLevel(FPUKind FPUKind)
ArchKind parseCPUArch(StringRef CPU)
bool isDoublePrecision(const FPURestriction restriction)
unsigned getArchAttr(ArchKind AK)
StringRef getFPUName(FPUKind FPUKind)
FPUVersion getFPUVersion(FPUKind FPUKind)
bool getHWDivFeatures(uint64_t HWDivKind, std::vector< StringRef > &Features)
uint64_t getDefaultExtensions(StringRef CPU, ArchKind AK)
FPUKind getDefaultFPU(StringRef CPU, ArchKind AK)
bool getExtensionFeatures(uint64_t Extensions, std::vector< StringRef > &Features)
void PrintSupportedExtensions(StringMap< StringRef > DescMap)
@ C
The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
raw_fd_ostream & outs()
This returns a reference to a raw_fd_ostream for standard output.
format_object< Ts... > format(const char *Fmt, const Ts &... Vals)
These are helper functions used to produce formatted output.
Definition: Format.h:125
FormattedString left_justify(StringRef Str, unsigned Width)
left_justify - append spaces after string so total output is Width characters.
Definition: Format.h:146
FPURestriction Restriction
NeonSupportLevel NeonSupport