26 .
Case(
"thumb,arm",
"arm,thumb")
34 for (
const auto &
A : ARMArchNames) {
35 if (
A.Name.endswith(Syn))
38 return ArchKind::INVALID;
46 case ArchKind::ARMV4T:
48 case ArchKind::ARMV5T:
49 case ArchKind::ARMV5TE:
50 case ArchKind::IWMMXT:
51 case ArchKind::IWMMXT2:
52 case ArchKind::XSCALE:
53 case ArchKind::ARMV5TEJ:
56 case ArchKind::ARMV6K:
57 case ArchKind::ARMV6T2:
58 case ArchKind::ARMV6KZ:
59 case ArchKind::ARMV6M:
61 case ArchKind::ARMV7A:
62 case ArchKind::ARMV7VE:
63 case ArchKind::ARMV7R:
64 case ArchKind::ARMV7M:
65 case ArchKind::ARMV7S:
66 case ArchKind::ARMV7EM:
67 case ArchKind::ARMV7K:
69 case ArchKind::ARMV8A:
70 case ArchKind::ARMV8_1A:
71 case ArchKind::ARMV8_2A:
72 case ArchKind::ARMV8_3A:
73 case ArchKind::ARMV8_4A:
74 case ArchKind::ARMV8_5A:
75 case ArchKind::ARMV8_6A:
76 case ArchKind::ARMV8_7A:
77 case ArchKind::ARMV8_8A:
78 case ArchKind::ARMV8_9A:
79 case ArchKind::ARMV8R:
80 case ArchKind::ARMV8MBaseline:
81 case ArchKind::ARMV8MMainline:
82 case ArchKind::ARMV8_1MMainline:
84 case ArchKind::ARMV9A:
85 case ArchKind::ARMV9_1A:
86 case ArchKind::ARMV9_2A:
87 case ArchKind::ARMV9_3A:
88 case ArchKind::ARMV9_4A:
90 case ArchKind::INVALID:
98 case ARM::ArchKind::ARMV6M:
99 case ARM::ArchKind::ARMV7M:
100 case ARM::ArchKind::ARMV7EM:
101 case ARM::ArchKind::ARMV8MMainline:
102 case ARM::ArchKind::ARMV8MBaseline:
103 case ARM::ArchKind::ARMV8_1MMainline:
104 return ARM::ProfileKind::M;
105 case ARM::ArchKind::ARMV7R:
106 case ARM::ArchKind::ARMV8R:
107 return ARM::ProfileKind::R;
108 case ARM::ArchKind::ARMV7A:
109 case ARM::ArchKind::ARMV7VE:
110 case ARM::ArchKind::ARMV7K:
111 case ARM::ArchKind::ARMV8A:
112 case ARM::ArchKind::ARMV8_1A:
113 case ARM::ArchKind::ARMV8_2A:
114 case ARM::ArchKind::ARMV8_3A:
115 case ARM::ArchKind::ARMV8_4A:
116 case ARM::ArchKind::ARMV8_5A:
117 case ARM::ArchKind::ARMV8_6A:
118 case ARM::ArchKind::ARMV8_7A:
119 case ARM::ArchKind::ARMV8_8A:
120 case ARM::ArchKind::ARMV8_9A:
121 case ARM::ArchKind::ARMV9A:
122 case ARM::ArchKind::ARMV9_1A:
123 case ARM::ArchKind::ARMV9_2A:
124 case ARM::ArchKind::ARMV9_3A:
125 case ARM::ArchKind::ARMV9_4A:
126 return ARM::ProfileKind::A;
127 case ARM::ArchKind::ARMV4:
128 case ARM::ArchKind::ARMV4T:
129 case ARM::ArchKind::ARMV5T:
130 case ARM::ArchKind::ARMV5TE:
131 case ARM::ArchKind::ARMV5TEJ:
132 case ARM::ArchKind::ARMV6:
133 case ARM::ArchKind::ARMV6K:
134 case ARM::ArchKind::ARMV6T2:
135 case ARM::ArchKind::ARMV6KZ:
136 case ARM::ArchKind::ARMV7S:
137 case ARM::ArchKind::IWMMXT:
138 case ARM::ArchKind::IWMMXT2:
139 case ARM::ArchKind::XSCALE:
140 case ARM::ArchKind::INVALID:
141 return ARM::ProfileKind::INVALID;
153 std::vector<StringRef> &Features) {
158 static const struct FPUFeatureNameInfo {
159 const char *PlusName, *MinusName;
162 } FPUFeatureInfoList[] = {
170 {
"+vfp2",
"-vfp2", FPUVersion::VFPV2, FPURestriction::D16},
171 {
"+vfp2sp",
"-vfp2sp", FPUVersion::VFPV2, FPURestriction::SP_D16},
172 {
"+vfp3",
"-vfp3", FPUVersion::VFPV3, FPURestriction::None},
173 {
"+vfp3d16",
"-vfp3d16", FPUVersion::VFPV3, FPURestriction::D16},
174 {
"+vfp3d16sp",
"-vfp3d16sp", FPUVersion::VFPV3, FPURestriction::SP_D16},
175 {
"+vfp3sp",
"-vfp3sp", FPUVersion::VFPV3, FPURestriction::None},
176 {
"+fp16",
"-fp16", FPUVersion::VFPV3_FP16, FPURestriction::SP_D16},
177 {
"+vfp4",
"-vfp4", FPUVersion::VFPV4, FPURestriction::None},
178 {
"+vfp4d16",
"-vfp4d16", FPUVersion::VFPV4, FPURestriction::D16},
179 {
"+vfp4d16sp",
"-vfp4d16sp", FPUVersion::VFPV4, FPURestriction::SP_D16},
180 {
"+vfp4sp",
"-vfp4sp", FPUVersion::VFPV4, FPURestriction::None},
181 {
"+fp-armv8",
"-fp-armv8", FPUVersion::VFPV5, FPURestriction::None},
182 {
"+fp-armv8d16",
"-fp-armv8d16", FPUVersion::VFPV5, FPURestriction::D16},
183 {
"+fp-armv8d16sp",
"-fp-armv8d16sp", FPUVersion::VFPV5, FPURestriction::SP_D16},
184 {
"+fp-armv8sp",
"-fp-armv8sp", FPUVersion::VFPV5, FPURestriction::None},
185 {
"+fullfp16",
"-fullfp16", FPUVersion::VFPV5_FULLFP16, FPURestriction::SP_D16},
186 {
"+fp64",
"-fp64", FPUVersion::VFPV2, FPURestriction::D16},
187 {
"+d32",
"-d32", FPUVersion::VFPV3, FPURestriction::None},
190 for (
const auto &
Info: FPUFeatureInfoList) {
192 FPUNames[
FPUKind].Restriction <=
Info.MaxRestriction)
193 Features.push_back(
Info.PlusName);
195 Features.push_back(
Info.MinusName);
198 static const struct NeonFeatureNameInfo {
199 const char *PlusName, *MinusName;
201 } NeonFeatureInfoList[] = {
202 {
"+neon",
"-neon", NeonSupportLevel::Neon},
203 {
"+sha2",
"-sha2", NeonSupportLevel::Crypto},
204 {
"+aes",
"-aes", NeonSupportLevel::Crypto},
207 for (
const auto &
Info: NeonFeatureInfoList) {
208 if (FPUNames[
FPUKind].NeonSupport >=
Info.MinSupportLevel)
209 Features.push_back(
Info.PlusName);
211 Features.push_back(
Info.MinusName);
219 for (
const auto &
F : FPUNames) {
228 return NeonSupportLevel::None;
229 return FPUNames[
FPUKind].NeonSupport;
234 .
Cases(
"fpa",
"fpe2",
"fpe3",
"maverick",
"invalid")
235 .
Case(
"vfp2",
"vfpv2")
236 .
Case(
"vfp3",
"vfpv3")
237 .
Case(
"vfp4",
"vfpv4")
238 .
Case(
"vfp3-d16",
"vfpv3-d16")
239 .
Case(
"vfp4-d16",
"vfpv4-d16")
240 .
Cases(
"fp4-sp-d16",
"vfpv4-sp-d16",
"fpv4-sp-d16")
241 .
Cases(
"fp4-dp-d16",
"fpv4-dp-d16",
"vfpv4-d16")
242 .
Case(
"fp5-sp-d16",
"fpv5-sp-d16")
243 .
Cases(
"fp5-dp-d16",
"fpv5-dp-d16",
"fpv5-d16")
245 .
Case(
"neon-vfpv3",
"neon")
257 return FPUVersion::NONE;
258 return FPUNames[
FPUKind].FPUVer;
263 return FPURestriction::None;
264 return FPUNames[
FPUKind].Restriction;
268 if (CPU ==
"generic")
272#define ARM_CPU_NAME(NAME, ID, DEFAULT_FPU, IS_DEFAULT, DEFAULT_EXT) \
273 .Case(NAME, DEFAULT_FPU)
274#include "llvm/TargetParser/ARMTargetParser.def"
279 if (CPU ==
"generic")
283#define ARM_CPU_NAME(NAME, ID, DEFAULT_FPU, IS_DEFAULT, DEFAULT_EXT) \
285 ARMArchNames[static_cast<unsigned>(ArchKind::ID)].ArchBaseExtensions | \
287#include "llvm/TargetParser/ARMTargetParser.def"
292 std::vector<StringRef> &Features) {
298 Features.push_back(
"+hwdiv-arm");
300 Features.push_back(
"-hwdiv-arm");
303 Features.push_back(
"+hwdiv");
305 Features.push_back(
"-hwdiv");
311 std::vector<StringRef> &Features) {
317 if ((
Extensions & AE.ID) == AE.ID && !AE.Feature.empty())
318 Features.push_back(AE.Feature);
319 else if (!AE.NegFeature.empty())
320 Features.push_back(AE.NegFeature);
327 return ARMArchNames[
static_cast<unsigned>(AK)].
Name;
331 return ARMArchNames[
static_cast<unsigned>(AK)].CPUAttr;
335 return ARMArchNames[
static_cast<unsigned>(AK)].
getSubArch();
339 return ARMArchNames[
static_cast<unsigned>(AK)].ArchAttr;
351 if (
Name.startswith(
"no")) {
361 if (!AE.Feature.empty() && ArchExt == AE.Name)
362 return StringRef(Negated ? AE.NegFeature : AE.Feature);
379 if (InputFPU.
Restriction != ARM::FPURestriction::SP_D16)
380 return ARM::FK_INVALID;
386 if (CandidateFPU.FPUVer == InputFPU.
FPUVer &&
387 CandidateFPU.NeonSupport == InputFPU.
NeonSupport &&
388 CandidateFPU.Restriction == ARM::FPURestriction::D16) {
389 return CandidateFPU.
ID;
394 return ARM::FK_INVALID;
399 std::vector<StringRef> &Features,
402 size_t StartingNumFeatures = Features.size();
411 if ((AE.ID &
ID) ==
ID && !AE.NegFeature.empty())
412 Features.push_back(AE.NegFeature);
414 if ((AE.ID &
ID) == AE.ID && !AE.Feature.empty())
415 Features.push_back(AE.Feature);
422 if (ArchExt ==
"fp" || ArchExt ==
"fp.dp") {
424 if (ArchExt ==
"fp.dp") {
426 Features.push_back(
"-fp64");
430 }
else if (Negated) {
438 return StartingNumFeatures != Features.size();
443 return ARM::ArchKind::INVALID;
444 if (AK < ARM::ArchKind::ARMV9A || AK > ARM::ArchKind::ARMV9_3A)
445 return ARM::ArchKind::INVALID;
446 unsigned AK_v8 =
static_cast<unsigned>(ARM::ArchKind::ARMV8_5A);
447 AK_v8 +=
static_cast<unsigned>(AK) -
448 static_cast<unsigned>(ARM::ArchKind::ARMV9A);
454 if (AK == ArchKind::INVALID)
459 if (CPU.ArchID == AK && CPU.Default)
478 if (ArchExt ==
A.Name)
489 return ArchKind::INVALID;
494 if (Arch.ArchID != ArchKind::INVALID)
503 if (
TT.isOSBinFormatMachO()) {
511 }
else if (
TT.isOSWindows())
516 switch (
TT.getEnvironment()) {
522 return "aapcs-linux";
529 if (
TT.isOSFreeBSD() ||
TT.isOSOpenBSD() ||
TT.isOHOSFamily())
530 return "aapcs-linux";
545 if (!MArch.
empty() && MArch ==
"v6")
546 return "arm1176jzf-s";
547 if (!MArch.
empty() && MArch ==
"v7")
595 return "arm1176jzf-s";
605 outs() <<
"All available -march extensions for ARM\n\n"
607 << (DescMap.
empty() ?
"\n" :
"Description\n");
610 if (!Ext.Feature.empty()) {
611 std::string Description = DescMap[Ext.Name].str();
613 <<
format(Description.empty() ?
"%s\n" :
"%-20s%s\n",
614 Ext.Name.str().c_str(), Description.c_str());
static StringRef getHWDivSynonym(StringRef HWDiv)
static bool stripNegationPrefix(StringRef &Name)
static ARM::ProfileKind getProfileKind(ARM::ArchKind AK)
static ARM::FPUKind findDoublePrecisionFPU(ARM::FPUKind InputFPUKind)
static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")
static GCRegistry::Add< StatepointGC > D("statepoint-example", "an example strategy for statepoint")
Analysis containing CSE Info
cl::list< SPIRV::Extension::Extension > Extensions("spirv-extensions", cl::desc("SPIR-V extensions"), cl::ZeroOrMore, cl::Hidden, cl::values(clEnumValN(SPIRV::Extension::SPV_INTEL_arbitrary_precision_integers, "SPV_INTEL_arbitrary_precision_integers", "Allows generating arbitrary width integer types"), clEnumValN(SPIRV::Extension::SPV_INTEL_optnone, "SPV_INTEL_optnone", "Adds OptNoneINTEL value for Function Control mask that " "indicates a request to not optimize the function"), clEnumValN(SPIRV::Extension::SPV_KHR_no_integer_wrap_decoration, "SPV_KHR_no_integer_wrap_decoration", "Adds decorations to indicate that a given instruction does " "not cause integer wrapping"), clEnumValN(SPIRV::Extension::SPV_KHR_bit_instructions, "SPV_KHR_bit_instructions", "This enables bit instructions to be used by SPIR-V modules " "without requiring the Shader capability")))
This file implements the StringSwitch template, which mimics a switch() statement whose cases are str...
static Triple::ArchType parseArch(StringRef ArchName)
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
void push_back(const T &Elt)
StringMap - This is an unconventional map that is specialized for handling keys that are "strings",...
StringRef - Represent a constant reference to a string, i.e.
constexpr bool empty() const
empty - Check if the string is empty.
bool equals(StringRef RHS) const
equals - Check for string equality, this is more efficient than compare() when the relative ordering ...
A switch()-like statement whose cases are string literals.
StringSwitch & Case(StringLiteral S, T Value)
StringSwitch & Cases(StringLiteral S0, StringLiteral S1, T Value)
Triple - Helper class for working with autoconf configuration names.
OSType getOS() const
Get the parsed operating system type of this triple.
EnvironmentType getEnvironment() const
Get the parsed environment type of this triple.
StringRef getArchName() const
Get the architecture (first) component of the triple.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
StringRef getArchExtName(uint64_t ArchExtKind)
StringRef getFPUSynonym(StringRef FPU)
bool getFPUFeatures(FPUKind FPUKind, std::vector< StringRef > &Features)
StringRef getCanonicalArchName(StringRef Arch)
MArch is expected to be of the form (arm|thumb)?(eb)?(v.
uint64_t parseHWDiv(StringRef HWDiv)
StringRef getCPUAttr(ArchKind AK)
StringRef getArchName(ArchKind AK)
StringRef computeDefaultTargetABI(const Triple &TT, StringRef CPU)
void fillValidCPUArchList(SmallVectorImpl< StringRef > &Values)
static const FPUName FPUNames[]
uint64_t parseArchExt(StringRef ArchExt)
ArchKind convertV9toV8(ArchKind AK)
ArchKind parseArch(StringRef Arch)
FPURestriction getFPURestriction(FPUKind FPUKind)
bool appendArchExtFeatures(StringRef CPU, ARM::ArchKind AK, StringRef ArchExt, std::vector< StringRef > &Features, FPUKind &ArgFPUKind)
const struct llvm::ARM::@411 HWDivNames[]
StringRef getArchSynonym(StringRef Arch)
Converts e.g. "armv8" -> "armv8-a".
StringRef getDefaultCPU(StringRef Arch)
StringRef getArchExtFeature(StringRef ArchExt)
const CpuNames CPUNames[]
ProfileKind parseArchProfile(StringRef Arch)
FPUKind parseFPU(StringRef FPU)
StringRef getSubArch(ArchKind AK)
static const ArchNames ARMArchNames[]
StringRef getARMCPUForArch(const llvm::Triple &Triple, StringRef MArch={})
Get the (LLVM) name of the minimum ARM CPU for the arch we are targeting.
unsigned parseArchVersion(StringRef Arch)
const ExtName ARCHExtNames[]
NeonSupportLevel getFPUNeonSupportLevel(FPUKind FPUKind)
ArchKind parseCPUArch(StringRef CPU)
unsigned getArchAttr(ArchKind AK)
StringRef getFPUName(FPUKind FPUKind)
FPUVersion getFPUVersion(FPUKind FPUKind)
bool getHWDivFeatures(uint64_t HWDivKind, std::vector< StringRef > &Features)
uint64_t getDefaultExtensions(StringRef CPU, ArchKind AK)
FPUKind getDefaultFPU(StringRef CPU, ArchKind AK)
bool getExtensionFeatures(uint64_t Extensions, std::vector< StringRef > &Features)
void PrintSupportedExtensions(StringMap< StringRef > DescMap)
@ C
The default llvm calling convention, compatible with C.
This is an optimization pass for GlobalISel generic memory operations.
raw_fd_ostream & outs()
This returns a reference to a raw_fd_ostream for standard output.
format_object< Ts... > format(const char *Fmt, const Ts &... Vals)
These are helper functions used to produce formatted output.
FormattedString left_justify(StringRef Str, unsigned Width)
left_justify - append spaces after string so total output is Width characters.
FPURestriction Restriction
NeonSupportLevel NeonSupport