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21 #define DEBUG_TYPE "llvm-mca"
72 for (
const InstRef &
I : Pending)
75 for (
const InstRef &
I : Ready)
80 Error ExecuteStage::issueReadyInstructions() {
83 if (Error Err = issueInstruction(
IR))
90 return ErrorSuccess();
99 HWS.
cycleEvent(Freed, Executed, Pending, Ready);
100 NumDispatchedOpcodes = 0;
101 NumIssuedOpcodes = 0;
119 return issueReadyInstructions();
123 if (!EnablePressureEvents)
128 if (!HWS.
hadTokenStall() && NumDispatchedOpcodes <= NumIssuedOpcodes)
134 LLVM_DEBUG(
dbgs() <<
"[E] Backpressure increased because of unavailable "
135 "pipeline resources: "
144 if (RegDeps.size()) {
146 dbgs() <<
"[E] Backpressure increased by register dependencies\n");
151 if (MemDeps.size()) {
152 LLVM_DEBUG(
dbgs() <<
"[E] Backpressure increased by memory dependencies\n");
164 assert(Inst.
isReady() &&
"Instruction in an inconsistent state!");
169 "Cannot eliminate a memory op!");
173 Error ExecuteStage::handleInstructionEliminated(InstRef &
IR) {
180 IR.getInstruction()->forceExecuted();
194 if (
IR.getInstruction()->isEliminated())
195 return handleInstructionEliminated(
IR);
204 NumDispatchedOpcodes += NumMicroOps;
207 if (!IsReadyInstruction) {
224 return issueInstruction(
IR);
229 notifyEvent<HWInstructionEvent>(
235 notifyEvent<HWInstructionEvent>(
241 notifyEvent<HWInstructionEvent>(
246 LLVM_DEBUG(
dbgs() <<
"[E] Resource Available: [" << RR.first <<
'.'
247 << RR.second <<
"]\n");
249 Listener->onResourceAvailable(RR);
255 dbgs() <<
"[E] Instruction Issued: #" <<
IR <<
'\n';
257 assert(
Use.second.getDenominator() == 1 &&
"Invalid cycles!");
258 dbgs() <<
"[E] Resource Used: [" <<
Use.first.first <<
'.'
259 <<
Use.first.second <<
"], ";
260 dbgs() <<
"cycles: " <<
Use.second.getNumerator() <<
'\n';
272 bool Reserved)
const {
273 uint64_t UsedBuffers =
IR.getInstruction()->getDesc().UsedBuffers;
278 for (
unsigned I = 0,
E = BufferIDs.size();
I <
E; ++
I) {
279 uint64_t CurrentBufferMask = UsedBuffers & (-UsedBuffers);
281 UsedBuffers ^= CurrentBufferMask;
286 Listener->onReservedBuffers(
IR, BufferIDs);
291 Listener->onReleasedBuffers(
IR, BufferIDs);
bool dispatch(InstRef &IR)
Reserves buffer and LSUnit queue resources that are necessary to issue this instruction.
This is an optimization pass for GlobalISel generic memory operations.
void analyzeDataDependencies(SmallVectorImpl< InstRef > &RegDeps, SmallVectorImpl< InstRef > &MemDeps)
This method is called by the ExecuteStage at the end of each cycle to identify bottlenecks caused by ...
void notifyInstructionPending(const InstRef &IR) const
void instructionCheck(const InstRef &IR) const
An instruction propagated through the simulated instruction pipeline.
bool isEliminated() const
std::pair< uint64_t, uint64_t > ResourceRef
A resource unit identifier.
unsigned getResourceID(uint64_t Mask) const
Convert a resource mask into a valid llvm processor resource identifier.
static void verifyInstructionEliminated(const InstRef &IR)
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
MutableArrayRef - Represent a mutable reference to an array (0 or more elements consecutively in memo...
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
bool mustIssueImmediately(const InstRef &IR) const
Returns true if IR has to be issued immediately, or if IR is a zero latency instruction.
uint64_t analyzeResourcePressure(SmallVectorImpl< InstRef > &Insts)
Returns a mask of busy resources, and populates vector Insts with instructions that could not be issu...
Statically lint checks LLVM IR
void notifyReservedOrReleasedBuffers(const InstRef &IR, bool Reserved) const
void notifyInstructionExecuted(const InstRef &IR) const
unsigned countPopulation(T Value)
Count the number of set bits in a value.
bool hadTokenStall() const
Subclass of Error for the sole purpose of identifying the success path in the type system.
const std::set< HWEventListener * > & getListeners() const
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
HWStallEvent::GenericEventType toHWStallEventType(Scheduler::Status Status)
An InstRef contains both a SourceMgr index and Instruction pair.
bool isAvailable(const InstRef &IR) const override
Returns true if it can execute IR during this cycle.
unsigned getNumMicroOps() const
void issueInstruction(InstRef &IR, SmallVectorImpl< std::pair< ResourceRef, ResourceCycles >> &Used, SmallVectorImpl< InstRef > &Pending, SmallVectorImpl< InstRef > &Ready)
Issue an instruction and populates a vector of used pipeline resources, and a vector of instructions ...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Error cycleStart() override
Called once at the start of each cycle.
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
@ SC_DISPATCH_GROUP_STALL
void notifyResourceAvailable(const ResourceRef &RR) const
Status isAvailable(const InstRef &IR)
Check if the instruction in 'IR' can be dispatched during this cycle.
Error cycleEnd() override
Called once at the end of each cycle.
Lightweight error class with error context and mandatory checking.
std::pair< ResourceRef, ResourceCycles > ResourceUse
InstRef select()
Select the next instruction to issue from the ReadySet.
Error execute(InstRef &IR) override
The primary action that this stage performs on instruction IR.
void notifyInstructionReady(const InstRef &IR) const
Error moveToTheNextStage(InstRef &IR)
Called when an instruction is ready to move the next pipeline stage.
FormattedNumber format_hex(uint64_t N, unsigned Width, bool Upper=false)
format_hex - Output N as a fixed width hexadecimal.
void notifyInstructionIssued(const InstRef &IR, MutableArrayRef< ResourceUse > Used) const
void notifyEvent(const EventT &Event) const
Notify listeners of a particular hardware event.
A Use represents the edge between a Value definition and its users.
void cycleEvent(SmallVectorImpl< ResourceRef > &Freed, SmallVectorImpl< InstRef > &Executed, SmallVectorImpl< InstRef > &Pending, SmallVectorImpl< InstRef > &Ready)
This routine notifies the Scheduler that a new cycle just started.