LLVM  14.0.0git
HexagonMCCodeEmitter.h
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1 //===- HexagonMCCodeEmitter.h - Hexagon Target Descriptions -----*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 ///
9 /// \file
10 /// Definition for classes that emit Hexagon machine code from MCInsts
11 ///
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONMCCODEEMITTER_H
15 #define LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONMCCODEEMITTER_H
16 
18 #include "llvm/MC/MCCodeEmitter.h"
19 #include "llvm/MC/MCExpr.h"
21 #include <cstddef>
22 #include <cstdint>
23 #include <memory>
24 
25 namespace llvm {
26 
27 class MCContext;
28 class MCInst;
29 class MCInstrInfo;
30 class MCOperand;
31 class MCSubtargetInfo;
32 class raw_ostream;
33 
35  MCContext &MCT;
36  MCInstrInfo const &MCII;
37 
38  // A mutable state of the emitter when encoding bundles and duplexes.
39  struct EmitterState {
40  unsigned Addend = 0;
41  bool Extended = false;
42  bool SubInst1 = false;
43  const MCInst *Bundle = nullptr;
44  size_t Index = 0;
45  };
46  mutable EmitterState State;
47 
48 public:
50  : MCT(MCT), MCII(MII) {}
51 
52  void encodeInstruction(MCInst const &MI, raw_ostream &OS,
54  MCSubtargetInfo const &STI) const override;
55 
58  const MCSubtargetInfo &STI,
59  uint32_t Parse) const;
60 
61  // TableGen'erated function for getting the
62  // binary encoding for an instruction.
65  MCSubtargetInfo const &STI) const;
66 
67  /// Return binary encoding of operand.
68  unsigned getMachineOpValue(MCInst const &MI, MCOperand const &MO,
70  MCSubtargetInfo const &STI) const;
71 
72 private:
73  // helper routine for getMachineOpValue()
74  unsigned getExprOpValue(const MCInst &MI, const MCOperand &MO,
76  const MCSubtargetInfo &STI) const;
77 
78  Hexagon::Fixups getFixupNoBits(MCInstrInfo const &MCII, const MCInst &MI,
79  const MCOperand &MO,
81 
82  // Return parse bits for instruction `MCI' inside bundle `MCB'
83  uint32_t parseBits(size_t Last, MCInst const &MCB, MCInst const &MCI) const;
84 
85  FeatureBitset computeAvailableFeatures(const FeatureBitset &FB) const;
86  void
87  verifyInstructionPredicates(const MCInst &MI,
88  const FeatureBitset &AvailableFeatures) const;
89 };
90 
91 } // end namespace llvm
92 
93 #endif // LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONMCCODEEMITTER_H
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:103
llvm
---------------------— PointerInfo ------------------------------------—
Definition: AllocatorList.h:23
llvm::MCContext
Context object for machine code objects.
Definition: MCContext.h:72
llvm::HexagonMCCodeEmitter::getMachineOpValue
unsigned getMachineOpValue(MCInst const &MI, MCOperand const &MO, SmallVectorImpl< MCFixup > &Fixups, MCSubtargetInfo const &STI) const
Return binary encoding of operand.
Definition: HexagonMCCodeEmitter.cpp:712
MCCodeEmitter.h
llvm::FeatureBitset
Container class for subtarget features.
Definition: SubtargetFeature.h:40
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
llvm::Hexagon::Fixups
Fixups
Definition: HexagonFixupKinds.h:16
HexagonFixupKinds.h
llvm::HexagonMCCodeEmitter::getBinaryCodeForInstr
uint64_t getBinaryCodeForInstr(MCInst const &MI, SmallVectorImpl< MCFixup > &Fixups, MCSubtargetInfo const &STI) const
SubtargetFeature.h
llvm::AArch64::Fixups
Fixups
Definition: AArch64FixupKinds.h:17
llvm::HexagonMCCodeEmitter
Definition: HexagonMCCodeEmitter.h:34
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:53
llvm::HexagonMCCodeEmitter::encodeInstruction
void encodeInstruction(MCInst const &MI, raw_ostream &OS, SmallVectorImpl< MCFixup > &Fixups, MCSubtargetInfo const &STI) const override
Emit the bundle.
Definition: HexagonMCCodeEmitter.cpp:367
llvm::lltok::Kind
Kind
Definition: LLToken.h:18
llvm::HexagonMCCodeEmitter::HexagonMCCodeEmitter
HexagonMCCodeEmitter(MCInstrInfo const &MII, MCContext &MCT)
Definition: HexagonMCCodeEmitter.h:49
llvm::MCSymbolRefExpr::VariantKind
VariantKind
Definition: MCExpr.h:194
Index
uint32_t Index
Definition: ELFObjHandler.cpp:84
uint64_t
uint32_t
llvm::HexagonMCCodeEmitter::EncodeSingleInstruction
void EncodeSingleInstruction(const MCInst &MI, raw_ostream &OS, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI, uint32_t Parse) const
EncodeSingleInstruction - Emit a single.
Definition: HexagonMCCodeEmitter.cpp:400
llvm::MCInstrInfo
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:25
llvm::MCCodeEmitter
MCCodeEmitter - Generic instruction encoding interface.
Definition: MCCodeEmitter.h:21
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:43
llvm::MCOperand
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:36
MCExpr.h
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition: MCSubtargetInfo.h:75
llvm::MCExpr
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:35