LLVM
22.0.0git
lib
Target
Hexagon
MCTargetDesc
HexagonMCCodeEmitter.h
Go to the documentation of this file.
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//===- HexagonMCCodeEmitter.h - Hexagon Target Descriptions -----*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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///
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/// \file
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/// Definition for classes that emit Hexagon machine code from MCInsts
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///
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONMCCODEEMITTER_H
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#define LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONMCCODEEMITTER_H
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#include "
MCTargetDesc/HexagonFixupKinds.h
"
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#include "
MCTargetDesc/HexagonMCExpr.h
"
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#include "
llvm/MC/MCCodeEmitter.h
"
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#include "
llvm/MC/MCExpr.h
"
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#include "
llvm/TargetParser/SubtargetFeature.h
"
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#include <cstddef>
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#include <cstdint>
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namespace
llvm
{
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class
MCContext
;
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class
MCInst
;
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class
MCInstrInfo
;
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class
MCOperand
;
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class
MCSubtargetInfo
;
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class
raw_ostream
;
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class
HexagonMCCodeEmitter
:
public
MCCodeEmitter
{
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MCContext
&MCT;
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MCInstrInfo
const
&MCII;
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// A mutable state of the emitter when encoding bundles and duplexes.
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struct
EmitterState {
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unsigned
Addend = 0;
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bool
Extended =
false
;
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bool
SubInst1 =
false
;
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const
MCInst
*Bundle =
nullptr
;
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size_t
Index = 0;
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};
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mutable
EmitterState State;
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public
:
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HexagonMCCodeEmitter
(
MCInstrInfo
const
&MII,
MCContext
&MCT)
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: MCT(MCT), MCII(MII) {}
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void
encodeInstruction
(
MCInst
const
&
MI
,
SmallVectorImpl<char>
&CB,
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SmallVectorImpl<MCFixup>
&Fixups,
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MCSubtargetInfo
const
&STI)
const override
;
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void
encodeSingleInstruction
(
const
MCInst
&
MI
,
SmallVectorImpl<char>
&CB,
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SmallVectorImpl<MCFixup>
&Fixups,
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const
MCSubtargetInfo
&STI,
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uint32_t
Parse)
const
;
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// TableGen'erated function for getting the
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// binary encoding for an instruction.
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uint64_t
getBinaryCodeForInstr
(
MCInst
const
&
MI
,
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SmallVectorImpl<MCFixup>
&Fixups,
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MCSubtargetInfo
const
&STI)
const
;
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/// Return binary encoding of operand.
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unsigned
getMachineOpValue
(
MCInst
const
&
MI
,
MCOperand
const
&MO,
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SmallVectorImpl<MCFixup>
&Fixups,
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MCSubtargetInfo
const
&STI)
const
;
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private
:
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// helper routine for getMachineOpValue()
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unsigned
getExprOpValue(
const
MCInst
&
MI
,
const
MCOperand
&MO,
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const
MCExpr
*ME,
SmallVectorImpl<MCFixup>
&Fixups,
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const
MCSubtargetInfo
&STI)
const
;
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Hexagon::Fixups
getFixupNoBits(
MCInstrInfo
const
&MCII,
const
MCInst
&
MI
,
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const
MCOperand
&MO,
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HexagonMCExpr::VariantKind
Kind)
const
;
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// Return parse bits for instruction `MCI' inside bundle `MCB'
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uint32_t
parseBits(
size_t
Last
,
MCInst
const
&MCB,
MCInst
const
&MCI)
const
;
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};
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}
// end namespace llvm
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#endif
// LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONMCCODEEMITTER_H
HexagonFixupKinds.h
HexagonMCExpr.h
MI
IRTranslator LLVM IR MI
Definition
IRTranslator.cpp:110
MCCodeEmitter.h
MCExpr.h
SubtargetFeature.h
llvm::HexagonMCCodeEmitter::encodeSingleInstruction
void encodeSingleInstruction(const MCInst &MI, SmallVectorImpl< char > &CB, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI, uint32_t Parse) const
Definition
HexagonMCCodeEmitter.cpp:426
llvm::HexagonMCCodeEmitter::getMachineOpValue
unsigned getMachineOpValue(MCInst const &MI, MCOperand const &MO, SmallVectorImpl< MCFixup > &Fixups, MCSubtargetInfo const &STI) const
Return binary encoding of operand.
Definition
HexagonMCCodeEmitter.cpp:734
llvm::HexagonMCCodeEmitter::getBinaryCodeForInstr
uint64_t getBinaryCodeForInstr(MCInst const &MI, SmallVectorImpl< MCFixup > &Fixups, MCSubtargetInfo const &STI) const
llvm::HexagonMCCodeEmitter::HexagonMCCodeEmitter
HexagonMCCodeEmitter(MCInstrInfo const &MII, MCContext &MCT)
Definition
HexagonMCCodeEmitter.h:49
llvm::HexagonMCCodeEmitter::encodeInstruction
void encodeInstruction(MCInst const &MI, SmallVectorImpl< char > &CB, SmallVectorImpl< MCFixup > &Fixups, MCSubtargetInfo const &STI) const override
Emit the bundle.
Definition
HexagonMCCodeEmitter.cpp:395
llvm::HexagonMCExpr::VariantKind
VariantKind
Definition
HexagonMCExpr.h:17
llvm::MCCodeEmitter::MCCodeEmitter
MCCodeEmitter()
llvm::MCContext
Context object for machine code objects.
Definition
MCContext.h:83
llvm::MCExpr
Base class for the full range of assembler expressions which are needed for parsing.
Definition
MCExpr.h:34
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition
MCInst.h:188
llvm::MCInstrInfo
Interface to description of machine instruction set.
Definition
MCInstrInfo.h:27
llvm::MCOperand
Instances of this class represent operands of the MCInst class.
Definition
MCInst.h:40
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition
MCSubtargetInfo.h:77
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition
SmallVector.h:574
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition
raw_ostream.h:53
uint32_t
uint64_t
llvm::Hexagon::Fixups
Fixups
Definition
HexagonFixupKinds.h:16
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition
AddressRanges.h:18
llvm::PseudoProbeReservedId::Last
@ Last
Definition
PseudoProbe.h:28
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