LLVM 17.0.0git
HexagonMCCodeEmitter.h
Go to the documentation of this file.
1//===- HexagonMCCodeEmitter.h - Hexagon Target Descriptions -----*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8///
9/// \file
10/// Definition for classes that emit Hexagon machine code from MCInsts
11///
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONMCCODEEMITTER_H
15#define LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONMCCODEEMITTER_H
16
19#include "llvm/MC/MCExpr.h"
21#include <cstddef>
22#include <cstdint>
23#include <memory>
24
25namespace llvm {
26
27class MCContext;
28class MCInst;
29class MCInstrInfo;
30class MCOperand;
31class MCSubtargetInfo;
32class raw_ostream;
33
35 MCContext &MCT;
36 MCInstrInfo const &MCII;
37
38 // A mutable state of the emitter when encoding bundles and duplexes.
39 struct EmitterState {
40 unsigned Addend = 0;
41 bool Extended = false;
42 bool SubInst1 = false;
43 const MCInst *Bundle = nullptr;
44 size_t Index = 0;
45 };
46 mutable EmitterState State;
47
48public:
50 : MCT(MCT), MCII(MII) {}
51
52 void encodeInstruction(MCInst const &MI, raw_ostream &OS,
54 MCSubtargetInfo const &STI) const override;
55
58 const MCSubtargetInfo &STI,
59 uint32_t Parse) const;
60
61 // TableGen'erated function for getting the
62 // binary encoding for an instruction.
65 MCSubtargetInfo const &STI) const;
66
67 /// Return binary encoding of operand.
68 unsigned getMachineOpValue(MCInst const &MI, MCOperand const &MO,
70 MCSubtargetInfo const &STI) const;
71
72private:
73 // helper routine for getMachineOpValue()
74 unsigned getExprOpValue(const MCInst &MI, const MCOperand &MO,
75 const MCExpr *ME, SmallVectorImpl<MCFixup> &Fixups,
76 const MCSubtargetInfo &STI) const;
77
78 Hexagon::Fixups getFixupNoBits(MCInstrInfo const &MCII, const MCInst &MI,
79 const MCOperand &MO,
80 const MCSymbolRefExpr::VariantKind Kind) const;
81
82 // Return parse bits for instruction `MCI' inside bundle `MCB'
83 uint32_t parseBits(size_t Last, MCInst const &MCB, MCInst const &MCI) const;
84};
85
86} // end namespace llvm
87
88#endif // LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONMCCODEEMITTER_H
IRTranslator LLVM IR MI
void encodeInstruction(MCInst const &MI, raw_ostream &OS, SmallVectorImpl< MCFixup > &Fixups, MCSubtargetInfo const &STI) const override
Emit the bundle.
void EncodeSingleInstruction(const MCInst &MI, raw_ostream &OS, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI, uint32_t Parse) const
EncodeSingleInstruction - Emit a single.
unsigned getMachineOpValue(MCInst const &MI, MCOperand const &MO, SmallVectorImpl< MCFixup > &Fixups, MCSubtargetInfo const &STI) const
Return binary encoding of operand.
uint64_t getBinaryCodeForInstr(MCInst const &MI, SmallVectorImpl< MCFixup > &Fixups, MCSubtargetInfo const &STI) const
HexagonMCCodeEmitter(MCInstrInfo const &MII, MCContext &MCT)
MCCodeEmitter - Generic instruction encoding interface.
Definition: MCCodeEmitter.h:21
Context object for machine code objects.
Definition: MCContext.h:76
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:35
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:26
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:36
Generic base class for all target subtargets.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:577
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:52
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18