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38 #define DEBUG_TYPE "mccodeemitter"
41 using namespace Hexagon;
43 STATISTIC(MCNumEmitted,
"Number of MC instructions emitted");
47 #define _ fixup_Invalid
48 #define P(x) Hexagon::fixup_Hexagon##x
49 static const std::map<unsigned, std::vector<unsigned>>
ExtFixups = {
52 _,
_,
P(_DTPREL_16_X),
P(_DTPREL_11_X),
53 P(_DTPREL_11_X),
P(_9_X),
_,
P(_DTPREL_11_X),
54 P(_DTPREL_16_X),
_,
_,
_,
55 P(_DTPREL_16_X),
_,
_,
_,
62 _,
_,
P(_GOT_11_X),
_ ,
63 _ ,
P(_9_X),
_,
P(_GOT_11_X),
64 P(_GOT_16_X),
_,
_,
_,
65 P(_GOT_16_X),
_,
_,
_,
72 _,
_,
P(_GOTREL_11_X),
P(_GOTREL_11_X),
73 P(_GOTREL_11_X),
P(_9_X),
_,
P(_GOTREL_11_X),
74 P(_GOTREL_16_X),
_,
_,
_,
75 P(_GOTREL_16_X),
_,
_,
_,
82 _,
_,
P(_TPREL_16_X),
P(_TPREL_11_X),
83 P(_TPREL_11_X),
P(_9_X),
_,
P(_TPREL_11_X),
84 P(_TPREL_16_X),
_,
_,
_,
85 P(_TPREL_16_X),
_,
_,
_,
92 _,
_,
P(_GD_GOT_16_X),
P(_GD_GOT_11_X),
93 P(_GD_GOT_11_X),
P(_9_X),
_,
P(_GD_GOT_11_X),
94 P(_GD_GOT_16_X),
_,
_,
_,
95 P(_GD_GOT_16_X),
_,
_,
_,
103 _,
P(_9_X),
_,
P(_GD_PLT_B22_PCREL_X),
106 _,
_,
P(_GD_PLT_B22_PCREL_X),
_,
112 _,
_,
P(_IE_16_X),
_,
114 P(_IE_16_X),
_,
_,
_,
115 P(_IE_16_X),
_,
_,
_,
122 _,
_,
P(_IE_GOT_11_X),
P(_IE_GOT_11_X),
123 P(_IE_GOT_11_X),
P(_9_X),
_,
P(_IE_GOT_11_X),
124 P(_IE_GOT_16_X),
_,
_,
_,
125 P(_IE_GOT_16_X),
_,
_,
_,
129 P(_IE_GOT_32_6_X) }},
132 _,
_,
P(_LD_GOT_11_X),
P(_LD_GOT_11_X),
133 P(_LD_GOT_11_X),
P(_9_X),
_,
P(_LD_GOT_11_X),
134 P(_LD_GOT_16_X),
_,
_,
_,
135 P(_LD_GOT_16_X),
_,
_,
_,
139 P(_LD_GOT_32_6_X) }},
143 _,
P(_9_X),
_,
P(_LD_PLT_B22_PCREL_X),
146 _,
_,
P(_LD_PLT_B22_PCREL_X),
_,
152 _,
_,
P(_6_PCREL_X),
_,
162 _,
_,
P(_6_X),
P(_8_X),
163 P(_8_X),
P(_9_X),
P(_10_X),
P(_11_X),
164 P(_12_X),
P(_B13_PCREL),
_,
P(_B15_PCREL_X),
166 _,
_,
P(_B22_PCREL_X),
_,
173 static const std::map<unsigned, std::vector<unsigned>>
StdFixups = {
179 P(_DTPREL_16),
_,
_,
_,
210 _,
_,
P(_PLT_B22_PCREL),
_,
217 _,
_,
_,
P(_TPREL_11_X),
219 P(_TPREL_16),
_,
_,
_,
229 P(_GD_GOT_16),
_,
_,
_,
240 _,
_,
P(_GD_PLT_B22_PCREL),
_,
249 P(_GPREL16_0),
_,
_,
_,
279 P(_IE_GOT_16),
_,
_,
_,
289 P(_LD_GOT_16),
_,
_,
_,
300 _,
_,
P(_LD_PLT_B22_PCREL),
_,
328 _,
P(_B13_PCREL),
_,
P(_B15_PCREL),
330 _,
_,
P(_B22_PCREL),
_,
340 uint32_t HexagonMCCodeEmitter::parseBits(
size_t Last,
MCInst const &MCB,
341 MCInst const &MCI)
const {
343 if (State.Index == 0) {
346 assert(State.Index != Last);
350 if (State.Index == 1) {
353 assert(State.Index != Last);
358 assert(State.Index == Last);
361 if (State.Index == Last)
375 State.Extended =
false;
383 verifyInstructionPredicates(HMI, Features);
385 EncodeSingleInstruction(HMI, OS,
Fixups, STI, parseBits(Last, HMB, HMI));
393 unsigned Producer2) {
394 return (Consumer == Producer) || (Consumer == Producer2) ||
409 "pseudo-instruction found");
413 Binary = getBinaryCodeForInstr(
MI,
Fixups, STI);
414 unsigned Opc =
MI.getOpcode();
418 if (!Binary && Opc != DuplexIClass0 && Opc != A4_ext) {
426 if (Opc >= Hexagon::DuplexIClass0 && Opc <= Hexagon::DuplexIClassF) {
428 "Emitting duplex without duplex parse bits");
429 unsigned DupIClass =
MI.getOpcode() - Hexagon::DuplexIClass0;
433 Binary = ((DupIClass & 0xE) << (29 - 1)) | ((DupIClass & 0x1) << 13);
435 const MCInst *Sub0 =
MI.getOperand(0).getInst();
436 const MCInst *Sub1 =
MI.getOperand(1).getInst();
439 unsigned SubBits0 = getBinaryCodeForInstr(*Sub0,
Fixups, STI);
441 State.SubInst1 =
true;
442 unsigned SubBits1 = getBinaryCodeForInstr(*Sub1,
Fixups, STI);
443 State.SubInst1 =
false;
445 Binary |= SubBits0 | (SubBits1 << 16);
454 Stream <<
"Unrecognized relocation combination: width=" <<
Width
466 using namespace Hexagon;
471 for (
auto I = Instrs.begin(),
N = Instrs.end();
I !=
N; ++
I) {
472 if (
I->getInst() != &
MI)
474 assert(
I+1 !=
N &&
"Extender cannot be last in packet");
475 const MCInst &NextI = *(
I+1)->getInst();
484 static const std::map<unsigned,unsigned> Relocs = {
498 auto F = Relocs.find(VarKind);
499 if (
F != Relocs.end())
507 static const std::map<unsigned,unsigned> RelocsLo = {
519 static const std::map<unsigned,unsigned> RelocsHi = {
533 case Hexagon::A2_tfril: {
534 auto F = RelocsLo.find(VarKind);
535 if (
F != RelocsLo.end())
540 case Hexagon::A2_tfrih: {
541 auto F = RelocsHi.find(VarKind);
542 if (
F != RelocsHi.end())
577 unsigned HexagonMCCodeEmitter::getExprOpValue(
const MCInst &
MI,
580 if (isa<HexagonMCExpr>(ME))
583 if (ME->evaluateAsAbsolute(
Value)) {
590 if (State.Extended && InstExtendable && !IsSub0) {
591 unsigned OpIdx = ~0u;
592 for (
unsigned I = 0,
E =
MI.getNumOperands();
I !=
E; ++
I) {
593 if (&MO != &
MI.getOperand(
I))
626 <<
"\nOpcode: " << Opc <<
"\nRelocation bits: "
627 << FixupWidth <<
"\nAddend: " << State.Addend
628 <<
"\nVariant: " <<
unsigned(VarKind)
629 <<
"\n----------------------------------------\n");
634 if (FixupWidth == 16 && !State.Extended) {
648 for (
const MCPhysReg *U =
D.getImplicitUses(); U && *U; ++U)
649 if (*U == Hexagon::GP)
665 switch (FixupWidth) {
677 else if (FixupWidth == 7 && BranchOrCR)
690 auto FindVK = FixupTable.find(VarKind);
691 if (FindVK != FixupTable.end())
715 size_t OperandNumber = ~0U;
716 for (
unsigned i = 0,
n =
MI.getNumOperands();
i <
n; ++
i)
717 if (&
MI.getOperand(
i) == &MO) {
721 assert((OperandNumber != ~0U) &&
"Operand not found");
726 unsigned SOffset = 0;
727 unsigned VOffset = 0;
729 unsigned DefReg1 = Hexagon::NoRegister;
730 unsigned DefReg2 = Hexagon::NoRegister;
733 const MCOperand *
I = Instrs.begin() + State.Index - 1;
736 assert(
I != Instrs.begin() - 1 &&
"Couldn't find producer");
737 MCInst const &Inst = *
I->getInst();
741 DefReg1 = Hexagon::NoRegister;
742 DefReg2 = Hexagon::NoRegister;
761 "Unpredicated consumer depending on predicated producer");
779 case GeneralSubRegsRegClassID:
780 case GeneralDoubleLow8RegsRegClassID:
785 return MCT.getRegisterInfo()->getEncodingValue(
Reg);
796 #define ENABLE_INSTR_PREDICATE_VERIFIER
797 #include "HexagonGenMCCodeEmitter.inc"
VariantKind getKind() const
@ fixup_Hexagon_DTPREL_LO16
unsigned getOpcode() const
Return the opcode number for this descriptor.
@ fixup_Hexagon_TPREL_HI16
@ fixup_Hexagon_B22_PCREL
@ fixup_Hexagon_6_PCREL_X
This is an optimization pass for GlobalISel generic memory operations.
const MCInstrDesc & getDesc(MCInstrInfo const &MCII, MCInst const &MCI)
static const std::map< unsigned, std::vector< unsigned > > ExtFixups
@ fixup_Hexagon_LD_PLT_B22_PCREL_X
static Lanai::Fixups FixupKind(const MCExpr *Expr)
@ fixup_Hexagon_B32_PCREL_X
@ fixup_Hexagon_GD_GOT_LO16
@ fixup_Hexagon_GD_GOT_32_6_X
bool isBranch() const
Returns true if this is a conditional, unconditional, or indirect branch.
unsigned getDuplexRegisterNumbering(unsigned Reg)
Context object for machine code objects.
@ fixup_Hexagon_DTPREL_32_6_X
unsigned getMachineOpValue(MCInst const &MI, MCOperand const &MO, SmallVectorImpl< MCFixup > &Fixups, MCSubtargetInfo const &STI) const
Return binary encoding of operand.
A raw_ostream that writes to an std::string.
static bool RegisterMatches(unsigned Consumer, unsigned Producer, unsigned Producer2)
static const MCConstantExpr * create(int64_t Value, MCContext &Ctx, bool PrintInHex=false, unsigned SizeInBytes=0)
static bool isPCRel(unsigned Kind)
#define HEXAGON_INSTR_SIZE
@ fixup_Hexagon_IE_GOT_HI16
static MCFixup create(uint32_t Offset, const MCExpr *Value, MCFixupKind Kind, SMLoc Loc=SMLoc())
Reg
All possible values of the reg field in the ModR/M byte.
@ fixup_Hexagon_B9_PCREL_X
@ fixup_Hexagon_GPREL16_0
@ fixup_Hexagon_B13_PCREL_X
unsigned getExtentAlignment(MCInstrInfo const &MCII, MCInst const &MCI)
bool isImmext(MCInst const &MCI)
Container class for subtarget features.
bool isSubInstruction(MCInst const &MCI)
@ fixup_Hexagon_LD_GOT_LO16
Instances of this class represent a single low-level machine instruction.
@ fixup_Hexagon_GOTREL_32_6_X
Binary assembler expressions.
@ fixup_Hexagon_DTPREL_HI16
@ fixup_Hexagon_GPREL16_3
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
@ fixup_Hexagon_IE_GOT_32_6_X
@ fixup_Hexagon_TPREL_LO16
bool isPredicatedTrue(MCInstrInfo const &MCII, MCInst const &MCI)
bool s27_2_reloc(MCExpr const &Expr)
@ fixup_Hexagon_GD_PLT_B22_PCREL
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
bool hasNewValue2(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn produces a second value.
bool isNewValue(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn expects newly produced value.
bool isPredicated(MCInstrInfo const &MCII, MCInst const &MCI)
(vector float) vec_cmpeq(*A, *B) C
bool isVector(MCInstrInfo const &MCII, MCInst const &MCI)
bool isBundle(MCInst const &MCI)
@ fixup_Hexagon_LD_PLT_B32_PCREL_X
StringRef getName(MCInstrInfo const &MCII, MCInst const &MCI)
Describe properties that are true of each instruction in the target description file.
iterator_range< Hexagon::PacketIterator > bundleInstructions(MCInstrInfo const &MCII, MCInst const &MCI)
const FeatureBitset & getFeatureBits() const
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
STATISTIC(NumFunctions, "Total number of functions")
unsigned getExtentBits(MCInstrInfo const &MCII, MCInst const &MCI)
This class implements an extremely fast bulk output stream that can only output to a stream.
void encodeInstruction(MCInst const &MI, raw_ostream &OS, SmallVectorImpl< MCFixup > &Fixups, MCSubtargetInfo const &STI) const override
Emit the bundle.
static const std::map< unsigned, std::vector< unsigned > > StdFixups
bool hasNewValue(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn produces a value.
constexpr size_t array_lengthof(T(&)[N])
Find the length of an array.
size_t bundleSize(MCInst const &MCI)
@ Binary
Binary expressions.
@ fixup_Hexagon_GD_PLT_B22_PCREL_X
@ fixup_Hexagon_GPREL16_1
@ fixup_Hexagon_B15_PCREL_X
@ fixup_Hexagon_LD_GOT_HI16
static GCRegistry::Add< StatepointGC > D("statepoint-example", "an example strategy for statepoint")
bool isCall() const
Return true if the instruction is a call.
@ fixup_Hexagon_IE_32_6_X
unsigned SubregisterBit(unsigned Consumer, unsigned Producer, unsigned Producer2)
static Register UseReg(const MachineOperand &MO)
@ fixup_Hexagon_TPREL_32_6_X
@ fixup_Hexagon_GOTREL_HI16
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
@ fixup_Hexagon_GOT_32_6_X
bool isDuplex(MCInstrInfo const &MCII, MCInst const &MCI)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
@ fixup_Hexagon_GOTREL_LO16
@ fixup_Hexagon_GD_GOT_HI16
Represent a reference to a symbol from inside an expression.
bool isOuterLoop(MCInst const &MCI)
static const MCBinaryExpr * createAdd(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
static const unsigned fixup_Invalid
bool isExtentSigned(MCInstrInfo const &MCII, MCInst const &MCI)
@ fixup_Hexagon_LD_PLT_B22_PCREL
PowerPC TLS Dynamic Call Fixup
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
const MCOperand & getNewValueOperand(MCInstrInfo const &MCII, MCInst const &MCI)
void EncodeSingleInstruction(const MCInst &MI, raw_ostream &OS, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI, uint32_t Parse) const
EncodeSingleInstruction - Emit a single.
bool isPseudo(uint64_t TSFlags)
unsigned short getExtendableOp(MCInstrInfo const &MCII, MCInst const &MCI)
@ fixup_Hexagon_GPREL16_2
@ fixup_Hexagon_GD_PLT_B32_PCREL_X
const MCOperand & getNewValueOperand2(MCInstrInfo const &MCII, MCInst const &MCI)
static void raise_relocation_error(unsigned Width, unsigned Kind)
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Interface to description of machine instruction set.
@ fixup_Hexagon_B22_PCREL_X
unsigned getType(MCInstrInfo const &MCII, MCInst const &MCI)
Return the Hexagon ISA class for the insn.
MCCodeEmitter - Generic instruction encoding interface.
@ fixup_Hexagon_B7_PCREL_X
const MCExpr * getExpr() const
bool IsSingleConsumerRefPairProducer(unsigned Producer, unsigned Consumer)
@ fixup_Hexagon_PLT_B22_PCREL
@ fixup_Hexagon_LD_GOT_32_6_X
MCFixupKind
Extensible enumeration to represent the type of a fixup.
MCCodeEmitter * createHexagonMCCodeEmitter(const MCInstrInfo &MCII, MCContext &MCT)
@ fixup_Hexagon_B15_PCREL
@ fixup_Hexagon_IE_GOT_LO16
@ SymbolRef
References to labels and assigned expressions.
const MCExpr & getExpr(MCExpr const &Expr)
@ fixup_Hexagon_B13_PCREL
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Instances of this class represent operands of the MCInst class.
bool isExtended(MCInstrInfo const &MCII, MCInst const &MCI)
The same transformation can work with an even modulo with the addition of a and shrink the compare RHS by the same amount Unless the target supports that transformation probably isn t worthwhile The transformation can also easily be made to work with non zero equality for n
Generic base class for all target subtargets.
Encode information on a single operation to perform on a byte sequence (e.g., an encoded instruction)...
LLVM Value Representation.
Base class for the full range of assembler expressions which are needed for parsing.
bool isExtendable(MCInstrInfo const &MCII, MCInst const &MCI)
unsigned getReg() const
Returns the register number.
bool isInnerLoop(MCInst const &MCI)