31 #define DEBUG_TYPE "mccodeemitter"
33 STATISTIC(MCNumEmitted,
"Number of MC instructions emitted");
39 class LanaiMCCodeEmitter :
public MCCodeEmitter {
41 LanaiMCCodeEmitter(
const MCInstrInfo &MCII, MCContext &
C) {}
42 LanaiMCCodeEmitter(
const LanaiMCCodeEmitter &) =
delete;
43 void operator=(
const LanaiMCCodeEmitter &) =
delete;
44 ~LanaiMCCodeEmitter()
override =
default;
51 uint64_t getBinaryCodeForInstr(
const MCInst &Inst,
52 SmallVectorImpl<MCFixup> &
Fixups,
53 const MCSubtargetInfo &SubtargetInfo)
const;
57 unsigned getMachineOpValue(
const MCInst &Inst,
const MCOperand &MCOp,
58 SmallVectorImpl<MCFixup> &
Fixups,
59 const MCSubtargetInfo &SubtargetInfo)
const;
61 unsigned getRiMemoryOpValue(
const MCInst &Inst,
unsigned OpNo,
62 SmallVectorImpl<MCFixup> &
Fixups,
63 const MCSubtargetInfo &SubtargetInfo)
const;
65 unsigned getRrMemoryOpValue(
const MCInst &Inst,
unsigned OpNo,
66 SmallVectorImpl<MCFixup> &
Fixups,
67 const MCSubtargetInfo &SubtargetInfo)
const;
69 unsigned getSplsOpValue(
const MCInst &Inst,
unsigned OpNo,
70 SmallVectorImpl<MCFixup> &
Fixups,
71 const MCSubtargetInfo &SubtargetInfo)
const;
74 SmallVectorImpl<MCFixup> &
Fixups,
75 const MCSubtargetInfo &SubtargetInfo)
const;
77 void encodeInstruction(
const MCInst &Inst, raw_ostream &Ostream,
78 SmallVectorImpl<MCFixup> &
Fixups,
79 const MCSubtargetInfo &SubtargetInfo)
const override;
81 unsigned adjustPqBitsRmAndRrm(
const MCInst &Inst,
unsigned Value,
82 const MCSubtargetInfo &STI)
const;
84 unsigned adjustPqBitsSpls(
const MCInst &Inst,
unsigned Value,
85 const MCSubtargetInfo &STI)
const;
91 if (isa<MCSymbolRefExpr>(Expr))
93 if (
const LanaiMCExpr *McExpr = dyn_cast<LanaiMCExpr>(Expr)) {
109 unsigned LanaiMCCodeEmitter::getMachineOpValue(
110 const MCInst &Inst,
const MCOperand &MCOp, SmallVectorImpl<MCFixup> &
Fixups,
111 const MCSubtargetInfo &SubtargetInfo)
const {
115 return static_cast<unsigned>(MCOp.getImm());
119 const MCExpr *Expr = MCOp.getExpr();
123 const MCBinaryExpr *
BinaryExpr =
static_cast<const MCBinaryExpr *
>(Expr);
136 unsigned PBitShift,
unsigned QBitShift) {
143 Value &= ~(1 << PBitShift);
147 Value |= (1 << PBitShift);
151 "Expected register operand.");
152 Value &= ~(1 << QBitShift);
155 Value |= (1 << QBitShift);
161 LanaiMCCodeEmitter::adjustPqBitsRmAndRrm(
const MCInst &Inst,
unsigned Value,
162 const MCSubtargetInfo &STI)
const {
167 LanaiMCCodeEmitter::adjustPqBitsSpls(
const MCInst &Inst,
unsigned Value,
168 const MCSubtargetInfo &STI)
const {
172 void LanaiMCCodeEmitter::encodeInstruction(
173 const MCInst &Inst, raw_ostream &Ostream, SmallVectorImpl<MCFixup> &
Fixups,
174 const MCSubtargetInfo &SubtargetInfo)
const {
176 unsigned Value = getBinaryCodeForInstr(Inst,
Fixups, SubtargetInfo);
180 for (
int i = (4 - 1) * 8;
i >= 0;
i -= 8)
181 Ostream <<
static_cast<char>((
Value >>
i) & 0xff);
185 unsigned LanaiMCCodeEmitter::getRiMemoryOpValue(
186 const MCInst &Inst,
unsigned OpNo, SmallVectorImpl<MCFixup> &
Fixups,
187 const MCSubtargetInfo &SubtargetInfo)
const {
189 const MCOperand Op1 = Inst.getOperand(OpNo + 0);
190 const MCOperand Op2 = Inst.getOperand(OpNo + 1);
191 const MCOperand AluOp = Inst.getOperand(OpNo + 2);
193 assert(Op1.isReg() &&
"First operand is not register.");
194 assert((Op2.isImm() || Op2.isExpr()) &&
195 "Second operand is neither an immediate nor an expression.");
197 "Register immediate only supports addition operator");
202 "Constant value truncated (limited to 16-bit)");
204 Encoding |= (Op2.getImm() & 0xffff);
205 if (Op2.getImm() != 0) {
207 Encoding |= (0
x3 << 16);
209 Encoding |= (0x1 << 16);
212 getMachineOpValue(Inst, Op2,
Fixups, SubtargetInfo);
217 unsigned LanaiMCCodeEmitter::getRrMemoryOpValue(
218 const MCInst &Inst,
unsigned OpNo, SmallVectorImpl<MCFixup> &
Fixups,
219 const MCSubtargetInfo &SubtargetInfo)
const {
221 const MCOperand Op1 = Inst.getOperand(OpNo + 0);
222 const MCOperand Op2 = Inst.getOperand(OpNo + 1);
223 const MCOperand AluMCOp = Inst.getOperand(OpNo + 2);
225 assert(Op1.isReg() &&
"First operand is not register.");
227 assert(Op2.isReg() &&
"Second operand is not register.");
230 assert(AluMCOp.isImm() &&
"Third operator is not immediate.");
232 unsigned AluOp = AluMCOp.getImm();
236 Encoding |= (0x3 << 8);
238 Encoding |= (0x1 << 8);
256 LanaiMCCodeEmitter::getSplsOpValue(
const MCInst &Inst,
unsigned OpNo,
257 SmallVectorImpl<MCFixup> &
Fixups,
258 const MCSubtargetInfo &SubtargetInfo)
const {
260 const MCOperand Op1 = Inst.getOperand(OpNo + 0);
261 const MCOperand Op2 = Inst.getOperand(OpNo + 1);
262 const MCOperand AluOp = Inst.getOperand(OpNo + 2);
264 assert(Op1.isReg() &&
"First operand is not register.");
265 assert((Op2.isImm() || Op2.isExpr()) &&
266 "Second operand is neither an immediate nor an expression.");
268 "Register immediate only supports addition operator");
272 assert(isInt<10>(Op2.getImm()) &&
273 "Constant value truncated (limited to 10-bit)");
275 Encoding |= (Op2.getImm() & 0x3ff);
276 if (Op2.getImm() != 0) {
278 Encoding |= (0
x3 << 10);
280 Encoding |= (0x1 << 10);
283 getMachineOpValue(Inst, Op2,
Fixups, SubtargetInfo);
289 const MCInst &Inst,
unsigned OpNo, SmallVectorImpl<MCFixup> &
Fixups,
290 const MCSubtargetInfo &SubtargetInfo)
const {
291 const MCOperand &MCOp = Inst.getOperand(OpNo);
292 if (MCOp.isReg() || MCOp.isImm())
293 return getMachineOpValue(Inst, MCOp,
Fixups, SubtargetInfo);
301 #include "LanaiGenMCCodeEmitter.inc"
308 return new LanaiMCCodeEmitter(InstrInfo, context);