LLVM 18.0.0git
LanaiMCCodeEmitter.cpp
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1//===-- LanaiMCCodeEmitter.cpp - Convert Lanai code to machine code -------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements the LanaiMCCodeEmitter class.
10//
11//===----------------------------------------------------------------------===//
12
13#include "LanaiAluCode.h"
18#include "llvm/ADT/Statistic.h"
20#include "llvm/MC/MCExpr.h"
21#include "llvm/MC/MCFixup.h"
22#include "llvm/MC/MCInst.h"
23#include "llvm/MC/MCInstrInfo.h"
29#include <cassert>
30#include <cstdint>
31
32#define DEBUG_TYPE "mccodeemitter"
33
34STATISTIC(MCNumEmitted, "Number of MC instructions emitted");
35
36namespace llvm {
37
38namespace {
39
40class LanaiMCCodeEmitter : public MCCodeEmitter {
41public:
42 LanaiMCCodeEmitter(const MCInstrInfo &MCII, MCContext &C) {}
43 LanaiMCCodeEmitter(const LanaiMCCodeEmitter &) = delete;
44 void operator=(const LanaiMCCodeEmitter &) = delete;
45 ~LanaiMCCodeEmitter() override = default;
46
47 // The functions below are called by TableGen generated functions for getting
48 // the binary encoding of instructions/opereands.
49
50 // getBinaryCodeForInstr - TableGen'erated function for getting the
51 // binary encoding for an instruction.
52 uint64_t getBinaryCodeForInstr(const MCInst &Inst,
53 SmallVectorImpl<MCFixup> &Fixups,
54 const MCSubtargetInfo &SubtargetInfo) const;
55
56 // getMachineOpValue - Return binary encoding of operand. If the machine
57 // operand requires relocation, record the relocation and return zero.
58 unsigned getMachineOpValue(const MCInst &Inst, const MCOperand &MCOp,
59 SmallVectorImpl<MCFixup> &Fixups,
60 const MCSubtargetInfo &SubtargetInfo) const;
61
62 unsigned getRiMemoryOpValue(const MCInst &Inst, unsigned OpNo,
63 SmallVectorImpl<MCFixup> &Fixups,
64 const MCSubtargetInfo &SubtargetInfo) const;
65
66 unsigned getRrMemoryOpValue(const MCInst &Inst, unsigned OpNo,
67 SmallVectorImpl<MCFixup> &Fixups,
68 const MCSubtargetInfo &SubtargetInfo) const;
69
70 unsigned getSplsOpValue(const MCInst &Inst, unsigned OpNo,
71 SmallVectorImpl<MCFixup> &Fixups,
72 const MCSubtargetInfo &SubtargetInfo) const;
73
74 unsigned getBranchTargetOpValue(const MCInst &Inst, unsigned OpNo,
75 SmallVectorImpl<MCFixup> &Fixups,
76 const MCSubtargetInfo &SubtargetInfo) const;
77
78 void encodeInstruction(const MCInst &Inst, SmallVectorImpl<char> &CB,
79 SmallVectorImpl<MCFixup> &Fixups,
80 const MCSubtargetInfo &SubtargetInfo) const override;
81
82 unsigned adjustPqBitsRmAndRrm(const MCInst &Inst, unsigned Value,
83 const MCSubtargetInfo &STI) const;
84
85 unsigned adjustPqBitsSpls(const MCInst &Inst, unsigned Value,
86 const MCSubtargetInfo &STI) const;
87};
88
89} // end anonymous namespace
90
91static Lanai::Fixups FixupKind(const MCExpr *Expr) {
92 if (isa<MCSymbolRefExpr>(Expr))
94 if (const LanaiMCExpr *McExpr = dyn_cast<LanaiMCExpr>(Expr)) {
95 LanaiMCExpr::VariantKind ExprKind = McExpr->getKind();
96 switch (ExprKind) {
103 }
104 }
105 return Lanai::Fixups(0);
106}
107
108// getMachineOpValue - Return binary encoding of operand. If the machine
109// operand requires relocation, record the relocation and return zero.
110unsigned LanaiMCCodeEmitter::getMachineOpValue(
111 const MCInst &Inst, const MCOperand &MCOp, SmallVectorImpl<MCFixup> &Fixups,
112 const MCSubtargetInfo &SubtargetInfo) const {
113 if (MCOp.isReg())
114 return getLanaiRegisterNumbering(MCOp.getReg());
115 if (MCOp.isImm())
116 return static_cast<unsigned>(MCOp.getImm());
117
118 // MCOp must be an expression
119 assert(MCOp.isExpr());
120 const MCExpr *Expr = MCOp.getExpr();
121
122 // Extract the symbolic reference side of a binary expression.
123 if (Expr->getKind() == MCExpr::Binary) {
124 const MCBinaryExpr *BinaryExpr = static_cast<const MCBinaryExpr *>(Expr);
125 Expr = BinaryExpr->getLHS();
126 }
127
128 assert(isa<LanaiMCExpr>(Expr) || Expr->getKind() == MCExpr::SymbolRef);
129 // Push fixup (all info is contained within)
130 Fixups.push_back(
131 MCFixup::create(0, MCOp.getExpr(), MCFixupKind(FixupKind(Expr))));
132 return 0;
133}
134
135// Helper function to adjust P and Q bits on load and store instructions.
136static unsigned adjustPqBits(const MCInst &Inst, unsigned Value,
137 unsigned PBitShift, unsigned QBitShift) {
138 const MCOperand AluOp = Inst.getOperand(3);
139 unsigned AluCode = AluOp.getImm();
140
141 // Set the P bit to one iff the immediate is nonzero and not a post-op
142 // instruction.
143 const MCOperand Op2 = Inst.getOperand(2);
144 Value &= ~(1 << PBitShift);
145 if (!LPAC::isPostOp(AluCode) &&
146 ((Op2.isImm() && Op2.getImm() != 0) ||
147 (Op2.isReg() && Op2.getReg() != Lanai::R0) || (Op2.isExpr())))
148 Value |= (1 << PBitShift);
149
150 // Set the Q bit to one iff it is a post- or pre-op instruction.
151 assert(Inst.getOperand(0).isReg() && Inst.getOperand(1).isReg() &&
152 "Expected register operand.");
153 Value &= ~(1 << QBitShift);
154 if (LPAC::modifiesOp(AluCode) && ((Op2.isImm() && Op2.getImm() != 0) ||
155 (Op2.isReg() && Op2.getReg() != Lanai::R0)))
156 Value |= (1 << QBitShift);
157
158 return Value;
159}
160
161unsigned
162LanaiMCCodeEmitter::adjustPqBitsRmAndRrm(const MCInst &Inst, unsigned Value,
163 const MCSubtargetInfo &STI) const {
164 return adjustPqBits(Inst, Value, 17, 16);
165}
166
167unsigned
168LanaiMCCodeEmitter::adjustPqBitsSpls(const MCInst &Inst, unsigned Value,
169 const MCSubtargetInfo &STI) const {
170 return adjustPqBits(Inst, Value, 11, 10);
171}
172
173void LanaiMCCodeEmitter::encodeInstruction(
174 const MCInst &Inst, SmallVectorImpl<char> &CB,
175 SmallVectorImpl<MCFixup> &Fixups,
176 const MCSubtargetInfo &SubtargetInfo) const {
177 // Get instruction encoding and emit it
178 unsigned Value = getBinaryCodeForInstr(Inst, Fixups, SubtargetInfo);
179 ++MCNumEmitted; // Keep track of the number of emitted insns.
180
181 support::endian::write<uint32_t>(CB, Value, support::big);
182}
183
184// Encode Lanai Memory Operand
185unsigned LanaiMCCodeEmitter::getRiMemoryOpValue(
186 const MCInst &Inst, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups,
187 const MCSubtargetInfo &SubtargetInfo) const {
188 unsigned Encoding;
189 const MCOperand Op1 = Inst.getOperand(OpNo + 0);
190 const MCOperand Op2 = Inst.getOperand(OpNo + 1);
191 const MCOperand AluOp = Inst.getOperand(OpNo + 2);
192
193 assert(Op1.isReg() && "First operand is not register.");
194 assert((Op2.isImm() || Op2.isExpr()) &&
195 "Second operand is neither an immediate nor an expression.");
196 assert((LPAC::getAluOp(AluOp.getImm()) == LPAC::ADD) &&
197 "Register immediate only supports addition operator");
198
199 Encoding = (getLanaiRegisterNumbering(Op1.getReg()) << 18);
200 if (Op2.isImm()) {
201 assert(isInt<16>(Op2.getImm()) &&
202 "Constant value truncated (limited to 16-bit)");
203
204 Encoding |= (Op2.getImm() & 0xffff);
205 if (Op2.getImm() != 0) {
206 if (LPAC::isPreOp(AluOp.getImm()))
207 Encoding |= (0x3 << 16);
208 if (LPAC::isPostOp(AluOp.getImm()))
209 Encoding |= (0x1 << 16);
210 }
211 } else
212 getMachineOpValue(Inst, Op2, Fixups, SubtargetInfo);
213
214 return Encoding;
215}
216
217unsigned LanaiMCCodeEmitter::getRrMemoryOpValue(
218 const MCInst &Inst, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups,
219 const MCSubtargetInfo &SubtargetInfo) const {
220 unsigned Encoding;
221 const MCOperand Op1 = Inst.getOperand(OpNo + 0);
222 const MCOperand Op2 = Inst.getOperand(OpNo + 1);
223 const MCOperand AluMCOp = Inst.getOperand(OpNo + 2);
224
225 assert(Op1.isReg() && "First operand is not register.");
226 Encoding = (getLanaiRegisterNumbering(Op1.getReg()) << 15);
227 assert(Op2.isReg() && "Second operand is not register.");
228 Encoding |= (getLanaiRegisterNumbering(Op2.getReg()) << 10);
229
230 assert(AluMCOp.isImm() && "Third operator is not immediate.");
231 // Set BBB
232 unsigned AluOp = AluMCOp.getImm();
233 Encoding |= LPAC::encodeLanaiAluCode(AluOp) << 5;
234 // Set P and Q
235 if (LPAC::isPreOp(AluOp))
236 Encoding |= (0x3 << 8);
237 if (LPAC::isPostOp(AluOp))
238 Encoding |= (0x1 << 8);
239 // Set JJJJ
240 switch (LPAC::getAluOp(AluOp)) {
241 case LPAC::SHL:
242 case LPAC::SRL:
243 Encoding |= 0x10;
244 break;
245 case LPAC::SRA:
246 Encoding |= 0x18;
247 break;
248 default:
249 break;
250 }
251
252 return Encoding;
253}
254
255unsigned
256LanaiMCCodeEmitter::getSplsOpValue(const MCInst &Inst, unsigned OpNo,
257 SmallVectorImpl<MCFixup> &Fixups,
258 const MCSubtargetInfo &SubtargetInfo) const {
259 unsigned Encoding;
260 const MCOperand Op1 = Inst.getOperand(OpNo + 0);
261 const MCOperand Op2 = Inst.getOperand(OpNo + 1);
262 const MCOperand AluOp = Inst.getOperand(OpNo + 2);
263
264 assert(Op1.isReg() && "First operand is not register.");
265 assert((Op2.isImm() || Op2.isExpr()) &&
266 "Second operand is neither an immediate nor an expression.");
267 assert((LPAC::getAluOp(AluOp.getImm()) == LPAC::ADD) &&
268 "Register immediate only supports addition operator");
269
270 Encoding = (getLanaiRegisterNumbering(Op1.getReg()) << 12);
271 if (Op2.isImm()) {
272 assert(isInt<10>(Op2.getImm()) &&
273 "Constant value truncated (limited to 10-bit)");
274
275 Encoding |= (Op2.getImm() & 0x3ff);
276 if (Op2.getImm() != 0) {
277 if (LPAC::isPreOp(AluOp.getImm()))
278 Encoding |= (0x3 << 10);
279 if (LPAC::isPostOp(AluOp.getImm()))
280 Encoding |= (0x1 << 10);
281 }
282 } else
283 getMachineOpValue(Inst, Op2, Fixups, SubtargetInfo);
284
285 return Encoding;
286}
287
288unsigned LanaiMCCodeEmitter::getBranchTargetOpValue(
289 const MCInst &Inst, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups,
290 const MCSubtargetInfo &SubtargetInfo) const {
291 const MCOperand &MCOp = Inst.getOperand(OpNo);
292 if (MCOp.isReg() || MCOp.isImm())
293 return getMachineOpValue(Inst, MCOp, Fixups, SubtargetInfo);
294
295 Fixups.push_back(MCFixup::create(
296 0, MCOp.getExpr(), static_cast<MCFixupKind>(Lanai::FIXUP_LANAI_25)));
297
298 return 0;
299}
300
301#include "LanaiGenMCCodeEmitter.inc"
302
303} // end namespace llvm
304
307 MCContext &context) {
308 return new LanaiMCCodeEmitter(InstrInfo, context);
309}
static uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, unsigned FixupKind, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI)
getBranchTargetOpValue - Helper function to get the branch target operand, which is either an immedia...
return InstrInfo
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file defines the SmallVector class.
This file defines the 'Statistic' class, which is designed to be an easy way to expose various metric...
#define STATISTIC(VARNAME, DESC)
Definition: Statistic.h:167
MCCodeEmitter - Generic instruction encoding interface.
Definition: MCCodeEmitter.h:21
Context object for machine code objects.
Definition: MCContext.h:76
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:35
@ SymbolRef
References to labels and assigned expressions.
Definition: MCExpr.h:40
@ Binary
Binary expressions.
Definition: MCExpr.h:38
static MCFixup create(uint32_t Offset, const MCExpr *Value, MCFixupKind Kind, SMLoc Loc=SMLoc())
Definition: MCFixup.h:86
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:206
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:26
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:36
int64_t getImm() const
Definition: MCInst.h:80
bool isImm() const
Definition: MCInst.h:62
unsigned getReg() const
Returns the register number.
Definition: MCInst.h:69
bool isReg() const
Definition: MCInst.h:61
bool isExpr() const
Definition: MCInst.h:65
LLVM Value Representation.
Definition: Value.h:74
@ C
The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
static bool isPreOp(unsigned AluOp)
Definition: LanaiAluCode.h:57
static unsigned getAluOp(unsigned AluOp)
Definition: LanaiAluCode.h:52
static unsigned encodeLanaiAluCode(unsigned AluOp)
Definition: LanaiAluCode.h:47
static bool isPostOp(unsigned AluOp)
Definition: LanaiAluCode.h:59
static bool modifiesOp(unsigned AluOp)
Definition: LanaiAluCode.h:71
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
MCCodeEmitter * createLanaiMCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx)
MCFixupKind
Extensible enumeration to represent the type of a fixup.
Definition: MCFixup.h:21
static unsigned adjustPqBits(const MCInst &Inst, unsigned Value, unsigned PBitShift, unsigned QBitShift)
static unsigned getLanaiRegisterNumbering(unsigned Reg)
Definition: LanaiBaseInfo.h:40