LLVM  14.0.0git
ARMMCCodeEmitter.cpp
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1 //===-- ARM/ARMMCCodeEmitter.cpp - Convert ARM code to machine code -------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the ARMMCCodeEmitter class.
10 //
11 //===----------------------------------------------------------------------===//
12 
16 #include "MCTargetDesc/ARMMCExpr.h"
17 #include "llvm/ADT/APFloat.h"
18 #include "llvm/ADT/APInt.h"
19 #include "llvm/ADT/SmallVector.h"
20 #include "llvm/ADT/Statistic.h"
21 #include "llvm/ADT/Triple.h"
22 #include "llvm/MC/MCCodeEmitter.h"
23 #include "llvm/MC/MCContext.h"
24 #include "llvm/MC/MCExpr.h"
25 #include "llvm/MC/MCFixup.h"
26 #include "llvm/MC/MCInst.h"
27 #include "llvm/MC/MCInstrDesc.h"
28 #include "llvm/MC/MCInstrInfo.h"
29 #include "llvm/MC/MCRegisterInfo.h"
31 #include "llvm/Support/Casting.h"
32 #include "llvm/Support/Compiler.h"
36 #include <algorithm>
37 #include <cassert>
38 #include <cstdint>
39 #include <cstdlib>
40 
41 using namespace llvm;
42 
43 #define DEBUG_TYPE "mccodeemitter"
44 
45 STATISTIC(MCNumEmitted, "Number of MC instructions emitted.");
46 STATISTIC(MCNumCPRelocations, "Number of constant pool relocations created.");
47 
48 namespace {
49 
50 class ARMMCCodeEmitter : public MCCodeEmitter {
51  const MCInstrInfo &MCII;
52  MCContext &CTX;
53  bool IsLittleEndian;
54 
55 public:
56  ARMMCCodeEmitter(const MCInstrInfo &mcii, MCContext &ctx, bool IsLittle)
57  : MCII(mcii), CTX(ctx), IsLittleEndian(IsLittle) {
58  }
59  ARMMCCodeEmitter(const ARMMCCodeEmitter &) = delete;
60  ARMMCCodeEmitter &operator=(const ARMMCCodeEmitter &) = delete;
61  ~ARMMCCodeEmitter() override = default;
62 
63  bool isThumb(const MCSubtargetInfo &STI) const {
64  return STI.getFeatureBits()[ARM::ModeThumb];
65  }
66 
67  bool isThumb2(const MCSubtargetInfo &STI) const {
68  return isThumb(STI) && STI.getFeatureBits()[ARM::FeatureThumb2];
69  }
70 
71  bool isTargetMachO(const MCSubtargetInfo &STI) const {
72  const Triple &TT = STI.getTargetTriple();
73  return TT.isOSBinFormatMachO();
74  }
75 
76  unsigned getMachineSoImmOpValue(unsigned SoImm) const;
77 
78  // getBinaryCodeForInstr - TableGen'erated function for getting the
79  // binary encoding for an instruction.
80  uint64_t getBinaryCodeForInstr(const MCInst &MI,
82  const MCSubtargetInfo &STI) const;
83 
84  /// getMachineOpValue - Return binary encoding of operand. If the machine
85  /// operand requires relocation, record the relocation and return zero.
86  unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
88  const MCSubtargetInfo &STI) const;
89 
90  /// getHiLo16ImmOpValue - Return the encoding for the hi / low 16-bit of
91  /// the specified operand. This is used for operands with :lower16: and
92  /// :upper16: prefixes.
93  uint32_t getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx,
95  const MCSubtargetInfo &STI) const;
96 
97  bool EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx,
98  unsigned &Reg, unsigned &Imm,
100  const MCSubtargetInfo &STI) const;
101 
102  /// getThumbBLTargetOpValue - Return encoding info for Thumb immediate
103  /// BL branch target.
104  uint32_t getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
106  const MCSubtargetInfo &STI) const;
107 
108  /// getThumbBLXTargetOpValue - Return encoding info for Thumb immediate
109  /// BLX branch target.
110  uint32_t getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
112  const MCSubtargetInfo &STI) const;
113 
114  /// getThumbBRTargetOpValue - Return encoding info for Thumb branch target.
115  uint32_t getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx,
117  const MCSubtargetInfo &STI) const;
118 
119  /// getThumbBCCTargetOpValue - Return encoding info for Thumb branch target.
120  uint32_t getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx,
122  const MCSubtargetInfo &STI) const;
123 
124  /// getThumbCBTargetOpValue - Return encoding info for Thumb branch target.
125  uint32_t getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx,
127  const MCSubtargetInfo &STI) const;
128 
129  /// getBranchTargetOpValue - Return encoding info for 24-bit immediate
130  /// branch target.
131  uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
133  const MCSubtargetInfo &STI) const;
134 
135  /// getThumbBranchTargetOpValue - Return encoding info for 24-bit
136  /// immediate Thumb2 direct branch target.
137  uint32_t getThumbBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
139  const MCSubtargetInfo &STI) const;
140 
141  /// getARMBranchTargetOpValue - Return encoding info for 24-bit immediate
142  /// branch target.
143  uint32_t getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
145  const MCSubtargetInfo &STI) const;
146  uint32_t getARMBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
148  const MCSubtargetInfo &STI) const;
149  uint32_t getARMBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
151  const MCSubtargetInfo &STI) const;
152 
153  /// getAdrLabelOpValue - Return encoding info for 12-bit immediate
154  /// ADR label target.
155  uint32_t getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
157  const MCSubtargetInfo &STI) const;
158  uint32_t getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
160  const MCSubtargetInfo &STI) const;
161  uint32_t getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
163  const MCSubtargetInfo &STI) const;
164 
165  uint32_t getITMaskOpValue(const MCInst &MI, unsigned OpIdx,
167  const MCSubtargetInfo &STI) const;
168 
169  /// getMVEShiftImmOpValue - Return encoding info for the 'sz:imm5'
170  /// operand.
171  uint32_t getMVEShiftImmOpValue(const MCInst &MI, unsigned OpIdx,
173  const MCSubtargetInfo &STI) const;
174 
175  /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12'
176  /// operand.
177  uint32_t getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
179  const MCSubtargetInfo &STI) const;
180 
181  /// getThumbAddrModeRegRegOpValue - Return encoding for 'reg + reg' operand.
182  uint32_t getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx,
184  const MCSubtargetInfo &STI) const;
185 
186  /// getT2AddrModeImm8s4OpValue - Return encoding info for 'reg +/- imm8<<2'
187  /// operand.
188  uint32_t getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx,
190  const MCSubtargetInfo &STI) const;
191 
192  /// getT2AddrModeImm7s4OpValue - Return encoding info for 'reg +/- imm7<<2'
193  /// operand.
194  uint32_t getT2AddrModeImm7s4OpValue(const MCInst &MI, unsigned OpIdx,
196  const MCSubtargetInfo &STI) const;
197 
198  /// getT2AddrModeImm0_1020s4OpValue - Return encoding info for 'reg + imm8<<2'
199  /// operand.
200  uint32_t getT2AddrModeImm0_1020s4OpValue(const MCInst &MI, unsigned OpIdx,
202  const MCSubtargetInfo &STI) const;
203 
204  /// getT2ScaledImmOpValue - Return encoding info for '+/- immX<<Y'
205  /// operand.
206  template<unsigned Bits, unsigned Shift>
207  uint32_t getT2ScaledImmOpValue(const MCInst &MI, unsigned OpIdx,
209  const MCSubtargetInfo &STI) const;
210 
211  /// getMveAddrModeRQOpValue - Return encoding info for 'reg, vreg'
212  /// operand.
213  uint32_t getMveAddrModeRQOpValue(const MCInst &MI, unsigned OpIdx,
215  const MCSubtargetInfo &STI) const;
216 
217  /// getMveAddrModeQOpValue - Return encoding info for 'reg +/- imm7<<{shift}'
218  /// operand.
219  template<int shift>
220  uint32_t getMveAddrModeQOpValue(const MCInst &MI, unsigned OpIdx,
222  const MCSubtargetInfo &STI) const;
223 
224  /// getLdStSORegOpValue - Return encoding info for 'reg +/- reg shop imm'
225  /// operand as needed by load/store instructions.
226  uint32_t getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,
228  const MCSubtargetInfo &STI) const;
229 
230  /// getLdStmModeOpValue - Return encoding for load/store multiple mode.
231  uint32_t getLdStmModeOpValue(const MCInst &MI, unsigned OpIdx,
233  const MCSubtargetInfo &STI) const {
234  ARM_AM::AMSubMode Mode = (ARM_AM::AMSubMode)MI.getOperand(OpIdx).getImm();
235  switch (Mode) {
236  default: llvm_unreachable("Unknown addressing sub-mode!");
237  case ARM_AM::da: return 0;
238  case ARM_AM::ia: return 1;
239  case ARM_AM::db: return 2;
240  case ARM_AM::ib: return 3;
241  }
242  }
243 
244  /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
245  ///
246  unsigned getShiftOp(ARM_AM::ShiftOpc ShOpc) const {
247  switch (ShOpc) {
248  case ARM_AM::no_shift:
249  case ARM_AM::lsl: return 0;
250  case ARM_AM::lsr: return 1;
251  case ARM_AM::asr: return 2;
252  case ARM_AM::ror:
253  case ARM_AM::rrx: return 3;
254  default:
255  llvm_unreachable("Invalid ShiftOpc!");
256  }
257  }
258 
259  /// getAddrMode2OffsetOpValue - Return encoding for am2offset operands.
260  uint32_t getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx,
262  const MCSubtargetInfo &STI) const;
263 
264  /// getPostIdxRegOpValue - Return encoding for postidx_reg operands.
265  uint32_t getPostIdxRegOpValue(const MCInst &MI, unsigned OpIdx,
267  const MCSubtargetInfo &STI) const;
268 
269  /// getAddrMode3OffsetOpValue - Return encoding for am3offset operands.
270  uint32_t getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx,
272  const MCSubtargetInfo &STI) const;
273 
274  /// getAddrMode3OpValue - Return encoding for addrmode3 operands.
275  uint32_t getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx,
277  const MCSubtargetInfo &STI) const;
278 
279  /// getAddrModeThumbSPOpValue - Return encoding info for 'reg +/- imm12'
280  /// operand.
281  uint32_t getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx,
283  const MCSubtargetInfo &STI) const;
284 
285  /// getAddrModeISOpValue - Encode the t_addrmode_is# operands.
286  uint32_t getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx,
288  const MCSubtargetInfo &STI) const;
289 
290  /// getAddrModePCOpValue - Return encoding for t_addrmode_pc operands.
291  uint32_t getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx,
293  const MCSubtargetInfo &STI) const;
294 
295  /// getAddrMode5OpValue - Return encoding info for 'reg +/- (imm8 << 2)' operand.
296  uint32_t getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
298  const MCSubtargetInfo &STI) const;
299 
300  /// getAddrMode5FP16OpValue - Return encoding info for 'reg +/- (imm8 << 1)' operand.
301  uint32_t getAddrMode5FP16OpValue(const MCInst &MI, unsigned OpIdx,
303  const MCSubtargetInfo &STI) const;
304 
305  /// getCCOutOpValue - Return encoding of the 's' bit.
306  unsigned getCCOutOpValue(const MCInst &MI, unsigned Op,
308  const MCSubtargetInfo &STI) const {
309  // The operand is either reg0 or CPSR. The 's' bit is encoded as '0' or
310  // '1' respectively.
311  return MI.getOperand(Op).getReg() == ARM::CPSR;
312  }
313 
314  unsigned getModImmOpValue(const MCInst &MI, unsigned Op,
316  const MCSubtargetInfo &ST) const {
317  const MCOperand &MO = MI.getOperand(Op);
318 
319  // Support for fixups (MCFixup)
320  if (MO.isExpr()) {
321  const MCExpr *Expr = MO.getExpr();
322  // Fixups resolve to plain values that need to be encoded.
324  Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
325  return 0;
326  }
327 
328  // Immediate is already in its encoded format
329  return MO.getImm();
330  }
331 
332  /// getT2SOImmOpValue - Return an encoded 12-bit shifted-immediate value.
333  unsigned getT2SOImmOpValue(const MCInst &MI, unsigned Op,
335  const MCSubtargetInfo &STI) const {
336  const MCOperand &MO = MI.getOperand(Op);
337 
338  // Support for fixups (MCFixup)
339  if (MO.isExpr()) {
340  const MCExpr *Expr = MO.getExpr();
341  // Fixups resolve to plain values that need to be encoded.
343  Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
344  return 0;
345  }
346  unsigned SoImm = MO.getImm();
347  unsigned Encoded = ARM_AM::getT2SOImmVal(SoImm);
348  assert(Encoded != ~0U && "Not a Thumb2 so_imm value?");
349  return Encoded;
350  }
351 
352  unsigned getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum,
354  const MCSubtargetInfo &STI) const;
355  template<unsigned Bits, unsigned Shift>
356  unsigned getT2AddrModeImmOpValue(const MCInst &MI, unsigned OpNum,
358  const MCSubtargetInfo &STI) const;
359  unsigned getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum,
361  const MCSubtargetInfo &STI) const;
362 
363  /// getSORegOpValue - Return an encoded so_reg shifted register value.
364  unsigned getSORegRegOpValue(const MCInst &MI, unsigned Op,
366  const MCSubtargetInfo &STI) const;
367  unsigned getSORegImmOpValue(const MCInst &MI, unsigned Op,
369  const MCSubtargetInfo &STI) const;
370  unsigned getT2SORegOpValue(const MCInst &MI, unsigned Op,
372  const MCSubtargetInfo &STI) const;
373 
374  unsigned getNEONVcvtImm32OpValue(const MCInst &MI, unsigned Op,
376  const MCSubtargetInfo &STI) const {
377  return 64 - MI.getOperand(Op).getImm();
378  }
379 
380  unsigned getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op,
382  const MCSubtargetInfo &STI) const;
383 
384  unsigned getRegisterListOpValue(const MCInst &MI, unsigned Op,
386  const MCSubtargetInfo &STI) const;
387  unsigned getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op,
389  const MCSubtargetInfo &STI) const;
390  unsigned getAddrMode6OneLane32AddressOpValue(const MCInst &MI, unsigned Op,
392  const MCSubtargetInfo &STI) const;
393  unsigned getAddrMode6DupAddressOpValue(const MCInst &MI, unsigned Op,
395  const MCSubtargetInfo &STI) const;
396  unsigned getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op,
398  const MCSubtargetInfo &STI) const;
399 
400  unsigned getShiftRight8Imm(const MCInst &MI, unsigned Op,
402  const MCSubtargetInfo &STI) const;
403  unsigned getShiftRight16Imm(const MCInst &MI, unsigned Op,
405  const MCSubtargetInfo &STI) const;
406  unsigned getShiftRight32Imm(const MCInst &MI, unsigned Op,
408  const MCSubtargetInfo &STI) const;
409  unsigned getShiftRight64Imm(const MCInst &MI, unsigned Op,
411  const MCSubtargetInfo &STI) const;
412 
413  unsigned getThumbSRImmOpValue(const MCInst &MI, unsigned Op,
415  const MCSubtargetInfo &STI) const;
416 
417  unsigned NEONThumb2DataIPostEncoder(const MCInst &MI,
418  unsigned EncodedValue,
419  const MCSubtargetInfo &STI) const;
420  unsigned NEONThumb2LoadStorePostEncoder(const MCInst &MI,
421  unsigned EncodedValue,
422  const MCSubtargetInfo &STI) const;
423  unsigned NEONThumb2DupPostEncoder(const MCInst &MI,
424  unsigned EncodedValue,
425  const MCSubtargetInfo &STI) const;
426  unsigned NEONThumb2V8PostEncoder(const MCInst &MI,
427  unsigned EncodedValue,
428  const MCSubtargetInfo &STI) const;
429 
430  unsigned VFPThumb2PostEncoder(const MCInst &MI,
431  unsigned EncodedValue,
432  const MCSubtargetInfo &STI) const;
433 
434  uint32_t getPowerTwoOpValue(const MCInst &MI, unsigned OpIdx,
436  const MCSubtargetInfo &STI) const;
437 
438  void EmitByte(unsigned char C, raw_ostream &OS) const {
439  OS << (char)C;
440  }
441 
442  void EmitConstant(uint64_t Val, unsigned Size, raw_ostream &OS) const {
443  // Output the constant in little endian byte order.
444  for (unsigned i = 0; i != Size; ++i) {
445  unsigned Shift = IsLittleEndian ? i * 8 : (Size - 1 - i) * 8;
446  EmitByte((Val >> Shift) & 0xff, OS);
447  }
448  }
449 
450  void encodeInstruction(const MCInst &MI, raw_ostream &OS,
452  const MCSubtargetInfo &STI) const override;
453 
454  template <bool isNeg, ARM::Fixups fixup>
455  uint32_t getBFTargetOpValue(const MCInst &MI, unsigned OpIdx,
457  const MCSubtargetInfo &STI) const;
458 
459  uint32_t getBFAfterTargetOpValue(const MCInst &MI, unsigned OpIdx,
461  const MCSubtargetInfo &STI) const;
462 
463  uint32_t getVPTMaskOpValue(const MCInst &MI, unsigned OpIdx,
465  const MCSubtargetInfo &STI) const;
466  uint32_t getRestrictedCondCodeOpValue(const MCInst &MI, unsigned OpIdx,
468  const MCSubtargetInfo &STI) const;
469  template <unsigned size>
470  uint32_t getMVEPairVectorIndexOpValue(const MCInst &MI, unsigned OpIdx,
472  const MCSubtargetInfo &STI) const;
473 };
474 
475 } // end anonymous namespace
476 
477 /// NEONThumb2DataIPostEncoder - Post-process encoded NEON data-processing
478 /// instructions, and rewrite them to their Thumb2 form if we are currently in
479 /// Thumb2 mode.
480 unsigned ARMMCCodeEmitter::NEONThumb2DataIPostEncoder(const MCInst &MI,
481  unsigned EncodedValue,
482  const MCSubtargetInfo &STI) const {
483  if (isThumb2(STI)) {
484  // NEON Thumb2 data-processsing encodings are very simple: bit 24 is moved
485  // to bit 12 of the high half-word (i.e. bit 28), and bits 27-24 are
486  // set to 1111.
487  unsigned Bit24 = EncodedValue & 0x01000000;
488  unsigned Bit28 = Bit24 << 4;
489  EncodedValue &= 0xEFFFFFFF;
490  EncodedValue |= Bit28;
491  EncodedValue |= 0x0F000000;
492  }
493 
494  return EncodedValue;
495 }
496 
497 /// NEONThumb2LoadStorePostEncoder - Post-process encoded NEON load/store
498 /// instructions, and rewrite them to their Thumb2 form if we are currently in
499 /// Thumb2 mode.
500 unsigned ARMMCCodeEmitter::NEONThumb2LoadStorePostEncoder(const MCInst &MI,
501  unsigned EncodedValue,
502  const MCSubtargetInfo &STI) const {
503  if (isThumb2(STI)) {
504  EncodedValue &= 0xF0FFFFFF;
505  EncodedValue |= 0x09000000;
506  }
507 
508  return EncodedValue;
509 }
510 
511 /// NEONThumb2DupPostEncoder - Post-process encoded NEON vdup
512 /// instructions, and rewrite them to their Thumb2 form if we are currently in
513 /// Thumb2 mode.
514 unsigned ARMMCCodeEmitter::NEONThumb2DupPostEncoder(const MCInst &MI,
515  unsigned EncodedValue,
516  const MCSubtargetInfo &STI) const {
517  if (isThumb2(STI)) {
518  EncodedValue &= 0x00FFFFFF;
519  EncodedValue |= 0xEE000000;
520  }
521 
522  return EncodedValue;
523 }
524 
525 /// Post-process encoded NEON v8 instructions, and rewrite them to Thumb2 form
526 /// if we are in Thumb2.
527 unsigned ARMMCCodeEmitter::NEONThumb2V8PostEncoder(const MCInst &MI,
528  unsigned EncodedValue,
529  const MCSubtargetInfo &STI) const {
530  if (isThumb2(STI)) {
531  EncodedValue |= 0xC000000; // Set bits 27-26
532  }
533 
534  return EncodedValue;
535 }
536 
537 /// VFPThumb2PostEncoder - Post-process encoded VFP instructions and rewrite
538 /// them to their Thumb2 form if we are currently in Thumb2 mode.
539 unsigned ARMMCCodeEmitter::
540 VFPThumb2PostEncoder(const MCInst &MI, unsigned EncodedValue,
541  const MCSubtargetInfo &STI) const {
542  if (isThumb2(STI)) {
543  EncodedValue &= 0x0FFFFFFF;
544  EncodedValue |= 0xE0000000;
545  }
546  return EncodedValue;
547 }
548 
549 /// getMachineOpValue - Return binary encoding of operand. If the machine
550 /// operand requires relocation, record the relocation and return zero.
551 unsigned ARMMCCodeEmitter::
552 getMachineOpValue(const MCInst &MI, const MCOperand &MO,
554  const MCSubtargetInfo &STI) const {
555  if (MO.isReg()) {
556  unsigned Reg = MO.getReg();
557  unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg);
558 
559  // In NEON, Q registers are encoded as 2x their register number,
560  // because they're using the same indices as the D registers they
561  // overlap. In MVE, there are no 64-bit vector instructions, so
562  // the encodings all refer to Q-registers by their literal
563  // register number.
564 
565  if (STI.getFeatureBits()[ARM::HasMVEIntegerOps])
566  return RegNo;
567 
568  switch (Reg) {
569  default:
570  return RegNo;
571  case ARM::Q0: case ARM::Q1: case ARM::Q2: case ARM::Q3:
572  case ARM::Q4: case ARM::Q5: case ARM::Q6: case ARM::Q7:
573  case ARM::Q8: case ARM::Q9: case ARM::Q10: case ARM::Q11:
574  case ARM::Q12: case ARM::Q13: case ARM::Q14: case ARM::Q15:
575  return 2 * RegNo;
576  }
577  } else if (MO.isImm()) {
578  return static_cast<unsigned>(MO.getImm());
579  } else if (MO.isDFPImm()) {
580  return static_cast<unsigned>(APFloat(bit_cast<double>(MO.getDFPImm()))
581  .bitcastToAPInt()
582  .getHiBits(32)
583  .getLimitedValue());
584  }
585 
586  llvm_unreachable("Unable to encode MCOperand!");
587 }
588 
589 /// getAddrModeImmOpValue - Return encoding info for 'reg +/- imm' operand.
590 bool ARMMCCodeEmitter::
591 EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx, unsigned &Reg,
592  unsigned &Imm, SmallVectorImpl<MCFixup> &Fixups,
593  const MCSubtargetInfo &STI) const {
594  const MCOperand &MO = MI.getOperand(OpIdx);
595  const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
596 
598 
599  int32_t SImm = MO1.getImm();
600  bool isAdd = true;
601 
602  // Special value for #-0
603  if (SImm == INT32_MIN) {
604  SImm = 0;
605  isAdd = false;
606  }
607 
608  // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
609  if (SImm < 0) {
610  SImm = -SImm;
611  isAdd = false;
612  }
613 
614  Imm = SImm;
615  return isAdd;
616 }
617 
618 /// getBranchTargetOpValue - Helper function to get the branch target operand,
619 /// which is either an immediate or requires a fixup.
620 static uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
621  unsigned FixupKind,
623  const MCSubtargetInfo &STI) {
624  const MCOperand &MO = MI.getOperand(OpIdx);
625 
626  // If the destination is an immediate, we have nothing to do.
627  if (MO.isImm()) return MO.getImm();
628  assert(MO.isExpr() && "Unexpected branch target type!");
629  const MCExpr *Expr = MO.getExpr();
631  Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
632 
633  // All of the information is in the fixup.
634  return 0;
635 }
636 
637 // Thumb BL and BLX use a strange offset encoding where bits 22 and 21 are
638 // determined by negating them and XOR'ing them with bit 23.
639 static int32_t encodeThumbBLOffset(int32_t offset) {
640  offset >>= 1;
641  uint32_t S = (offset & 0x800000) >> 23;
642  uint32_t J1 = (offset & 0x400000) >> 22;
643  uint32_t J2 = (offset & 0x200000) >> 21;
644  J1 = (~J1 & 0x1);
645  J2 = (~J2 & 0x1);
646  J1 ^= S;
647  J2 ^= S;
648 
649  offset &= ~0x600000;
650  offset |= J1 << 22;
651  offset |= J2 << 21;
652 
653  return offset;
654 }
655 
656 /// getThumbBLTargetOpValue - Return encoding info for immediate branch target.
657 uint32_t ARMMCCodeEmitter::
658 getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
660  const MCSubtargetInfo &STI) const {
661  const MCOperand MO = MI.getOperand(OpIdx);
662  if (MO.isExpr())
664  Fixups, STI);
665  return encodeThumbBLOffset(MO.getImm());
666 }
667 
668 /// getThumbBLXTargetOpValue - Return encoding info for Thumb immediate
669 /// BLX branch target.
670 uint32_t ARMMCCodeEmitter::
671 getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
673  const MCSubtargetInfo &STI) const {
674  const MCOperand MO = MI.getOperand(OpIdx);
675  if (MO.isExpr())
677  Fixups, STI);
678  return encodeThumbBLOffset(MO.getImm());
679 }
680 
681 /// getThumbBRTargetOpValue - Return encoding info for Thumb branch target.
682 uint32_t ARMMCCodeEmitter::
683 getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx,
685  const MCSubtargetInfo &STI) const {
686  const MCOperand MO = MI.getOperand(OpIdx);
687  if (MO.isExpr())
689  Fixups, STI);
690  return (MO.getImm() >> 1);
691 }
692 
693 /// getThumbBCCTargetOpValue - Return encoding info for Thumb branch target.
694 uint32_t ARMMCCodeEmitter::
695 getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx,
697  const MCSubtargetInfo &STI) const {
698  const MCOperand MO = MI.getOperand(OpIdx);
699  if (MO.isExpr())
701  Fixups, STI);
702  return (MO.getImm() >> 1);
703 }
704 
705 /// getThumbCBTargetOpValue - Return encoding info for Thumb branch target.
706 uint32_t ARMMCCodeEmitter::
707 getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx,
709  const MCSubtargetInfo &STI) const {
710  const MCOperand MO = MI.getOperand(OpIdx);
711  if (MO.isExpr())
713  return (MO.getImm() >> 1);
714 }
715 
716 /// Return true if this branch has a non-always predication
717 static bool HasConditionalBranch(const MCInst &MI) {
718  int NumOp = MI.getNumOperands();
719  if (NumOp >= 2) {
720  for (int i = 0; i < NumOp-1; ++i) {
721  const MCOperand &MCOp1 = MI.getOperand(i);
722  const MCOperand &MCOp2 = MI.getOperand(i + 1);
723  if (MCOp1.isImm() && MCOp2.isReg() &&
724  (MCOp2.getReg() == 0 || MCOp2.getReg() == ARM::CPSR)) {
725  if (ARMCC::CondCodes(MCOp1.getImm()) != ARMCC::AL)
726  return true;
727  }
728  }
729  }
730  return false;
731 }
732 
733 /// getBranchTargetOpValue - Return encoding info for 24-bit immediate branch
734 /// target.
736 getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
738  const MCSubtargetInfo &STI) const {
739  // FIXME: This really, really shouldn't use TargetMachine. We don't want
740  // coupling between MC and TM anywhere we can help it.
741  if (isThumb2(STI))
742  return
744  return getARMBranchTargetOpValue(MI, OpIdx, Fixups, STI);
745 }
746 
747 /// getBranchTargetOpValue - Return encoding info for 24-bit immediate branch
748 /// target.
749 uint32_t ARMMCCodeEmitter::
750 getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
752  const MCSubtargetInfo &STI) const {
753  const MCOperand MO = MI.getOperand(OpIdx);
754  if (MO.isExpr()) {
760  }
761 
762  return MO.getImm() >> 2;
763 }
764 
765 uint32_t ARMMCCodeEmitter::
766 getARMBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
768  const MCSubtargetInfo &STI) const {
769  const MCOperand MO = MI.getOperand(OpIdx);
770  if (MO.isExpr()) {
775  }
776 
777  return MO.getImm() >> 2;
778 }
779 
780 uint32_t ARMMCCodeEmitter::
781 getARMBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
783  const MCSubtargetInfo &STI) const {
784  const MCOperand MO = MI.getOperand(OpIdx);
785  if (MO.isExpr())
787 
788  return MO.getImm() >> 1;
789 }
790 
791 /// getUnconditionalBranchTargetOpValue - Return encoding info for 24-bit
792 /// immediate branch target.
793 uint32_t ARMMCCodeEmitter::getThumbBranchTargetOpValue(
794  const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups,
795  const MCSubtargetInfo &STI) const {
796  unsigned Val = 0;
797  const MCOperand MO = MI.getOperand(OpIdx);
798 
799  if(MO.isExpr())
801  else
802  Val = MO.getImm() >> 1;
803 
804  bool I = (Val & 0x800000);
805  bool J1 = (Val & 0x400000);
806  bool J2 = (Val & 0x200000);
807  if (I ^ J1)
808  Val &= ~0x400000;
809  else
810  Val |= 0x400000;
811 
812  if (I ^ J2)
813  Val &= ~0x200000;
814  else
815  Val |= 0x200000;
816 
817  return Val;
818 }
819 
820 /// getAdrLabelOpValue - Return encoding info for 12-bit shifted-immediate
821 /// ADR label target.
822 uint32_t ARMMCCodeEmitter::
823 getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
825  const MCSubtargetInfo &STI) const {
826  const MCOperand MO = MI.getOperand(OpIdx);
827  if (MO.isExpr())
829  Fixups, STI);
830  int64_t offset = MO.getImm();
831  uint32_t Val = 0x2000;
832 
833  int SoImmVal;
834  if (offset == INT32_MIN) {
835  Val = 0x1000;
836  SoImmVal = 0;
837  } else if (offset < 0) {
838  Val = 0x1000;
839  offset *= -1;
840  SoImmVal = ARM_AM::getSOImmVal(offset);
841  if(SoImmVal == -1) {
842  Val = 0x2000;
843  offset *= -1;
844  SoImmVal = ARM_AM::getSOImmVal(offset);
845  }
846  } else {
847  SoImmVal = ARM_AM::getSOImmVal(offset);
848  if(SoImmVal == -1) {
849  Val = 0x1000;
850  offset *= -1;
851  SoImmVal = ARM_AM::getSOImmVal(offset);
852  }
853  }
854 
855  assert(SoImmVal != -1 && "Not a valid so_imm value!");
856 
857  Val |= SoImmVal;
858  return Val;
859 }
860 
861 /// getT2AdrLabelOpValue - Return encoding info for 12-bit immediate ADR label
862 /// target.
863 uint32_t ARMMCCodeEmitter::
864 getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
866  const MCSubtargetInfo &STI) const {
867  const MCOperand MO = MI.getOperand(OpIdx);
868  if (MO.isExpr())
870  Fixups, STI);
871  int32_t Val = MO.getImm();
872  if (Val == INT32_MIN)
873  Val = 0x1000;
874  else if (Val < 0) {
875  Val *= -1;
876  Val |= 0x1000;
877  }
878  return Val;
879 }
880 
881 /// getITMaskOpValue - Return the architectural encoding of an IT
882 /// predication mask, given the MCOperand format.
883 uint32_t ARMMCCodeEmitter::
884 getITMaskOpValue(const MCInst &MI, unsigned OpIdx,
886  const MCSubtargetInfo &STI) const {
887  const MCOperand MaskMO = MI.getOperand(OpIdx);
888  assert(MaskMO.isImm() && "Unexpected operand type!");
889 
890  unsigned Mask = MaskMO.getImm();
891 
892  // IT masks are encoded as a sequence of replacement low-order bits
893  // for the condition code. So if the low bit of the starting
894  // condition code is 1, then we have to flip all the bits above the
895  // terminating bit (which is the lowest 1 bit).
896  assert(OpIdx > 0 && "IT mask appears first!");
897  const MCOperand CondMO = MI.getOperand(OpIdx-1);
898  assert(CondMO.isImm() && "Unexpected operand type!");
899  if (CondMO.getImm() & 1) {
900  unsigned LowBit = Mask & -Mask;
901  unsigned BitsAboveLowBit = 0xF & (-LowBit << 1);
902  Mask ^= BitsAboveLowBit;
903  }
904 
905  return Mask;
906 }
907 
908 /// getThumbAdrLabelOpValue - Return encoding info for 8-bit immediate ADR label
909 /// target.
910 uint32_t ARMMCCodeEmitter::
911 getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
913  const MCSubtargetInfo &STI) const {
914  const MCOperand MO = MI.getOperand(OpIdx);
915  if (MO.isExpr())
917  Fixups, STI);
918  return MO.getImm();
919 }
920 
921 /// getThumbAddrModeRegRegOpValue - Return encoding info for 'reg + reg'
922 /// operand.
923 uint32_t ARMMCCodeEmitter::
924 getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx,
926  const MCSubtargetInfo &STI) const {
927  // [Rn, Rm]
928  // {5-3} = Rm
929  // {2-0} = Rn
930  const MCOperand &MO1 = MI.getOperand(OpIdx);
931  const MCOperand &MO2 = MI.getOperand(OpIdx + 1);
932  unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg());
933  unsigned Rm = CTX.getRegisterInfo()->getEncodingValue(MO2.getReg());
934  return (Rm << 3) | Rn;
935 }
936 
937 /// getMVEShiftImmOpValue - Return encoding info for the 'sz:imm5'
938 /// operand.
939 uint32_t
940 ARMMCCodeEmitter::getMVEShiftImmOpValue(const MCInst &MI, unsigned OpIdx,
942  const MCSubtargetInfo &STI) const {
943  // {4-0} = szimm5
944  // The value we are trying to encode is an immediate between either the
945  // range of [1-7] or [1-15] depending on whether we are dealing with the
946  // u8/s8 or the u16/s16 variants respectively.
947  // This value is encoded as follows, if ShiftImm is the value within those
948  // ranges then the encoding szimm5 = ShiftImm + size, where size is either 8
949  // or 16.
950 
951  unsigned Size, ShiftImm;
952  switch(MI.getOpcode()) {
953  case ARM::MVE_VSHLL_imms16bh:
954  case ARM::MVE_VSHLL_imms16th:
955  case ARM::MVE_VSHLL_immu16bh:
956  case ARM::MVE_VSHLL_immu16th:
957  Size = 16;
958  break;
959  case ARM::MVE_VSHLL_imms8bh:
960  case ARM::MVE_VSHLL_imms8th:
961  case ARM::MVE_VSHLL_immu8bh:
962  case ARM::MVE_VSHLL_immu8th:
963  Size = 8;
964  break;
965  default:
966  llvm_unreachable("Use of operand not supported by this instruction");
967  }
968  ShiftImm = MI.getOperand(OpIdx).getImm();
969  return Size + ShiftImm;
970 }
971 
972 /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12' operand.
973 uint32_t ARMMCCodeEmitter::
974 getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
976  const MCSubtargetInfo &STI) const {
977  // {17-13} = reg
978  // {12} = (U)nsigned (add == '1', sub == '0')
979  // {11-0} = imm12
980  unsigned Reg = 0, Imm12 = 0;
981  bool isAdd = true;
982  // If The first operand isn't a register, we have a label reference.
983  const MCOperand &MO = MI.getOperand(OpIdx);
984  if (MO.isReg()) {
985  const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
986  if (MO1.isImm()) {
987  isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm12, Fixups, STI);
988  } else if (MO1.isExpr()) {
989  assert(!isThumb(STI) && !isThumb2(STI) &&
990  "Thumb mode requires different encoding");
992  isAdd = false; // 'U' bit is set as part of the fixup.
994  Fixups.push_back(MCFixup::create(0, MO1.getExpr(), Kind, MI.getLoc()));
995  }
996  } else if (MO.isExpr()) {
997  Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC.
998  isAdd = false; // 'U' bit is set as part of the fixup.
1000  if (isThumb2(STI))
1002  else
1004  Fixups.push_back(MCFixup::create(0, MO.getExpr(), Kind, MI.getLoc()));
1005 
1006  ++MCNumCPRelocations;
1007  } else {
1008  Reg = ARM::PC;
1009  int32_t Offset = MO.getImm();
1010  if (Offset == INT32_MIN) {
1011  Offset = 0;
1012  isAdd = false;
1013  } else if (Offset < 0) {
1014  Offset *= -1;
1015  isAdd = false;
1016  }
1017  Imm12 = Offset;
1018  }
1019  uint32_t Binary = Imm12 & 0xfff;
1020  // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
1021  if (isAdd)
1022  Binary |= (1 << 12);
1023  Binary |= (Reg << 13);
1024  return Binary;
1025 }
1026 
1027 template<unsigned Bits, unsigned Shift>
1028 uint32_t ARMMCCodeEmitter::
1029 getT2ScaledImmOpValue(const MCInst &MI, unsigned OpIdx,
1031  const MCSubtargetInfo &STI) const {
1032  // FIXME: The immediate operand should have already been encoded like this
1033  // before ever getting here. The encoder method should just need to combine
1034  // the MI operands for the register and the offset into a single
1035  // representation for the complex operand in the .td file. This isn't just
1036  // style, unfortunately. As-is, we can't represent the distinct encoding
1037  // for #-0.
1038 
1039  // {Bits} = (U)nsigned (add == '1', sub == '0')
1040  // {(Bits-1)-0} = immediate
1041  int32_t Imm = MI.getOperand(OpIdx).getImm();
1042  bool isAdd = Imm >= 0;
1043 
1044  // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
1045  if (Imm < 0)
1046  Imm = -(uint32_t)Imm;
1047 
1048  Imm >>= Shift;
1049 
1050  uint32_t Binary = Imm & ((1U << Bits) - 1);
1051  // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
1052  if (isAdd)
1053  Binary |= (1U << Bits);
1054  return Binary;
1055 }
1056 
1057 /// getMveAddrModeRQOpValue - Return encoding info for 'reg, vreg'
1058 /// operand.
1059 uint32_t ARMMCCodeEmitter::
1060 getMveAddrModeRQOpValue(const MCInst &MI, unsigned OpIdx,
1062  const MCSubtargetInfo &STI) const {
1063  // {6-3} Rn
1064  // {2-0} Qm
1065  const MCOperand &M0 = MI.getOperand(OpIdx);
1066  const MCOperand &M1 = MI.getOperand(OpIdx + 1);
1067 
1068  unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(M0.getReg());
1069  unsigned Qm = CTX.getRegisterInfo()->getEncodingValue(M1.getReg());
1070 
1071  assert(Qm < 8 && "Qm is supposed to be encodable in 3 bits");
1072 
1073  return (Rn << 3) | Qm;
1074 }
1075 
1076 /// getMveAddrModeRQOpValue - Return encoding info for 'reg, vreg'
1077 /// operand.
1078 template<int shift>
1079 uint32_t ARMMCCodeEmitter::
1080 getMveAddrModeQOpValue(const MCInst &MI, unsigned OpIdx,
1082  const MCSubtargetInfo &STI) const {
1083  // {10-8} Qm
1084  // {7-0} Imm
1085  const MCOperand &M0 = MI.getOperand(OpIdx);
1086  const MCOperand &M1 = MI.getOperand(OpIdx + 1);
1087 
1088  unsigned Qm = CTX.getRegisterInfo()->getEncodingValue(M0.getReg());
1089  int32_t Imm = M1.getImm();
1090 
1091  bool isAdd = Imm >= 0;
1092 
1093  Imm >>= shift;
1094 
1095  if (!isAdd)
1096  Imm = -(uint32_t)Imm;
1097 
1098  Imm &= 0x7f;
1099 
1100  if (isAdd)
1101  Imm |= 0x80;
1102 
1103  assert(Qm < 8 && "Qm is supposed to be encodable in 3 bits");
1104 
1105  return (Qm << 8) | Imm;
1106 }
1107 
1108 /// getT2AddrModeImm8s4OpValue - Return encoding info for
1109 /// 'reg +/- imm8<<2' operand.
1110 uint32_t ARMMCCodeEmitter::
1111 getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx,
1113  const MCSubtargetInfo &STI) const {
1114  // {12-9} = reg
1115  // {8} = (U)nsigned (add == '1', sub == '0')
1116  // {7-0} = imm8
1117  unsigned Reg, Imm8;
1118  bool isAdd = true;
1119  // If The first operand isn't a register, we have a label reference.
1120  const MCOperand &MO = MI.getOperand(OpIdx);
1121  if (!MO.isReg()) {
1122  Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC.
1123  Imm8 = 0;
1124  isAdd = false ; // 'U' bit is set as part of the fixup.
1125 
1126  assert(MO.isExpr() && "Unexpected machine operand type!");
1127  const MCExpr *Expr = MO.getExpr();
1129  Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
1130 
1131  ++MCNumCPRelocations;
1132  } else
1133  isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups, STI);
1134 
1135  // FIXME: The immediate operand should have already been encoded like this
1136  // before ever getting here. The encoder method should just need to combine
1137  // the MI operands for the register and the offset into a single
1138  // representation for the complex operand in the .td file. This isn't just
1139  // style, unfortunately. As-is, we can't represent the distinct encoding
1140  // for #-0.
1141  assert(((Imm8 & 0x3) == 0) && "Not a valid immediate!");
1142  uint32_t Binary = (Imm8 >> 2) & 0xff;
1143  // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
1144  if (isAdd)
1145  Binary |= (1 << 8);
1146  Binary |= (Reg << 9);
1147  return Binary;
1148 }
1149 
1150 /// getT2AddrModeImm7s4OpValue - Return encoding info for
1151 /// 'reg +/- imm7<<2' operand.
1152 uint32_t
1153 ARMMCCodeEmitter::getT2AddrModeImm7s4OpValue(const MCInst &MI, unsigned OpIdx,
1155  const MCSubtargetInfo &STI) const {
1156  // {11-8} = reg
1157  // {7} = (A)dd (add == '1', sub == '0')
1158  // {6-0} = imm7
1159  unsigned Reg, Imm7;
1160  // If The first operand isn't a register, we have a label reference.
1161  bool isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm7, Fixups, STI);
1162 
1163  // FIXME: The immediate operand should have already been encoded like this
1164  // before ever getting here. The encoder method should just need to combine
1165  // the MI operands for the register and the offset into a single
1166  // representation for the complex operand in the .td file. This isn't just
1167  // style, unfortunately. As-is, we can't represent the distinct encoding
1168  // for #-0.
1169  uint32_t Binary = (Imm7 >> 2) & 0xff;
1170  // Immediate is always encoded as positive. The 'A' bit controls add vs sub.
1171  if (isAdd)
1172  Binary |= (1 << 7);
1173  Binary |= (Reg << 8);
1174  return Binary;
1175 }
1176 
1177 /// getT2AddrModeImm0_1020s4OpValue - Return encoding info for
1178 /// 'reg + imm8<<2' operand.
1179 uint32_t ARMMCCodeEmitter::
1180 getT2AddrModeImm0_1020s4OpValue(const MCInst &MI, unsigned OpIdx,
1182  const MCSubtargetInfo &STI) const {
1183  // {11-8} = reg
1184  // {7-0} = imm8
1185  const MCOperand &MO = MI.getOperand(OpIdx);
1186  const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1187  unsigned Reg = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1188  unsigned Imm8 = MO1.getImm();
1189  return (Reg << 8) | Imm8;
1190 }
1191 
1192 uint32_t
1193 ARMMCCodeEmitter::getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx,
1195  const MCSubtargetInfo &STI) const {
1196  // {20-16} = imm{15-12}
1197  // {11-0} = imm{11-0}
1198  const MCOperand &MO = MI.getOperand(OpIdx);
1199  if (MO.isImm())
1200  // Hi / lo 16 bits already extracted during earlier passes.
1201  return static_cast<unsigned>(MO.getImm());
1202 
1203  // Handle :upper16: and :lower16: assembly prefixes.
1204  const MCExpr *E = MO.getExpr();
1205  MCFixupKind Kind;
1206  if (E->getKind() == MCExpr::Target) {
1207  const ARMMCExpr *ARM16Expr = cast<ARMMCExpr>(E);
1208  E = ARM16Expr->getSubExpr();
1209 
1210  if (const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(E)) {
1211  const int64_t Value = MCE->getValue();
1212  if (Value > UINT32_MAX)
1213  report_fatal_error("constant value truncated (limited to 32-bit)");
1214 
1215  switch (ARM16Expr->getKind()) {
1217  return (int32_t(Value) & 0xffff0000) >> 16;
1219  return (int32_t(Value) & 0x0000ffff);
1220  default: llvm_unreachable("Unsupported ARMFixup");
1221  }
1222  }
1223 
1224  switch (ARM16Expr->getKind()) {
1225  default: llvm_unreachable("Unsupported ARMFixup");
1229  break;
1233  break;
1234  }
1235 
1236  Fixups.push_back(MCFixup::create(0, E, Kind, MI.getLoc()));
1237  return 0;
1238  }
1239  // If the expression doesn't have :upper16: or :lower16: on it,
1240  // it's just a plain immediate expression, previously those evaluated to
1241  // the lower 16 bits of the expression regardless of whether
1242  // we have a movt or a movw, but that led to misleadingly results.
1243  // This is disallowed in the AsmParser in validateInstruction()
1244  // so this should never happen.
1245  llvm_unreachable("expression without :upper16: or :lower16:");
1246 }
1247 
1248 uint32_t ARMMCCodeEmitter::
1249 getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,
1251  const MCSubtargetInfo &STI) const {
1252  const MCOperand &MO = MI.getOperand(OpIdx);
1253  const MCOperand &MO1 = MI.getOperand(OpIdx+1);
1254  const MCOperand &MO2 = MI.getOperand(OpIdx+2);
1255  unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1256  unsigned Rm = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg());
1257  unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm());
1258  bool isAdd = ARM_AM::getAM2Op(MO2.getImm()) == ARM_AM::add;
1260  unsigned SBits = getShiftOp(ShOp);
1261 
1262  // While "lsr #32" and "asr #32" exist, they are encoded with a 0 in the shift
1263  // amount. However, it would be an easy mistake to make so check here.
1264  assert((ShImm & ~0x1f) == 0 && "Out of range shift amount");
1265 
1266  // {16-13} = Rn
1267  // {12} = isAdd
1268  // {11-0} = shifter
1269  // {3-0} = Rm
1270  // {4} = 0
1271  // {6-5} = type
1272  // {11-7} = imm
1273  uint32_t Binary = Rm;
1274  Binary |= Rn << 13;
1275  Binary |= SBits << 5;
1276  Binary |= ShImm << 7;
1277  if (isAdd)
1278  Binary |= 1 << 12;
1279  return Binary;
1280 }
1281 
1282 uint32_t ARMMCCodeEmitter::
1283 getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx,
1285  const MCSubtargetInfo &STI) const {
1286  // {13} 1 == imm12, 0 == Rm
1287  // {12} isAdd
1288  // {11-0} imm12/Rm
1289  const MCOperand &MO = MI.getOperand(OpIdx);
1290  const MCOperand &MO1 = MI.getOperand(OpIdx+1);
1291  unsigned Imm = MO1.getImm();
1292  bool isAdd = ARM_AM::getAM2Op(Imm) == ARM_AM::add;
1293  bool isReg = MO.getReg() != 0;
1295  // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm12
1296  if (isReg) {
1298  Binary <<= 7; // Shift amount is bits [11:7]
1299  Binary |= getShiftOp(ShOp) << 5; // Shift type is bits [6:5]
1300  Binary |= CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); // Rm is bits [3:0]
1301  }
1302  return Binary | (isAdd << 12) | (isReg << 13);
1303 }
1304 
1305 uint32_t ARMMCCodeEmitter::
1306 getPostIdxRegOpValue(const MCInst &MI, unsigned OpIdx,
1308  const MCSubtargetInfo &STI) const {
1309  // {4} isAdd
1310  // {3-0} Rm
1311  const MCOperand &MO = MI.getOperand(OpIdx);
1312  const MCOperand &MO1 = MI.getOperand(OpIdx+1);
1313  bool isAdd = MO1.getImm() != 0;
1314  return CTX.getRegisterInfo()->getEncodingValue(MO.getReg()) | (isAdd << 4);
1315 }
1316 
1317 uint32_t ARMMCCodeEmitter::
1318 getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx,
1320  const MCSubtargetInfo &STI) const {
1321  // {9} 1 == imm8, 0 == Rm
1322  // {8} isAdd
1323  // {7-4} imm7_4/zero
1324  // {3-0} imm3_0/Rm
1325  const MCOperand &MO = MI.getOperand(OpIdx);
1326  const MCOperand &MO1 = MI.getOperand(OpIdx+1);
1327  unsigned Imm = MO1.getImm();
1328  bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add;
1329  bool isImm = MO.getReg() == 0;
1331  // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8
1332  if (!isImm)
1334  return Imm8 | (isAdd << 8) | (isImm << 9);
1335 }
1336 
1337 uint32_t ARMMCCodeEmitter::
1338 getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx,
1340  const MCSubtargetInfo &STI) const {
1341  // {13} 1 == imm8, 0 == Rm
1342  // {12-9} Rn
1343  // {8} isAdd
1344  // {7-4} imm7_4/zero
1345  // {3-0} imm3_0/Rm
1346  const MCOperand &MO = MI.getOperand(OpIdx);
1347  const MCOperand &MO1 = MI.getOperand(OpIdx+1);
1348  const MCOperand &MO2 = MI.getOperand(OpIdx+2);
1349 
1350  // If The first operand isn't a register, we have a label reference.
1351  if (!MO.isReg()) {
1352  unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC.
1353 
1354  assert(MO.isExpr() && "Unexpected machine operand type!");
1355  const MCExpr *Expr = MO.getExpr();
1357  Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
1358 
1359  ++MCNumCPRelocations;
1360  return (Rn << 9) | (1 << 13);
1361  }
1362  unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1363  unsigned Imm = MO2.getImm();
1364  bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add;
1365  bool isImm = MO1.getReg() == 0;
1367  // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8
1368  if (!isImm)
1369  Imm8 = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg());
1370  return (Rn << 9) | Imm8 | (isAdd << 8) | (isImm << 13);
1371 }
1372 
1373 /// getAddrModeThumbSPOpValue - Encode the t_addrmode_sp operands.
1374 uint32_t ARMMCCodeEmitter::
1375 getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx,
1377  const MCSubtargetInfo &STI) const {
1378  // [SP, #imm]
1379  // {7-0} = imm8
1380  const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1381  assert(MI.getOperand(OpIdx).getReg() == ARM::SP &&
1382  "Unexpected base register!");
1383 
1384  // The immediate is already shifted for the implicit zeroes, so no change
1385  // here.
1386  return MO1.getImm() & 0xff;
1387 }
1388 
1389 /// getAddrModeISOpValue - Encode the t_addrmode_is# operands.
1390 uint32_t ARMMCCodeEmitter::
1391 getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx,
1393  const MCSubtargetInfo &STI) const {
1394  // [Rn, #imm]
1395  // {7-3} = imm5
1396  // {2-0} = Rn
1397  const MCOperand &MO = MI.getOperand(OpIdx);
1398  const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1399  unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1400  unsigned Imm5 = MO1.getImm();
1401  return ((Imm5 & 0x1f) << 3) | Rn;
1402 }
1403 
1404 /// getAddrModePCOpValue - Return encoding for t_addrmode_pc operands.
1405 uint32_t ARMMCCodeEmitter::
1406 getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx,
1408  const MCSubtargetInfo &STI) const {
1409  const MCOperand MO = MI.getOperand(OpIdx);
1410  if (MO.isExpr())
1412  return (MO.getImm() >> 2);
1413 }
1414 
1415 /// getAddrMode5OpValue - Return encoding info for 'reg +/- (imm8 << 2)' operand.
1416 uint32_t ARMMCCodeEmitter::
1417 getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
1419  const MCSubtargetInfo &STI) const {
1420  // {12-9} = reg
1421  // {8} = (U)nsigned (add == '1', sub == '0')
1422  // {7-0} = imm8
1423  unsigned Reg, Imm8;
1424  bool isAdd;
1425  // If The first operand isn't a register, we have a label reference.
1426  const MCOperand &MO = MI.getOperand(OpIdx);
1427  if (!MO.isReg()) {
1428  Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC.
1429  Imm8 = 0;
1430  isAdd = false; // 'U' bit is handled as part of the fixup.
1431 
1432  assert(MO.isExpr() && "Unexpected machine operand type!");
1433  const MCExpr *Expr = MO.getExpr();
1434  MCFixupKind Kind;
1435  if (isThumb2(STI))
1437  else
1439  Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
1440 
1441  ++MCNumCPRelocations;
1442  } else {
1443  EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups, STI);
1444  isAdd = ARM_AM::getAM5Op(Imm8) == ARM_AM::add;
1445  }
1446 
1448  // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
1449  if (isAdd)
1450  Binary |= (1 << 8);
1451  Binary |= (Reg << 9);
1452  return Binary;
1453 }
1454 
1455 /// getAddrMode5FP16OpValue - Return encoding info for 'reg +/- (imm8 << 1)' operand.
1456 uint32_t ARMMCCodeEmitter::
1457 getAddrMode5FP16OpValue(const MCInst &MI, unsigned OpIdx,
1459  const MCSubtargetInfo &STI) const {
1460  // {12-9} = reg
1461  // {8} = (U)nsigned (add == '1', sub == '0')
1462  // {7-0} = imm8
1463  unsigned Reg, Imm8;
1464  bool isAdd;
1465  // If The first operand isn't a register, we have a label reference.
1466  const MCOperand &MO = MI.getOperand(OpIdx);
1467  if (!MO.isReg()) {
1468  Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC.
1469  Imm8 = 0;
1470  isAdd = false; // 'U' bit is handled as part of the fixup.
1471 
1472  assert(MO.isExpr() && "Unexpected machine operand type!");
1473  const MCExpr *Expr = MO.getExpr();
1474  MCFixupKind Kind;
1475  if (isThumb2(STI))
1477  else
1479  Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
1480 
1481  ++MCNumCPRelocations;
1482  } else {
1483  EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups, STI);
1484  isAdd = ARM_AM::getAM5Op(Imm8) == ARM_AM::add;
1485  }
1486 
1488  // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
1489  if (isAdd)
1490  Binary |= (1 << 8);
1491  Binary |= (Reg << 9);
1492  return Binary;
1493 }
1494 
1495 unsigned ARMMCCodeEmitter::
1496 getSORegRegOpValue(const MCInst &MI, unsigned OpIdx,
1498  const MCSubtargetInfo &STI) const {
1499  // Sub-operands are [reg, reg, imm]. The first register is Rm, the reg to be
1500  // shifted. The second is Rs, the amount to shift by, and the third specifies
1501  // the type of the shift.
1502  //
1503  // {3-0} = Rm.
1504  // {4} = 1
1505  // {6-5} = type
1506  // {11-8} = Rs
1507  // {7} = 0
1508 
1509  const MCOperand &MO = MI.getOperand(OpIdx);
1510  const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1511  const MCOperand &MO2 = MI.getOperand(OpIdx + 2);
1513 
1514  // Encode Rm.
1515  unsigned Binary = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1516 
1517  // Encode the shift opcode.
1518  unsigned SBits = 0;
1519  unsigned Rs = MO1.getReg();
1520  if (Rs) {
1521  // Set shift operand (bit[7:4]).
1522  // LSL - 0001
1523  // LSR - 0011
1524  // ASR - 0101
1525  // ROR - 0111
1526  switch (SOpc) {
1527  default: llvm_unreachable("Unknown shift opc!");
1528  case ARM_AM::lsl: SBits = 0x1; break;
1529  case ARM_AM::lsr: SBits = 0x3; break;
1530  case ARM_AM::asr: SBits = 0x5; break;
1531  case ARM_AM::ror: SBits = 0x7; break;
1532  }
1533  }
1534 
1535  Binary |= SBits << 4;
1536 
1537  // Encode the shift operation Rs.
1538  // Encode Rs bit[11:8].
1539  assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
1540  return Binary | (CTX.getRegisterInfo()->getEncodingValue(Rs) << ARMII::RegRsShift);
1541 }
1542 
1543 unsigned ARMMCCodeEmitter::
1544 getSORegImmOpValue(const MCInst &MI, unsigned OpIdx,
1546  const MCSubtargetInfo &STI) const {
1547  // Sub-operands are [reg, imm]. The first register is Rm, the reg to be
1548  // shifted. The second is the amount to shift by.
1549  //
1550  // {3-0} = Rm.
1551  // {4} = 0
1552  // {6-5} = type
1553  // {11-7} = imm
1554 
1555  const MCOperand &MO = MI.getOperand(OpIdx);
1556  const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1558 
1559  // Encode Rm.
1560  unsigned Binary = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1561 
1562  // Encode the shift opcode.
1563  unsigned SBits = 0;
1564 
1565  // Set shift operand (bit[6:4]).
1566  // LSL - 000
1567  // LSR - 010
1568  // ASR - 100
1569  // ROR - 110
1570  // RRX - 110 and bit[11:8] clear.
1571  switch (SOpc) {
1572  default: llvm_unreachable("Unknown shift opc!");
1573  case ARM_AM::lsl: SBits = 0x0; break;
1574  case ARM_AM::lsr: SBits = 0x2; break;
1575  case ARM_AM::asr: SBits = 0x4; break;
1576  case ARM_AM::ror: SBits = 0x6; break;
1577  case ARM_AM::rrx:
1578  Binary |= 0x60;
1579  return Binary;
1580  }
1581 
1582  // Encode shift_imm bit[11:7].
1583  Binary |= SBits << 4;
1584  unsigned Offset = ARM_AM::getSORegOffset(MO1.getImm());
1585  assert(Offset < 32 && "Offset must be in range 0-31!");
1586  return Binary | (Offset << 7);
1587 }
1588 
1589 
1590 unsigned ARMMCCodeEmitter::
1591 getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum,
1593  const MCSubtargetInfo &STI) const {
1594  const MCOperand &MO1 = MI.getOperand(OpNum);
1595  const MCOperand &MO2 = MI.getOperand(OpNum+1);
1596  const MCOperand &MO3 = MI.getOperand(OpNum+2);
1597 
1598  // Encoded as [Rn, Rm, imm].
1599  // FIXME: Needs fixup support.
1600  unsigned Value = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg());
1601  Value <<= 4;
1602  Value |= CTX.getRegisterInfo()->getEncodingValue(MO2.getReg());
1603  Value <<= 2;
1604  Value |= MO3.getImm();
1605 
1606  return Value;
1607 }
1608 
1609 template<unsigned Bits, unsigned Shift>
1610 unsigned ARMMCCodeEmitter::
1611 getT2AddrModeImmOpValue(const MCInst &MI, unsigned OpNum,
1613  const MCSubtargetInfo &STI) const {
1614  const MCOperand &MO1 = MI.getOperand(OpNum);
1615  const MCOperand &MO2 = MI.getOperand(OpNum+1);
1616 
1617  // FIXME: Needs fixup support.
1618  unsigned Value = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg());
1619 
1620  // If the immediate is B bits long, we need B+1 bits in order
1621  // to represent the (inverse of the) sign bit.
1622  Value <<= (Bits + 1);
1623  int32_t tmp = (int32_t)MO2.getImm();
1624  if (tmp == INT32_MIN) { // represents subtracting zero rather than adding it
1625  tmp = 0;
1626  } else if (tmp < 0) {
1627  tmp = abs(tmp);
1628  } else {
1629  Value |= (1U << Bits); // Set the ADD bit
1630  }
1631  Value |= (tmp >> Shift) & ((1U << Bits) - 1);
1632  return Value;
1633 }
1634 
1635 unsigned ARMMCCodeEmitter::
1636 getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum,
1638  const MCSubtargetInfo &STI) const {
1639  const MCOperand &MO1 = MI.getOperand(OpNum);
1640 
1641  // FIXME: Needs fixup support.
1642  unsigned Value = 0;
1643  int32_t tmp = (int32_t)MO1.getImm();
1644  if (tmp < 0)
1645  tmp = abs(tmp);
1646  else
1647  Value |= 256; // Set the ADD bit
1648  Value |= tmp & 255;
1649  return Value;
1650 }
1651 
1652 unsigned ARMMCCodeEmitter::
1653 getT2SORegOpValue(const MCInst &MI, unsigned OpIdx,
1655  const MCSubtargetInfo &STI) const {
1656  // Sub-operands are [reg, imm]. The first register is Rm, the reg to be
1657  // shifted. The second is the amount to shift by.
1658  //
1659  // {3-0} = Rm.
1660  // {4} = 0
1661  // {6-5} = type
1662  // {11-7} = imm
1663 
1664  const MCOperand &MO = MI.getOperand(OpIdx);
1665  const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1667 
1668  // Encode Rm.
1669  unsigned Binary = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1670 
1671  // Encode the shift opcode.
1672  unsigned SBits = 0;
1673  // Set shift operand (bit[6:4]).
1674  // LSL - 000
1675  // LSR - 010
1676  // ASR - 100
1677  // ROR - 110
1678  switch (SOpc) {
1679  default: llvm_unreachable("Unknown shift opc!");
1680  case ARM_AM::lsl: SBits = 0x0; break;
1681  case ARM_AM::lsr: SBits = 0x2; break;
1682  case ARM_AM::asr: SBits = 0x4; break;
1684  case ARM_AM::ror: SBits = 0x6; break;
1685  }
1686 
1687  Binary |= SBits << 4;
1688  if (SOpc == ARM_AM::rrx)
1689  return Binary;
1690 
1691  // Encode shift_imm bit[11:7].
1692  return Binary | ARM_AM::getSORegOffset(MO1.getImm()) << 7;
1693 }
1694 
1695 unsigned ARMMCCodeEmitter::
1696 getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op,
1698  const MCSubtargetInfo &STI) const {
1699  // 10 bits. lower 5 bits are the lsb of the mask, high five bits are the
1700  // msb of the mask.
1701  const MCOperand &MO = MI.getOperand(Op);
1702  uint32_t v = ~MO.getImm();
1703  uint32_t lsb = countTrailingZeros(v);
1704  uint32_t msb = (32 - countLeadingZeros (v)) - 1;
1705  assert(v != 0 && lsb < 32 && msb < 32 && "Illegal bitfield mask!");
1706  return lsb | (msb << 5);
1707 }
1708 
1709 unsigned ARMMCCodeEmitter::
1710 getRegisterListOpValue(const MCInst &MI, unsigned Op,
1712  const MCSubtargetInfo &STI) const {
1713  // VLDM/VSTM/VSCCLRM:
1714  // {12-8} = Vd
1715  // {7-0} = Number of registers
1716  //
1717  // LDM/STM:
1718  // {15-0} = Bitfield of GPRs.
1719  unsigned Reg = MI.getOperand(Op).getReg();
1720  bool SPRRegs = ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg);
1721  bool DPRRegs = ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg);
1722 
1723  unsigned Binary = 0;
1724 
1725  if (SPRRegs || DPRRegs) {
1726  // VLDM/VSTM/VSCCLRM
1727  unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg);
1728  unsigned NumRegs = (MI.getNumOperands() - Op) & 0xff;
1729  Binary |= (RegNo & 0x1f) << 8;
1730 
1731  // Ignore VPR
1732  if (MI.getOpcode() == ARM::VSCCLRMD || MI.getOpcode() == ARM::VSCCLRMS)
1733  --NumRegs;
1734  if (SPRRegs)
1735  Binary |= NumRegs;
1736  else
1737  Binary |= NumRegs * 2;
1738  } else {
1739  const MCRegisterInfo &MRI = *CTX.getRegisterInfo();
1741  [&](const MCOperand &LHS, const MCOperand &RHS) {
1742  return MRI.getEncodingValue(LHS.getReg()) <
1743  MRI.getEncodingValue(RHS.getReg());
1744  }));
1745  for (unsigned I = Op, E = MI.getNumOperands(); I < E; ++I) {
1746  unsigned RegNo = MRI.getEncodingValue(MI.getOperand(I).getReg());
1747  Binary |= 1 << RegNo;
1748  }
1749  }
1750 
1751  return Binary;
1752 }
1753 
1754 /// getAddrMode6AddressOpValue - Encode an addrmode6 register number along
1755 /// with the alignment operand.
1756 unsigned ARMMCCodeEmitter::
1757 getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op,
1759  const MCSubtargetInfo &STI) const {
1760  const MCOperand &Reg = MI.getOperand(Op);
1761  const MCOperand &Imm = MI.getOperand(Op + 1);
1762 
1763  unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg.getReg());
1764  unsigned Align = 0;
1765 
1766  switch (Imm.getImm()) {
1767  default: break;
1768  case 2:
1769  case 4:
1770  case 8: Align = 0x01; break;
1771  case 16: Align = 0x02; break;
1772  case 32: Align = 0x03; break;
1773  }
1774 
1775  return RegNo | (Align << 4);
1776 }
1777 
1778 /// getAddrMode6OneLane32AddressOpValue - Encode an addrmode6 register number
1779 /// along with the alignment operand for use in VST1 and VLD1 with size 32.
1780 unsigned ARMMCCodeEmitter::
1781 getAddrMode6OneLane32AddressOpValue(const MCInst &MI, unsigned Op,
1783  const MCSubtargetInfo &STI) const {
1784  const MCOperand &Reg = MI.getOperand(Op);
1785  const MCOperand &Imm = MI.getOperand(Op + 1);
1786 
1787  unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg.getReg());
1788  unsigned Align = 0;
1789 
1790  switch (Imm.getImm()) {
1791  default: break;
1792  case 8:
1793  case 16:
1794  case 32: // Default '0' value for invalid alignments of 8, 16, 32 bytes.
1795  case 2: Align = 0x00; break;
1796  case 4: Align = 0x03; break;
1797  }
1798 
1799  return RegNo | (Align << 4);
1800 }
1801 
1802 
1803 /// getAddrMode6DupAddressOpValue - Encode an addrmode6 register number and
1804 /// alignment operand for use in VLD-dup instructions. This is the same as
1805 /// getAddrMode6AddressOpValue except for the alignment encoding, which is
1806 /// different for VLD4-dup.
1807 unsigned ARMMCCodeEmitter::
1808 getAddrMode6DupAddressOpValue(const MCInst &MI, unsigned Op,
1810  const MCSubtargetInfo &STI) const {
1811  const MCOperand &Reg = MI.getOperand(Op);
1812  const MCOperand &Imm = MI.getOperand(Op + 1);
1813 
1814  unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg.getReg());
1815  unsigned Align = 0;
1816 
1817  switch (Imm.getImm()) {
1818  default: break;
1819  case 2:
1820  case 4:
1821  case 8: Align = 0x01; break;
1822  case 16: Align = 0x03; break;
1823  }
1824 
1825  return RegNo | (Align << 4);
1826 }
1827 
1828 unsigned ARMMCCodeEmitter::
1829 getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op,
1831  const MCSubtargetInfo &STI) const {
1832  const MCOperand &MO = MI.getOperand(Op);
1833  if (MO.getReg() == 0) return 0x0D;
1834  return CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1835 }
1836 
1837 unsigned ARMMCCodeEmitter::
1838 getShiftRight8Imm(const MCInst &MI, unsigned Op,
1840  const MCSubtargetInfo &STI) const {
1841  return 8 - MI.getOperand(Op).getImm();
1842 }
1843 
1844 unsigned ARMMCCodeEmitter::
1845 getShiftRight16Imm(const MCInst &MI, unsigned Op,
1847  const MCSubtargetInfo &STI) const {
1848  return 16 - MI.getOperand(Op).getImm();
1849 }
1850 
1851 unsigned ARMMCCodeEmitter::
1852 getShiftRight32Imm(const MCInst &MI, unsigned Op,
1854  const MCSubtargetInfo &STI) const {
1855  return 32 - MI.getOperand(Op).getImm();
1856 }
1857 
1858 unsigned ARMMCCodeEmitter::
1859 getShiftRight64Imm(const MCInst &MI, unsigned Op,
1861  const MCSubtargetInfo &STI) const {
1862  return 64 - MI.getOperand(Op).getImm();
1863 }
1864 
1865 void ARMMCCodeEmitter::
1866 encodeInstruction(const MCInst &MI, raw_ostream &OS,
1868  const MCSubtargetInfo &STI) const {
1869  // Pseudo instructions don't get encoded.
1870  const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
1871  uint64_t TSFlags = Desc.TSFlags;
1872  if ((TSFlags & ARMII::FormMask) == ARMII::Pseudo)
1873  return;
1874 
1875  int Size;
1876  if (Desc.getSize() == 2 || Desc.getSize() == 4)
1877  Size = Desc.getSize();
1878  else
1879  llvm_unreachable("Unexpected instruction size!");
1880 
1881  uint32_t Binary = getBinaryCodeForInstr(MI, Fixups, STI);
1882  // Thumb 32-bit wide instructions need to emit the high order halfword
1883  // first.
1884  if (isThumb(STI) && Size == 4) {
1885  EmitConstant(Binary >> 16, 2, OS);
1886  EmitConstant(Binary & 0xffff, 2, OS);
1887  } else
1888  EmitConstant(Binary, Size, OS);
1889  ++MCNumEmitted; // Keep track of the # of mi's emitted.
1890 }
1891 
1892 template <bool isNeg, ARM::Fixups fixup>
1893 uint32_t
1894 ARMMCCodeEmitter::getBFTargetOpValue(const MCInst &MI, unsigned OpIdx,
1896  const MCSubtargetInfo &STI) const {
1897  const MCOperand MO = MI.getOperand(OpIdx);
1898  if (MO.isExpr())
1900  return isNeg ? -(MO.getImm() >> 1) : (MO.getImm() >> 1);
1901 }
1902 
1903 uint32_t
1904 ARMMCCodeEmitter::getBFAfterTargetOpValue(const MCInst &MI, unsigned OpIdx,
1906  const MCSubtargetInfo &STI) const {
1907  const MCOperand MO = MI.getOperand(OpIdx);
1908  const MCOperand BranchMO = MI.getOperand(0);
1909 
1910  if (MO.isExpr()) {
1911  assert(BranchMO.isExpr());
1912  const MCExpr *DiffExpr = MCBinaryExpr::createSub(
1913  MO.getExpr(), BranchMO.getExpr(), CTX);
1915  Fixups.push_back(llvm::MCFixup::create(0, DiffExpr, Kind, MI.getLoc()));
1916  return 0;
1917  }
1918 
1919  assert(MO.isImm() && BranchMO.isImm());
1920  int Diff = MO.getImm() - BranchMO.getImm();
1921  assert(Diff == 4 || Diff == 2);
1922 
1923  return Diff == 4;
1924 }
1925 
1926 uint32_t ARMMCCodeEmitter::getVPTMaskOpValue(const MCInst &MI, unsigned OpIdx,
1928  const MCSubtargetInfo &STI)const {
1929  const MCOperand MO = MI.getOperand(OpIdx);
1930  assert(MO.isImm() && "Unexpected operand type!");
1931 
1932  int Value = MO.getImm();
1933  int Imm = 0;
1934 
1935  // VPT Masks are actually encoded as a series of invert/don't invert bits,
1936  // rather than true/false bits.
1937  unsigned PrevBit = 0;
1938  for (int i = 3; i >= 0; --i) {
1939  unsigned Bit = (Value >> i) & 1;
1940 
1941  // Check if we are at the end of the mask.
1942  if ((Value & ~(~0U << i)) == 0) {
1943  Imm |= (1 << i);
1944  break;
1945  }
1946 
1947  // Convert the bit in the mask based on the previous bit.
1948  if (Bit != PrevBit)
1949  Imm |= (1 << i);
1950 
1951  PrevBit = Bit;
1952  }
1953 
1954  return Imm;
1955 }
1956 
1957 uint32_t ARMMCCodeEmitter::getRestrictedCondCodeOpValue(
1958  const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups,
1959  const MCSubtargetInfo &STI) const {
1960 
1961  const MCOperand MO = MI.getOperand(OpIdx);
1962  assert(MO.isImm() && "Unexpected operand type!");
1963 
1964  switch (MO.getImm()) {
1965  default:
1966  assert(0 && "Unexpected Condition!");
1967  return 0;
1968  case ARMCC::HS:
1969  case ARMCC::EQ:
1970  return 0;
1971  case ARMCC::HI:
1972  case ARMCC::NE:
1973  return 1;
1974  case ARMCC::GE:
1975  return 4;
1976  case ARMCC::LT:
1977  return 5;
1978  case ARMCC::GT:
1979  return 6;
1980  case ARMCC::LE:
1981  return 7;
1982  }
1983 }
1984 
1985 uint32_t ARMMCCodeEmitter::
1986 getPowerTwoOpValue(const MCInst &MI, unsigned OpIdx,
1988  const MCSubtargetInfo &STI) const {
1989  const MCOperand &MO = MI.getOperand(OpIdx);
1990  assert(MO.isImm() && "Unexpected operand type!");
1991  return countTrailingZeros((uint64_t)MO.getImm());
1992 }
1993 
1994 template <unsigned start>
1995 uint32_t ARMMCCodeEmitter::
1996 getMVEPairVectorIndexOpValue(const MCInst &MI, unsigned OpIdx,
1998  const MCSubtargetInfo &STI) const {
1999  const MCOperand MO = MI.getOperand(OpIdx);
2000  assert(MO.isImm() && "Unexpected operand type!");
2001 
2002  int Value = MO.getImm();
2003  return Value - start;
2004 }
2005 
2006 #include "ARMGenMCCodeEmitter.inc"
2007 
2009  const MCRegisterInfo &MRI,
2010  MCContext &Ctx) {
2011  return new ARMMCCodeEmitter(MCII, Ctx, true);
2012 }
2013 
2015  const MCRegisterInfo &MRI,
2016  MCContext &Ctx) {
2017  return new ARMMCCodeEmitter(MCII, Ctx, false);
2018 }
llvm::Check::Size
@ Size
Definition: FileCheck.h:73
llvm::ARM_AM::ror
@ ror
Definition: ARMAddressingModes.h:32
i
i
Definition: README.txt:29
llvm::lltok::APFloat
@ APFloat
Definition: LLToken.h:495
llvm::ARM::fixup_t2_pcrel_9
@ fixup_t2_pcrel_9
Definition: ARMFixupKinds.h:38
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:105
MathExtras.h
llvm
This file implements support for optimizing divisions by a constant.
Definition: AllocatorList.h:23
Reg
unsigned Reg
Definition: MachineSink.cpp:1566
llvm::ARM_AM::getAM3Offset
unsigned char getAM3Offset(unsigned AM3Opc)
Definition: ARMAddressingModes.h:450
llvm::ARM_AM::lsr
@ lsr
Definition: ARMAddressingModes.h:31
llvm::drop_begin
auto drop_begin(T &&RangeOrContainer, size_t N=1)
Return a range covering RangeOrContainer with the first N elements excluded.
Definition: STLExtras.h:266
llvm::ARM::PredBlockMask::TT
@ TT
llvm::FixupKind
static Lanai::Fixups FixupKind(const MCExpr *Expr)
Definition: LanaiMCCodeEmitter.cpp:90
llvm::ARM::fixup_arm_ldst_pcrel_12
@ fixup_arm_ldst_pcrel_12
Definition: ARMFixupKinds.h:18
HasConditionalBranch
static bool HasConditionalBranch(const MCInst &MI)
Return true if this branch has a non-always predication.
Definition: ARMMCCodeEmitter.cpp:717
llvm::MCOperand::isReg
bool isReg() const
Definition: MCInst.h:61
MCInstrDesc.h
llvm::MCContext
Context object for machine code objects.
Definition: MCContext.h:72
llvm::MCContext::getRegisterInfo
const MCRegisterInfo * getRegisterInfo() const
Definition: MCContext.h:425
MCCodeEmitter.h
llvm::ARM::fixup_arm_pcrel_9
@ fixup_arm_pcrel_9
Definition: ARMFixupKinds.h:35
llvm::ARMCC::GE
@ GE
Definition: ARMBaseInfo.h:41
Statistic.h
llvm::MCFixup::create
static MCFixup create(uint32_t Offset, const MCExpr *Value, MCFixupKind Kind, SMLoc Loc=SMLoc())
Definition: MCFixup.h:87
ErrorHandling.h
encodeThumbBLOffset
static int32_t encodeThumbBLOffset(int32_t offset)
Definition: ARMMCCodeEmitter.cpp:639
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:45
llvm::ARM::fixup_arm_adr_pcrel_12
@ fixup_arm_adr_pcrel_12
Definition: ARMFixupKinds.h:45
llvm::ARM_AM::getAM3Op
AddrOpc getAM3Op(unsigned AM3Opc)
Definition: ARMAddressingModes.h:451
APInt.h
llvm::MCRegisterInfo::getEncodingValue
uint16_t getEncodingValue(MCRegister RegNo) const
Returns the encoding for RegNo.
Definition: MCRegisterInfo.h:553
Shift
bool Shift
Definition: README.txt:468
llvm::tgtok::Bits
@ Bits
Definition: TGLexer.h:50
llvm::ARM_AM::getAM2Offset
unsigned getAM2Offset(unsigned AM2Opc)
Definition: ARMAddressingModes.h:419
llvm::ARMII::Pseudo
@ Pseudo
Definition: ARMBaseInfo.h:314
llvm::ARM_AM::getSORegOffset
unsigned getSORegOffset(unsigned Op)
Definition: ARMAddressingModes.h:115
Offset
uint64_t Offset
Definition: ELFObjHandler.cpp:81
ARMMCExpr.h
llvm::ARM_AM::ShiftOpc
ShiftOpc
Definition: ARMAddressingModes.h:27
llvm::ARMMCExpr::getKind
VariantKind getKind() const
getOpcode - Get the kind of this expression.
Definition: ARMMCExpr.h:51
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
llvm::ARM::fixup_arm_mod_imm
@ fixup_arm_mod_imm
Definition: ARMFixupKinds.h:103
tmp
alloca< 16 x float >, align 16 %tmp2=alloca< 16 x float >, align 16 store< 16 x float > %A,< 16 x float > *%tmp %s=bitcast< 16 x float > *%tmp to i8 *%s2=bitcast< 16 x float > *%tmp2 to i8 *call void @llvm.memcpy.i64(i8 *%s, i8 *%s2, i64 64, i32 16) %R=load< 16 x float > *%tmp2 ret< 16 x float > %R } declare void @llvm.memcpy.i64(i8 *nocapture, i8 *nocapture, i64, i32) nounwind which compiles to:_foo:subl $140, %esp movaps %xmm3, 112(%esp) movaps %xmm2, 96(%esp) movaps %xmm1, 80(%esp) movaps %xmm0, 64(%esp) movl 60(%esp), %eax movl %eax, 124(%esp) movl 56(%esp), %eax movl %eax, 120(%esp) movl 52(%esp), %eax< many many more 32-bit copies > movaps(%esp), %xmm0 movaps 16(%esp), %xmm1 movaps 32(%esp), %xmm2 movaps 48(%esp), %xmm3 addl $140, %esp ret On Nehalem, it may even be cheaper to just use movups when unaligned than to fall back to lower-granularity chunks. Implement processor-specific optimizations for parity with GCC on these processors. GCC does two optimizations:1. ix86_pad_returns inserts a noop before ret instructions if immediately preceded by a conditional branch or is the target of a jump. 2. ix86_avoid_jump_misspredicts inserts noops in cases where a 16-byte block of code contains more than 3 branches. The first one is done for all AMDs, Core2, and "Generic" The second one is done for:Atom, Pentium Pro, all AMDs, Pentium 4, Nocona, Core 2, and "Generic" Testcase:int x(int a) { return(a &0xf0)> >4 tmp
Definition: README.txt:1347
llvm::ARM::fixup_arm_movt_hi16
@ fixup_arm_movt_hi16
Definition: ARMFixupKinds.h:97
llvm::msgpack::Type::Binary
@ Binary
llvm::BitmaskEnumDetail::Mask
std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
llvm::ARM::fixup_thumb_adr_pcrel_10
@ fixup_thumb_adr_pcrel_10
Definition: ARMFixupKinds.h:43
llvm::ARM::fixup_t2_uncondbranch
@ fixup_t2_uncondbranch
Definition: ARMFixupKinds.h:57
llvm::ARM_AM::getAM5Op
AddrOpc getAM5Op(unsigned AM5Opc)
Definition: ARMAddressingModes.h:494
llvm::ARMII::FormMask
@ FormMask
Definition: ARMBaseInfo.h:311
ARMFixupKinds.h
x3
In x86 we generate this spiffy xmm0 xmm0 ret in x86 we generate this which could be xmm1 movss xmm1 xmm0 ret In sse4 we could use insertps to make both better Here s another testcase that could use x3
Definition: README-SSE.txt:547
llvm::createARMBEMCCodeEmitter
MCCodeEmitter * createARMBEMCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, MCContext &Ctx)
Definition: ARMMCCodeEmitter.cpp:2014
llvm::MCInstrDesc::TSFlags
uint64_t TSFlags
Definition: MCInstrDesc.h:203
llvm::ARMCC::EQ
@ EQ
Definition: ARMBaseInfo.h:31
llvm::ARM_AM::getSOImmVal
int getSOImmVal(unsigned Arg)
getSOImmVal - Given a 32-bit immediate, if it is something that can fit into an shifter_operand immed...
Definition: ARMAddressingModes.h:163
llvm::MCInstrDesc::getSize
unsigned getSize() const
Return the number of bytes in the encoding of this instruction, or zero if the encoding size cannot b...
Definition: MCInstrDesc.h:616
llvm::ARM_AM::getSORegShOp
ShiftOpc getSORegShOp(unsigned Op)
Definition: ARMAddressingModes.h:116
ARMBaseInfo.h
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
llvm::ARM::fixup_arm_thumb_br
@ fixup_arm_thumb_br
Definition: ARMFixupKinds.h:60
llvm::MCExpr::Target
@ Target
Target specific expression.
Definition: MCExpr.h:42
llvm::ARM::fixup_arm_ldst_abs_12
@ fixup_arm_ldst_abs_12
Definition: ARMFixupKinds.h:40
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
llvm::MCSubtargetInfo::getTargetTriple
const Triple & getTargetTriple() const
Definition: MCSubtargetInfo.h:107
MCContext.h
llvm::ARM_AM::no_shift
@ no_shift
Definition: ARMAddressingModes.h:28
llvm::ARM_AM::getAM2Op
AddrOpc getAM2Op(unsigned AM2Opc)
Definition: ARMAddressingModes.h:422
llvm::M68kBeads::Imm8
@ Imm8
Definition: M68kBaseInfo.h:63
MCInstrInfo.h
llvm::MCOperand::getImm
int64_t getImm() const
Definition: MCInst.h:80
MCInst.h
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:195
llvm::AArch64::Fixups
Fixups
Definition: AArch64FixupKinds.h:17
MCSubtargetInfo.h
llvm::MCSubtargetInfo::getFeatureBits
const FeatureBitset & getFeatureBits() const
Definition: MCSubtargetInfo.h:111
llvm::M0
unsigned M0(unsigned Val)
Definition: VE.h:371
llvm::ARMCC::HI
@ HI
Definition: ARMBaseInfo.h:39
getBranchTargetOpValue
static uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, unsigned FixupKind, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI)
getBranchTargetOpValue - Helper function to get the branch target operand, which is either an immedia...
Definition: ARMMCCodeEmitter.cpp:620
llvm::ARM::fixup_arm_uncondbl
@ fixup_arm_uncondbl
Definition: ARMFixupKinds.h:72
llvm::report_fatal_error
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:140
llvm::STATISTIC
STATISTIC(NumFunctions, "Total number of functions")
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:53
APFloat.h
This file declares a class to represent arbitrary precision floating point values and provide a varie...
llvm::ARM::fixup_t2_pcrel_10
@ fixup_t2_pcrel_10
Definition: ARMFixupKinds.h:32
llvm::createARMLEMCCodeEmitter
MCCodeEmitter * createARMLEMCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, MCContext &Ctx)
Definition: ARMMCCodeEmitter.cpp:2008
isThumb
static bool isThumb(const MCSubtargetInfo &STI)
Definition: ARMAsmPrinter.cpp:470
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::ARM_AM::getT2SOImmVal
int getT2SOImmVal(unsigned Arg)
getT2SOImmVal - Given a 32-bit immediate, if it is something that can fit into a Thumb-2 shifter_oper...
Definition: ARMAddressingModes.h:320
llvm::ARM::fixup_arm_condbranch
@ fixup_arm_condbranch
Definition: ARMFixupKinds.h:49
llvm::ARM_AM::AMSubMode
AMSubMode
Definition: ARMAddressingModes.h:66
llvm::lltok::Kind
Kind
Definition: LLToken.h:18
llvm::ARM::fixup_t2_adr_pcrel_12
@ fixup_t2_adr_pcrel_12
Definition: ARMFixupKinds.h:47
llvm::ARMMCExpr::getSubExpr
const MCExpr * getSubExpr() const
getSubExpr - Get the child of this expression.
Definition: ARMMCExpr.h:54
llvm::MCConstantExpr
Definition: MCExpr.h:144
llvm::ARM::fixup_t2_so_imm
@ fixup_t2_so_imm
Definition: ARMFixupKinds.h:106
llvm::ARM_AM::rrx
@ rrx
Definition: ARMAddressingModes.h:33
llvm::ARMCC::NE
@ NE
Definition: ARMBaseInfo.h:32
llvm::ARM::fixup_arm_movw_lo16
@ fixup_arm_movw_lo16
Definition: ARMFixupKinds.h:98
llvm::ARM::fixup_arm_thumb_bl
@ fixup_arm_thumb_bl
Definition: ARMFixupKinds.h:81
llvm::ARMCC::AL
@ AL
Definition: ARMBaseInfo.h:45
llvm::ARM::fixup_bfcsel_else_target
@ fixup_bfcsel_else_target
Definition: ARMFixupKinds.h:113
llvm::MCOperand::isImm
bool isImm() const
Definition: MCInst.h:62
uint64_t
llvm::ARM_MB::ST
@ ST
Definition: ARMBaseInfo.h:73
EmitConstant
static unsigned EmitConstant(uint64_t Val, unsigned Size, unsigned Pad, uint64_t &Buffer, unsigned Offset)
Definition: M68kMCCodeEmitter.cpp:173
llvm::ARM::fixup_arm_thumb_blx
@ fixup_arm_thumb_blx
Definition: ARMFixupKinds.h:84
llvm::ARM_AM::add
@ add
Definition: ARMAddressingModes.h:39
llvm::ARMMCExpr
Definition: ARMMCExpr.h:16
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::ARMII::RegRsShift
@ RegRsShift
Definition: ARMBaseInfo.h:443
MCRegisterInfo.h
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::ARM::fixup_t2_movt_hi16
@ fixup_t2_movt_hi16
Definition: ARMFixupKinds.h:99
llvm::ARMMCExpr::VK_ARM_LO16
@ VK_ARM_LO16
Definition: ARMMCExpr.h:21
llvm::MCBinaryExpr::createSub
static const MCBinaryExpr * createSub(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition: MCExpr.h:609
Mode
SI Whole Quad Mode
Definition: SIWholeQuadMode.cpp:262
isReg
static bool isReg(const MCInst &MI, unsigned OpNo)
Definition: MipsInstPrinter.cpp:31
Triple.h
llvm::ARMCC::GT
@ GT
Definition: ARMBaseInfo.h:43
ARMAddressingModes.h
llvm::countTrailingZeros
unsigned countTrailingZeros(T Val, ZeroBehavior ZB=ZB_Width)
Count number of 0's from the least significant bit to the most stopping at the first 1.
Definition: MathExtras.h:156
llvm::ARM::fixup_t2_ldst_pcrel_12
@ fixup_t2_ldst_pcrel_12
Definition: ARMFixupKinds.h:21
llvm::ARM::fixup_arm_thumb_bcc
@ fixup_arm_thumb_bcc
Definition: ARMFixupKinds.h:93
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:134
uint32_t
MCFixup.h
Compiler.h
llvm::ARM::fixup_arm_uncondbranch
@ fixup_arm_uncondbranch
Definition: ARMFixupKinds.h:51
S
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
Definition: README.txt:210
llvm::ARM::fixup_arm_condbl
@ fixup_arm_condbl
Definition: ARMFixupKinds.h:75
llvm::MCRegisterInfo
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Definition: MCRegisterInfo.h:135
llvm::ARM_AM::getAM2ShiftOpc
ShiftOpc getAM2ShiftOpc(unsigned AM2Opc)
Definition: ARMAddressingModes.h:425
LLVM_FALLTHROUGH
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:286
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
adjust::ldi::fixup
static void fixup(unsigned Size, const MCFixup &Fixup, uint64_t &Value, MCContext *Ctx=nullptr)
Adjusts a value to fix up the immediate of an LDI Rd, K instruction.
Definition: AVRAsmBackend.cpp:202
llvm::ARMCC::HS
@ HS
Definition: ARMBaseInfo.h:33
llvm::ARM_AM::ia
@ ia
Definition: ARMAddressingModes.h:68
llvm::ARM::fixup_t2_movw_lo16
@ fixup_t2_movw_lo16
Definition: ARMFixupKinds.h:100
llvm::MCInstrInfo
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:25
llvm::ARMCC::LE
@ LE
Definition: ARMBaseInfo.h:44
llvm::MCCodeEmitter
MCCodeEmitter - Generic instruction encoding interface.
Definition: MCCodeEmitter.h:21
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:324
Casting.h
llvm::ARM_AM::getAM5Offset
unsigned char getAM5Offset(unsigned AM5Opc)
Definition: ARMAddressingModes.h:493
llvm::MCOperand::getExpr
const MCExpr * getExpr() const
Definition: MCInst.h:114
llvm::ARM_AM::da
@ da
Definition: ARMAddressingModes.h:70
llvm::TargetStackID::Value
Value
Definition: TargetFrameLowering.h:27
llvm::is_sorted
bool is_sorted(R &&Range, Compare C)
Wrapper function around std::is_sorted to check if elements in a range R are sorted with respect to a...
Definition: STLExtras.h:1622
llvm::ARM::fixup_t2_condbranch
@ fixup_t2_condbranch
Definition: ARMFixupKinds.h:54
llvm::ARMCC::CondCodes
CondCodes
Definition: ARMBaseInfo.h:30
llvm::countLeadingZeros
unsigned countLeadingZeros(T Val, ZeroBehavior ZB=ZB_Width)
Count number of 0's from the most significant bit to the least stopping at the first 1.
Definition: MathExtras.h:225
llvm::MCOperand::isExpr
bool isExpr() const
Definition: MCInst.h:65
llvm::ARM_AM::db
@ db
Definition: ARMAddressingModes.h:71
llvm::MCFixupKind
MCFixupKind
Extensible enumeration to represent the type of a fixup.
Definition: MCFixup.h:21
false
Function Alias Analysis false
Definition: AliasAnalysis.cpp:847
llvm::MCOperand::getDFPImm
uint64_t getDFPImm() const
Definition: MCInst.h:100
SmallVector.h
llvm::ARM::fixup_arm_pcrel_10_unscaled
@ fixup_arm_pcrel_10_unscaled
Definition: ARMFixupKinds.h:25
llvm::ARMMCExpr::VK_ARM_HI16
@ VK_ARM_HI16
Definition: ARMMCExpr.h:20
llvm::ARM::fixup_arm_thumb_cb
@ fixup_arm_thumb_cb
Definition: ARMFixupKinds.h:87
llvm::ARM_AM::ib
@ ib
Definition: ARMAddressingModes.h:69
shift
http eax xorl edx cl sete al setne dl sall eax sall edx But that requires good bit subreg support this might be better It s an extra shift
Definition: README.txt:30
llvm::tgtok::Bit
@ Bit
Definition: TGLexer.h:50
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:43
llvm::MCOperand
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:36
llvm::ARM::fixup_arm_pcrel_10
@ fixup_arm_pcrel_10
Definition: ARMFixupKinds.h:29
llvm::MCInstrInfo::get
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode.
Definition: MCInstrInfo.h:62
llvm::ARM::fixup_arm_thumb_cp
@ fixup_arm_thumb_cp
Definition: ARMFixupKinds.h:90
llvm::M1
unsigned M1(unsigned Val)
Definition: VE.h:372
llvm::ARM::fixup_arm_blx
@ fixup_arm_blx
Definition: ARMFixupKinds.h:78
raw_ostream.h
llvm::abs
APFloat abs(APFloat X)
Returns the absolute value of the argument.
Definition: APFloat.h:1282
MCExpr.h
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition: MCSubtargetInfo.h:75
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
llvm::MCOperand::isDFPImm
bool isDFPImm() const
Definition: MCInst.h:64
llvm::MCExpr
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:35
llvm::ARM_AM::lsl
@ lsl
Definition: ARMAddressingModes.h:30
llvm::ARM_AM::asr
@ asr
Definition: ARMAddressingModes.h:29
llvm::ARMCC::LT
@ LT
Definition: ARMBaseInfo.h:42
llvm::MCOperand::getReg
unsigned getReg() const
Returns the register number.
Definition: MCInst.h:69