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ARMMCCodeEmitter.cpp
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1//===-- ARM/ARMMCCodeEmitter.cpp - Convert ARM code to machine code -------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements the ARMMCCodeEmitter class.
10//
11//===----------------------------------------------------------------------===//
12
13#include "MCTargetDesc/ARMAddressingModes.h"
14#include "MCTargetDesc/ARMBaseInfo.h"
15#include "MCTargetDesc/ARMFixupKinds.h"
16#include "MCTargetDesc/ARMMCAsmInfo.h"
17#include "llvm/ADT/APFloat.h"
18#include "llvm/ADT/APInt.h"
19#include "llvm/ADT/SmallVector.h"
20#include "llvm/ADT/Statistic.h"
21#include "llvm/MC/MCCodeEmitter.h"
22#include "llvm/MC/MCContext.h"
23#include "llvm/MC/MCExpr.h"
24#include "llvm/MC/MCFixup.h"
25#include "llvm/MC/MCInst.h"
26#include "llvm/MC/MCInstrDesc.h"
27#include "llvm/MC/MCInstrInfo.h"
28#include "llvm/MC/MCRegisterInfo.h"
29#include "llvm/MC/MCSubtargetInfo.h"
30#include "llvm/Support/Casting.h"
31#include "llvm/Support/Compiler.h"
32#include "llvm/Support/EndianStream.h"
33#include "llvm/Support/ErrorHandling.h"
34#include "llvm/Support/MathExtras.h"
35#include "llvm/TargetParser/Triple.h"
36#include <cassert>
37#include <cstdint>
38#include <cstdlib>
39
40using namespace llvm;
41
42#define DEBUG_TYPE "mccodeemitter"
43
44STATISTIC(MCNumEmitted, "Number of MC instructions emitted.");
45STATISTIC(MCNumCPRelocations, "Number of constant pool relocations created.");
46
47namespace {
48
49class ARMMCCodeEmitter : public MCCodeEmitter {
50 const MCInstrInfo &MCII;
51 MCContext &CTX;
52 bool IsLittleEndian;
53
54public:
55 ARMMCCodeEmitter(const MCInstrInfo &mcii, MCContext &ctx, bool IsLittle)
56 : MCII(mcii), CTX(ctx), IsLittleEndian(IsLittle) {
57 }
58 ARMMCCodeEmitter(const ARMMCCodeEmitter &) = delete;
59 ARMMCCodeEmitter &operator=(const ARMMCCodeEmitter &) = delete;
60 ~ARMMCCodeEmitter() override = default;
61
62 bool isThumb(const MCSubtargetInfo &STI) const {
63 return STI.hasFeature(ARM::ModeThumb);
64 }
65
66 bool isThumb2(const MCSubtargetInfo &STI) const {
67 return isThumb(STI) && STI.hasFeature(ARM::FeatureThumb2);
68 }
69
70 bool isTargetMachO(const MCSubtargetInfo &STI) const {
71 const Triple &TT = STI.getTargetTriple();
72 return TT.isOSBinFormatMachO();
73 }
74
75 unsigned getMachineSoImmOpValue(unsigned SoImm) const;
76
77 // getBinaryCodeForInstr - TableGen'erated function for getting the
78 // binary encoding for an instruction.
79 uint64_t getBinaryCodeForInstr(const MCInst &MI,
80 SmallVectorImpl<MCFixup> &Fixups,
81 const MCSubtargetInfo &STI) const;
82
83 /// getMachineOpValue - Return binary encoding of operand. If the machine
84 /// operand requires relocation, record the relocation and return zero.
85 unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
86 SmallVectorImpl<MCFixup> &Fixups,
87 const MCSubtargetInfo &STI) const;
88
89 /// getHiLoImmOpValue - Return the encoding for either the hi / low 16-bit, or
90 /// high/middle-high/middle-low/low 8 bits of the specified operand. This is
91 /// used for operands with :lower16:, :upper16: :lower0_7:, :lower8_15:,
92 /// :higher0_7:, and :higher8_15: prefixes.
93 uint32_t getHiLoImmOpValue(const MCInst &MI, unsigned OpIdx,
94 SmallVectorImpl<MCFixup> &Fixups,
95 const MCSubtargetInfo &STI) const;
96
97 bool EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx,
98 unsigned &Reg, unsigned &Imm,
99 SmallVectorImpl<MCFixup> &Fixups,
100 const MCSubtargetInfo &STI) const;
101
102 /// getThumbBLTargetOpValue - Return encoding info for Thumb immediate
103 /// BL branch target.
104 uint32_t getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
105 SmallVectorImpl<MCFixup> &Fixups,
106 const MCSubtargetInfo &STI) const;
107
108 /// getThumbBLXTargetOpValue - Return encoding info for Thumb immediate
109 /// BLX branch target.
110 uint32_t getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
111 SmallVectorImpl<MCFixup> &Fixups,
112 const MCSubtargetInfo &STI) const;
113
114 /// getThumbBRTargetOpValue - Return encoding info for Thumb branch target.
115 uint32_t getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx,
116 SmallVectorImpl<MCFixup> &Fixups,
117 const MCSubtargetInfo &STI) const;
118
119 /// getThumbBCCTargetOpValue - Return encoding info for Thumb branch target.
120 uint32_t getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx,
121 SmallVectorImpl<MCFixup> &Fixups,
122 const MCSubtargetInfo &STI) const;
123
124 /// getThumbCBTargetOpValue - Return encoding info for Thumb branch target.
125 uint32_t getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx,
126 SmallVectorImpl<MCFixup> &Fixups,
127 const MCSubtargetInfo &STI) const;
128
129 /// getBranchTargetOpValue - Return encoding info for 24-bit immediate
130 /// branch target.
131 uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
132 SmallVectorImpl<MCFixup> &Fixups,
133 const MCSubtargetInfo &STI) const;
134
135 /// getThumbBranchTargetOpValue - Return encoding info for 24-bit
136 /// immediate Thumb2 direct branch target.
137 uint32_t getThumbBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
138 SmallVectorImpl<MCFixup> &Fixups,
139 const MCSubtargetInfo &STI) const;
140
141 /// getARMBranchTargetOpValue - Return encoding info for 24-bit immediate
142 /// branch target.
143 uint32_t getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
144 SmallVectorImpl<MCFixup> &Fixups,
145 const MCSubtargetInfo &STI) const;
146 uint32_t getARMBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
147 SmallVectorImpl<MCFixup> &Fixups,
148 const MCSubtargetInfo &STI) const;
149 uint32_t getARMBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
150 SmallVectorImpl<MCFixup> &Fixups,
151 const MCSubtargetInfo &STI) const;
152
153 /// getAdrLabelOpValue - Return encoding info for 12-bit immediate
154 /// ADR label target.
155 uint32_t getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
156 SmallVectorImpl<MCFixup> &Fixups,
157 const MCSubtargetInfo &STI) const;
158 uint32_t getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
159 SmallVectorImpl<MCFixup> &Fixups,
160 const MCSubtargetInfo &STI) const;
161 uint32_t getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
162 SmallVectorImpl<MCFixup> &Fixups,
163 const MCSubtargetInfo &STI) const;
164
165 uint32_t getITMaskOpValue(const MCInst &MI, unsigned OpIdx,
166 SmallVectorImpl<MCFixup> &Fixups,
167 const MCSubtargetInfo &STI) const;
168
169 /// getMVEShiftImmOpValue - Return encoding info for the 'sz:imm5'
170 /// operand.
171 uint32_t getMVEShiftImmOpValue(const MCInst &MI, unsigned OpIdx,
172 SmallVectorImpl<MCFixup> &Fixups,
173 const MCSubtargetInfo &STI) const;
174
175 /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12'
176 /// operand.
177 uint32_t getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
178 SmallVectorImpl<MCFixup> &Fixups,
179 const MCSubtargetInfo &STI) const;
180
181 /// getThumbAddrModeRegRegOpValue - Return encoding for 'reg + reg' operand.
182 uint32_t getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx,
183 SmallVectorImpl<MCFixup> &Fixups,
184 const MCSubtargetInfo &STI) const;
185
186 /// getT2AddrModeImm8s4OpValue - Return encoding info for 'reg +/- imm8<<2'
187 /// operand.
188 uint32_t getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx,
189 SmallVectorImpl<MCFixup> &Fixups,
190 const MCSubtargetInfo &STI) const;
191
192 /// getT2AddrModeImm7s4OpValue - Return encoding info for 'reg +/- imm7<<2'
193 /// operand.
194 uint32_t getT2AddrModeImm7s4OpValue(const MCInst &MI, unsigned OpIdx,
195 SmallVectorImpl<MCFixup> &Fixups,
196 const MCSubtargetInfo &STI) const;
197
198 /// getT2AddrModeImm0_1020s4OpValue - Return encoding info for 'reg + imm8<<2'
199 /// operand.
200 uint32_t getT2AddrModeImm0_1020s4OpValue(const MCInst &MI, unsigned OpIdx,
201 SmallVectorImpl<MCFixup> &Fixups,
202 const MCSubtargetInfo &STI) const;
203
204 /// getT2ScaledImmOpValue - Return encoding info for '+/- immX<<Y'
205 /// operand.
206 template<unsigned Bits, unsigned Shift>
207 uint32_t getT2ScaledImmOpValue(const MCInst &MI, unsigned OpIdx,
208 SmallVectorImpl<MCFixup> &Fixups,
209 const MCSubtargetInfo &STI) const;
210
211 /// getMveAddrModeRQOpValue - Return encoding info for 'reg, vreg'
212 /// operand.
213 uint32_t getMveAddrModeRQOpValue(const MCInst &MI, unsigned OpIdx,
214 SmallVectorImpl<MCFixup> &Fixups,
215 const MCSubtargetInfo &STI) const;
216
217 /// getMveAddrModeQOpValue - Return encoding info for 'reg +/- imm7<<{shift}'
218 /// operand.
219 template<int shift>
220 uint32_t getMveAddrModeQOpValue(const MCInst &MI, unsigned OpIdx,
221 SmallVectorImpl<MCFixup> &Fixups,
222 const MCSubtargetInfo &STI) const;
223
224 /// getLdStSORegOpValue - Return encoding info for 'reg +/- reg shop imm'
225 /// operand as needed by load/store instructions.
226 uint32_t getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,
227 SmallVectorImpl<MCFixup> &Fixups,
228 const MCSubtargetInfo &STI) const;
229
230 /// getLdStmModeOpValue - Return encoding for load/store multiple mode.
231 uint32_t getLdStmModeOpValue(const MCInst &MI, unsigned OpIdx,
232 SmallVectorImpl<MCFixup> &Fixups,
233 const MCSubtargetInfo &STI) const {
234 ARM_AM::AMSubMode Mode = (ARM_AM::AMSubMode)MI.getOperand(OpIdx).getImm();
235 switch (Mode) {
236 default: llvm_unreachable("Unknown addressing sub-mode!");
237 case ARM_AM::da: return 0;
238 case ARM_AM::ia: return 1;
239 case ARM_AM::db: return 2;
240 case ARM_AM::ib: return 3;
241 }
242 }
243
244 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
245 ///
246 unsigned getShiftOp(ARM_AM::ShiftOpc ShOpc) const {
247 switch (ShOpc) {
248 case ARM_AM::no_shift:
249 case ARM_AM::lsl: return 0;
250 case ARM_AM::lsr: return 1;
251 case ARM_AM::asr: return 2;
252 case ARM_AM::ror:
253 case ARM_AM::rrx: return 3;
254 default:
255 llvm_unreachable("Invalid ShiftOpc!");
256 }
257 }
258
259 /// getAddrMode2OffsetOpValue - Return encoding for am2offset operands.
260 uint32_t getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx,
261 SmallVectorImpl<MCFixup> &Fixups,
262 const MCSubtargetInfo &STI) const;
263
264 /// getPostIdxRegOpValue - Return encoding for postidx_reg operands.
265 uint32_t getPostIdxRegOpValue(const MCInst &MI, unsigned OpIdx,
266 SmallVectorImpl<MCFixup> &Fixups,
267 const MCSubtargetInfo &STI) const;
268
269 /// getAddrMode3OffsetOpValue - Return encoding for am3offset operands.
270 uint32_t getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx,
271 SmallVectorImpl<MCFixup> &Fixups,
272 const MCSubtargetInfo &STI) const;
273
274 /// getAddrMode3OpValue - Return encoding for addrmode3 operands.
275 uint32_t getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx,
276 SmallVectorImpl<MCFixup> &Fixups,
277 const MCSubtargetInfo &STI) const;
278
279 /// getAddrModeThumbSPOpValue - Return encoding info for 'reg +/- imm12'
280 /// operand.
281 uint32_t getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx,
282 SmallVectorImpl<MCFixup> &Fixups,
283 const MCSubtargetInfo &STI) const;
284
285 /// getAddrModeISOpValue - Encode the t_addrmode_is# operands.
286 uint32_t getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx,
287 SmallVectorImpl<MCFixup> &Fixups,
288 const MCSubtargetInfo &STI) const;
289
290 /// getAddrModePCOpValue - Return encoding for t_addrmode_pc operands.
291 uint32_t getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx,
292 SmallVectorImpl<MCFixup> &Fixups,
293 const MCSubtargetInfo &STI) const;
294
295 /// getAddrMode5OpValue - Return encoding info for 'reg +/- (imm8 << 2)' operand.
296 uint32_t getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
297 SmallVectorImpl<MCFixup> &Fixups,
298 const MCSubtargetInfo &STI) const;
299
300 /// getAddrMode5FP16OpValue - Return encoding info for 'reg +/- (imm8 << 1)' operand.
301 uint32_t getAddrMode5FP16OpValue(const MCInst &MI, unsigned OpIdx,
302 SmallVectorImpl<MCFixup> &Fixups,
303 const MCSubtargetInfo &STI) const;
304
305 /// getCCOutOpValue - Return encoding of the 's' bit.
306 unsigned getCCOutOpValue(const MCInst &MI, unsigned Op,
307 SmallVectorImpl<MCFixup> &Fixups,
308 const MCSubtargetInfo &STI) const {
309 // The operand is either reg0 or CPSR. The 's' bit is encoded as '0' or
310 // '1' respectively.
311 return MI.getOperand(Op).getReg() == ARM::CPSR;
312 }
313
314 unsigned getModImmOpValue(const MCInst &MI, unsigned Op,
315 SmallVectorImpl<MCFixup> &Fixups,
316 const MCSubtargetInfo &ST) const;
317
318 /// getT2SOImmOpValue - Return an encoded 12-bit shifted-immediate value.
319 unsigned getT2SOImmOpValue(const MCInst &MI, unsigned Op,
320 SmallVectorImpl<MCFixup> &Fixups,
321 const MCSubtargetInfo &STI) const;
322
323 unsigned getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum,
324 SmallVectorImpl<MCFixup> &Fixups,
325 const MCSubtargetInfo &STI) const;
326 template<unsigned Bits, unsigned Shift>
327 unsigned getT2AddrModeImmOpValue(const MCInst &MI, unsigned OpNum,
328 SmallVectorImpl<MCFixup> &Fixups,
329 const MCSubtargetInfo &STI) const;
330 unsigned getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum,
331 SmallVectorImpl<MCFixup> &Fixups,
332 const MCSubtargetInfo &STI) const;
333
334 /// getSORegOpValue - Return an encoded so_reg shifted register value.
335 unsigned getSORegRegOpValue(const MCInst &MI, unsigned Op,
336 SmallVectorImpl<MCFixup> &Fixups,
337 const MCSubtargetInfo &STI) const;
338 unsigned getSORegImmOpValue(const MCInst &MI, unsigned Op,
339 SmallVectorImpl<MCFixup> &Fixups,
340 const MCSubtargetInfo &STI) const;
341 unsigned getT2SORegOpValue(const MCInst &MI, unsigned Op,
342 SmallVectorImpl<MCFixup> &Fixups,
343 const MCSubtargetInfo &STI) const;
344
345 unsigned getNEONVcvtImm32OpValue(const MCInst &MI, unsigned Op,
346 SmallVectorImpl<MCFixup> &Fixups,
347 const MCSubtargetInfo &STI) const {
348 return 64 - MI.getOperand(Op).getImm();
349 }
350
351 unsigned getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op,
352 SmallVectorImpl<MCFixup> &Fixups,
353 const MCSubtargetInfo &STI) const;
354
355 unsigned getRegisterListOpValue(const MCInst &MI, unsigned Op,
356 SmallVectorImpl<MCFixup> &Fixups,
357 const MCSubtargetInfo &STI) const;
358 unsigned getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op,
359 SmallVectorImpl<MCFixup> &Fixups,
360 const MCSubtargetInfo &STI) const;
361 unsigned getAddrMode6OneLane32AddressOpValue(const MCInst &MI, unsigned Op,
362 SmallVectorImpl<MCFixup> &Fixups,
363 const MCSubtargetInfo &STI) const;
364 unsigned getAddrMode6DupAddressOpValue(const MCInst &MI, unsigned Op,
365 SmallVectorImpl<MCFixup> &Fixups,
366 const MCSubtargetInfo &STI) const;
367 unsigned getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op,
368 SmallVectorImpl<MCFixup> &Fixups,
369 const MCSubtargetInfo &STI) const;
370
371 unsigned getShiftRight8Imm(const MCInst &MI, unsigned Op,
372 SmallVectorImpl<MCFixup> &Fixups,
373 const MCSubtargetInfo &STI) const;
374 unsigned getShiftRight16Imm(const MCInst &MI, unsigned Op,
375 SmallVectorImpl<MCFixup> &Fixups,
376 const MCSubtargetInfo &STI) const;
377 unsigned getShiftRight32Imm(const MCInst &MI, unsigned Op,
378 SmallVectorImpl<MCFixup> &Fixups,
379 const MCSubtargetInfo &STI) const;
380 unsigned getShiftRight64Imm(const MCInst &MI, unsigned Op,
381 SmallVectorImpl<MCFixup> &Fixups,
382 const MCSubtargetInfo &STI) const;
383
384 unsigned getThumbSRImmOpValue(const MCInst &MI, unsigned Op,
385 SmallVectorImpl<MCFixup> &Fixups,
386 const MCSubtargetInfo &STI) const;
387
388 unsigned NEONThumb2DataIPostEncoder(const MCInst &MI,
389 unsigned EncodedValue,
390 const MCSubtargetInfo &STI) const;
391 unsigned NEONThumb2LoadStorePostEncoder(const MCInst &MI,
392 unsigned EncodedValue,
393 const MCSubtargetInfo &STI) const;
394 unsigned NEONThumb2DupPostEncoder(const MCInst &MI,
395 unsigned EncodedValue,
396 const MCSubtargetInfo &STI) const;
397 unsigned NEONThumb2V8PostEncoder(const MCInst &MI,
398 unsigned EncodedValue,
399 const MCSubtargetInfo &STI) const;
400
401 unsigned VFPThumb2PostEncoder(const MCInst &MI,
402 unsigned EncodedValue,
403 const MCSubtargetInfo &STI) const;
404
405 uint32_t getPowerTwoOpValue(const MCInst &MI, unsigned OpIdx,
406 SmallVectorImpl<MCFixup> &Fixups,
407 const MCSubtargetInfo &STI) const;
408
409 void encodeInstruction(const MCInst &MI, SmallVectorImpl<char> &CB,
410 SmallVectorImpl<MCFixup> &Fixups,
411 const MCSubtargetInfo &STI) const override;
412
413 template <bool isNeg, ARM::Fixups fixup>
414 uint32_t getBFTargetOpValue(const MCInst &MI, unsigned OpIdx,
415 SmallVectorImpl<MCFixup> &Fixups,
416 const MCSubtargetInfo &STI) const;
417
418 uint32_t getBFAfterTargetOpValue(const MCInst &MI, unsigned OpIdx,
419 SmallVectorImpl<MCFixup> &Fixups,
420 const MCSubtargetInfo &STI) const;
421
422 uint32_t getVPTMaskOpValue(const MCInst &MI, unsigned OpIdx,
423 SmallVectorImpl<MCFixup> &Fixups,
424 const MCSubtargetInfo &STI) const;
425 uint32_t getRestrictedCondCodeOpValue(const MCInst &MI, unsigned OpIdx,
426 SmallVectorImpl<MCFixup> &Fixups,
427 const MCSubtargetInfo &STI) const;
428 template <unsigned size>
429 uint32_t getMVEPairVectorIndexOpValue(const MCInst &MI, unsigned OpIdx,
430 SmallVectorImpl<MCFixup> &Fixups,
431 const MCSubtargetInfo &STI) const;
432};
433
434} // end anonymous namespace
435
473
474/// NEONThumb2DataIPostEncoder - Post-process encoded NEON data-processing
475/// instructions, and rewrite them to their Thumb2 form if we are currently in
476/// Thumb2 mode.
477unsigned ARMMCCodeEmitter::NEONThumb2DataIPostEncoder(const MCInst &MI,
478 unsigned EncodedValue,
479 const MCSubtargetInfo &STI) const {
480 if (isThumb2(STI)) {
481 // NEON Thumb2 data-processsing encodings are very simple: bit 24 is moved
482 // to bit 12 of the high half-word (i.e. bit 28), and bits 27-24 are
483 // set to 1111.
484 unsigned Bit24 = EncodedValue & 0x01000000;
485 unsigned Bit28 = Bit24 << 4;
486 EncodedValue &= 0xEFFFFFFF;
487 EncodedValue |= Bit28;
488 EncodedValue |= 0x0F000000;
489 }
490
491 return EncodedValue;
492}
493
494/// NEONThumb2LoadStorePostEncoder - Post-process encoded NEON load/store
495/// instructions, and rewrite them to their Thumb2 form if we are currently in
496/// Thumb2 mode.
497unsigned ARMMCCodeEmitter::NEONThumb2LoadStorePostEncoder(const MCInst &MI,
498 unsigned EncodedValue,
499 const MCSubtargetInfo &STI) const {
500 if (isThumb2(STI)) {
501 EncodedValue &= 0xF0FFFFFF;
502 EncodedValue |= 0x09000000;
503 }
504
505 return EncodedValue;
506}
507
508/// NEONThumb2DupPostEncoder - Post-process encoded NEON vdup
509/// instructions, and rewrite them to their Thumb2 form if we are currently in
510/// Thumb2 mode.
511unsigned ARMMCCodeEmitter::NEONThumb2DupPostEncoder(const MCInst &MI,
512 unsigned EncodedValue,
513 const MCSubtargetInfo &STI) const {
514 if (isThumb2(STI)) {
515 EncodedValue &= 0x00FFFFFF;
516 EncodedValue |= 0xEE000000;
517 }
518
519 return EncodedValue;
520}
521
522/// Post-process encoded NEON v8 instructions, and rewrite them to Thumb2 form
523/// if we are in Thumb2.
524unsigned ARMMCCodeEmitter::NEONThumb2V8PostEncoder(const MCInst &MI,
525 unsigned EncodedValue,
526 const MCSubtargetInfo &STI) const {
527 if (isThumb2(STI)) {
528 EncodedValue |= 0xC000000; // Set bits 27-26
529 }
530
531 return EncodedValue;
532}
533
534/// VFPThumb2PostEncoder - Post-process encoded VFP instructions and rewrite
535/// them to their Thumb2 form if we are currently in Thumb2 mode.
536unsigned ARMMCCodeEmitter::
537VFPThumb2PostEncoder(const MCInst &MI, unsigned EncodedValue,
538 const MCSubtargetInfo &STI) const {
539 if (isThumb2(STI)) {
540 EncodedValue &= 0x0FFFFFFF;
541 EncodedValue |= 0xE0000000;
542 }
543 return EncodedValue;
544}
545
546/// getMachineOpValue - Return binary encoding of operand. If the machine
547/// operand requires relocation, record the relocation and return zero.
548unsigned ARMMCCodeEmitter::
549getMachineOpValue(const MCInst &MI, const MCOperand &MO,
550 SmallVectorImpl<MCFixup> &Fixups,
551 const MCSubtargetInfo &STI) const {
552 if (MO.isReg()) {
553 MCRegister Reg = MO.getReg();
554 unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg);
555
556 // In NEON, Q registers are encoded as 2x their register number,
557 // because they're using the same indices as the D registers they
558 // overlap. In MVE, there are no 64-bit vector instructions, so
559 // the encodings all refer to Q-registers by their literal
560 // register number.
561
562 if (STI.hasFeature(ARM::HasMVEIntegerOps))
563 return RegNo;
564
565 switch (Reg.id()) {
566 default:
567 return RegNo;
568 case ARM::Q0: case ARM::Q1: case ARM::Q2: case ARM::Q3:
569 case ARM::Q4: case ARM::Q5: case ARM::Q6: case ARM::Q7:
570 case ARM::Q8: case ARM::Q9: case ARM::Q10: case ARM::Q11:
571 case ARM::Q12: case ARM::Q13: case ARM::Q14: case ARM::Q15:
572 return 2 * RegNo;
573 }
574 } else if (MO.isImm()) {
575 return static_cast<unsigned>(MO.getImm());
576 } else if (MO.isDFPImm()) {
577 return static_cast<unsigned>(APFloat(bit_cast<double>(MO.getDFPImm()))
578 .bitcastToAPInt()
579 .getHiBits(32)
580 .getLimitedValue());
581 }
582
583 llvm_unreachable("Unable to encode MCOperand!");
584}
585
586/// getAddrModeImmOpValue - Return encoding info for 'reg +/- imm' operand.
587bool ARMMCCodeEmitter::
588EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx, unsigned &Reg,
589 unsigned &Imm, SmallVectorImpl<MCFixup> &Fixups,
590 const MCSubtargetInfo &STI) const {
591 const MCOperand &MO = MI.getOperand(OpIdx);
592 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
593
594 Reg = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
595
596 int32_t SImm = MO1.getImm();
597 bool isAdd = true;
598
599 // Special value for #-0
600 if (SImm == INT32_MIN) {
601 SImm = 0;
602 isAdd = false;
603 }
604
605 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
606 if (SImm < 0) {
607 SImm = -SImm;
608 isAdd = false;
609 }
610
611 Imm = SImm;
612 return isAdd;
613}
614
615/// getBranchTargetOpValue - Helper function to get the branch target operand,
616/// which is either an immediate or requires a fixup.
617static uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
618 unsigned FixupKind,
619 SmallVectorImpl<MCFixup> &Fixups,
620 const MCSubtargetInfo &STI) {
621 const MCOperand &MO = MI.getOperand(OpIdx);
622
623 // If the destination is an immediate, we have nothing to do.
624 if (MO.isImm()) return MO.getImm();
625 assert(MO.isExpr() && "Unexpected branch target type!");
626 const MCExpr *Expr = MO.getExpr();
627 MCFixupKind Kind = MCFixupKind(FixupKind);
628 addFixup(Fixups, 0, Expr, Kind);
629
630 // All of the information is in the fixup.
631 return 0;
632}
633
634// Thumb BL and BLX use a strange offset encoding where bits 22 and 21 are
635// determined by negating them and XOR'ing them with bit 23.
636static int32_t encodeThumbBLOffset(int32_t offset) {
637 offset >>= 1;
638 uint32_t S = (offset & 0x800000) >> 23;
639 uint32_t J1 = (offset & 0x400000) >> 22;
640 uint32_t J2 = (offset & 0x200000) >> 21;
641 J1 = (~J1 & 0x1);
642 J2 = (~J2 & 0x1);
643 J1 ^= S;
644 J2 ^= S;
645
646 offset &= ~0x600000;
647 offset |= J1 << 22;
648 offset |= J2 << 21;
649
650 return offset;
651}
652
653/// getThumbBLTargetOpValue - Return encoding info for immediate branch target.
654uint32_t ARMMCCodeEmitter::
655getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
656 SmallVectorImpl<MCFixup> &Fixups,
657 const MCSubtargetInfo &STI) const {
658 const MCOperand MO = MI.getOperand(OpIdx);
659 if (MO.isExpr())
660 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_bl,
661 Fixups, STI);
662 return encodeThumbBLOffset(MO.getImm());
663}
664
665/// getThumbBLXTargetOpValue - Return encoding info for Thumb immediate
666/// BLX branch target.
667uint32_t ARMMCCodeEmitter::
668getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
669 SmallVectorImpl<MCFixup> &Fixups,
670 const MCSubtargetInfo &STI) const {
671 const MCOperand MO = MI.getOperand(OpIdx);
672 if (MO.isExpr())
673 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_blx,
674 Fixups, STI);
675 return encodeThumbBLOffset(MO.getImm());
676}
677
678/// getThumbBRTargetOpValue - Return encoding info for Thumb branch target.
679uint32_t ARMMCCodeEmitter::
680getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx,
681 SmallVectorImpl<MCFixup> &Fixups,
682 const MCSubtargetInfo &STI) const {
683 const MCOperand MO = MI.getOperand(OpIdx);
684 if (MO.isExpr())
685 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_br,
686 Fixups, STI);
687 return (MO.getImm() >> 1);
688}
689
690/// getThumbBCCTargetOpValue - Return encoding info for Thumb branch target.
691uint32_t ARMMCCodeEmitter::
692getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx,
693 SmallVectorImpl<MCFixup> &Fixups,
694 const MCSubtargetInfo &STI) const {
695 const MCOperand MO = MI.getOperand(OpIdx);
696 if (MO.isExpr())
697 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_bcc,
698 Fixups, STI);
699 return (MO.getImm() >> 1);
700}
701
702/// getThumbCBTargetOpValue - Return encoding info for Thumb branch target.
703uint32_t ARMMCCodeEmitter::
704getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx,
705 SmallVectorImpl<MCFixup> &Fixups,
706 const MCSubtargetInfo &STI) const {
707 const MCOperand MO = MI.getOperand(OpIdx);
708 if (MO.isExpr())
709 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_cb, Fixups, STI);
710 return (MO.getImm() >> 1);
711}
712
713/// Return true if this branch has a non-always predication
714static bool HasConditionalBranch(const MCInst &MI) {
715 int NumOp = MI.getNumOperands();
716 if (NumOp >= 2) {
717 for (int i = 0; i < NumOp-1; ++i) {
718 const MCOperand &MCOp1 = MI.getOperand(i);
719 const MCOperand &MCOp2 = MI.getOperand(i + 1);
720 if (MCOp1.isImm() && MCOp2.isReg() &&
721 (!MCOp2.getReg() || MCOp2.getReg() == ARM::CPSR)) {
722 if (ARMCC::CondCodes(MCOp1.getImm()) != ARMCC::AL)
723 return true;
724 }
725 }
726 }
727 return false;
728}
729
730/// getBranchTargetOpValue - Return encoding info for 24-bit immediate branch
731/// target.
732uint32_t ARMMCCodeEmitter::
733getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
734 SmallVectorImpl<MCFixup> &Fixups,
735 const MCSubtargetInfo &STI) const {
736 // FIXME: This really, really shouldn't use TargetMachine. We don't want
737 // coupling between MC and TM anywhere we can help it.
738 if (isThumb2(STI))
739 return
740 ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_condbranch, Fixups, STI);
741 return getARMBranchTargetOpValue(MI, OpIdx, Fixups, STI);
742}
743
744/// getBranchTargetOpValue - Return encoding info for 24-bit immediate branch
745/// target.
746uint32_t ARMMCCodeEmitter::
747getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
748 SmallVectorImpl<MCFixup> &Fixups,
749 const MCSubtargetInfo &STI) const {
750 const MCOperand MO = MI.getOperand(OpIdx);
751 if (MO.isExpr()) {
752 if (HasConditionalBranch(MI))
753 return ::getBranchTargetOpValue(MI, OpIdx,
754 ARM::fixup_arm_condbranch, Fixups, STI);
755 return ::getBranchTargetOpValue(MI, OpIdx,
756 ARM::fixup_arm_uncondbranch, Fixups, STI);
757 }
758
759 return MO.getImm() >> 2;
760}
761
762uint32_t ARMMCCodeEmitter::
763getARMBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
764 SmallVectorImpl<MCFixup> &Fixups,
765 const MCSubtargetInfo &STI) const {
766 const MCOperand MO = MI.getOperand(OpIdx);
767 if (MO.isExpr()) {
768 if (HasConditionalBranch(MI))
769 return ::getBranchTargetOpValue(MI, OpIdx,
770 ARM::fixup_arm_condbl, Fixups, STI);
771 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_uncondbl, Fixups, STI);
772 }
773
774 return MO.getImm() >> 2;
775}
776
777uint32_t ARMMCCodeEmitter::
778getARMBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
779 SmallVectorImpl<MCFixup> &Fixups,
780 const MCSubtargetInfo &STI) const {
781 const MCOperand MO = MI.getOperand(OpIdx);
782 if (MO.isExpr())
783 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_blx, Fixups, STI);
784
785 return MO.getImm() >> 1;
786}
787
788/// getUnconditionalBranchTargetOpValue - Return encoding info for 24-bit
789/// immediate branch target.
790uint32_t ARMMCCodeEmitter::getThumbBranchTargetOpValue(
791 const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups,
792 const MCSubtargetInfo &STI) const {
793 unsigned Val = 0;
794 const MCOperand MO = MI.getOperand(OpIdx);
795
796 if(MO.isExpr())
797 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_uncondbranch, Fixups, STI);
798 else
799 Val = MO.getImm() >> 1;
800
801 bool I = (Val & 0x800000);
802 bool J1 = (Val & 0x400000);
803 bool J2 = (Val & 0x200000);
804 if (I ^ J1)
805 Val &= ~0x400000;
806 else
807 Val |= 0x400000;
808
809 if (I ^ J2)
810 Val &= ~0x200000;
811 else
812 Val |= 0x200000;
813
814 return Val;
815}
816
817/// getAdrLabelOpValue - Return encoding info for 12-bit shifted-immediate
818/// ADR label target.
819uint32_t ARMMCCodeEmitter::
820getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
821 SmallVectorImpl<MCFixup> &Fixups,
822 const MCSubtargetInfo &STI) const {
823 const MCOperand MO = MI.getOperand(OpIdx);
824 if (MO.isExpr())
825 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_adr_pcrel_12,
826 Fixups, STI);
827 int64_t offset = MO.getImm();
828 uint32_t Val = 0x2000;
829
830 int SoImmVal;
831 if (offset == INT32_MIN) {
832 Val = 0x1000;
833 SoImmVal = 0;
834 } else if (offset < 0) {
835 Val = 0x1000;
836 offset *= -1;
837 SoImmVal = ARM_AM::getSOImmVal(offset);
838 if(SoImmVal == -1) {
839 Val = 0x2000;
840 offset *= -1;
841 SoImmVal = ARM_AM::getSOImmVal(offset);
842 }
843 } else {
844 SoImmVal = ARM_AM::getSOImmVal(offset);
845 if(SoImmVal == -1) {
846 Val = 0x1000;
847 offset *= -1;
848 SoImmVal = ARM_AM::getSOImmVal(offset);
849 }
850 }
851
852 assert(SoImmVal != -1 && "Not a valid so_imm value!");
853
854 Val |= SoImmVal;
855 return Val;
856}
857
858/// getT2AdrLabelOpValue - Return encoding info for 12-bit immediate ADR label
859/// target.
860uint32_t ARMMCCodeEmitter::
861getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
862 SmallVectorImpl<MCFixup> &Fixups,
863 const MCSubtargetInfo &STI) const {
864 const MCOperand MO = MI.getOperand(OpIdx);
865 if (MO.isExpr())
866 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_adr_pcrel_12,
867 Fixups, STI);
868 int32_t Val = MO.getImm();
869 if (Val == INT32_MIN)
870 Val = 0x1000;
871 else if (Val < 0) {
872 Val *= -1;
873 Val |= 0x1000;
874 }
875 return Val;
876}
877
878/// getITMaskOpValue - Return the architectural encoding of an IT
879/// predication mask, given the MCOperand format.
880uint32_t ARMMCCodeEmitter::
881getITMaskOpValue(const MCInst &MI, unsigned OpIdx,
882 SmallVectorImpl<MCFixup> &Fixups,
883 const MCSubtargetInfo &STI) const {
884 const MCOperand MaskMO = MI.getOperand(OpIdx);
885 assert(MaskMO.isImm() && "Unexpected operand type!");
886
887 unsigned Mask = MaskMO.getImm();
888
889 // IT masks are encoded as a sequence of replacement low-order bits
890 // for the condition code. So if the low bit of the starting
891 // condition code is 1, then we have to flip all the bits above the
892 // terminating bit (which is the lowest 1 bit).
893 assert(OpIdx > 0 && "IT mask appears first!");
894 const MCOperand CondMO = MI.getOperand(OpIdx-1);
895 assert(CondMO.isImm() && "Unexpected operand type!");
896 if (CondMO.getImm() & 1) {
897 unsigned LowBit = Mask & -Mask;
898 unsigned BitsAboveLowBit = 0xF & (-LowBit << 1);
899 Mask ^= BitsAboveLowBit;
900 }
901
902 return Mask;
903}
904
905/// getThumbAdrLabelOpValue - Return encoding info for 8-bit immediate ADR label
906/// target.
907uint32_t ARMMCCodeEmitter::
908getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
909 SmallVectorImpl<MCFixup> &Fixups,
910 const MCSubtargetInfo &STI) const {
911 const MCOperand MO = MI.getOperand(OpIdx);
912 if (MO.isExpr())
913 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_thumb_adr_pcrel_10,
914 Fixups, STI);
915 return MO.getImm();
916}
917
918/// getThumbAddrModeRegRegOpValue - Return encoding info for 'reg + reg'
919/// operand.
920uint32_t ARMMCCodeEmitter::
921getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx,
922 SmallVectorImpl<MCFixup> &,
923 const MCSubtargetInfo &STI) const {
924 // [Rn, Rm]
925 // {5-3} = Rm
926 // {2-0} = Rn
927 const MCOperand &MO1 = MI.getOperand(OpIdx);
928 const MCOperand &MO2 = MI.getOperand(OpIdx + 1);
929 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg());
930 unsigned Rm = CTX.getRegisterInfo()->getEncodingValue(MO2.getReg());
931 return (Rm << 3) | Rn;
932}
933
934/// getMVEShiftImmOpValue - Return encoding info for the 'sz:imm5'
935/// operand.
936uint32_t
937ARMMCCodeEmitter::getMVEShiftImmOpValue(const MCInst &MI, unsigned OpIdx,
938 SmallVectorImpl<MCFixup> &Fixups,
939 const MCSubtargetInfo &STI) const {
940 // {4-0} = szimm5
941 // The value we are trying to encode is an immediate between either the
942 // range of [1-7] or [1-15] depending on whether we are dealing with the
943 // u8/s8 or the u16/s16 variants respectively.
944 // This value is encoded as follows, if ShiftImm is the value within those
945 // ranges then the encoding szimm5 = ShiftImm + size, where size is either 8
946 // or 16.
947
948 unsigned Size, ShiftImm;
949 switch(MI.getOpcode()) {
950 case ARM::MVE_VSHLL_imms16bh:
951 case ARM::MVE_VSHLL_imms16th:
952 case ARM::MVE_VSHLL_immu16bh:
953 case ARM::MVE_VSHLL_immu16th:
954 Size = 16;
955 break;
956 case ARM::MVE_VSHLL_imms8bh:
957 case ARM::MVE_VSHLL_imms8th:
958 case ARM::MVE_VSHLL_immu8bh:
959 case ARM::MVE_VSHLL_immu8th:
960 Size = 8;
961 break;
962 default:
963 llvm_unreachable("Use of operand not supported by this instruction");
964 }
965 ShiftImm = MI.getOperand(OpIdx).getImm();
966 return Size + ShiftImm;
967}
968
969/// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12' operand.
970uint32_t ARMMCCodeEmitter::
971getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
972 SmallVectorImpl<MCFixup> &Fixups,
973 const MCSubtargetInfo &STI) const {
974 // {17-13} = reg
975 // {12} = (U)nsigned (add == '1', sub == '0')
976 // {11-0} = imm12
977 unsigned Reg = 0, Imm12 = 0;
978 bool isAdd = true;
979 // If The first operand isn't a register, we have a label reference.
980 const MCOperand &MO = MI.getOperand(OpIdx);
981 if (MO.isReg()) {
982 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
983 if (MO1.isImm()) {
984 isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm12, Fixups, STI);
985 } else if (MO1.isExpr()) {
986 assert(!isThumb(STI) && !isThumb2(STI) &&
987 "Thumb mode requires different encoding");
988 Reg = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
989 isAdd = false; // 'U' bit is set as part of the fixup.
990 MCFixupKind Kind = ARM::fixup_arm_ldst_abs_12;
991 addFixup(Fixups, 0, MO1.getExpr(), Kind);
992 }
993 } else if (MO.isExpr()) {
994 Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC.
995 isAdd = false; // 'U' bit is set as part of the fixup.
996 MCFixupKind Kind;
997 if (isThumb2(STI))
998 Kind = ARM::fixup_t2_ldst_pcrel_12;
999 else
1000 Kind = ARM::fixup_arm_ldst_pcrel_12;
1001 addFixup(Fixups, 0, MO.getExpr(), Kind);
1002
1003 ++MCNumCPRelocations;
1004 } else {
1005 Reg = ARM::PC;
1006 int32_t Offset = MO.getImm();
1007 if (Offset == INT32_MIN) {
1008 Offset = 0;
1009 isAdd = false;
1010 } else if (Offset < 0) {
1011 Offset *= -1;
1012 isAdd = false;
1013 }
1014 Imm12 = Offset;
1015 }
1016 uint32_t Binary = Imm12 & 0xfff;
1017 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
1018 if (isAdd)
1019 Binary |= (1 << 12);
1020 Binary |= (Reg << 13);
1021 return Binary;
1022}
1023
1024template<unsigned Bits, unsigned Shift>
1025uint32_t ARMMCCodeEmitter::
1026getT2ScaledImmOpValue(const MCInst &MI, unsigned OpIdx,
1027 SmallVectorImpl<MCFixup> &Fixups,
1028 const MCSubtargetInfo &STI) const {
1029 // FIXME: The immediate operand should have already been encoded like this
1030 // before ever getting here. The encoder method should just need to combine
1031 // the MI operands for the register and the offset into a single
1032 // representation for the complex operand in the .td file. This isn't just
1033 // style, unfortunately. As-is, we can't represent the distinct encoding
1034 // for #-0.
1035
1036 // {Bits} = (U)nsigned (add == '1', sub == '0')
1037 // {(Bits-1)-0} = immediate
1038 int32_t Imm = MI.getOperand(OpIdx).getImm();
1039 bool isAdd = Imm >= 0;
1040
1041 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
1042 if (Imm < 0)
1043 Imm = -(uint32_t)Imm;
1044
1045 Imm >>= Shift;
1046
1047 uint32_t Binary = Imm & ((1U << Bits) - 1);
1048 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
1049 if (isAdd)
1050 Binary |= (1U << Bits);
1051 return Binary;
1052}
1053
1054/// getMveAddrModeRQOpValue - Return encoding info for 'reg, vreg'
1055/// operand.
1056uint32_t ARMMCCodeEmitter::
1057getMveAddrModeRQOpValue(const MCInst &MI, unsigned OpIdx,
1058 SmallVectorImpl<MCFixup> &Fixups,
1059 const MCSubtargetInfo &STI) const {
1060 // {6-3} Rn
1061 // {2-0} Qm
1062 const MCOperand &M0 = MI.getOperand(OpIdx);
1063 const MCOperand &M1 = MI.getOperand(OpIdx + 1);
1064
1065 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(M0.getReg());
1066 unsigned Qm = CTX.getRegisterInfo()->getEncodingValue(M1.getReg());
1067
1068 assert(Qm < 8 && "Qm is supposed to be encodable in 3 bits");
1069
1070 return (Rn << 3) | Qm;
1071}
1072
1073/// getMveAddrModeRQOpValue - Return encoding info for 'reg, vreg'
1074/// operand.
1075template<int shift>
1076uint32_t ARMMCCodeEmitter::
1077getMveAddrModeQOpValue(const MCInst &MI, unsigned OpIdx,
1078 SmallVectorImpl<MCFixup> &Fixups,
1079 const MCSubtargetInfo &STI) const {
1080 // {10-8} Qm
1081 // {7-0} Imm
1082 const MCOperand &M0 = MI.getOperand(OpIdx);
1083 const MCOperand &M1 = MI.getOperand(OpIdx + 1);
1084
1085 unsigned Qm = CTX.getRegisterInfo()->getEncodingValue(M0.getReg());
1086 int32_t Imm = M1.getImm();
1087
1088 bool isAdd = Imm >= 0;
1089
1090 Imm >>= shift;
1091
1092 if (!isAdd)
1093 Imm = -(uint32_t)Imm;
1094
1095 Imm &= 0x7f;
1096
1097 if (isAdd)
1098 Imm |= 0x80;
1099
1100 assert(Qm < 8 && "Qm is supposed to be encodable in 3 bits");
1101
1102 return (Qm << 8) | Imm;
1103}
1104
1105/// getT2AddrModeImm8s4OpValue - Return encoding info for
1106/// 'reg +/- imm8<<2' operand.
1107uint32_t ARMMCCodeEmitter::
1108getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx,
1109 SmallVectorImpl<MCFixup> &Fixups,
1110 const MCSubtargetInfo &STI) const {
1111 // {12-9} = reg
1112 // {8} = (U)nsigned (add == '1', sub == '0')
1113 // {7-0} = imm8
1114 unsigned Reg, Imm8;
1115 bool isAdd = true;
1116 // If The first operand isn't a register, we have a label reference.
1117 const MCOperand &MO = MI.getOperand(OpIdx);
1118 if (!MO.isReg()) {
1119 Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC.
1120 Imm8 = 0;
1121 isAdd = false ; // 'U' bit is set as part of the fixup.
1122
1123 assert(MO.isExpr() && "Unexpected machine operand type!");
1124 const MCExpr *Expr = MO.getExpr();
1125 MCFixupKind Kind = ARM::fixup_t2_pcrel_10;
1126 addFixup(Fixups, 0, Expr, Kind);
1127
1128 ++MCNumCPRelocations;
1129 } else
1130 isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups, STI);
1131
1132 // FIXME: The immediate operand should have already been encoded like this
1133 // before ever getting here. The encoder method should just need to combine
1134 // the MI operands for the register and the offset into a single
1135 // representation for the complex operand in the .td file. This isn't just
1136 // style, unfortunately. As-is, we can't represent the distinct encoding
1137 // for #-0.
1138 assert(((Imm8 & 0x3) == 0) && "Not a valid immediate!");
1139 uint32_t Binary = (Imm8 >> 2) & 0xff;
1140 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
1141 if (isAdd)
1142 Binary |= (1 << 8);
1143 Binary |= (Reg << 9);
1144 return Binary;
1145}
1146
1147/// getT2AddrModeImm7s4OpValue - Return encoding info for
1148/// 'reg +/- imm7<<2' operand.
1149uint32_t
1150ARMMCCodeEmitter::getT2AddrModeImm7s4OpValue(const MCInst &MI, unsigned OpIdx,
1151 SmallVectorImpl<MCFixup> &Fixups,
1152 const MCSubtargetInfo &STI) const {
1153 // {11-8} = reg
1154 // {7} = (A)dd (add == '1', sub == '0')
1155 // {6-0} = imm7
1156 unsigned Reg, Imm7;
1157 // If The first operand isn't a register, we have a label reference.
1158 bool isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm7, Fixups, STI);
1159
1160 // FIXME: The immediate operand should have already been encoded like this
1161 // before ever getting here. The encoder method should just need to combine
1162 // the MI operands for the register and the offset into a single
1163 // representation for the complex operand in the .td file. This isn't just
1164 // style, unfortunately. As-is, we can't represent the distinct encoding
1165 // for #-0.
1166 uint32_t Binary = (Imm7 >> 2) & 0xff;
1167 // Immediate is always encoded as positive. The 'A' bit controls add vs sub.
1168 if (isAdd)
1169 Binary |= (1 << 7);
1170 Binary |= (Reg << 8);
1171 return Binary;
1172}
1173
1174/// getT2AddrModeImm0_1020s4OpValue - Return encoding info for
1175/// 'reg + imm8<<2' operand.
1176uint32_t ARMMCCodeEmitter::
1177getT2AddrModeImm0_1020s4OpValue(const MCInst &MI, unsigned OpIdx,
1178 SmallVectorImpl<MCFixup> &Fixups,
1179 const MCSubtargetInfo &STI) const {
1180 // {11-8} = reg
1181 // {7-0} = imm8
1182 const MCOperand &MO = MI.getOperand(OpIdx);
1183 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1184 unsigned Reg = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1185 unsigned Imm8 = MO1.getImm();
1186 return (Reg << 8) | Imm8;
1187}
1188
1189uint32_t ARMMCCodeEmitter::getHiLoImmOpValue(const MCInst &MI, unsigned OpIdx,
1190 SmallVectorImpl<MCFixup> &Fixups,
1191 const MCSubtargetInfo &STI) const {
1192 // {20-16} = imm{15-12}
1193 // {11-0} = imm{11-0}
1194 const MCOperand &MO = MI.getOperand(OpIdx);
1195 if (MO.isImm())
1196 // Hi / lo bits already extracted during earlier passes.
1197 return static_cast<unsigned>(MO.getImm());
1198
1199 // Handle :upper16:, :lower16:, :upper8_15:, :upper0_7:, :lower8_15:
1200 // :lower0_7: assembly prefixes.
1201 const MCExpr *E = MO.getExpr();
1202 MCFixupKind Kind;
1203 if (E->getKind() == MCExpr::Specifier) {
1204 auto *ARM16Expr = cast<MCSpecifierExpr>(E);
1205 E = ARM16Expr->getSubExpr();
1206
1207 if (const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(E)) {
1208 const int64_t Value = MCE->getValue();
1209 if (Value > UINT32_MAX)
1210 report_fatal_error("constant value truncated (limited to 32-bit)");
1211
1212 switch (ARM16Expr->getSpecifier()) {
1213 case ARM::S_HI16:
1214 return (int32_t(Value) & 0xffff0000) >> 16;
1215 case ARM::S_LO16:
1216 return (int32_t(Value) & 0x0000ffff);
1217
1218 case ARM::S_HI_8_15:
1219 return (int32_t(Value) & 0xff000000) >> 24;
1220 case ARM::S_HI_0_7:
1221 return (int32_t(Value) & 0x00ff0000) >> 16;
1222 case ARM::S_LO_8_15:
1223 return (int32_t(Value) & 0x0000ff00) >> 8;
1224 case ARM::S_LO_0_7:
1225 return (int32_t(Value) & 0x000000ff);
1226
1227 default: llvm_unreachable("Unsupported ARMFixup");
1228 }
1229 }
1230
1231 switch (ARM16Expr->getSpecifier()) {
1232 default: llvm_unreachable("Unsupported ARMFixup");
1233 case ARM::S_HI16:
1234 Kind = MCFixupKind(isThumb(STI) ? ARM::fixup_t2_movt_hi16
1235 : ARM::fixup_arm_movt_hi16);
1236 break;
1237 case ARM::S_LO16:
1238 Kind = MCFixupKind(isThumb(STI) ? ARM::fixup_t2_movw_lo16
1239 : ARM::fixup_arm_movw_lo16);
1240 break;
1241 case ARM::S_HI_8_15:
1242 if (!isThumb(STI))
1243 llvm_unreachable(":upper_8_15: not supported in Arm state");
1244 Kind = ARM::fixup_arm_thumb_upper_8_15;
1245 break;
1246 case ARM::S_HI_0_7:
1247 if (!isThumb(STI))
1248 llvm_unreachable(":upper_0_7: not supported in Arm state");
1249 Kind = ARM::fixup_arm_thumb_upper_0_7;
1250 break;
1251 case ARM::S_LO_8_15:
1252 if (!isThumb(STI))
1253 llvm_unreachable(":lower_8_15: not supported in Arm state");
1254 Kind = ARM::fixup_arm_thumb_lower_8_15;
1255 break;
1256 case ARM::S_LO_0_7:
1257 if (!isThumb(STI))
1258 llvm_unreachable(":lower_0_7: not supported in Arm state");
1259 Kind = ARM::fixup_arm_thumb_lower_0_7;
1260 break;
1261 }
1262
1263 addFixup(Fixups, 0, E, Kind);
1264 return 0;
1265 }
1266 // If the expression doesn't have :upper16:, :lower16: on it, it's just a
1267 // plain immediate expression, previously those evaluated to the lower 16 bits
1268 // of the expression regardless of whether we have a movt or a movw, but that
1269 // led to misleadingly results. This is disallowed in the AsmParser in
1270 // validateInstruction() so this should never happen. The same holds for
1271 // thumb1 :upper8_15:, :upper0_7:, lower8_15: or :lower0_7: with movs or adds.
1272 llvm_unreachable("expression without :upper16:, :lower16:, :upper8_15:,"
1273 ":upper0_7:, lower8_15: or :lower0_7:");
1274}
1275
1276uint32_t ARMMCCodeEmitter::
1277getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,
1278 SmallVectorImpl<MCFixup> &Fixups,
1279 const MCSubtargetInfo &STI) const {
1280 const MCOperand &MO = MI.getOperand(OpIdx);
1281 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
1282 const MCOperand &MO2 = MI.getOperand(OpIdx+2);
1283 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1284 unsigned Rm = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg());
1285 unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm());
1286 bool isAdd = ARM_AM::getAM2Op(MO2.getImm()) == ARM_AM::add;
1287 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(MO2.getImm());
1288 unsigned SBits = getShiftOp(ShOp);
1289
1290 // While "lsr #32" and "asr #32" exist, they are encoded with a 0 in the shift
1291 // amount. However, it would be an easy mistake to make so check here.
1292 assert((ShImm & ~0x1f) == 0 && "Out of range shift amount");
1293
1294 // {16-13} = Rn
1295 // {12} = isAdd
1296 // {11-0} = shifter
1297 // {3-0} = Rm
1298 // {4} = 0
1299 // {6-5} = type
1300 // {11-7} = imm
1301 uint32_t Binary = Rm;
1302 Binary |= Rn << 13;
1303 Binary |= SBits << 5;
1304 Binary |= ShImm << 7;
1305 if (isAdd)
1306 Binary |= 1 << 12;
1307 return Binary;
1308}
1309
1310uint32_t ARMMCCodeEmitter::
1311getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx,
1312 SmallVectorImpl<MCFixup> &Fixups,
1313 const MCSubtargetInfo &STI) const {
1314 // {13} 1 == imm12, 0 == Rm
1315 // {12} isAdd
1316 // {11-0} imm12/Rm
1317 const MCOperand &MO = MI.getOperand(OpIdx);
1318 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
1319 unsigned Imm = MO1.getImm();
1320 bool isAdd = ARM_AM::getAM2Op(Imm) == ARM_AM::add;
1321 bool isReg = MO.getReg().isValid();
1322 uint32_t Binary = ARM_AM::getAM2Offset(Imm);
1323 // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm12
1324 if (isReg) {
1325 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(Imm);
1326 Binary <<= 7; // Shift amount is bits [11:7]
1327 Binary |= getShiftOp(ShOp) << 5; // Shift type is bits [6:5]
1328 Binary |= CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); // Rm is bits [3:0]
1329 }
1330 return Binary | (isAdd << 12) | (isReg << 13);
1331}
1332
1333uint32_t ARMMCCodeEmitter::
1334getPostIdxRegOpValue(const MCInst &MI, unsigned OpIdx,
1335 SmallVectorImpl<MCFixup> &Fixups,
1336 const MCSubtargetInfo &STI) const {
1337 // {4} isAdd
1338 // {3-0} Rm
1339 const MCOperand &MO = MI.getOperand(OpIdx);
1340 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
1341 bool isAdd = MO1.getImm() != 0;
1342 return CTX.getRegisterInfo()->getEncodingValue(MO.getReg()) | (isAdd << 4);
1343}
1344
1345uint32_t ARMMCCodeEmitter::
1346getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx,
1347 SmallVectorImpl<MCFixup> &Fixups,
1348 const MCSubtargetInfo &STI) const {
1349 // {9} 1 == imm8, 0 == Rm
1350 // {8} isAdd
1351 // {7-4} imm7_4/zero
1352 // {3-0} imm3_0/Rm
1353 const MCOperand &MO = MI.getOperand(OpIdx);
1354 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
1355 unsigned Imm = MO1.getImm();
1356 bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add;
1357 bool isImm = !MO.getReg().isValid();
1358 uint32_t Imm8 = ARM_AM::getAM3Offset(Imm);
1359 // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8
1360 if (!isImm)
1361 Imm8 = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1362 return Imm8 | (isAdd << 8) | (isImm << 9);
1363}
1364
1365uint32_t ARMMCCodeEmitter::
1366getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx,
1367 SmallVectorImpl<MCFixup> &Fixups,
1368 const MCSubtargetInfo &STI) const {
1369 // {13} 1 == imm8, 0 == Rm
1370 // {12-9} Rn
1371 // {8} isAdd
1372 // {7-4} imm7_4/zero
1373 // {3-0} imm3_0/Rm
1374 const MCOperand &MO = MI.getOperand(OpIdx);
1375 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
1376 const MCOperand &MO2 = MI.getOperand(OpIdx+2);
1377
1378 // If The first operand isn't a register, we have a label reference.
1379 if (!MO.isReg()) {
1380 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC.
1381
1382 assert(MO.isExpr() && "Unexpected machine operand type!");
1383 const MCExpr *Expr = MO.getExpr();
1384 MCFixupKind Kind = ARM::fixup_arm_pcrel_10_unscaled;
1385 addFixup(Fixups, 0, Expr, Kind);
1386
1387 ++MCNumCPRelocations;
1388 return (Rn << 9) | (1 << 13);
1389 }
1390 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1391 unsigned Imm = MO2.getImm();
1392 bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add;
1393 bool isImm = !MO1.getReg().isValid();
1394 uint32_t Imm8 = ARM_AM::getAM3Offset(Imm);
1395 // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8
1396 if (!isImm)
1397 Imm8 = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg());
1398 return (Rn << 9) | Imm8 | (isAdd << 8) | (isImm << 13);
1399}
1400
1401/// getAddrModeThumbSPOpValue - Encode the t_addrmode_sp operands.
1402uint32_t ARMMCCodeEmitter::
1403getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx,
1404 SmallVectorImpl<MCFixup> &Fixups,
1405 const MCSubtargetInfo &STI) const {
1406 // [SP, #imm]
1407 // {7-0} = imm8
1408 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1409 assert(MI.getOperand(OpIdx).getReg() == ARM::SP &&
1410 "Unexpected base register!");
1411
1412 // The immediate is already shifted for the implicit zeroes, so no change
1413 // here.
1414 return MO1.getImm() & 0xff;
1415}
1416
1417/// getAddrModeISOpValue - Encode the t_addrmode_is# operands.
1418uint32_t ARMMCCodeEmitter::
1419getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx,
1420 SmallVectorImpl<MCFixup> &Fixups,
1421 const MCSubtargetInfo &STI) const {
1422 // [Rn, #imm]
1423 // {7-3} = imm5
1424 // {2-0} = Rn
1425 const MCOperand &MO = MI.getOperand(OpIdx);
1426 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1427 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1428 unsigned Imm5 = MO1.getImm();
1429 return ((Imm5 & 0x1f) << 3) | Rn;
1430}
1431
1432/// getAddrModePCOpValue - Return encoding for t_addrmode_pc operands.
1433uint32_t ARMMCCodeEmitter::
1434getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx,
1435 SmallVectorImpl<MCFixup> &Fixups,
1436 const MCSubtargetInfo &STI) const {
1437 const MCOperand MO = MI.getOperand(OpIdx);
1438 if (MO.isExpr())
1439 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_cp, Fixups, STI);
1440 return (MO.getImm() >> 2);
1441}
1442
1443/// getAddrMode5OpValue - Return encoding info for 'reg +/- (imm8 << 2)' operand.
1444uint32_t ARMMCCodeEmitter::
1445getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
1446 SmallVectorImpl<MCFixup> &Fixups,
1447 const MCSubtargetInfo &STI) const {
1448 // {12-9} = reg
1449 // {8} = (U)nsigned (add == '1', sub == '0')
1450 // {7-0} = imm8
1451 unsigned Reg, Imm8;
1452 bool isAdd;
1453 // If The first operand isn't a register, we have a label reference.
1454 const MCOperand &MO = MI.getOperand(OpIdx);
1455 if (!MO.isReg()) {
1456 Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC.
1457 Imm8 = 0;
1458 isAdd = false; // 'U' bit is handled as part of the fixup.
1459
1460 assert(MO.isExpr() && "Unexpected machine operand type!");
1461 const MCExpr *Expr = MO.getExpr();
1462 MCFixupKind Kind;
1463 if (isThumb2(STI))
1464 Kind = ARM::fixup_t2_pcrel_10;
1465 else
1466 Kind = ARM::fixup_arm_pcrel_10;
1467 addFixup(Fixups, 0, Expr, Kind);
1468
1469 ++MCNumCPRelocations;
1470 } else {
1471 EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups, STI);
1472 isAdd = ARM_AM::getAM5Op(Imm8) == ARM_AM::add;
1473 }
1474
1475 uint32_t Binary = ARM_AM::getAM5Offset(Imm8);
1476 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
1477 if (isAdd)
1478 Binary |= (1 << 8);
1479 Binary |= (Reg << 9);
1480 return Binary;
1481}
1482
1483/// getAddrMode5FP16OpValue - Return encoding info for 'reg +/- (imm8 << 1)' operand.
1484uint32_t ARMMCCodeEmitter::
1485getAddrMode5FP16OpValue(const MCInst &MI, unsigned OpIdx,
1486 SmallVectorImpl<MCFixup> &Fixups,
1487 const MCSubtargetInfo &STI) const {
1488 // {12-9} = reg
1489 // {8} = (U)nsigned (add == '1', sub == '0')
1490 // {7-0} = imm8
1491 unsigned Reg, Imm8;
1492 bool isAdd;
1493 // If The first operand isn't a register, we have a label reference.
1494 const MCOperand &MO = MI.getOperand(OpIdx);
1495 if (!MO.isReg()) {
1496 Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC.
1497 Imm8 = 0;
1498 isAdd = false; // 'U' bit is handled as part of the fixup.
1499
1500 assert(MO.isExpr() && "Unexpected machine operand type!");
1501 const MCExpr *Expr = MO.getExpr();
1502 MCFixupKind Kind;
1503 if (isThumb2(STI))
1504 Kind = ARM::fixup_t2_pcrel_9;
1505 else
1506 Kind = ARM::fixup_arm_pcrel_9;
1507 addFixup(Fixups, 0, Expr, Kind);
1508
1509 ++MCNumCPRelocations;
1510 } else {
1511 EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups, STI);
1512 isAdd = ARM_AM::getAM5Op(Imm8) == ARM_AM::add;
1513 }
1514
1515 uint32_t Binary = ARM_AM::getAM5Offset(Imm8);
1516 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
1517 if (isAdd)
1518 Binary |= (1 << 8);
1519 Binary |= (Reg << 9);
1520 return Binary;
1521}
1522
1523unsigned ARMMCCodeEmitter::getModImmOpValue(const MCInst &MI, unsigned Op,
1524 SmallVectorImpl<MCFixup> &Fixups,
1525 const MCSubtargetInfo &ST) const {
1526 const MCOperand &MO = MI.getOperand(Op);
1527
1528 // Support for fixups (MCFixup)
1529 if (MO.isExpr()) {
1530 const MCExpr *Expr = MO.getExpr();
1531 // Fixups resolve to plain values that need to be encoded.
1532 MCFixupKind Kind = ARM::fixup_arm_mod_imm;
1533 addFixup(Fixups, 0, Expr, Kind);
1534 return 0;
1535 }
1536
1537 // Immediate is already in its encoded format
1538 return MO.getImm();
1539}
1540
1541unsigned ARMMCCodeEmitter::getT2SOImmOpValue(const MCInst &MI, unsigned Op,
1542 SmallVectorImpl<MCFixup> &Fixups,
1543 const MCSubtargetInfo &STI) const {
1544 const MCOperand &MO = MI.getOperand(Op);
1545
1546 // Support for fixups (MCFixup)
1547 if (MO.isExpr()) {
1548 const MCExpr *Expr = MO.getExpr();
1549 // Fixups resolve to plain values that need to be encoded.
1550 MCFixupKind Kind = ARM::fixup_t2_so_imm;
1551 addFixup(Fixups, 0, Expr, Kind);
1552 return 0;
1553 }
1554 unsigned SoImm = MO.getImm();
1555 unsigned Encoded = ARM_AM::getT2SOImmVal(SoImm);
1556 assert(Encoded != ~0U && "Not a Thumb2 so_imm value?");
1557 return Encoded;
1558}
1559
1560unsigned ARMMCCodeEmitter::
1561getSORegRegOpValue(const MCInst &MI, unsigned OpIdx,
1562 SmallVectorImpl<MCFixup> &Fixups,
1563 const MCSubtargetInfo &STI) const {
1564 // Sub-operands are [reg, reg, imm]. The first register is Rm, the reg to be
1565 // shifted. The second is Rs, the amount to shift by, and the third specifies
1566 // the type of the shift.
1567 //
1568 // {3-0} = Rm.
1569 // {4} = 1
1570 // {6-5} = type
1571 // {11-8} = Rs
1572 // {7} = 0
1573
1574 const MCOperand &MO = MI.getOperand(OpIdx);
1575 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1576 const MCOperand &MO2 = MI.getOperand(OpIdx + 2);
1577 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
1578
1579 // Encode Rm.
1580 unsigned Binary = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1581
1582 // Encode the shift opcode.
1583 unsigned SBits = 0;
1584 MCRegister Rs = MO1.getReg();
1585 if (Rs) {
1586 // Set shift operand (bit[7:4]).
1587 // LSL - 0001
1588 // LSR - 0011
1589 // ASR - 0101
1590 // ROR - 0111
1591 switch (SOpc) {
1592 default: llvm_unreachable("Unknown shift opc!");
1593 case ARM_AM::lsl: SBits = 0x1; break;
1594 case ARM_AM::lsr: SBits = 0x3; break;
1595 case ARM_AM::asr: SBits = 0x5; break;
1596 case ARM_AM::ror: SBits = 0x7; break;
1597 }
1598 }
1599
1600 Binary |= SBits << 4;
1601
1602 // Encode the shift operation Rs.
1603 // Encode Rs bit[11:8].
1604 assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
1605 return Binary | (CTX.getRegisterInfo()->getEncodingValue(Rs) << ARMII::RegRsShift);
1606}
1607
1608unsigned ARMMCCodeEmitter::
1609getSORegImmOpValue(const MCInst &MI, unsigned OpIdx,
1610 SmallVectorImpl<MCFixup> &Fixups,
1611 const MCSubtargetInfo &STI) const {
1612 // Sub-operands are [reg, imm]. The first register is Rm, the reg to be
1613 // shifted. The second is the amount to shift by.
1614 //
1615 // {3-0} = Rm.
1616 // {4} = 0
1617 // {6-5} = type
1618 // {11-7} = imm
1619
1620 const MCOperand &MO = MI.getOperand(OpIdx);
1621 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1622 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO1.getImm());
1623
1624 // Encode Rm.
1625 unsigned Binary = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1626
1627 // Encode the shift opcode.
1628 unsigned SBits = 0;
1629
1630 // Set shift operand (bit[6:4]).
1631 // LSL - 000
1632 // LSR - 010
1633 // ASR - 100
1634 // ROR - 110
1635 // RRX - 110 and bit[11:8] clear.
1636 switch (SOpc) {
1637 default: llvm_unreachable("Unknown shift opc!");
1638 case ARM_AM::lsl: SBits = 0x0; break;
1639 case ARM_AM::lsr: SBits = 0x2; break;
1640 case ARM_AM::asr: SBits = 0x4; break;
1641 case ARM_AM::ror: SBits = 0x6; break;
1642 case ARM_AM::rrx:
1643 Binary |= 0x60;
1644 return Binary;
1645 }
1646
1647 // Encode shift_imm bit[11:7].
1648 Binary |= SBits << 4;
1649 unsigned Offset = ARM_AM::getSORegOffset(MO1.getImm());
1650 assert(Offset < 32 && "Offset must be in range 0-31!");
1651 return Binary | (Offset << 7);
1652}
1653
1654
1655unsigned ARMMCCodeEmitter::
1656getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum,
1657 SmallVectorImpl<MCFixup> &Fixups,
1658 const MCSubtargetInfo &STI) const {
1659 const MCOperand &MO1 = MI.getOperand(OpNum);
1660 const MCOperand &MO2 = MI.getOperand(OpNum+1);
1661 const MCOperand &MO3 = MI.getOperand(OpNum+2);
1662
1663 // Encoded as [Rn, Rm, imm].
1664 // FIXME: Needs fixup support.
1665 unsigned Value = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg());
1666 Value <<= 4;
1667 Value |= CTX.getRegisterInfo()->getEncodingValue(MO2.getReg());
1668 Value <<= 2;
1669 Value |= MO3.getImm();
1670
1671 return Value;
1672}
1673
1674template<unsigned Bits, unsigned Shift>
1675unsigned ARMMCCodeEmitter::
1676getT2AddrModeImmOpValue(const MCInst &MI, unsigned OpNum,
1677 SmallVectorImpl<MCFixup> &Fixups,
1678 const MCSubtargetInfo &STI) const {
1679 const MCOperand &MO1 = MI.getOperand(OpNum);
1680 const MCOperand &MO2 = MI.getOperand(OpNum+1);
1681
1682 // FIXME: Needs fixup support.
1683 unsigned Value = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg());
1684
1685 // If the immediate is B bits long, we need B+1 bits in order
1686 // to represent the (inverse of the) sign bit.
1687 Value <<= (Bits + 1);
1688 int32_t tmp = (int32_t)MO2.getImm();
1689 if (tmp == INT32_MIN) { // represents subtracting zero rather than adding it
1690 tmp = 0;
1691 } else if (tmp < 0) {
1692 tmp = abs(tmp);
1693 } else {
1694 Value |= (1U << Bits); // Set the ADD bit
1695 }
1696 Value |= (tmp >> Shift) & ((1U << Bits) - 1);
1697 return Value;
1698}
1699
1700unsigned ARMMCCodeEmitter::
1701getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum,
1702 SmallVectorImpl<MCFixup> &Fixups,
1703 const MCSubtargetInfo &STI) const {
1704 const MCOperand &MO1 = MI.getOperand(OpNum);
1705
1706 // FIXME: Needs fixup support.
1707 unsigned Value = 0;
1708 auto tmp = static_cast<uint32_t>(MO1.getImm());
1709 if (static_cast<int32_t>(tmp) < 0)
1710 tmp = -tmp;
1711 else
1712 Value |= 256; // Set the ADD bit
1713 Value |= tmp & 255;
1714 return Value;
1715}
1716
1717unsigned ARMMCCodeEmitter::
1718getT2SORegOpValue(const MCInst &MI, unsigned OpIdx,
1719 SmallVectorImpl<MCFixup> &Fixups,
1720 const MCSubtargetInfo &STI) const {
1721 // Sub-operands are [reg, imm]. The first register is Rm, the reg to be
1722 // shifted. The second is the amount to shift by.
1723 //
1724 // {3-0} = Rm.
1725 // {4} = 0
1726 // {6-5} = type
1727 // {11-7} = imm
1728
1729 const MCOperand &MO = MI.getOperand(OpIdx);
1730 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1731 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO1.getImm());
1732
1733 // Encode Rm.
1734 unsigned Binary = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1735
1736 // Encode the shift opcode.
1737 unsigned SBits = 0;
1738 // Set shift operand (bit[6:4]).
1739 // LSL - 000
1740 // LSR - 010
1741 // ASR - 100
1742 // ROR - 110
1743 switch (SOpc) {
1744 default: llvm_unreachable("Unknown shift opc!");
1745 case ARM_AM::lsl: SBits = 0x0; break;
1746 case ARM_AM::lsr: SBits = 0x2; break;
1747 case ARM_AM::asr: SBits = 0x4; break;
1748 case ARM_AM::rrx: [[fallthrough]];
1749 case ARM_AM::ror: SBits = 0x6; break;
1750 }
1751
1752 Binary |= SBits << 4;
1753 if (SOpc == ARM_AM::rrx)
1754 return Binary;
1755
1756 // Encode shift_imm bit[11:7].
1757 return Binary | ARM_AM::getSORegOffset(MO1.getImm()) << 7;
1758}
1759
1760unsigned ARMMCCodeEmitter::
1761getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op,
1762 SmallVectorImpl<MCFixup> &Fixups,
1763 const MCSubtargetInfo &STI) const {
1764 // 10 bits. lower 5 bits are the lsb of the mask, high five bits are the
1765 // msb of the mask.
1766 const MCOperand &MO = MI.getOperand(Op);
1767 uint32_t v = ~MO.getImm();
1768 uint32_t lsb = llvm::countr_zero(v);
1769 uint32_t msb = llvm::Log2_32(v);
1770 assert(v != 0 && lsb < 32 && msb < 32 && "Illegal bitfield mask!");
1771 return lsb | (msb << 5);
1772}
1773
1774unsigned ARMMCCodeEmitter::
1775getRegisterListOpValue(const MCInst &MI, unsigned Op,
1776 SmallVectorImpl<MCFixup> &Fixups,
1777 const MCSubtargetInfo &STI) const {
1778 // VLDM/VSTM/VSCCLRM:
1779 // {12-8} = Vd
1780 // {7-0} = Number of registers
1781 //
1782 // LDM/STM:
1783 // {15-0} = Bitfield of GPRs.
1784 MCRegister Reg = MI.getOperand(Op).getReg();
1785 bool SPRRegs = ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg);
1786 bool DPRRegs = ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg);
1787
1788 unsigned Binary = 0;
1789
1790 if (SPRRegs || DPRRegs || Reg == ARM::VPR) {
1791 // VLDM/VSTM/VSCCLRM
1792 unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg);
1793 unsigned NumRegs = (MI.getNumOperands() - Op) & 0xff;
1794 Binary |= (RegNo & 0x1f) << 8;
1795
1796 if (MI.getOpcode() == ARM::VSCCLRMD)
1797 // Ignore VPR
1798 --NumRegs;
1799 else if (MI.getOpcode() == ARM::VSCCLRMS) {
1800 // The register list can contain both S registers and D registers, with D
1801 // registers counting as two registers. VPR doesn't count towards the
1802 // number of registers.
1803 NumRegs = 0;
1804 for (unsigned I = Op, E = MI.getNumOperands(); I < E; ++I) {
1805 Reg = MI.getOperand(I).getReg();
1806 if (ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg))
1807 NumRegs += 1;
1808 else if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg))
1809 NumRegs += 2;
1810 }
1811 }
1812 if (SPRRegs)
1813 Binary |= NumRegs;
1814 else
1815 Binary |= NumRegs * 2;
1816 } else {
1817 const MCRegisterInfo &MRI = *CTX.getRegisterInfo();
1818 assert(is_sorted(drop_begin(MI, Op),
1819 [&](const MCOperand &LHS, const MCOperand &RHS) {
1820 return MRI.getEncodingValue(LHS.getReg()) <
1821 MRI.getEncodingValue(RHS.getReg());
1822 }));
1823 for (unsigned I = Op, E = MI.getNumOperands(); I < E; ++I) {
1824 unsigned RegNo = MRI.getEncodingValue(MI.getOperand(I).getReg());
1825 Binary |= 1 << RegNo;
1826 }
1827 }
1828
1829 return Binary;
1830}
1831
1832/// getAddrMode6AddressOpValue - Encode an addrmode6 register number along
1833/// with the alignment operand.
1834unsigned ARMMCCodeEmitter::
1835getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op,
1836 SmallVectorImpl<MCFixup> &Fixups,
1837 const MCSubtargetInfo &STI) const {
1838 const MCOperand &Reg = MI.getOperand(Op);
1839 const MCOperand &Imm = MI.getOperand(Op + 1);
1840
1841 unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg.getReg());
1842 unsigned Align = 0;
1843
1844 switch (Imm.getImm()) {
1845 default: break;
1846 case 2:
1847 case 4:
1848 case 8: Align = 0x01; break;
1849 case 16: Align = 0x02; break;
1850 case 32: Align = 0x03; break;
1851 }
1852
1853 return RegNo | (Align << 4);
1854}
1855
1856/// getAddrMode6OneLane32AddressOpValue - Encode an addrmode6 register number
1857/// along with the alignment operand for use in VST1 and VLD1 with size 32.
1858unsigned ARMMCCodeEmitter::
1859getAddrMode6OneLane32AddressOpValue(const MCInst &MI, unsigned Op,
1860 SmallVectorImpl<MCFixup> &Fixups,
1861 const MCSubtargetInfo &STI) const {
1862 const MCOperand &Reg = MI.getOperand(Op);
1863 const MCOperand &Imm = MI.getOperand(Op + 1);
1864
1865 unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg.getReg());
1866 unsigned Align = 0;
1867
1868 switch (Imm.getImm()) {
1869 default: break;
1870 case 8:
1871 case 16:
1872 case 32: // Default '0' value for invalid alignments of 8, 16, 32 bytes.
1873 case 2: Align = 0x00; break;
1874 case 4: Align = 0x03; break;
1875 }
1876
1877 return RegNo | (Align << 4);
1878}
1879
1880
1881/// getAddrMode6DupAddressOpValue - Encode an addrmode6 register number and
1882/// alignment operand for use in VLD-dup instructions. This is the same as
1883/// getAddrMode6AddressOpValue except for the alignment encoding, which is
1884/// different for VLD4-dup.
1885unsigned ARMMCCodeEmitter::
1886getAddrMode6DupAddressOpValue(const MCInst &MI, unsigned Op,
1887 SmallVectorImpl<MCFixup> &Fixups,
1888 const MCSubtargetInfo &STI) const {
1889 const MCOperand &Reg = MI.getOperand(Op);
1890 const MCOperand &Imm = MI.getOperand(Op + 1);
1891
1892 unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg.getReg());
1893 unsigned Align = 0;
1894
1895 switch (Imm.getImm()) {
1896 default: break;
1897 case 2:
1898 case 4:
1899 case 8: Align = 0x01; break;
1900 case 16: Align = 0x03; break;
1901 }
1902
1903 return RegNo | (Align << 4);
1904}
1905
1906unsigned ARMMCCodeEmitter::
1907getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op,
1908 SmallVectorImpl<MCFixup> &Fixups,
1909 const MCSubtargetInfo &STI) const {
1910 const MCOperand &MO = MI.getOperand(Op);
1911 if (!MO.getReg())
1912 return 0x0D;
1913 return CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1914}
1915
1916unsigned ARMMCCodeEmitter::
1917getShiftRight8Imm(const MCInst &MI, unsigned Op,
1918 SmallVectorImpl<MCFixup> &Fixups,
1919 const MCSubtargetInfo &STI) const {
1920 return 8 - MI.getOperand(Op).getImm();
1921}
1922
1923unsigned ARMMCCodeEmitter::
1924getShiftRight16Imm(const MCInst &MI, unsigned Op,
1925 SmallVectorImpl<MCFixup> &Fixups,
1926 const MCSubtargetInfo &STI) const {
1927 return 16 - MI.getOperand(Op).getImm();
1928}
1929
1930unsigned ARMMCCodeEmitter::
1931getShiftRight32Imm(const MCInst &MI, unsigned Op,
1932 SmallVectorImpl<MCFixup> &Fixups,
1933 const MCSubtargetInfo &STI) const {
1934 return 32 - MI.getOperand(Op).getImm();
1935}
1936
1937unsigned ARMMCCodeEmitter::
1938getShiftRight64Imm(const MCInst &MI, unsigned Op,
1939 SmallVectorImpl<MCFixup> &Fixups,
1940 const MCSubtargetInfo &STI) const {
1941 return 64 - MI.getOperand(Op).getImm();
1942}
1943
1944void ARMMCCodeEmitter::encodeInstruction(const MCInst &MI,
1945 SmallVectorImpl<char> &CB,
1946 SmallVectorImpl<MCFixup> &Fixups,
1947 const MCSubtargetInfo &STI) const {
1948 // Pseudo instructions don't get encoded.
1949 const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
1950 uint64_t TSFlags = Desc.TSFlags;
1951 if ((TSFlags & ARMII::FormMask) == ARMII::Pseudo)
1952 return;
1953
1954 int Size;
1955 if (Desc.getSize() == 2 || Desc.getSize() == 4)
1956 Size = Desc.getSize();
1957 else
1958 llvm_unreachable("Unexpected instruction size!");
1959
1960 auto Endian =
1961 IsLittleEndian ? llvm::endianness::little : llvm::endianness::big;
1962 uint32_t Binary = getBinaryCodeForInstr(MI, Fixups, STI);
1963 if (Size == 2) {
1964 support::endian::write<uint16_t>(CB, Binary, Endian);
1965 } else if (isThumb(STI)) {
1966 // Thumb 32-bit wide instructions need to emit the high order halfword
1967 // first.
1968 support::endian::write<uint16_t>(CB, Binary >> 16, Endian);
1969 support::endian::write<uint16_t>(CB, Binary & 0xffff, Endian);
1970 } else {
1971 support::endian::write<uint32_t>(CB, Binary, Endian);
1972 }
1973 ++MCNumEmitted; // Keep track of the # of mi's emitted.
1974}
1975
1976template <bool isNeg, ARM::Fixups fixup>
1977uint32_t
1978ARMMCCodeEmitter::getBFTargetOpValue(const MCInst &MI, unsigned OpIdx,
1979 SmallVectorImpl<MCFixup> &Fixups,
1980 const MCSubtargetInfo &STI) const {
1981 const MCOperand MO = MI.getOperand(OpIdx);
1982 if (MO.isExpr())
1983 return ::getBranchTargetOpValue(MI, OpIdx, fixup, Fixups, STI);
1984 return isNeg ? -(MO.getImm() >> 1) : (MO.getImm() >> 1);
1985}
1986
1987uint32_t
1988ARMMCCodeEmitter::getBFAfterTargetOpValue(const MCInst &MI, unsigned OpIdx,
1989 SmallVectorImpl<MCFixup> &Fixups,
1990 const MCSubtargetInfo &STI) const {
1991 const MCOperand MO = MI.getOperand(OpIdx);
1992 const MCOperand BranchMO = MI.getOperand(0);
1993
1994 if (MO.isExpr()) {
1995 assert(BranchMO.isExpr());
1996 const MCExpr *DiffExpr = MCBinaryExpr::createSub(
1997 MO.getExpr(), BranchMO.getExpr(), CTX);
1998 MCFixupKind Kind = ARM::fixup_bfcsel_else_target;
1999 addFixup(Fixups, 0, DiffExpr, Kind);
2000 return 0;
2001 }
2002
2003 assert(MO.isImm() && BranchMO.isImm());
2004 int Diff = MO.getImm() - BranchMO.getImm();
2005 assert(Diff == 4 || Diff == 2);
2006
2007 return Diff == 4;
2008}
2009
2010uint32_t ARMMCCodeEmitter::getVPTMaskOpValue(const MCInst &MI, unsigned OpIdx,
2011 SmallVectorImpl<MCFixup> &Fixups,
2012 const MCSubtargetInfo &STI)const {
2013 const MCOperand MO = MI.getOperand(OpIdx);
2014 assert(MO.isImm() && "Unexpected operand type!");
2015
2016 int Value = MO.getImm();
2017 int Imm = 0;
2018
2019 // VPT Masks are actually encoded as a series of invert/don't invert bits,
2020 // rather than true/false bits.
2021 unsigned PrevBit = 0;
2022 for (int i = 3; i >= 0; --i) {
2023 unsigned Bit = (Value >> i) & 1;
2024
2025 // Check if we are at the end of the mask.
2026 if ((Value & ~(~0U << i)) == 0) {
2027 Imm |= (1 << i);
2028 break;
2029 }
2030
2031 // Convert the bit in the mask based on the previous bit.
2032 if (Bit != PrevBit)
2033 Imm |= (1 << i);
2034
2035 PrevBit = Bit;
2036 }
2037
2038 return Imm;
2039}
2040
2041uint32_t ARMMCCodeEmitter::getRestrictedCondCodeOpValue(
2042 const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups,
2043 const MCSubtargetInfo &STI) const {
2044
2045 const MCOperand MO = MI.getOperand(OpIdx);
2046 assert(MO.isImm() && "Unexpected operand type!");
2047
2048 switch (MO.getImm()) {
2049 default:
2050 assert(0 && "Unexpected Condition!");
2051 return 0;
2052 case ARMCC::HS:
2053 case ARMCC::EQ:
2054 return 0;
2055 case ARMCC::HI:
2056 case ARMCC::NE:
2057 return 1;
2058 case ARMCC::GE:
2059 return 4;
2060 case ARMCC::LT:
2061 return 5;
2062 case ARMCC::GT:
2063 return 6;
2064 case ARMCC::LE:
2065 return 7;
2066 }
2067}
2068
2069uint32_t ARMMCCodeEmitter::
2070getPowerTwoOpValue(const MCInst &MI, unsigned OpIdx,
2071 SmallVectorImpl<MCFixup> &Fixups,
2072 const MCSubtargetInfo &STI) const {
2073 const MCOperand &MO = MI.getOperand(OpIdx);
2074 assert(MO.isImm() && "Unexpected operand type!");
2075 return llvm::countr_zero((uint64_t)MO.getImm());
2076}
2077
2078template <unsigned start>
2079uint32_t ARMMCCodeEmitter::
2080getMVEPairVectorIndexOpValue(const MCInst &MI, unsigned OpIdx,
2081 SmallVectorImpl<MCFixup> &Fixups,
2082 const MCSubtargetInfo &STI) const {
2083 const MCOperand MO = MI.getOperand(OpIdx);
2084 assert(MO.isImm() && "Unexpected operand type!");
2085
2086 int Value = MO.getImm();
2087 return Value - start;
2088}
2089
2090#include "ARMGenMCCodeEmitter.inc"
2091
2092MCCodeEmitter *llvm::createARMLEMCCodeEmitter(const MCInstrInfo &MCII,
2093 MCContext &Ctx) {
2094 return new ARMMCCodeEmitter(MCII, Ctx, true);
2095}
2096
2097MCCodeEmitter *llvm::createARMBEMCCodeEmitter(const MCInstrInfo &MCII,
2098 MCContext &Ctx) {
2099 return new ARMMCCodeEmitter(MCII, Ctx, false);
2100}
MRI
unsigned const MachineRegisterInfo * MRI
Definition AArch64AdvSIMDScalarPass.cpp:103
addFixup
static void addFixup(SmallVectorImpl< MCFixup > &Fixups, uint32_t Offset, const MCExpr *Value, uint16_t Kind, bool PCRel=false)
Definition AArch64MCCodeEmitter.cpp:226
assert
assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")
APFloat.h
This file declares a class to represent arbitrary precision floating point values and provide a varie...
APInt.h
This file implements a class to represent arbitrary precision integral constant values and operations...
isThumb
static bool isThumb(const MCSubtargetInfo &STI)
Definition ARMAsmPrinter.cpp:488
HasConditionalBranch
static bool HasConditionalBranch(const MCInst &MI)
Return true if this branch has a non-always predication.
Definition ARMMCCodeEmitter.cpp:714
addFixup
static void addFixup(SmallVectorImpl< MCFixup > &Fixups, uint32_t Offset, const MCExpr *Value, uint16_t Kind)
Definition ARMMCCodeEmitter.cpp:436
encodeThumbBLOffset
static int32_t encodeThumbBLOffset(int32_t offset)
Definition ARMMCCodeEmitter.cpp:636
getBranchTargetOpValue
static uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, unsigned FixupKind, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI)
getBranchTargetOpValue - Helper function to get the branch target operand, which is either an immedia...
Definition ARMMCCodeEmitter.cpp:617
false
Function Alias Analysis false
Definition AliasAnalysis.cpp:734
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
isNeg
static bool isNeg(Value *V)
Returns true if the operation is a negation of V, and it works for both integers and floats.
Definition ComplexDeinterleavingPass.cpp:614
MI
IRTranslator LLVM IR MI
Definition IRTranslator.cpp:110
I
#define I(x, y, z)
Definition MD5.cpp:58
Reg
Register Reg
Definition MachineSink.cpp:2117
isReg
static bool isReg(const MCInst &MI, unsigned OpNo)
Definition MipsInstPrinter.cpp:32
OpIdx
MachineInstr unsigned OpIdx
Definition NVPTXPrologEpilogPass.cpp:56
Mode
static cl::opt< RegAllocEvictionAdvisorAnalysisLegacy::AdvisorMode > Mode("regalloc-enable-advisor", cl::Hidden, cl::init(RegAllocEvictionAdvisorAnalysisLegacy::AdvisorMode::Default), cl::desc("Enable regalloc advisor mode"), cl::values(clEnumValN(RegAllocEvictionAdvisorAnalysisLegacy::AdvisorMode::Default, "default", "Default"), clEnumValN(RegAllocEvictionAdvisorAnalysisLegacy::AdvisorMode::Release, "release", "precompiled"), clEnumValN(RegAllocEvictionAdvisorAnalysisLegacy::AdvisorMode::Development, "development", "for training")))
contains
static bool contains(SmallPtrSetImpl< ConstantExpr * > &Cache, ConstantExpr *Expr, Constant *C)
Definition Value.cpp:480
SmallVector.h
This file defines the SmallVector class.
Statistic.h
This file defines the 'Statistic' class, which is designed to be an easy way to expose various metric...
STATISTIC
#define STATISTIC(VARNAME, DESC)
Definition Statistic.h:171
RHS
Value * RHS
Definition X86PartialReduction.cpp:74
LHS
Value * LHS
Definition X86PartialReduction.cpp:73
llvm::MCBinaryExpr::createSub
static const MCBinaryExpr * createSub(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition MCExpr.h:428
llvm::MCCodeEmitter
MCCodeEmitter - Generic instruction encoding interface.
Definition MCCodeEmitter.h:23
llvm::MCContext
Context object for machine code objects.
Definition MCContext.h:83
llvm::MCContext::getRegisterInfo
const MCRegisterInfo * getRegisterInfo() const
Definition MCContext.h:414
llvm::MCExpr
Base class for the full range of assembler expressions which are needed for parsing.
Definition MCExpr.h:34
llvm::MCExpr::Specifier
@ Specifier
Expression with a relocation specifier.
Definition MCExpr.h:45
llvm::MCFixup::create
static MCFixup create(uint32_t Offset, const MCExpr *Value, MCFixupKind Kind, bool PCRel=false)
Consider bit fields if we need more flags.
Definition MCFixup.h:86
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition MCInst.h:188
llvm::MCInstrInfo
Interface to description of machine instruction set.
Definition MCInstrInfo.h:27
llvm::MCInstrInfo::get
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode.
Definition MCInstrInfo.h:90
llvm::MCOperand
Instances of this class represent operands of the MCInst class.
Definition MCInst.h:40
llvm::MCOperand::getImm
int64_t getImm() const
Definition MCInst.h:84
llvm::MCOperand::isImm
bool isImm() const
Definition MCInst.h:66
llvm::MCOperand::isReg
bool isReg() const
Definition MCInst.h:65
llvm::MCOperand::getReg
MCRegister getReg() const
Returns the register number.
Definition MCInst.h:73
llvm::MCOperand::isDFPImm
bool isDFPImm() const
Definition MCInst.h:68
llvm::MCOperand::getExpr
const MCExpr * getExpr() const
Definition MCInst.h:118
llvm::MCOperand::getDFPImm
uint64_t getDFPImm() const
Definition MCInst.h:104
llvm::MCOperand::isExpr
bool isExpr() const
Definition MCInst.h:69
llvm::MCRegisterInfo::getEncodingValue
uint16_t getEncodingValue(MCRegister Reg) const
Returns the encoding for Reg.
Definition MCRegisterInfo.h:477
llvm::MCRegister::isValid
constexpr bool isValid() const
Definition MCRegister.h:76
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition MCSubtargetInfo.h:77
llvm::MCSubtargetInfo::hasFeature
bool hasFeature(unsigned Feature) const
Definition MCSubtargetInfo.h:122
llvm::MCSubtargetInfo::getTargetTriple
const Triple & getTargetTriple() const
Definition MCSubtargetInfo.h:111
llvm::Register::id
constexpr unsigned id() const
Definition Register.h:95
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition SmallVector.h:575
llvm::Value
LLVM Value Representation.
Definition Value.h:75
uint16_t
uint32_t
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition ErrorHandling.h:164
llvm::AMDGPU::HSAMD::Kernel::Arg::Key::Align
constexpr char Align[]
Key for Kernel::Arg::Metadata::mAlign.
Definition AMDGPUMetadata.h:183
llvm::ARM_AM::getAM3Offset
unsigned char getAM3Offset(unsigned AM3Opc)
Definition ARMAddressingModes.h:437
llvm::ARM_AM::getSORegOffset
unsigned getSORegOffset(unsigned Op)
Definition ARMAddressingModes.h:101
llvm::ARM_AM::getSOImmVal
int getSOImmVal(unsigned Arg)
getSOImmVal - Given a 32-bit immediate, if it is something that can fit into an shifter_operand immed...
Definition ARMAddressingModes.h:149
llvm::ARM_AM::getAM2ShiftOpc
ShiftOpc getAM2ShiftOpc(unsigned AM2Opc)
Definition ARMAddressingModes.h:412
llvm::ARM_AM::getAM2Offset
unsigned getAM2Offset(unsigned AM2Opc)
Definition ARMAddressingModes.h:406
llvm::ARM_AM::AMSubMode
AMSubMode
Definition ARMAddressingModes.h:66
llvm::ARM_AM::da
@ da
Definition ARMAddressingModes.h:70
llvm::ARM_AM::ib
@ ib
Definition ARMAddressingModes.h:69
llvm::ARM_AM::db
@ db
Definition ARMAddressingModes.h:71
llvm::ARM_AM::ia
@ ia
Definition ARMAddressingModes.h:68
llvm::ARM_AM::getT2SOImmVal
int getT2SOImmVal(unsigned Arg)
getT2SOImmVal - Given a 32-bit immediate, if it is something that can fit into a Thumb-2 shifter_oper...
Definition ARMAddressingModes.h:307
llvm::ARM_AM::getSORegShOp
ShiftOpc getSORegShOp(unsigned Op)
Definition ARMAddressingModes.h:102
llvm::ARM_AM::getAM5Op
AddrOpc getAM5Op(unsigned AM5Opc)
Definition ARMAddressingModes.h:481
llvm::ARM_AM::add
@ add
Definition ARMAddressingModes.h:39
llvm::ARM_AM::ShiftOpc
ShiftOpc
Definition ARMAddressingModes.h:27
llvm::ARM_AM::lsr
@ lsr
Definition ARMAddressingModes.h:31
llvm::ARM_AM::asr
@ asr
Definition ARMAddressingModes.h:29
llvm::ARM_AM::no_shift
@ no_shift
Definition ARMAddressingModes.h:28
llvm::ARM_AM::lsl
@ lsl
Definition ARMAddressingModes.h:30
llvm::ARM_AM::rrx
@ rrx
Definition ARMAddressingModes.h:33
llvm::ARM_AM::ror
@ ror
Definition ARMAddressingModes.h:32
llvm::ARM_AM::getAM5Offset
unsigned char getAM5Offset(unsigned AM5Opc)
Definition ARMAddressingModes.h:480
llvm::ARM_AM::getAM2Op
AddrOpc getAM2Op(unsigned AM2Opc)
Definition ARMAddressingModes.h:409
llvm::ARM_AM::getAM3Op
AddrOpc getAM3Op(unsigned AM3Opc)
Definition ARMAddressingModes.h:438
llvm::ARM::fixup_thumb_adr_pcrel_10
@ fixup_thumb_adr_pcrel_10
Definition ARMFixupKinds.h:43
llvm::ARM::fixup_arm_thumb_upper_8_15
@ fixup_arm_thumb_upper_8_15
Definition ARMFixupKinds.h:103
llvm::ARM::fixup_arm_adr_pcrel_12
@ fixup_arm_adr_pcrel_12
Definition ARMFixupKinds.h:45
llvm::ARM::fixup_arm_uncondbranch
@ fixup_arm_uncondbranch
Definition ARMFixupKinds.h:51
llvm::ARM::fixup_arm_movw_lo16
@ fixup_arm_movw_lo16
Definition ARMFixupKinds.h:98
llvm::ARM::fixup_t2_ldst_pcrel_12
@ fixup_t2_ldst_pcrel_12
Definition ARMFixupKinds.h:21
llvm::ARM::fixup_arm_thumb_lower_0_7
@ fixup_arm_thumb_lower_0_7
Definition ARMFixupKinds.h:106
llvm::ARM::fixup_arm_ldst_abs_12
@ fixup_arm_ldst_abs_12
Definition ARMFixupKinds.h:40
llvm::ARM::fixup_arm_movt_hi16
@ fixup_arm_movt_hi16
Definition ARMFixupKinds.h:97
llvm::ARM::fixup_arm_thumb_blx
@ fixup_arm_thumb_blx
Definition ARMFixupKinds.h:84
llvm::ARM::fixup_t2_uncondbranch
@ fixup_t2_uncondbranch
Definition ARMFixupKinds.h:57
llvm::ARM::fixup_arm_pcrel_10_unscaled
@ fixup_arm_pcrel_10_unscaled
Definition ARMFixupKinds.h:25
llvm::ARM::fixup_arm_thumb_bcc
@ fixup_arm_thumb_bcc
Definition ARMFixupKinds.h:93
llvm::ARM::fixup_arm_thumb_upper_0_7
@ fixup_arm_thumb_upper_0_7
Definition ARMFixupKinds.h:104
llvm::ARM::fixup_bfcsel_else_target
@ fixup_bfcsel_else_target
Definition ARMFixupKinds.h:119
llvm::ARM::fixup_t2_adr_pcrel_12
@ fixup_t2_adr_pcrel_12
Definition ARMFixupKinds.h:47
llvm::ARM::fixup_t2_condbranch
@ fixup_t2_condbranch
Definition ARMFixupKinds.h:54
llvm::ARM::fixup_arm_ldst_pcrel_12
@ fixup_arm_ldst_pcrel_12
Definition ARMFixupKinds.h:18
llvm::ARM::fixup_arm_thumb_lower_8_15
@ fixup_arm_thumb_lower_8_15
Definition ARMFixupKinds.h:105
llvm::ARM::fixup_arm_condbranch
@ fixup_arm_condbranch
Definition ARMFixupKinds.h:49
llvm::BitmaskEnumDetail::Mask
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition BitmaskEnum.h:126
llvm::support::endian::write
void write(void *memory, value_type value, endianness endian)
Write a value to memory with a particular endianness.
Definition Endian.h:92
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition AddressRanges.h:18
llvm::drop_begin
auto drop_begin(T &&RangeOrContainer, size_t N=1)
Return a range covering RangeOrContainer with the first N elements excluded.
Definition STLExtras.h:318
llvm::Offset
@ Offset
Definition DWP.cpp:477
llvm::Value
FunctionAddr VTableAddr Value
Definition InstrProf.h:137
llvm::dyn_cast
decltype(auto) dyn_cast(const From &Val)
dyn_cast<X> - Return the argument parameter cast to the specified type.
Definition Casting.h:649
llvm::abs
APFloat abs(APFloat X)
Returns the absolute value of the argument.
Definition APFloat.h:1563
llvm::createARMLEMCCodeEmitter
MCCodeEmitter * createARMLEMCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx)
Definition ARMMCCodeEmitter.cpp:2092
llvm::Desc
Op::Description Desc
Definition DWARFExpressionPrinter.cpp:23
llvm::countr_zero
int countr_zero(T Val)
Count number of 0's from the least significant bit to the most stopping at the first 1.
Definition bit.h:186
llvm::M1
unsigned M1(unsigned Val)
Definition VE.h:377
llvm::Log2_32
unsigned Log2_32(uint32_t Value)
Return the floor log base 2 of the specified value, -1 if the value is zero.
Definition MathExtras.h:342
llvm::MCFixupKind
uint16_t MCFixupKind
Extensible enumeration to represent the type of a fixup.
Definition MCFixup.h:22
llvm::getImm
MachineInstr * getImm(const MachineOperand &MO, const MachineRegisterInfo *MRI)
Definition SPIRVUtils.cpp:976
llvm::FixupKind
static Lanai::Fixups FixupKind(const MCExpr *Expr)
Definition LanaiMCCodeEmitter.cpp:89
llvm::report_fatal_error
LLVM_ABI void report_fatal_error(Error Err, bool gen_crash_diag=true)
Definition Error.cpp:167
llvm::is_sorted
bool is_sorted(R &&Range, Compare C)
Wrapper function around std::is_sorted to check if elements in a range R are sorted with respect to a...
Definition STLExtras.h:1900
llvm::bit_cast
To bit_cast(const From &from) noexcept
Definition bit.h:90
llvm::Op
DWARFExpression::Operation Op
Definition DWARFExpressionPrinter.cpp:22
llvm::M0
unsigned M0(unsigned Val)
Definition VE.h:376
llvm::cast
decltype(auto) cast(const From &Val)
cast<X> - Return the argument parameter cast to the specified type.
Definition Casting.h:565
llvm::createARMBEMCCodeEmitter
MCCodeEmitter * createARMBEMCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx)
Definition ARMMCCodeEmitter.cpp:2097
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