42#define DEBUG_TYPE "mccodeemitter"
44STATISTIC(MCNumEmitted,
"Number of MC instructions emitted.");
45STATISTIC(MCNumCPRelocations,
"Number of constant pool relocations created.");
56 : MCII(mcii), CTX(ctx), IsLittleEndian(IsLittle) {
58 ARMMCCodeEmitter(
const ARMMCCodeEmitter &) =
delete;
59 ARMMCCodeEmitter &operator=(
const ARMMCCodeEmitter &) =
delete;
60 ~ARMMCCodeEmitter()
override =
default;
62 bool isThumb(
const MCSubtargetInfo &STI)
const {
66 bool isThumb2(
const MCSubtargetInfo &STI)
const {
70 bool isTargetMachO(
const MCSubtargetInfo &STI)
const {
72 return TT.isOSBinFormatMachO();
75 unsigned getMachineSoImmOpValue(
unsigned SoImm)
const;
79 uint64_t getBinaryCodeForInstr(
const MCInst &
MI,
80 SmallVectorImpl<MCFixup> &Fixups,
81 const MCSubtargetInfo &STI)
const;
85 unsigned getMachineOpValue(
const MCInst &
MI,
const MCOperand &MO,
86 SmallVectorImpl<MCFixup> &Fixups,
87 const MCSubtargetInfo &STI)
const;
93 uint32_t getHiLoImmOpValue(
const MCInst &
MI,
unsigned OpIdx,
94 SmallVectorImpl<MCFixup> &Fixups,
95 const MCSubtargetInfo &STI)
const;
97 bool EncodeAddrModeOpValues(
const MCInst &
MI,
unsigned OpIdx,
98 unsigned &
Reg,
unsigned &Imm,
99 SmallVectorImpl<MCFixup> &Fixups,
100 const MCSubtargetInfo &STI)
const;
104 uint32_t getThumbBLTargetOpValue(
const MCInst &
MI,
unsigned OpIdx,
105 SmallVectorImpl<MCFixup> &Fixups,
106 const MCSubtargetInfo &STI)
const;
110 uint32_t getThumbBLXTargetOpValue(
const MCInst &
MI,
unsigned OpIdx,
111 SmallVectorImpl<MCFixup> &Fixups,
112 const MCSubtargetInfo &STI)
const;
115 uint32_t getThumbBRTargetOpValue(
const MCInst &
MI,
unsigned OpIdx,
116 SmallVectorImpl<MCFixup> &Fixups,
117 const MCSubtargetInfo &STI)
const;
120 uint32_t getThumbBCCTargetOpValue(
const MCInst &
MI,
unsigned OpIdx,
121 SmallVectorImpl<MCFixup> &Fixups,
122 const MCSubtargetInfo &STI)
const;
125 uint32_t getThumbCBTargetOpValue(
const MCInst &
MI,
unsigned OpIdx,
126 SmallVectorImpl<MCFixup> &Fixups,
127 const MCSubtargetInfo &STI)
const;
132 SmallVectorImpl<MCFixup> &Fixups,
133 const MCSubtargetInfo &STI)
const;
137 uint32_t getThumbBranchTargetOpValue(
const MCInst &
MI,
unsigned OpIdx,
138 SmallVectorImpl<MCFixup> &Fixups,
139 const MCSubtargetInfo &STI)
const;
143 uint32_t getARMBranchTargetOpValue(
const MCInst &
MI,
unsigned OpIdx,
144 SmallVectorImpl<MCFixup> &Fixups,
145 const MCSubtargetInfo &STI)
const;
146 uint32_t getARMBLTargetOpValue(
const MCInst &
MI,
unsigned OpIdx,
147 SmallVectorImpl<MCFixup> &Fixups,
148 const MCSubtargetInfo &STI)
const;
149 uint32_t getARMBLXTargetOpValue(
const MCInst &
MI,
unsigned OpIdx,
150 SmallVectorImpl<MCFixup> &Fixups,
151 const MCSubtargetInfo &STI)
const;
155 uint32_t getAdrLabelOpValue(
const MCInst &
MI,
unsigned OpIdx,
156 SmallVectorImpl<MCFixup> &Fixups,
157 const MCSubtargetInfo &STI)
const;
158 uint32_t getThumbAdrLabelOpValue(
const MCInst &
MI,
unsigned OpIdx,
159 SmallVectorImpl<MCFixup> &Fixups,
160 const MCSubtargetInfo &STI)
const;
161 uint32_t getT2AdrLabelOpValue(
const MCInst &
MI,
unsigned OpIdx,
162 SmallVectorImpl<MCFixup> &Fixups,
163 const MCSubtargetInfo &STI)
const;
165 uint32_t getITMaskOpValue(
const MCInst &
MI,
unsigned OpIdx,
166 SmallVectorImpl<MCFixup> &Fixups,
167 const MCSubtargetInfo &STI)
const;
171 uint32_t getMVEShiftImmOpValue(
const MCInst &
MI,
unsigned OpIdx,
172 SmallVectorImpl<MCFixup> &Fixups,
173 const MCSubtargetInfo &STI)
const;
177 uint32_t getAddrModeImm12OpValue(
const MCInst &
MI,
unsigned OpIdx,
178 SmallVectorImpl<MCFixup> &Fixups,
179 const MCSubtargetInfo &STI)
const;
182 uint32_t getThumbAddrModeRegRegOpValue(
const MCInst &
MI,
unsigned OpIdx,
183 SmallVectorImpl<MCFixup> &Fixups,
184 const MCSubtargetInfo &STI)
const;
188 uint32_t getT2AddrModeImm8s4OpValue(
const MCInst &
MI,
unsigned OpIdx,
189 SmallVectorImpl<MCFixup> &Fixups,
190 const MCSubtargetInfo &STI)
const;
194 uint32_t getT2AddrModeImm7s4OpValue(
const MCInst &
MI,
unsigned OpIdx,
195 SmallVectorImpl<MCFixup> &Fixups,
196 const MCSubtargetInfo &STI)
const;
200 uint32_t getT2AddrModeImm0_1020s4OpValue(
const MCInst &
MI,
unsigned OpIdx,
201 SmallVectorImpl<MCFixup> &Fixups,
202 const MCSubtargetInfo &STI)
const;
206 template<
unsigned Bits,
unsigned Shift>
207 uint32_t getT2ScaledImmOpValue(
const MCInst &
MI,
unsigned OpIdx,
208 SmallVectorImpl<MCFixup> &Fixups,
209 const MCSubtargetInfo &STI)
const;
213 uint32_t getMveAddrModeRQOpValue(
const MCInst &
MI,
unsigned OpIdx,
214 SmallVectorImpl<MCFixup> &Fixups,
215 const MCSubtargetInfo &STI)
const;
220 uint32_t getMveAddrModeQOpValue(
const MCInst &
MI,
unsigned OpIdx,
221 SmallVectorImpl<MCFixup> &Fixups,
222 const MCSubtargetInfo &STI)
const;
226 uint32_t getLdStSORegOpValue(
const MCInst &
MI,
unsigned OpIdx,
227 SmallVectorImpl<MCFixup> &Fixups,
228 const MCSubtargetInfo &STI)
const;
231 uint32_t getLdStmModeOpValue(
const MCInst &
MI,
unsigned OpIdx,
232 SmallVectorImpl<MCFixup> &Fixups,
233 const MCSubtargetInfo &STI)
const {
260 uint32_t getAddrMode2OffsetOpValue(
const MCInst &
MI,
unsigned OpIdx,
261 SmallVectorImpl<MCFixup> &Fixups,
262 const MCSubtargetInfo &STI)
const;
265 uint32_t getPostIdxRegOpValue(
const MCInst &
MI,
unsigned OpIdx,
266 SmallVectorImpl<MCFixup> &Fixups,
267 const MCSubtargetInfo &STI)
const;
270 uint32_t getAddrMode3OffsetOpValue(
const MCInst &
MI,
unsigned OpIdx,
271 SmallVectorImpl<MCFixup> &Fixups,
272 const MCSubtargetInfo &STI)
const;
275 uint32_t getAddrMode3OpValue(
const MCInst &
MI,
unsigned OpIdx,
276 SmallVectorImpl<MCFixup> &Fixups,
277 const MCSubtargetInfo &STI)
const;
281 uint32_t getAddrModeThumbSPOpValue(
const MCInst &
MI,
unsigned OpIdx,
282 SmallVectorImpl<MCFixup> &Fixups,
283 const MCSubtargetInfo &STI)
const;
286 uint32_t getAddrModeISOpValue(
const MCInst &
MI,
unsigned OpIdx,
287 SmallVectorImpl<MCFixup> &Fixups,
288 const MCSubtargetInfo &STI)
const;
291 uint32_t getAddrModePCOpValue(
const MCInst &
MI,
unsigned OpIdx,
292 SmallVectorImpl<MCFixup> &Fixups,
293 const MCSubtargetInfo &STI)
const;
296 uint32_t getAddrMode5OpValue(
const MCInst &
MI,
unsigned OpIdx,
297 SmallVectorImpl<MCFixup> &Fixups,
298 const MCSubtargetInfo &STI)
const;
301 uint32_t getAddrMode5FP16OpValue(
const MCInst &
MI,
unsigned OpIdx,
302 SmallVectorImpl<MCFixup> &Fixups,
303 const MCSubtargetInfo &STI)
const;
306 unsigned getCCOutOpValue(
const MCInst &
MI,
unsigned Op,
307 SmallVectorImpl<MCFixup> &Fixups,
308 const MCSubtargetInfo &STI)
const {
311 return MI.getOperand(
Op).getReg() == ARM::CPSR;
314 unsigned getModImmOpValue(
const MCInst &
MI,
unsigned Op,
315 SmallVectorImpl<MCFixup> &Fixups,
316 const MCSubtargetInfo &ST)
const;
319 unsigned getT2SOImmOpValue(
const MCInst &
MI,
unsigned Op,
320 SmallVectorImpl<MCFixup> &Fixups,
321 const MCSubtargetInfo &STI)
const;
323 unsigned getT2AddrModeSORegOpValue(
const MCInst &
MI,
unsigned OpNum,
324 SmallVectorImpl<MCFixup> &Fixups,
325 const MCSubtargetInfo &STI)
const;
326 template<
unsigned Bits,
unsigned Shift>
327 unsigned getT2AddrModeImmOpValue(
const MCInst &
MI,
unsigned OpNum,
328 SmallVectorImpl<MCFixup> &Fixups,
329 const MCSubtargetInfo &STI)
const;
330 unsigned getT2AddrModeImm8OffsetOpValue(
const MCInst &
MI,
unsigned OpNum,
331 SmallVectorImpl<MCFixup> &Fixups,
332 const MCSubtargetInfo &STI)
const;
335 unsigned getSORegRegOpValue(
const MCInst &
MI,
unsigned Op,
336 SmallVectorImpl<MCFixup> &Fixups,
337 const MCSubtargetInfo &STI)
const;
338 unsigned getSORegImmOpValue(
const MCInst &
MI,
unsigned Op,
339 SmallVectorImpl<MCFixup> &Fixups,
340 const MCSubtargetInfo &STI)
const;
341 unsigned getT2SORegOpValue(
const MCInst &
MI,
unsigned Op,
342 SmallVectorImpl<MCFixup> &Fixups,
343 const MCSubtargetInfo &STI)
const;
345 unsigned getNEONVcvtImm32OpValue(
const MCInst &
MI,
unsigned Op,
346 SmallVectorImpl<MCFixup> &Fixups,
347 const MCSubtargetInfo &STI)
const {
348 return 64 -
MI.getOperand(
Op).getImm();
351 unsigned getBitfieldInvertedMaskOpValue(
const MCInst &
MI,
unsigned Op,
352 SmallVectorImpl<MCFixup> &Fixups,
353 const MCSubtargetInfo &STI)
const;
355 unsigned getRegisterListOpValue(
const MCInst &
MI,
unsigned Op,
356 SmallVectorImpl<MCFixup> &Fixups,
357 const MCSubtargetInfo &STI)
const;
358 unsigned getAddrMode6AddressOpValue(
const MCInst &
MI,
unsigned Op,
359 SmallVectorImpl<MCFixup> &Fixups,
360 const MCSubtargetInfo &STI)
const;
361 unsigned getAddrMode6OneLane32AddressOpValue(
const MCInst &
MI,
unsigned Op,
362 SmallVectorImpl<MCFixup> &Fixups,
363 const MCSubtargetInfo &STI)
const;
364 unsigned getAddrMode6DupAddressOpValue(
const MCInst &
MI,
unsigned Op,
365 SmallVectorImpl<MCFixup> &Fixups,
366 const MCSubtargetInfo &STI)
const;
367 unsigned getAddrMode6OffsetOpValue(
const MCInst &
MI,
unsigned Op,
368 SmallVectorImpl<MCFixup> &Fixups,
369 const MCSubtargetInfo &STI)
const;
371 unsigned getShiftRight8Imm(
const MCInst &
MI,
unsigned Op,
372 SmallVectorImpl<MCFixup> &Fixups,
373 const MCSubtargetInfo &STI)
const;
374 unsigned getShiftRight16Imm(
const MCInst &
MI,
unsigned Op,
375 SmallVectorImpl<MCFixup> &Fixups,
376 const MCSubtargetInfo &STI)
const;
377 unsigned getShiftRight32Imm(
const MCInst &
MI,
unsigned Op,
378 SmallVectorImpl<MCFixup> &Fixups,
379 const MCSubtargetInfo &STI)
const;
380 unsigned getShiftRight64Imm(
const MCInst &
MI,
unsigned Op,
381 SmallVectorImpl<MCFixup> &Fixups,
382 const MCSubtargetInfo &STI)
const;
384 unsigned getThumbSRImmOpValue(
const MCInst &
MI,
unsigned Op,
385 SmallVectorImpl<MCFixup> &Fixups,
386 const MCSubtargetInfo &STI)
const;
388 unsigned NEONThumb2DataIPostEncoder(
const MCInst &
MI,
389 unsigned EncodedValue,
390 const MCSubtargetInfo &STI)
const;
391 unsigned NEONThumb2LoadStorePostEncoder(
const MCInst &
MI,
392 unsigned EncodedValue,
393 const MCSubtargetInfo &STI)
const;
394 unsigned NEONThumb2DupPostEncoder(
const MCInst &
MI,
395 unsigned EncodedValue,
396 const MCSubtargetInfo &STI)
const;
397 unsigned NEONThumb2V8PostEncoder(
const MCInst &
MI,
398 unsigned EncodedValue,
399 const MCSubtargetInfo &STI)
const;
401 unsigned VFPThumb2PostEncoder(
const MCInst &
MI,
402 unsigned EncodedValue,
403 const MCSubtargetInfo &STI)
const;
405 uint32_t getPowerTwoOpValue(
const MCInst &
MI,
unsigned OpIdx,
406 SmallVectorImpl<MCFixup> &Fixups,
407 const MCSubtargetInfo &STI)
const;
409 void encodeInstruction(
const MCInst &
MI, SmallVectorImpl<char> &CB,
410 SmallVectorImpl<MCFixup> &Fixups,
411 const MCSubtargetInfo &STI)
const override;
413 template <
bool isNeg, ARM::Fixups fixup>
414 uint32_t getBFTargetOpValue(
const MCInst &
MI,
unsigned OpIdx,
415 SmallVectorImpl<MCFixup> &Fixups,
416 const MCSubtargetInfo &STI)
const;
418 uint32_t getBFAfterTargetOpValue(
const MCInst &
MI,
unsigned OpIdx,
419 SmallVectorImpl<MCFixup> &Fixups,
420 const MCSubtargetInfo &STI)
const;
422 uint32_t getVPTMaskOpValue(
const MCInst &
MI,
unsigned OpIdx,
423 SmallVectorImpl<MCFixup> &Fixups,
424 const MCSubtargetInfo &STI)
const;
425 uint32_t getRestrictedCondCodeOpValue(
const MCInst &
MI,
unsigned OpIdx,
426 SmallVectorImpl<MCFixup> &Fixups,
427 const MCSubtargetInfo &STI)
const;
428 template <
unsigned size>
429 uint32_t getMVEPairVectorIndexOpValue(
const MCInst &
MI,
unsigned OpIdx,
430 SmallVectorImpl<MCFixup> &Fixups,
431 const MCSubtargetInfo &STI)
const;
477unsigned ARMMCCodeEmitter::NEONThumb2DataIPostEncoder(
const MCInst &
MI,
478 unsigned EncodedValue,
484 unsigned Bit24 = EncodedValue & 0x01000000;
485 unsigned Bit28 = Bit24 << 4;
486 EncodedValue &= 0xEFFFFFFF;
487 EncodedValue |= Bit28;
488 EncodedValue |= 0x0F000000;
497unsigned ARMMCCodeEmitter::NEONThumb2LoadStorePostEncoder(
const MCInst &
MI,
498 unsigned EncodedValue,
499 const MCSubtargetInfo &STI)
const {
501 EncodedValue &= 0xF0FFFFFF;
502 EncodedValue |= 0x09000000;
511unsigned ARMMCCodeEmitter::NEONThumb2DupPostEncoder(
const MCInst &
MI,
512 unsigned EncodedValue,
513 const MCSubtargetInfo &STI)
const {
515 EncodedValue &= 0x00FFFFFF;
516 EncodedValue |= 0xEE000000;
524unsigned ARMMCCodeEmitter::NEONThumb2V8PostEncoder(
const MCInst &
MI,
525 unsigned EncodedValue,
526 const MCSubtargetInfo &STI)
const {
528 EncodedValue |= 0xC000000;
536unsigned ARMMCCodeEmitter::
537VFPThumb2PostEncoder(
const MCInst &
MI,
unsigned EncodedValue,
538 const MCSubtargetInfo &STI)
const {
540 EncodedValue &= 0x0FFFFFFF;
541 EncodedValue |= 0xE0000000;
548unsigned ARMMCCodeEmitter::
549getMachineOpValue(
const MCInst &
MI,
const MCOperand &MO,
550 SmallVectorImpl<MCFixup> &Fixups,
551 const MCSubtargetInfo &STI)
const {
568 case ARM::Q0:
case ARM::Q1:
case ARM::Q2:
case ARM::Q3:
569 case ARM::Q4:
case ARM::Q5:
case ARM::Q6:
case ARM::Q7:
570 case ARM::Q8:
case ARM::Q9:
case ARM::Q10:
case ARM::Q11:
571 case ARM::Q12:
case ARM::Q13:
case ARM::Q14:
case ARM::Q15:
574 }
else if (MO.
isImm()) {
575 return static_cast<unsigned>(MO.
getImm());
587bool ARMMCCodeEmitter::
588EncodeAddrModeOpValues(
const MCInst &
MI,
unsigned OpIdx,
unsigned &
Reg,
589 unsigned &Imm, SmallVectorImpl<MCFixup> &Fixups,
590 const MCSubtargetInfo &STI)
const {
591 const MCOperand &MO =
MI.getOperand(
OpIdx);
592 const MCOperand &MO1 =
MI.getOperand(
OpIdx + 1);
596 int32_t SImm = MO1.
getImm();
600 if (SImm == INT32_MIN) {
625 assert(MO.
isExpr() &&
"Unexpected branch target type!");
638 uint32_t S = (offset & 0x800000) >> 23;
639 uint32_t J1 = (offset & 0x400000) >> 22;
640 uint32_t J2 = (offset & 0x200000) >> 21;
654uint32_t ARMMCCodeEmitter::
655getThumbBLTargetOpValue(
const MCInst &
MI,
unsigned OpIdx,
656 SmallVectorImpl<MCFixup> &Fixups,
657 const MCSubtargetInfo &STI)
const {
658 const MCOperand MO =
MI.getOperand(
OpIdx);
667uint32_t ARMMCCodeEmitter::
668getThumbBLXTargetOpValue(
const MCInst &
MI,
unsigned OpIdx,
669 SmallVectorImpl<MCFixup> &Fixups,
670 const MCSubtargetInfo &STI)
const {
671 const MCOperand MO =
MI.getOperand(
OpIdx);
679uint32_t ARMMCCodeEmitter::
680getThumbBRTargetOpValue(
const MCInst &
MI,
unsigned OpIdx,
681 SmallVectorImpl<MCFixup> &Fixups,
682 const MCSubtargetInfo &STI)
const {
683 const MCOperand MO =
MI.getOperand(
OpIdx);
687 return (MO.
getImm() >> 1);
691uint32_t ARMMCCodeEmitter::
692getThumbBCCTargetOpValue(
const MCInst &
MI,
unsigned OpIdx,
693 SmallVectorImpl<MCFixup> &Fixups,
694 const MCSubtargetInfo &STI)
const {
695 const MCOperand MO =
MI.getOperand(
OpIdx);
699 return (MO.
getImm() >> 1);
703uint32_t ARMMCCodeEmitter::
704getThumbCBTargetOpValue(
const MCInst &
MI,
unsigned OpIdx,
705 SmallVectorImpl<MCFixup> &Fixups,
706 const MCSubtargetInfo &STI)
const {
707 const MCOperand MO =
MI.getOperand(
OpIdx);
710 return (MO.
getImm() >> 1);
715 int NumOp =
MI.getNumOperands();
717 for (
int i = 0; i < NumOp-1; ++i) {
732uint32_t ARMMCCodeEmitter::
733getBranchTargetOpValue(
const MCInst &
MI,
unsigned OpIdx,
734 SmallVectorImpl<MCFixup> &Fixups,
735 const MCSubtargetInfo &STI)
const {
741 return getARMBranchTargetOpValue(
MI,
OpIdx, Fixups, STI);
746uint32_t ARMMCCodeEmitter::
747getARMBranchTargetOpValue(
const MCInst &
MI,
unsigned OpIdx,
748 SmallVectorImpl<MCFixup> &Fixups,
749 const MCSubtargetInfo &STI)
const {
750 const MCOperand MO =
MI.getOperand(
OpIdx);
753 return ::getBranchTargetOpValue(
MI,
OpIdx,
755 return ::getBranchTargetOpValue(
MI,
OpIdx,
762uint32_t ARMMCCodeEmitter::
763getARMBLTargetOpValue(
const MCInst &
MI,
unsigned OpIdx,
764 SmallVectorImpl<MCFixup> &Fixups,
765 const MCSubtargetInfo &STI)
const {
766 const MCOperand MO =
MI.getOperand(
OpIdx);
769 return ::getBranchTargetOpValue(
MI,
OpIdx,
777uint32_t ARMMCCodeEmitter::
778getARMBLXTargetOpValue(
const MCInst &
MI,
unsigned OpIdx,
779 SmallVectorImpl<MCFixup> &Fixups,
780 const MCSubtargetInfo &STI)
const {
781 const MCOperand MO =
MI.getOperand(
OpIdx);
790uint32_t ARMMCCodeEmitter::getThumbBranchTargetOpValue(
791 const MCInst &
MI,
unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups,
792 const MCSubtargetInfo &STI)
const {
794 const MCOperand MO =
MI.getOperand(
OpIdx);
801 bool I = (Val & 0x800000);
802 bool J1 = (Val & 0x400000);
803 bool J2 = (Val & 0x200000);
819uint32_t ARMMCCodeEmitter::
820getAdrLabelOpValue(
const MCInst &
MI,
unsigned OpIdx,
821 SmallVectorImpl<MCFixup> &Fixups,
822 const MCSubtargetInfo &STI)
const {
823 const MCOperand MO =
MI.getOperand(
OpIdx);
827 int64_t offset = MO.
getImm();
828 uint32_t Val = 0x2000;
831 if (offset == INT32_MIN) {
834 }
else if (offset < 0) {
852 assert(SoImmVal != -1 &&
"Not a valid so_imm value!");
860uint32_t ARMMCCodeEmitter::
861getT2AdrLabelOpValue(
const MCInst &
MI,
unsigned OpIdx,
862 SmallVectorImpl<MCFixup> &Fixups,
863 const MCSubtargetInfo &STI)
const {
864 const MCOperand MO =
MI.getOperand(
OpIdx);
868 int32_t Val = MO.
getImm();
869 if (Val == INT32_MIN)
880uint32_t ARMMCCodeEmitter::
881getITMaskOpValue(
const MCInst &
MI,
unsigned OpIdx,
882 SmallVectorImpl<MCFixup> &Fixups,
883 const MCSubtargetInfo &STI)
const {
884 const MCOperand MaskMO =
MI.getOperand(
OpIdx);
885 assert(MaskMO.
isImm() &&
"Unexpected operand type!");
894 const MCOperand CondMO =
MI.getOperand(
OpIdx-1);
895 assert(CondMO.
isImm() &&
"Unexpected operand type!");
896 if (CondMO.
getImm() & 1) {
898 unsigned BitsAboveLowBit = 0xF & (-LowBit << 1);
899 Mask ^= BitsAboveLowBit;
907uint32_t ARMMCCodeEmitter::
908getThumbAdrLabelOpValue(
const MCInst &
MI,
unsigned OpIdx,
909 SmallVectorImpl<MCFixup> &Fixups,
910 const MCSubtargetInfo &STI)
const {
911 const MCOperand MO =
MI.getOperand(
OpIdx);
920uint32_t ARMMCCodeEmitter::
921getThumbAddrModeRegRegOpValue(
const MCInst &
MI,
unsigned OpIdx,
922 SmallVectorImpl<MCFixup> &,
923 const MCSubtargetInfo &STI)
const {
927 const MCOperand &MO1 =
MI.getOperand(
OpIdx);
928 const MCOperand &MO2 =
MI.getOperand(
OpIdx + 1);
931 return (Rm << 3) | Rn;
937ARMMCCodeEmitter::getMVEShiftImmOpValue(
const MCInst &
MI,
unsigned OpIdx,
938 SmallVectorImpl<MCFixup> &Fixups,
939 const MCSubtargetInfo &STI)
const {
948 unsigned Size, ShiftImm;
949 switch(
MI.getOpcode()) {
950 case ARM::MVE_VSHLL_imms16bh:
951 case ARM::MVE_VSHLL_imms16th:
952 case ARM::MVE_VSHLL_immu16bh:
953 case ARM::MVE_VSHLL_immu16th:
956 case ARM::MVE_VSHLL_imms8bh:
957 case ARM::MVE_VSHLL_imms8th:
958 case ARM::MVE_VSHLL_immu8bh:
959 case ARM::MVE_VSHLL_immu8th:
965 ShiftImm =
MI.getOperand(
OpIdx).getImm();
966 return Size + ShiftImm;
970uint32_t ARMMCCodeEmitter::
971getAddrModeImm12OpValue(
const MCInst &
MI,
unsigned OpIdx,
972 SmallVectorImpl<MCFixup> &Fixups,
973 const MCSubtargetInfo &STI)
const {
977 unsigned Reg = 0, Imm12 = 0;
980 const MCOperand &MO =
MI.getOperand(
OpIdx);
982 const MCOperand &MO1 =
MI.getOperand(
OpIdx + 1);
984 isAdd = EncodeAddrModeOpValues(
MI,
OpIdx,
Reg, Imm12, Fixups, STI);
985 }
else if (MO1.
isExpr()) {
987 "Thumb mode requires different encoding");
1003 ++MCNumCPRelocations;
1007 if (
Offset == INT32_MIN) {
1016 uint32_t
Binary = Imm12 & 0xfff;
1024template<
unsigned Bits,
unsigned Shift>
1025uint32_t ARMMCCodeEmitter::
1026getT2ScaledImmOpValue(
const MCInst &
MI,
unsigned OpIdx,
1027 SmallVectorImpl<MCFixup> &Fixups,
1028 const MCSubtargetInfo &STI)
const {
1039 bool isAdd =
Imm >= 0;
1043 Imm = -(uint32_t)Imm;
1056uint32_t ARMMCCodeEmitter::
1057getMveAddrModeRQOpValue(
const MCInst &
MI,
unsigned OpIdx,
1058 SmallVectorImpl<MCFixup> &Fixups,
1059 const MCSubtargetInfo &STI)
const {
1062 const MCOperand &
M0 =
MI.getOperand(
OpIdx);
1063 const MCOperand &
M1 =
MI.getOperand(
OpIdx + 1);
1068 assert(Qm < 8 &&
"Qm is supposed to be encodable in 3 bits");
1070 return (Rn << 3) | Qm;
1076uint32_t ARMMCCodeEmitter::
1077getMveAddrModeQOpValue(
const MCInst &
MI,
unsigned OpIdx,
1078 SmallVectorImpl<MCFixup> &Fixups,
1079 const MCSubtargetInfo &STI)
const {
1082 const MCOperand &
M0 =
MI.getOperand(
OpIdx);
1083 const MCOperand &
M1 =
MI.getOperand(
OpIdx + 1);
1086 int32_t
Imm =
M1.getImm();
1088 bool isAdd =
Imm >= 0;
1093 Imm = -(uint32_t)Imm;
1100 assert(Qm < 8 &&
"Qm is supposed to be encodable in 3 bits");
1102 return (Qm << 8) |
Imm;
1107uint32_t ARMMCCodeEmitter::
1108getT2AddrModeImm8s4OpValue(
const MCInst &
MI,
unsigned OpIdx,
1109 SmallVectorImpl<MCFixup> &Fixups,
1110 const MCSubtargetInfo &STI)
const {
1117 const MCOperand &MO =
MI.getOperand(
OpIdx);
1123 assert(MO.
isExpr() &&
"Unexpected machine operand type!");
1124 const MCExpr *Expr = MO.
getExpr();
1128 ++MCNumCPRelocations;
1130 isAdd = EncodeAddrModeOpValues(
MI,
OpIdx,
Reg, Imm8, Fixups, STI);
1138 assert(((Imm8 & 0x3) == 0) &&
"Not a valid immediate!");
1150ARMMCCodeEmitter::getT2AddrModeImm7s4OpValue(
const MCInst &
MI,
unsigned OpIdx,
1151 SmallVectorImpl<MCFixup> &Fixups,
1152 const MCSubtargetInfo &STI)
const {
1158 bool isAdd = EncodeAddrModeOpValues(
MI,
OpIdx,
Reg, Imm7, Fixups, STI);
1166 uint32_t
Binary = (Imm7 >> 2) & 0xff;
1176uint32_t ARMMCCodeEmitter::
1177getT2AddrModeImm0_1020s4OpValue(
const MCInst &
MI,
unsigned OpIdx,
1178 SmallVectorImpl<MCFixup> &Fixups,
1179 const MCSubtargetInfo &STI)
const {
1182 const MCOperand &MO =
MI.getOperand(
OpIdx);
1183 const MCOperand &MO1 =
MI.getOperand(
OpIdx + 1);
1189uint32_t ARMMCCodeEmitter::getHiLoImmOpValue(
const MCInst &
MI,
unsigned OpIdx,
1190 SmallVectorImpl<MCFixup> &Fixups,
1191 const MCSubtargetInfo &STI)
const {
1194 const MCOperand &MO =
MI.getOperand(
OpIdx);
1197 return static_cast<unsigned>(MO.
getImm());
1205 E = ARM16Expr->getSubExpr();
1208 const int64_t
Value = MCE->getValue();
1209 if (
Value > UINT32_MAX)
1212 switch (ARM16Expr->getSpecifier()) {
1214 return (int32_t(
Value) & 0xffff0000) >> 16;
1216 return (int32_t(
Value) & 0x0000ffff);
1219 return (int32_t(
Value) & 0xff000000) >> 24;
1221 return (int32_t(
Value) & 0x00ff0000) >> 16;
1223 return (int32_t(
Value) & 0x0000ff00) >> 8;
1225 return (int32_t(
Value) & 0x000000ff);
1231 switch (ARM16Expr->getSpecifier()) {
1273 ":upper0_7:, lower8_15: or :lower0_7:");
1276uint32_t ARMMCCodeEmitter::
1277getLdStSORegOpValue(
const MCInst &
MI,
unsigned OpIdx,
1278 SmallVectorImpl<MCFixup> &Fixups,
1279 const MCSubtargetInfo &STI)
const {
1280 const MCOperand &MO =
MI.getOperand(
OpIdx);
1281 const MCOperand &MO1 =
MI.getOperand(
OpIdx+1);
1282 const MCOperand &MO2 =
MI.getOperand(
OpIdx+2);
1288 unsigned SBits = getShiftOp(ShOp);
1292 assert((ShImm & ~0x1f) == 0 &&
"Out of range shift amount");
1310uint32_t ARMMCCodeEmitter::
1311getAddrMode2OffsetOpValue(
const MCInst &
MI,
unsigned OpIdx,
1312 SmallVectorImpl<MCFixup> &Fixups,
1313 const MCSubtargetInfo &STI)
const {
1317 const MCOperand &MO =
MI.getOperand(
OpIdx);
1318 const MCOperand &MO1 =
MI.getOperand(
OpIdx+1);
1327 Binary |= getShiftOp(ShOp) << 5;
1333uint32_t ARMMCCodeEmitter::
1334getPostIdxRegOpValue(
const MCInst &
MI,
unsigned OpIdx,
1335 SmallVectorImpl<MCFixup> &Fixups,
1336 const MCSubtargetInfo &STI)
const {
1339 const MCOperand &MO =
MI.getOperand(
OpIdx);
1340 const MCOperand &MO1 =
MI.getOperand(
OpIdx+1);
1341 bool isAdd = MO1.
getImm() != 0;
1345uint32_t ARMMCCodeEmitter::
1346getAddrMode3OffsetOpValue(
const MCInst &
MI,
unsigned OpIdx,
1347 SmallVectorImpl<MCFixup> &Fixups,
1348 const MCSubtargetInfo &STI)
const {
1353 const MCOperand &MO =
MI.getOperand(
OpIdx);
1354 const MCOperand &MO1 =
MI.getOperand(
OpIdx+1);
1362 return Imm8 | (isAdd << 8) | (isImm << 9);
1365uint32_t ARMMCCodeEmitter::
1366getAddrMode3OpValue(
const MCInst &
MI,
unsigned OpIdx,
1367 SmallVectorImpl<MCFixup> &Fixups,
1368 const MCSubtargetInfo &STI)
const {
1374 const MCOperand &MO =
MI.getOperand(
OpIdx);
1375 const MCOperand &MO1 =
MI.getOperand(
OpIdx+1);
1376 const MCOperand &MO2 =
MI.getOperand(
OpIdx+2);
1382 assert(MO.
isExpr() &&
"Unexpected machine operand type!");
1383 const MCExpr *Expr = MO.
getExpr();
1387 ++MCNumCPRelocations;
1388 return (Rn << 9) | (1 << 13);
1398 return (Rn << 9) |
Imm8 | (isAdd << 8) | (isImm << 13);
1402uint32_t ARMMCCodeEmitter::
1403getAddrModeThumbSPOpValue(
const MCInst &
MI,
unsigned OpIdx,
1404 SmallVectorImpl<MCFixup> &Fixups,
1405 const MCSubtargetInfo &STI)
const {
1408 const MCOperand &MO1 =
MI.getOperand(
OpIdx + 1);
1410 "Unexpected base register!");
1414 return MO1.
getImm() & 0xff;
1418uint32_t ARMMCCodeEmitter::
1419getAddrModeISOpValue(
const MCInst &
MI,
unsigned OpIdx,
1420 SmallVectorImpl<MCFixup> &Fixups,
1421 const MCSubtargetInfo &STI)
const {
1425 const MCOperand &MO =
MI.getOperand(
OpIdx);
1426 const MCOperand &MO1 =
MI.getOperand(
OpIdx + 1);
1428 unsigned Imm5 = MO1.
getImm();
1429 return ((Imm5 & 0x1f) << 3) | Rn;
1433uint32_t ARMMCCodeEmitter::
1434getAddrModePCOpValue(
const MCInst &
MI,
unsigned OpIdx,
1435 SmallVectorImpl<MCFixup> &Fixups,
1436 const MCSubtargetInfo &STI)
const {
1437 const MCOperand MO =
MI.getOperand(
OpIdx);
1440 return (MO.
getImm() >> 2);
1444uint32_t ARMMCCodeEmitter::
1445getAddrMode5OpValue(
const MCInst &
MI,
unsigned OpIdx,
1446 SmallVectorImpl<MCFixup> &Fixups,
1447 const MCSubtargetInfo &STI)
const {
1454 const MCOperand &MO =
MI.getOperand(
OpIdx);
1460 assert(MO.
isExpr() &&
"Unexpected machine operand type!");
1461 const MCExpr *Expr = MO.
getExpr();
1469 ++MCNumCPRelocations;
1471 EncodeAddrModeOpValues(
MI,
OpIdx,
Reg, Imm8, Fixups, STI);
1484uint32_t ARMMCCodeEmitter::
1485getAddrMode5FP16OpValue(
const MCInst &
MI,
unsigned OpIdx,
1486 SmallVectorImpl<MCFixup> &Fixups,
1487 const MCSubtargetInfo &STI)
const {
1494 const MCOperand &MO =
MI.getOperand(
OpIdx);
1500 assert(MO.
isExpr() &&
"Unexpected machine operand type!");
1501 const MCExpr *Expr = MO.
getExpr();
1509 ++MCNumCPRelocations;
1511 EncodeAddrModeOpValues(
MI,
OpIdx,
Reg, Imm8, Fixups, STI);
1523unsigned ARMMCCodeEmitter::getModImmOpValue(
const MCInst &
MI,
unsigned Op,
1524 SmallVectorImpl<MCFixup> &Fixups,
1525 const MCSubtargetInfo &ST)
const {
1526 const MCOperand &MO =
MI.getOperand(
Op);
1530 const MCExpr *Expr = MO.
getExpr();
1541unsigned ARMMCCodeEmitter::getT2SOImmOpValue(
const MCInst &
MI,
unsigned Op,
1542 SmallVectorImpl<MCFixup> &Fixups,
1543 const MCSubtargetInfo &STI)
const {
1544 const MCOperand &MO =
MI.getOperand(
Op);
1548 const MCExpr *Expr = MO.
getExpr();
1554 unsigned SoImm = MO.
getImm();
1556 assert(Encoded != ~0U &&
"Not a Thumb2 so_imm value?");
1560unsigned ARMMCCodeEmitter::
1561getSORegRegOpValue(
const MCInst &
MI,
unsigned OpIdx,
1562 SmallVectorImpl<MCFixup> &Fixups,
1563 const MCSubtargetInfo &STI)
const {
1574 const MCOperand &MO =
MI.getOperand(
OpIdx);
1575 const MCOperand &MO1 =
MI.getOperand(
OpIdx + 1);
1576 const MCOperand &MO2 =
MI.getOperand(
OpIdx + 2);
1584 MCRegister Rs = MO1.
getReg();
1608unsigned ARMMCCodeEmitter::
1609getSORegImmOpValue(
const MCInst &
MI,
unsigned OpIdx,
1610 SmallVectorImpl<MCFixup> &Fixups,
1611 const MCSubtargetInfo &STI)
const {
1620 const MCOperand &MO =
MI.getOperand(
OpIdx);
1621 const MCOperand &MO1 =
MI.getOperand(
OpIdx + 1);
1650 assert(
Offset < 32 &&
"Offset must be in range 0-31!");
1655unsigned ARMMCCodeEmitter::
1656getT2AddrModeSORegOpValue(
const MCInst &
MI,
unsigned OpNum,
1657 SmallVectorImpl<MCFixup> &Fixups,
1658 const MCSubtargetInfo &STI)
const {
1659 const MCOperand &MO1 =
MI.getOperand(OpNum);
1660 const MCOperand &MO2 =
MI.getOperand(OpNum+1);
1661 const MCOperand &MO3 =
MI.getOperand(OpNum+2);
1674template<
unsigned Bits,
unsigned Shift>
1675unsigned ARMMCCodeEmitter::
1676getT2AddrModeImmOpValue(
const MCInst &
MI,
unsigned OpNum,
1677 SmallVectorImpl<MCFixup> &Fixups,
1678 const MCSubtargetInfo &STI)
const {
1679 const MCOperand &MO1 =
MI.getOperand(OpNum);
1680 const MCOperand &MO2 =
MI.getOperand(OpNum+1);
1688 int32_t tmp = (int32_t)MO2.
getImm();
1689 if (tmp == INT32_MIN) {
1691 }
else if (tmp < 0) {
1696 Value |= (tmp >> Shift) & ((1U << Bits) - 1);
1700unsigned ARMMCCodeEmitter::
1701getT2AddrModeImm8OffsetOpValue(
const MCInst &
MI,
unsigned OpNum,
1702 SmallVectorImpl<MCFixup> &Fixups,
1703 const MCSubtargetInfo &STI)
const {
1704 const MCOperand &MO1 =
MI.getOperand(OpNum);
1708 auto tmp =
static_cast<uint32_t
>(MO1.
getImm());
1709 if (
static_cast<int32_t
>(tmp) < 0)
1717unsigned ARMMCCodeEmitter::
1718getT2SORegOpValue(
const MCInst &
MI,
unsigned OpIdx,
1719 SmallVectorImpl<MCFixup> &Fixups,
1720 const MCSubtargetInfo &STI)
const {
1729 const MCOperand &MO =
MI.getOperand(
OpIdx);
1730 const MCOperand &MO1 =
MI.getOperand(
OpIdx + 1);
1760unsigned ARMMCCodeEmitter::
1761getBitfieldInvertedMaskOpValue(
const MCInst &
MI,
unsigned Op,
1762 SmallVectorImpl<MCFixup> &Fixups,
1763 const MCSubtargetInfo &STI)
const {
1766 const MCOperand &MO =
MI.getOperand(
Op);
1767 uint32_t
v = ~MO.getImm();
1770 assert(v != 0 && lsb < 32 && msb < 32 &&
"Illegal bitfield mask!");
1771 return lsb | (msb << 5);
1774unsigned ARMMCCodeEmitter::
1775getRegisterListOpValue(
const MCInst &
MI,
unsigned Op,
1776 SmallVectorImpl<MCFixup> &Fixups,
1777 const MCSubtargetInfo &STI)
const {
1784 MCRegister
Reg =
MI.getOperand(
Op).getReg();
1785 bool SPRRegs = ARMMCRegisterClasses[ARM::SPRRegClassID].contains(
Reg);
1786 bool DPRRegs = ARMMCRegisterClasses[ARM::DPRRegClassID].contains(
Reg);
1790 if (SPRRegs || DPRRegs ||
Reg == ARM::VPR) {
1793 unsigned NumRegs = (
MI.getNumOperands() -
Op) & 0xff;
1794 Binary |= (RegNo & 0x1f) << 8;
1796 if (
MI.getOpcode() == ARM::VSCCLRMD)
1799 else if (
MI.getOpcode() == ARM::VSCCLRMS) {
1804 for (
unsigned I =
Op,
E =
MI.getNumOperands();
I <
E; ++
I) {
1805 Reg =
MI.getOperand(
I).getReg();
1806 if (ARMMCRegisterClasses[ARM::SPRRegClassID].
contains(
Reg))
1808 else if (ARMMCRegisterClasses[ARM::DPRRegClassID].
contains(
Reg))
1819 [&](
const MCOperand &
LHS,
const MCOperand &
RHS) {
1820 return MRI.getEncodingValue(
LHS.getReg()) <
1821 MRI.getEncodingValue(
RHS.getReg());
1823 for (
unsigned I =
Op,
E =
MI.getNumOperands();
I <
E; ++
I) {
1824 unsigned RegNo =
MRI.getEncodingValue(
MI.getOperand(
I).getReg());
1834unsigned ARMMCCodeEmitter::
1835getAddrMode6AddressOpValue(
const MCInst &
MI,
unsigned Op,
1836 SmallVectorImpl<MCFixup> &Fixups,
1837 const MCSubtargetInfo &STI)
const {
1838 const MCOperand &
Reg =
MI.getOperand(
Op);
1839 const MCOperand &
Imm =
MI.getOperand(
Op + 1);
1844 switch (
Imm.getImm()) {
1848 case 8:
Align = 0x01;
break;
1849 case 16:
Align = 0x02;
break;
1850 case 32:
Align = 0x03;
break;
1853 return RegNo | (
Align << 4);
1858unsigned ARMMCCodeEmitter::
1859getAddrMode6OneLane32AddressOpValue(
const MCInst &
MI,
unsigned Op,
1860 SmallVectorImpl<MCFixup> &Fixups,
1861 const MCSubtargetInfo &STI)
const {
1862 const MCOperand &
Reg =
MI.getOperand(
Op);
1863 const MCOperand &
Imm =
MI.getOperand(
Op + 1);
1868 switch (
Imm.getImm()) {
1873 case 2:
Align = 0x00;
break;
1874 case 4:
Align = 0x03;
break;
1877 return RegNo | (
Align << 4);
1885unsigned ARMMCCodeEmitter::
1886getAddrMode6DupAddressOpValue(
const MCInst &
MI,
unsigned Op,
1887 SmallVectorImpl<MCFixup> &Fixups,
1888 const MCSubtargetInfo &STI)
const {
1889 const MCOperand &
Reg =
MI.getOperand(
Op);
1890 const MCOperand &
Imm =
MI.getOperand(
Op + 1);
1895 switch (
Imm.getImm()) {
1899 case 8:
Align = 0x01;
break;
1900 case 16:
Align = 0x03;
break;
1903 return RegNo | (
Align << 4);
1906unsigned ARMMCCodeEmitter::
1907getAddrMode6OffsetOpValue(
const MCInst &
MI,
unsigned Op,
1908 SmallVectorImpl<MCFixup> &Fixups,
1909 const MCSubtargetInfo &STI)
const {
1910 const MCOperand &MO =
MI.getOperand(
Op);
1916unsigned ARMMCCodeEmitter::
1917getShiftRight8Imm(
const MCInst &
MI,
unsigned Op,
1918 SmallVectorImpl<MCFixup> &Fixups,
1919 const MCSubtargetInfo &STI)
const {
1920 return 8 -
MI.getOperand(
Op).getImm();
1923unsigned ARMMCCodeEmitter::
1924getShiftRight16Imm(
const MCInst &
MI,
unsigned Op,
1925 SmallVectorImpl<MCFixup> &Fixups,
1926 const MCSubtargetInfo &STI)
const {
1927 return 16 -
MI.getOperand(
Op).getImm();
1930unsigned ARMMCCodeEmitter::
1931getShiftRight32Imm(
const MCInst &
MI,
unsigned Op,
1932 SmallVectorImpl<MCFixup> &Fixups,
1933 const MCSubtargetInfo &STI)
const {
1934 return 32 -
MI.getOperand(
Op).getImm();
1937unsigned ARMMCCodeEmitter::
1938getShiftRight64Imm(
const MCInst &
MI,
unsigned Op,
1939 SmallVectorImpl<MCFixup> &Fixups,
1940 const MCSubtargetInfo &STI)
const {
1941 return 64 -
MI.getOperand(
Op).getImm();
1944void ARMMCCodeEmitter::encodeInstruction(
const MCInst &
MI,
1945 SmallVectorImpl<char> &CB,
1946 SmallVectorImpl<MCFixup> &Fixups,
1947 const MCSubtargetInfo &STI)
const {
1949 const MCInstrDesc &
Desc = MCII.
get(
MI.getOpcode());
1950 uint64_t TSFlags =
Desc.TSFlags;
1955 if (
Desc.getSize() == 2 ||
Desc.getSize() == 4)
1962 uint32_t
Binary = getBinaryCodeForInstr(
MI, Fixups, STI);
1976template <
bool isNeg, ARM::Fixups fixup>
1978ARMMCCodeEmitter::getBFTargetOpValue(
const MCInst &
MI,
unsigned OpIdx,
1979 SmallVectorImpl<MCFixup> &Fixups,
1980 const MCSubtargetInfo &STI)
const {
1981 const MCOperand MO =
MI.getOperand(
OpIdx);
1983 return ::getBranchTargetOpValue(
MI,
OpIdx, fixup, Fixups, STI);
1988ARMMCCodeEmitter::getBFAfterTargetOpValue(
const MCInst &
MI,
unsigned OpIdx,
1989 SmallVectorImpl<MCFixup> &Fixups,
1990 const MCSubtargetInfo &STI)
const {
1991 const MCOperand MO =
MI.getOperand(
OpIdx);
1992 const MCOperand BranchMO =
MI.getOperand(0);
1999 addFixup(Fixups, 0, DiffExpr, Kind);
2005 assert(Diff == 4 || Diff == 2);
2010uint32_t ARMMCCodeEmitter::getVPTMaskOpValue(
const MCInst &
MI,
unsigned OpIdx,
2011 SmallVectorImpl<MCFixup> &Fixups,
2012 const MCSubtargetInfo &STI)
const {
2013 const MCOperand MO =
MI.getOperand(
OpIdx);
2021 unsigned PrevBit = 0;
2022 for (
int i = 3; i >= 0; --i) {
2026 if ((
Value & ~(~0U << i)) == 0) {
2041uint32_t ARMMCCodeEmitter::getRestrictedCondCodeOpValue(
2042 const MCInst &
MI,
unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups,
2043 const MCSubtargetInfo &STI)
const {
2045 const MCOperand MO =
MI.getOperand(
OpIdx);
2050 assert(0 &&
"Unexpected Condition!");
2069uint32_t ARMMCCodeEmitter::
2070getPowerTwoOpValue(
const MCInst &
MI,
unsigned OpIdx,
2071 SmallVectorImpl<MCFixup> &Fixups,
2072 const MCSubtargetInfo &STI)
const {
2073 const MCOperand &MO =
MI.getOperand(
OpIdx);
2078template <
unsigned start>
2079uint32_t ARMMCCodeEmitter::
2080getMVEPairVectorIndexOpValue(
const MCInst &
MI,
unsigned OpIdx,
2081 SmallVectorImpl<MCFixup> &Fixups,
2082 const MCSubtargetInfo &STI)
const {
2083 const MCOperand MO =
MI.getOperand(
OpIdx);
2087 return Value - start;
2090#include "ARMGenMCCodeEmitter.inc"
2094 return new ARMMCCodeEmitter(MCII, Ctx,
true);
2099 return new ARMMCCodeEmitter(MCII, Ctx,
false);
unsigned const MachineRegisterInfo * MRI
static void addFixup(SmallVectorImpl< MCFixup > &Fixups, uint32_t Offset, const MCExpr *Value, uint16_t Kind, bool PCRel=false)
assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")
This file declares a class to represent arbitrary precision floating point values and provide a varie...
This file implements a class to represent arbitrary precision integral constant values and operations...
static bool isThumb(const MCSubtargetInfo &STI)
static bool HasConditionalBranch(const MCInst &MI)
Return true if this branch has a non-always predication.
static void addFixup(SmallVectorImpl< MCFixup > &Fixups, uint32_t Offset, const MCExpr *Value, uint16_t Kind)
static int32_t encodeThumbBLOffset(int32_t offset)
static uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, unsigned FixupKind, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI)
getBranchTargetOpValue - Helper function to get the branch target operand, which is either an immedia...
Function Alias Analysis false
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
static bool isNeg(Value *V)
Returns true if the operation is a negation of V, and it works for both integers and floats.
static bool isReg(const MCInst &MI, unsigned OpNo)
MachineInstr unsigned OpIdx
static cl::opt< RegAllocEvictionAdvisorAnalysisLegacy::AdvisorMode > Mode("regalloc-enable-advisor", cl::Hidden, cl::init(RegAllocEvictionAdvisorAnalysisLegacy::AdvisorMode::Default), cl::desc("Enable regalloc advisor mode"), cl::values(clEnumValN(RegAllocEvictionAdvisorAnalysisLegacy::AdvisorMode::Default, "default", "Default"), clEnumValN(RegAllocEvictionAdvisorAnalysisLegacy::AdvisorMode::Release, "release", "precompiled"), clEnumValN(RegAllocEvictionAdvisorAnalysisLegacy::AdvisorMode::Development, "development", "for training")))
static bool contains(SmallPtrSetImpl< ConstantExpr * > &Cache, ConstantExpr *Expr, Constant *C)
This file defines the SmallVector class.
This file defines the 'Statistic' class, which is designed to be an easy way to expose various metric...
#define STATISTIC(VARNAME, DESC)
static const MCBinaryExpr * createSub(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
MCCodeEmitter - Generic instruction encoding interface.
Context object for machine code objects.
const MCRegisterInfo * getRegisterInfo() const
Base class for the full range of assembler expressions which are needed for parsing.
@ Specifier
Expression with a relocation specifier.
static MCFixup create(uint32_t Offset, const MCExpr *Value, MCFixupKind Kind, bool PCRel=false)
Consider bit fields if we need more flags.
Instances of this class represent a single low-level machine instruction.
Interface to description of machine instruction set.
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode.
Instances of this class represent operands of the MCInst class.
MCRegister getReg() const
Returns the register number.
const MCExpr * getExpr() const
uint64_t getDFPImm() const
uint16_t getEncodingValue(MCRegister Reg) const
Returns the encoding for Reg.
constexpr bool isValid() const
Generic base class for all target subtargets.
bool hasFeature(unsigned Feature) const
const Triple & getTargetTriple() const
constexpr unsigned id() const
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
LLVM Value Representation.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
constexpr char Align[]
Key for Kernel::Arg::Metadata::mAlign.
unsigned char getAM3Offset(unsigned AM3Opc)
unsigned getSORegOffset(unsigned Op)
int getSOImmVal(unsigned Arg)
getSOImmVal - Given a 32-bit immediate, if it is something that can fit into an shifter_operand immed...
ShiftOpc getAM2ShiftOpc(unsigned AM2Opc)
unsigned getAM2Offset(unsigned AM2Opc)
int getT2SOImmVal(unsigned Arg)
getT2SOImmVal - Given a 32-bit immediate, if it is something that can fit into a Thumb-2 shifter_oper...
ShiftOpc getSORegShOp(unsigned Op)
AddrOpc getAM5Op(unsigned AM5Opc)
unsigned char getAM5Offset(unsigned AM5Opc)
AddrOpc getAM2Op(unsigned AM2Opc)
AddrOpc getAM3Op(unsigned AM3Opc)
@ fixup_thumb_adr_pcrel_10
@ fixup_arm_thumb_upper_8_15
@ fixup_arm_thumb_lower_0_7
@ fixup_arm_pcrel_10_unscaled
@ fixup_arm_thumb_upper_0_7
@ fixup_bfcsel_else_target
@ fixup_arm_ldst_pcrel_12
@ fixup_arm_thumb_lower_8_15
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
void write(void *memory, value_type value, endianness endian)
Write a value to memory with a particular endianness.
This is an optimization pass for GlobalISel generic memory operations.
auto drop_begin(T &&RangeOrContainer, size_t N=1)
Return a range covering RangeOrContainer with the first N elements excluded.
FunctionAddr VTableAddr Value
decltype(auto) dyn_cast(const From &Val)
dyn_cast<X> - Return the argument parameter cast to the specified type.
APFloat abs(APFloat X)
Returns the absolute value of the argument.
MCCodeEmitter * createARMLEMCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx)
int countr_zero(T Val)
Count number of 0's from the least significant bit to the most stopping at the first 1.
unsigned M1(unsigned Val)
unsigned Log2_32(uint32_t Value)
Return the floor log base 2 of the specified value, -1 if the value is zero.
uint16_t MCFixupKind
Extensible enumeration to represent the type of a fixup.
MachineInstr * getImm(const MachineOperand &MO, const MachineRegisterInfo *MRI)
static Lanai::Fixups FixupKind(const MCExpr *Expr)
LLVM_ABI void report_fatal_error(Error Err, bool gen_crash_diag=true)
bool is_sorted(R &&Range, Compare C)
Wrapper function around std::is_sorted to check if elements in a range R are sorted with respect to a...
To bit_cast(const From &from) noexcept
DWARFExpression::Operation Op
unsigned M0(unsigned Val)
decltype(auto) cast(const From &Val)
cast<X> - Return the argument parameter cast to the specified type.
MCCodeEmitter * createARMBEMCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx)