Go to the source code of this file.
|
#define | DEBUG_TYPE "legalizevectorops" |
|
#define | DAG_INSTRUCTION(NAME, NARG, ROUND_MODE, INTRINSIC, DAGN) case ISD::STRICT_##DAGN: |
|
#define | BEGIN_REGISTER_VP_SDNODE(VPID, LEGALPOS, ...) |
|
#define | DAG_INSTRUCTION(NAME, NARG, ROUND_MODE, INTRINSIC, DAGN) case ISD::STRICT_##DAGN: |
|
◆ BEGIN_REGISTER_VP_SDNODE
#define BEGIN_REGISTER_VP_SDNODE |
( |
|
VPID, |
|
|
|
LEGALPOS, |
|
|
|
... |
|
) |
| |
Value: case ISD::VPID: { \
EVT LegalizeVT = LEGALPOS < 0 ? Node->getValueType(-(1 + LEGALPOS)) \
: Node->getOperand(LEGALPOS).getValueType(); \
if (ISD::VPID == ISD::VP_SETCC) {
\
ISD::CondCode CCCode = cast<CondCodeSDNode>(Node->getOperand(2))->get(); \
Action = TLI.getCondCodeAction(CCCode, LegalizeVT.getSimpleVT()); \
break; \
} \
Action = TLI.getOperationAction(Node->getOpcode(), LegalizeVT); \
} break;
◆ DAG_INSTRUCTION [1/2]
#define DAG_INSTRUCTION |
( |
|
NAME, |
|
|
|
NARG, |
|
|
|
ROUND_MODE, |
|
|
|
INTRINSIC, |
|
|
|
DAGN |
|
) |
| case ISD::STRICT_##DAGN: |
◆ DAG_INSTRUCTION [2/2]
#define DAG_INSTRUCTION |
( |
|
NAME, |
|
|
|
NARG, |
|
|
|
ROUND_MODE, |
|
|
|
INTRINSIC, |
|
|
|
DAGN |
|
) |
| case ISD::STRICT_##DAGN: |
◆ DEBUG_TYPE
#define DEBUG_TYPE "legalizevectorops" |
◆ createBSWAPShuffleMask()