LLVM 17.0.0git
LoongArchDisassembler.cpp
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1//===-- LoongArchDisassembler.cpp - Disassembler for LoongArch ------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements the LoongArchDisassembler class.
10//
11//===----------------------------------------------------------------------===//
12
16#include "llvm/MC/MCContext.h"
19#include "llvm/MC/MCInst.h"
20#include "llvm/MC/MCInstrInfo.h"
24#include "llvm/Support/Endian.h"
25
26using namespace llvm;
27
28#define DEBUG_TYPE "loongarch-disassembler"
29
31
32namespace {
33class LoongArchDisassembler : public MCDisassembler {
34public:
35 LoongArchDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx)
36 : MCDisassembler(STI, Ctx) {}
37
39 ArrayRef<uint8_t> Bytes, uint64_t Address,
40 raw_ostream &CStream) const override;
41};
42} // end namespace
43
45 const MCSubtargetInfo &STI,
46 MCContext &Ctx) {
47 return new LoongArchDisassembler(STI, Ctx);
48}
49
51 // Register the disassembler for each target.
56}
57
59 uint64_t Address,
60 const MCDisassembler *Decoder) {
61 if (RegNo >= 32)
63 Inst.addOperand(MCOperand::createReg(LoongArch::R0 + RegNo));
65}
66
68 uint64_t Address,
69 const MCDisassembler *Decoder) {
70 if (RegNo >= 32)
72 Inst.addOperand(MCOperand::createReg(LoongArch::F0 + RegNo));
74}
75
77 uint64_t Address,
78 const MCDisassembler *Decoder) {
79 if (RegNo >= 32)
81 Inst.addOperand(MCOperand::createReg(LoongArch::F0_64 + RegNo));
83}
84
86 uint64_t Address,
87 const MCDisassembler *Decoder) {
88 if (RegNo >= 8)
90 Inst.addOperand(MCOperand::createReg(LoongArch::FCC0 + RegNo));
92}
93
95 uint64_t Address,
96 const MCDisassembler *Decoder) {
97 if (RegNo >= 4)
99 Inst.addOperand(MCOperand::createReg(LoongArch::FCSR0 + RegNo));
101}
102
103template <unsigned N, int P = 0>
105 int64_t Address,
106 const MCDisassembler *Decoder) {
107 assert(isUInt<N>(Imm) && "Invalid immediate");
108 Inst.addOperand(MCOperand::createImm(Imm + P));
110}
111
112template <unsigned N, unsigned S = 0>
114 int64_t Address,
115 const MCDisassembler *Decoder) {
116 assert(isUInt<N>(Imm) && "Invalid immediate");
117 // Shift left Imm <S> bits, then sign-extend the number in the bottom <N+S>
118 // bits.
119 Inst.addOperand(MCOperand::createImm(SignExtend64<N + S>(Imm << S)));
121}
122
123#include "LoongArchGenDisassemblerTables.inc"
124
125DecodeStatus LoongArchDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
126 ArrayRef<uint8_t> Bytes,
127 uint64_t Address,
128 raw_ostream &CS) const {
131
132 // We want to read exactly 4 bytes of data because all LoongArch instructions
133 // are fixed 32 bits.
134 if (Bytes.size() < 4) {
135 Size = 0;
137 }
138
140 // Calling the auto-generated decoder function.
141 Result = decodeInstruction(DecoderTable32, MI, Insn, Address, this, STI);
142 Size = 4;
143
144 return Result;
145}
SmallVector< AArch64_IMM::ImmInsnModel, 4 > Insn
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:127
uint64_t Size
IRTranslator LLVM IR MI
MCDisassembler::DecodeStatus DecodeStatus
static DecodeStatus DecodeCFRRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm, int64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeLoongArchDisassembler()
static MCDisassembler * createLoongArchDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
static DecodeStatus decodeSImmOperand(MCInst &Inst, uint64_t Imm, int64_t Address, const MCDisassembler *Decoder)
static DecodeStatus DecodeFCSRRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
#define P(N)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:163
const T * data() const
Definition: ArrayRef.h:160
Context object for machine code objects.
Definition: MCContext.h:76
Superclass for all disassemblers.
DecodeStatus
Ternary decode status.
virtual DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address, raw_ostream &CStream) const =0
Returns the disassembly of a single instruction.
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
void addOperand(const MCOperand Op)
Definition: MCInst.h:210
static MCOperand createReg(unsigned Reg)
Definition: MCInst.h:134
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:141
Generic base class for all target subtargets.
Target - Wrapper for Target specific information.
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:52
uint32_t read32le(const void *P)
Definition: Endian.h:381
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
Target & getTheLoongArch64Target()
Target & getTheLoongArch32Target()
static void RegisterMCDisassembler(Target &T, Target::MCDisassemblerCtorTy Fn)
RegisterMCDisassembler - Register a MCDisassembler implementation for the given target.