LLVM  15.0.0git
LoongArchDisassembler.cpp
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1 //===-- LoongArchDisassembler.cpp - Disassembler for LoongArch ------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the LoongArchDisassembler class.
10 //
11 //===----------------------------------------------------------------------===//
12 
16 #include "llvm/MC/MCContext.h"
17 #include "llvm/MC/MCDecoderOps.h"
19 #include "llvm/MC/MCInst.h"
20 #include "llvm/MC/MCInstrInfo.h"
21 #include "llvm/MC/MCRegisterInfo.h"
23 #include "llvm/MC/TargetRegistry.h"
24 #include "llvm/Support/Endian.h"
25 
26 using namespace llvm;
27 
28 #define DEBUG_TYPE "loongarch-disassembler"
29 
31 
32 namespace {
33 class LoongArchDisassembler : public MCDisassembler {
34 public:
35  LoongArchDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx)
36  : MCDisassembler(STI, Ctx) {}
37 
38  DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
39  ArrayRef<uint8_t> Bytes, uint64_t Address,
40  raw_ostream &CStream) const override;
41 };
42 } // end anonymous namespace
43 
45  const MCSubtargetInfo &STI,
46  MCContext &Ctx) {
47  return new LoongArchDisassembler(STI, Ctx);
48 }
49 
51  // Register the disassembler for each target.
56 }
57 
59  uint64_t Address,
60  const MCDisassembler *Decoder) {
61  if (RegNo >= 32)
62  return MCDisassembler::Fail;
63  Inst.addOperand(MCOperand::createReg(LoongArch::R0 + RegNo));
65 }
66 
68  uint64_t Address,
69  const MCDisassembler *Decoder) {
70  if (RegNo >= 32)
71  return MCDisassembler::Fail;
72  Inst.addOperand(MCOperand::createReg(LoongArch::F0 + RegNo));
74 }
75 
77  uint64_t Address,
78  const MCDisassembler *Decoder) {
79  if (RegNo >= 32)
80  return MCDisassembler::Fail;
81  Inst.addOperand(MCOperand::createReg(LoongArch::F0_64 + RegNo));
83 }
84 
86  uint64_t Address,
87  const MCDisassembler *Decoder) {
88  if (RegNo >= 8)
89  return MCDisassembler::Fail;
90  Inst.addOperand(MCOperand::createReg(LoongArch::FCC0 + RegNo));
92 }
93 
95  uint64_t Address,
96  const MCDisassembler *Decoder) {
97  if (RegNo >= 4)
98  return MCDisassembler::Fail;
99  Inst.addOperand(MCOperand::createReg(LoongArch::FCSR0 + RegNo));
101 }
102 
103 template <unsigned N, int P = 0>
105  int64_t Address,
106  const MCDisassembler *Decoder) {
107  assert(isUInt<N>(Imm) && "Invalid immediate");
110 }
111 
112 template <unsigned N, unsigned S = 0>
114  int64_t Address,
115  const MCDisassembler *Decoder) {
116  assert(isUInt<N>(Imm) && "Invalid immediate");
117  // Sign-extend the number in the bottom <N> bits of Imm, then shift left <S>
118  // bits.
119  Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm) << S));
121 }
122 
123 #include "LoongArchGenDisassemblerTables.inc"
124 
125 DecodeStatus LoongArchDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
126  ArrayRef<uint8_t> Bytes,
127  uint64_t Address,
128  raw_ostream &CS) const {
129  uint32_t Insn;
131 
132  // We want to read exactly 4 bytes of data because all LoongArch instructions
133  // are fixed 32 bits.
134  if (Bytes.size() < 4) {
135  Size = 0;
136  return MCDisassembler::Fail;
137  }
138 
140  // Calling the auto-generated decoder function.
141  Result = decodeInstruction(DecoderTable32, MI, Insn, Address, this, STI);
142  Size = 4;
143 
144  return Result;
145 }
llvm::Check::Size
@ Size
Definition: FileCheck.h:77
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:105
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
MCDisassembler.h
llvm::getTheLoongArch32Target
Target & getTheLoongArch32Target()
Definition: LoongArchTargetInfo.cpp:13
T
llvm::MCOperand::createImm
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:141
llvm::MCContext
Context object for machine code objects.
Definition: MCContext.h:76
P
This currently compiles esp xmm0 movsd esp eax eax esp ret We should use not the dag combiner This is because dagcombine2 needs to be able to see through the X86ISD::Wrapper which DAGCombine can t really do The code for turning x load into a single vector load is target independent and should be moved to the dag combiner The code for turning x load into a vector load can only handle a direct load from a global or a direct load from the stack It should be generalized to handle any load from P
Definition: README-SSE.txt:411
llvm::Target
Target - Wrapper for Target specific information.
Definition: TargetRegistry.h:145
llvm::TargetRegistry::RegisterMCDisassembler
static void RegisterMCDisassembler(Target &T, Target::MCDisassemblerCtorTy Fn)
RegisterMCDisassembler - Register a MCDisassembler implementation for the given target.
Definition: TargetRegistry.h:951
DecodeGPRRegisterClass
static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: LoongArchDisassembler.cpp:58
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
MCDecoderOps.h
llvm::ArrayRef::data
const T * data() const
Definition: ArrayRef.h:161
DecodeStatus
MCDisassembler::DecodeStatus DecodeStatus
Definition: LoongArchDisassembler.cpp:30
MCContext.h
MCInstrInfo.h
llvm::ms_demangle::QualifierMangleMode::Result
@ Result
llvm::MCDisassembler::Success
@ Success
Definition: MCDisassembler.h:112
MCInst.h
MCSubtargetInfo.h
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:54
llvm::MCDisassembler::DecodeStatus
DecodeStatus
Ternary decode status.
Definition: MCDisassembler.h:109
llvm::MCInst::addOperand
void addOperand(const MCOperand Op)
Definition: MCInst.h:210
createLoongArchDisassembler
static MCDisassembler * createLoongArchDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
Definition: LoongArchDisassembler.cpp:44
DecodeFCSRRegisterClass
static DecodeStatus DecodeFCSRRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: LoongArchDisassembler.cpp:94
uint64_t
LLVM_EXTERNAL_VISIBILITY
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:126
llvm::MCDisassembler
Superclass for all disassemblers.
Definition: MCDisassembler.h:85
MCRegisterInfo.h
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
decodeSImmOperand
static DecodeStatus decodeSImmOperand(MCInst &Inst, uint64_t Imm, int64_t Address, const MCDisassembler *Decoder)
Definition: LoongArchDisassembler.cpp:113
llvm::ArrayRef< uint8_t >
llvm::MCOperand::createReg
static MCOperand createReg(unsigned Reg)
Definition: MCInst.h:134
uint32_t
S
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
Definition: README.txt:210
llvm::MCDisassembler::Fail
@ Fail
Definition: MCDisassembler.h:110
Insn
SmallVector< AArch64_IMM::ImmInsnModel, 4 > Insn
Definition: AArch64MIPeepholeOpt.cpp:127
LoongArchTargetInfo.h
LoongArchBaseInfo.h
LLVMInitializeLoongArchDisassembler
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeLoongArchDisassembler()
Definition: LoongArchDisassembler.cpp:50
llvm::RISCVMatInt::Imm
@ Imm
Definition: RISCVMatInt.h:23
LoongArchMCTargetDesc.h
llvm::support::endian::read32le
uint32_t read32le(const void *P)
Definition: Endian.h:381
DecodeCFRRegisterClass
static DecodeStatus DecodeCFRRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: LoongArchDisassembler.cpp:85
llvm::ArrayRef::size
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:164
decodeUImmOperand
static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm, int64_t Address, const MCDisassembler *Decoder)
Definition: LoongArchDisassembler.cpp:104
DecodeFPR32RegisterClass
static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: LoongArchDisassembler.cpp:67
Endian.h
TargetRegistry.h
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition: MCSubtargetInfo.h:76
llvm::getTheLoongArch64Target
Target & getTheLoongArch64Target()
Definition: LoongArchTargetInfo.cpp:18
DecodeFPR64RegisterClass
static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition: LoongArchDisassembler.cpp:76