LLVM
15.0.0git
lib
Target
Mips
Mips16RegisterInfo.h
Go to the documentation of this file.
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//===-- Mips16RegisterInfo.h - Mips16 Register Information ------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the Mips16 implementation of the TargetRegisterInfo class.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_MIPS_MIPS16REGISTERINFO_H
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#define LLVM_LIB_TARGET_MIPS_MIPS16REGISTERINFO_H
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#include "
MipsRegisterInfo.h
"
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namespace
llvm
{
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class
Mips16RegisterInfo
:
public
MipsRegisterInfo
{
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public
:
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Mips16RegisterInfo
();
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bool
requiresRegisterScavenging
(
const
MachineFunction
&MF)
const override
;
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bool
requiresFrameIndexScavenging
(
const
MachineFunction
&MF)
const override
;
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bool
useFPForScavengingIndex
(
const
MachineFunction
&MF)
const override
;
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bool
saveScavengerRegister
(
MachineBasicBlock
&
MBB
,
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MachineBasicBlock::iterator
I
,
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MachineBasicBlock::iterator
&
UseMI
,
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const
TargetRegisterClass
*RC,
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Register
Reg
)
const override
;
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const
TargetRegisterClass
*
intRegClass
(
unsigned
Size)
const override
;
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private
:
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void
eliminateFI(
MachineBasicBlock::iterator
II,
unsigned
OpNo,
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int
FrameIndex
,
uint64_t
StackSize,
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int64_t SPOffset)
const override
;
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};
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}
// end namespace llvm
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#endif
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition:
AddressRanges.h:17
UseMI
MachineInstrBuilder & UseMI
Definition:
AArch64ExpandPseudoInsts.cpp:103
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition:
X86DisassemblerDecoder.h:462
llvm::Mips16RegisterInfo::requiresFrameIndexScavenging
bool requiresFrameIndexScavenging(const MachineFunction &MF) const override
Definition:
Mips16RegisterInfo.cpp:47
llvm::TargetRegisterClass
Definition:
TargetRegisterInfo.h:45
llvm::Mips16RegisterInfo
Definition:
Mips16RegisterInfo.h:20
MipsRegisterInfo.h
llvm::Mips16RegisterInfo::useFPForScavengingIndex
bool useFPForScavengingIndex(const MachineFunction &MF) const override
Definition:
Mips16RegisterInfo.cpp:52
llvm::MachineBasicBlock
Definition:
MachineBasicBlock.h:94
uint64_t
I
#define I(x, y, z)
Definition:
MD5.cpp:58
llvm::MipsRegisterInfo
Definition:
MipsRegisterInfo.h:27
llvm::Mips16RegisterInfo::requiresRegisterScavenging
bool requiresRegisterScavenging(const MachineFunction &MF) const override
Definition:
Mips16RegisterInfo.cpp:43
llvm::MachineFunction
Definition:
MachineFunction.h:257
llvm::Mips16RegisterInfo::Mips16RegisterInfo
Mips16RegisterInfo()
llvm::Register
Wrapper class representing virtual and physical registers.
Definition:
Register.h:19
llvm::ISD::FrameIndex
@ FrameIndex
Definition:
ISDOpcodes.h:80
MBB
MachineBasicBlock & MBB
Definition:
AArch64SLSHardening.cpp:74
llvm::Mips16RegisterInfo::intRegClass
const TargetRegisterClass * intRegClass(unsigned Size) const override
Return GPR register class.
Definition:
Mips16RegisterInfo.cpp:68
llvm::Mips16RegisterInfo::saveScavengerRegister
bool saveScavengerRegister(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, MachineBasicBlock::iterator &UseMI, const TargetRegisterClass *RC, Register Reg) const override
Definition:
Mips16RegisterInfo.cpp:56
llvm::MachineInstrBundleIterator< MachineInstr >
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