LLVM 19.0.0git
Macros | Typedefs | Functions | Variables
MachineSink.cpp File Reference
#include "llvm/ADT/DenseSet.h"
#include "llvm/ADT/DepthFirstIterator.h"
#include "llvm/ADT/MapVector.h"
#include "llvm/ADT/PointerIntPair.h"
#include "llvm/ADT/PostOrderIterator.h"
#include "llvm/ADT/SetVector.h"
#include "llvm/ADT/SmallSet.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/Analysis/AliasAnalysis.h"
#include "llvm/Analysis/CFG.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineBlockFrequencyInfo.h"
#include "llvm/CodeGen/MachineBranchProbabilityInfo.h"
#include "llvm/CodeGen/MachineCycleAnalysis.h"
#include "llvm/CodeGen/MachineDominators.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineLoopInfo.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachinePostDominators.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/RegisterClassInfo.h"
#include "llvm/CodeGen/RegisterPressure.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/CodeGen/TargetPassConfig.h"
#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/IR/BasicBlock.h"
#include "llvm/IR/DebugInfoMetadata.h"
#include "llvm/IR/LLVMContext.h"
#include "llvm/InitializePasses.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/Pass.h"
#include "llvm/Support/BranchProbability.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
#include <algorithm>
#include <cassert>
#include <cstdint>
#include <utility>
#include <vector>

Go to the source code of this file.

Macros

#define DEBUG_TYPE   "machine-sink"
 

Typedefs

using MIRegs = std::pair< MachineInstr *, SmallVector< unsigned, 2 > >
 

Functions

 STATISTIC (NumSunk, "Number of machine instructions sunk")
 
 STATISTIC (NumCycleSunk, "Number of machine instructions sunk into a cycle")
 
 STATISTIC (NumSplit, "Number of critical edges split")
 
 STATISTIC (NumCoalesces, "Number of copies coalesced")
 
 STATISTIC (NumPostRACopySink, "Number of copies sunk after RA")
 
 INITIALIZE_PASS_BEGIN (MachineSinking, DEBUG_TYPE, "Machine code sinking", false, false) INITIALIZE_PASS_END(MachineSinking
 
Machine code static false bool blockPrologueInterferes (const MachineBasicBlock *BB, MachineBasicBlock::const_iterator End, const MachineInstr &MI, const TargetRegisterInfo *TRI, const TargetInstrInfo *TII, const MachineRegisterInfo *MRI)
 Return true if a target defined block prologue instruction interferes with a sink candidate.
 
static bool mayLoadFromGOTOrConstantPool (MachineInstr &MI)
 Return true if this machine instruction loads from global offset table or constant pool.
 
static bool SinkingPreventsImplicitNullCheck (MachineInstr &MI, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI)
 Return true if MI is likely to be usable as a memory operation by the implicit null check optimization.
 
static bool attemptDebugCopyProp (MachineInstr &SinkInst, MachineInstr &DbgMI, Register Reg)
 If the sunk instruction is a copy, try to forward the copy instead of leaving an 'undef' DBG_VALUE in the original location.
 
static void performSink (MachineInstr &MI, MachineBasicBlock &SuccToSinkTo, MachineBasicBlock::iterator InsertPos, ArrayRef< MIRegs > DbgValuesToSink)
 Sink an instruction and its associated debug instructions.
 
 INITIALIZE_PASS (PostRAMachineSinking, "postra-machine-sink", "PostRA Machine Sink", false, false) static bool aliasWithRegsInLiveIn(MachineBasicBlock &MBB
 
LiveInRegUnits addLiveIns (MBB)
 
return !LiveInRegUnits available (Reg)
 
static MachineBasicBlockgetSingleLiveInSuccBB (MachineBasicBlock &CurBB, const SmallPtrSetImpl< MachineBasicBlock * > &SinkableBBs, unsigned Reg, const TargetRegisterInfo *TRI)
 
static MachineBasicBlockgetSingleLiveInSuccBB (MachineBasicBlock &CurBB, const SmallPtrSetImpl< MachineBasicBlock * > &SinkableBBs, ArrayRef< unsigned > DefedRegsInCopy, const TargetRegisterInfo *TRI)
 
static void clearKillFlags (MachineInstr *MI, MachineBasicBlock &CurBB, SmallVectorImpl< unsigned > &UsedOpsInCopy, LiveRegUnits &UsedRegUnits, const TargetRegisterInfo *TRI)
 
static void updateLiveIn (MachineInstr *MI, MachineBasicBlock *SuccBB, SmallVectorImpl< unsigned > &UsedOpsInCopy, SmallVectorImpl< unsigned > &DefedRegsInCopy)
 
static bool hasRegisterDependency (MachineInstr *MI, SmallVectorImpl< unsigned > &UsedOpsInCopy, SmallVectorImpl< unsigned > &DefedRegsInCopy, LiveRegUnits &ModifiedRegUnits, LiveRegUnits &UsedRegUnits)
 

Variables

static cl::opt< boolSplitEdges ("machine-sink-split", cl::desc("Split critical edges during machine sinking"), cl::init(true), cl::Hidden)
 
static cl::opt< boolUseBlockFreqInfo ("machine-sink-bfi", cl::desc("Use block frequency info to find successors to sink"), cl::init(true), cl::Hidden)
 
static cl::opt< unsignedSplitEdgeProbabilityThreshold ("machine-sink-split-probability-threshold", cl::desc("Percentage threshold for splitting single-instruction critical edge. " "If the branch threshold is higher than this threshold, we allow " "speculative execution of up to 1 instruction to avoid branching to " "splitted critical edge"), cl::init(40), cl::Hidden)
 
static cl::opt< unsignedSinkLoadInstsPerBlockThreshold ("machine-sink-load-instrs-threshold", cl::desc("Do not try to find alias store for a load if there is a in-path " "block whose instruction number is higher than this threshold."), cl::init(2000), cl::Hidden)
 
static cl::opt< unsignedSinkLoadBlocksThreshold ("machine-sink-load-blocks-threshold", cl::desc("Do not try to find alias store for a load if the block number in " "the straight line is higher than this threshold."), cl::init(20), cl::Hidden)
 
static cl::opt< boolSinkInstsIntoCycle ("sink-insts-to-avoid-spills", cl::desc("Sink instructions into cycles to avoid " "register spills"), cl::init(false), cl::Hidden)
 
static cl::opt< unsignedSinkIntoCycleLimit ("machine-sink-cycle-limit", cl::desc("The maximum number of instructions considered for cycle sinking."), cl::init(50), cl::Hidden)
 
 DEBUG_TYPE
 
Machine code sinking
 
Machine code false
 
unsigned Reg
 
unsigned const TargetRegisterInfoTRI
 

Macro Definition Documentation

◆ DEBUG_TYPE

#define DEBUG_TYPE   "machine-sink"

Definition at line 65 of file MachineSink.cpp.

Typedef Documentation

◆ MIRegs

using MIRegs = std::pair<MachineInstr *, SmallVector<unsigned, 2> >

Definition at line 1382 of file MachineSink.cpp.

Function Documentation

◆ addLiveIns()

LiveInRegUnits addLiveIns ( MBB  )

◆ attemptDebugCopyProp()

static bool attemptDebugCopyProp ( MachineInstr SinkInst,
MachineInstr DbgMI,
Register  Reg 
)
static

If the sunk instruction is a copy, try to forward the copy instead of leaving an 'undef' DBG_VALUE in the original location.

Don't do this if there's any subregister weirdness involved. Returns true if copy propagation occurred.

Definition at line 1332 of file MachineSink.cpp.

References llvm::MachineInstr::getDebugOperandsForReg(), llvm::TargetSubtargetInfo::getInstrInfo(), llvm::MachineInstr::getMF(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), llvm::MachineOperand::getSubReg(), llvm::MachineFunction::getSubtarget(), llvm::Register::isVirtual(), MRI, Reg, and TII.

Referenced by performSink().

◆ available()

return !LiveInRegUnits available ( Reg  )

◆ blockPrologueInterferes()

Machine code static false bool blockPrologueInterferes ( const MachineBasicBlock BB,
MachineBasicBlock::const_iterator  End,
const MachineInstr MI,
const TargetRegisterInfo TRI,
const TargetInstrInfo TII,
const MachineRegisterInfo MRI 
)
static

Return true if a target defined block prologue instruction interferes with a sink candidate.

Definition at line 285 of file MachineSink.cpp.

References End, MI, MRI, Reg, TII, and TRI.

◆ clearKillFlags()

static void clearKillFlags ( MachineInstr MI,
MachineBasicBlock CurBB,
SmallVectorImpl< unsigned > &  UsedOpsInCopy,
LiveRegUnits UsedRegUnits,
const TargetRegisterInfo TRI 
)
static

◆ getSingleLiveInSuccBB() [1/2]

static MachineBasicBlock * getSingleLiveInSuccBB ( MachineBasicBlock CurBB,
const SmallPtrSetImpl< MachineBasicBlock * > &  SinkableBBs,
ArrayRef< unsigned DefedRegsInCopy,
const TargetRegisterInfo TRI 
)
static

Definition at line 1909 of file MachineSink.cpp.

References getSingleLiveInSuccBB(), and TRI.

◆ getSingleLiveInSuccBB() [2/2]

static MachineBasicBlock * getSingleLiveInSuccBB ( MachineBasicBlock CurBB,
const SmallPtrSetImpl< MachineBasicBlock * > &  SinkableBBs,
unsigned  Reg,
const TargetRegisterInfo TRI 
)
static

◆ hasRegisterDependency()

static bool hasRegisterDependency ( MachineInstr MI,
SmallVectorImpl< unsigned > &  UsedOpsInCopy,
SmallVectorImpl< unsigned > &  DefedRegsInCopy,
LiveRegUnits ModifiedRegUnits,
LiveRegUnits UsedRegUnits 
)
static

◆ INITIALIZE_PASS()

INITIALIZE_PASS ( PostRAMachineSinking  ,
"postra-machine-sink"  ,
"PostRA Machine Sink"  ,
false  ,
false   
) &

◆ INITIALIZE_PASS_BEGIN()

INITIALIZE_PASS_BEGIN ( MachineSinking  ,
DEBUG_TYPE  ,
"Machine code sinking"  ,
false  ,
false   
)

◆ mayLoadFromGOTOrConstantPool()

static bool mayLoadFromGOTOrConstantPool ( MachineInstr MI)
static

Return true if this machine instruction loads from global offset table or constant pool.

Definition at line 648 of file MachineSink.cpp.

References assert(), and MI.

◆ performSink()

static void performSink ( MachineInstr MI,
MachineBasicBlock SuccToSinkTo,
MachineBasicBlock::iterator  InsertPos,
ArrayRef< MIRegs DbgValuesToSink 
)
static

◆ SinkingPreventsImplicitNullCheck()

static bool SinkingPreventsImplicitNullCheck ( MachineInstr MI,
const TargetInstrInfo TII,
const TargetRegisterInfo TRI 
)
static

Return true if MI is likely to be usable as a memory operation by the implicit null check optimization.

This is a "best effort" heuristic, and should not be relied upon for correctness. This returning true does not guarantee that the implicit null check optimization is legal over MI, and this returning false does not guarantee MI cannot possibly be used to do a null check.

Definition at line 1287 of file MachineSink.cpp.

References llvm::MachineOperand::getReg(), llvm::MachineOperand::isReg(), MBB, MI, llvm::Offset, llvm::MachineBasicBlock::pred_begin(), llvm::MachineBasicBlock::pred_size(), TII, and TRI.

◆ STATISTIC() [1/5]

STATISTIC ( NumCoalesces  ,
"Number of copies coalesced"   
)

◆ STATISTIC() [2/5]

STATISTIC ( NumCycleSunk  ,
"Number of machine instructions sunk into a cycle"   
)

◆ STATISTIC() [3/5]

STATISTIC ( NumPostRACopySink  ,
"Number of copies sunk after RA"   
)

References MRI, TII, and TRI.

◆ STATISTIC() [4/5]

STATISTIC ( NumSplit  ,
"Number of critical edges split"   
)

◆ STATISTIC() [5/5]

STATISTIC ( NumSunk  ,
"Number of machine instructions sunk"   
)

◆ updateLiveIn()

static void updateLiveIn ( MachineInstr MI,
MachineBasicBlock SuccBB,
SmallVectorImpl< unsigned > &  UsedOpsInCopy,
SmallVectorImpl< unsigned > &  DefedRegsInCopy 
)
static

Variable Documentation

◆ DEBUG_TYPE

DEBUG_TYPE

Definition at line 280 of file MachineSink.cpp.

◆ false

Machine code false

Definition at line 281 of file MachineSink.cpp.

◆ Reg

unsigned Reg

Definition at line 1874 of file MachineSink.cpp.

Referenced by llvm::LiveRegUnits::accumulateUsedDefed(), llvm::X86MachineFunctionInfo::addCandidateForPush2Pop2(), llvm::addDirectMem(), llvm::Loc::EntryValue::addExpr(), llvm::MachineRegisterInfo::addLiveIn(), llvm::FunctionLoweringInfo::AddLiveOutRegInfo(), llvm::PPCFunctionInfo::addMustSaveCR(), llvm::LivePhysRegs::addReg(), llvm::LiveRegUnits::addReg(), llvm::MCInstBuilder::addReg(), llvm::M68k::addRegIndirectWithDisp(), llvm::LiveRegUnits::addRegMasked(), llvm::addRegOffset(), llvm::SIMachineFunctionInfo::addToPrologEpilogSGPRSpills(), llvm::RegPressureTracker::advance(), llvm::CCState::AllocateReg(), llvm::CCState::AllocateStack(), llvm::analyzeArguments(), llvm::analyzeReturnValues(), llvm::LiveRegSet::appendTo(), llvm::RegScavenger::assignRegToScavengingIndex(), attemptDebugCopyProp(), llvm::LiveRegUnits::available(), llvm::MIPatternMatch::bind_helper< const ConstantFP * >::bind(), llvm::MIPatternMatch::bind_helper< LLT >::bind(), llvm::MIPatternMatch::bind_helper< MachineInstr * >::bind(), blockPrologueInterferes(), llvm::buildBuiltinVariableLoad(), llvm::buildEnqueueKernel(), llvm::buildOpDecorate(), llvm::RegPressureTracker::bumpDeadDefs(), llvm::RegPressureTracker::bumpDownwardPressure(), llvm::RegPressureTracker::bumpUpwardPressure(), llvm::CC_CSKY_ABIV2_SOFT_64(), llvm::CC_M68k_Any_AssignToReg(), llvm::CC_SystemZ_I128Indirect(), llvm::SIMachineFunctionInfo::checkFlag(), llvm::jitlink::aarch32::checkRegister(), llvm::LivePhysRegs::contains(), llvm::MCRegisterClass::contains(), llvm::LiveRegSet::contains(), llvm::TargetRegisterClass::contains(), convertFPR32ToFPR64(), convertFPR64ToFPR16(), convertFPR64ToFPR32(), convertVRToVRMx(), llvm::LiveIntervals::createAndComputeVirtRegInterval(), llvm::LiveIntervals::createEmptyInterval(), llvm::AMDGPUTargetLowering::CreateLiveInRegister(), llvm::AMDGPUTargetLowering::CreateLiveInRegisterRaw(), llvm::MachineOperand::CreateReg(), llvm::MCOperand::createReg(), llvm::mca::MCAOperand::createReg(), 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llvm::getDRegFromBReg(), llvm::MipsFunctionInfo::getEhDataRegFI(), llvm::SIRegisterInfo::getHWRegIndex(), llvm::LiveIntervals::getInterval(), llvm::MipsFunctionInfo::getISRRegFI(), llvm::getLanaiRegisterNumbering(), llvm::FunctionLoweringInfo::GetLiveOutRegInfo(), llvm::getLiveRegMap(), LiveDebugValues::MLocTracker::getLocID(), llvm::TargetRegisterInfo::getMatchingSuperReg(), llvm::AMDGPU::getMCReg(), getNextRegister(), llvm::MachineRegisterInfo::getOneDef(), llvm::getOpcodeDef(), llvm::RAGreedy::ExtraRegInfo::getOrAssignNewCascade(), llvm::LiveIntervals::getOrCreateEmptyInterval(), llvm::RAGreedy::ExtraRegInfo::getOrInitStage(), llvm::SIMachineFunctionInfo::getPrologEpilogSGPRSaveRestoreInfo(), llvm::rdf::PhysicalRegisterInfo::getRefForUnit(), llvm::RegisterSDNode::getReg(), llvm::SystemZMC::getRegAsGR32(), llvm::SystemZMC::getRegAsGR64(), llvm::SystemZMC::getRegAsGRH32(), llvm::TargetRegisterInfo::getRegAsmName(), llvm::SystemZMC::getRegAsVR128(), llvm::MachineRegisterInfo::getRegBankOrNull(), llvm::MachineRegisterInfo::getRegClass(), llvm::MachineRegisterInfo::getRegClassOrNull(), llvm::MachineRegisterInfo::getRegClassOrRegBank(), llvm::SPIRV::ModuleAnalysisInfo::getRegisterAlias(), llvm::AVRTargetLowering::getRegisterByName(), llvm::AVRRegisterInfo::getReservedRegs(), llvm::SIMachineFunctionInfo::getScratchSGPRCopyDstReg(), llvm::X86::getSegmentOverridePrefixForReg(), getSingleLiveInSuccBB(), llvm::RAGreedy::ExtraRegInfo::getStage(), llvm::TargetRegisterInfo::getSubReg(), llvm::MachineRegisterInfo::getType(), llvm::MachineRegisterInfo::getVRegAttrs(), llvm::MachineRegisterInfo::getVRegName(), llvm::WebAssembly::getWARegStackId(), llvm::getWRegFromXReg(), llvm::getXRegFromWReg(), llvm::BitTracker::has(), llvm::MachineInstr::hasDebugOperandForReg(), llvm::MCInstrDesc::hasImplicitUseOfPhysReg(), llvm::LiveIntervals::hasInterval(), llvm::SIMachineFunctionInfo::hasPrologEpilogSGPRSpillEntry(), llvm::SPIRV::ModuleAnalysisInfo::hasRegisterAlias(), hasRegisterDependency(), llvm::TargetRegisterInfo::hasRegUnit(), insertNoDuplicates(), llvm::MachineRegisterInfo::insertVRegByName(), llvm::FunctionLoweringInfo::InvalidatePHILiveOutRegInfo(), llvm::CCState::isAllocated(), llvm::outliner::Candidate::isAnyUnavailableAcrossOrOutOfSeq(), llvm::isARMArea1Register(), llvm::isARMArea2Register(), llvm::isARMArea3Register(), llvm::isARMLowRegister(), llvm::outliner::Candidate::isAvailableAcrossAndOutOfSeq(), llvm::outliner::Candidate::isAvailableInsideSeq(), llvm::isCalleeSavedRegister(), llvm::X86MachineFunctionInfo::isCandidateForPush2Pop2(), llvm::rdf::TargetOperandInfo::isFixedReg(), llvm::AMDGPU::isHi(), llvm::SystemZ::isHighReg(), llvm::AllocationOrder::isHint(), llvm::AMDGPU::isInlineValue(), llvm::PhiLoweringHelper::isLaneMaskReg(), llvm::LiveVariables::isLiveIn(), llvm::PPCRegisterInfo::isNonallocatableRegisterCalleeSave(), llvm::AMDGPU::isSGPR(), llvm::PPCInstrInfo::isSignExtended(), llvm::isSplitFPArea1Register(), llvm::isSplitFPArea2Register(), llvm::SIRegisterInfo::isVectorRegister(), llvm::PPC::isVFRegister(), llvm::PPC::isVRRegister(), llvm::PPCInstrInfo::isZeroExtended(), llvm::MachineInstr::killsRegister(), llvm::BitTracker::lookup(), llvm::rdf::DataFlowGraph::makeRegRef(), llvm::yaml::MappingTraits< VirtualRegisterDefinition >::mapping(), llvm::MIPatternMatch::OneUse_match< SubPatternT >::match(), llvm::MIPatternMatch::OneNonDBGUse_match< SubPatternT >::match(), llvm::MIPatternMatch::ConstantMatch< ConstT >::match(), llvm::MIPatternMatch::ICstOrSplatMatch< ConstT >::match(), llvm::MIPatternMatch::GCstAndRegMatch::match(), llvm::MIPatternMatch::GFCstAndRegMatch::match(), llvm::MIPatternMatch::GFCstOrSplatGFCstMatch::match(), llvm::MIPatternMatch::SpecificConstantMatch::match(), llvm::MIPatternMatch::SpecificConstantSplatMatch::match(), llvm::MIPatternMatch::SpecificConstantOrSplatMatch::match(), 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llvm::MachineRegisterInfo::use_nodbg_operands(), llvm::MachineRegisterInfo::use_operands(), llvm::VirtRegAuxInfo::weightCalcHelper(), and llvm::jitlink::aarch32::writeRegister().

◆ sinking

Machine code sinking

Definition at line 281 of file MachineSink.cpp.

◆ SinkInstsIntoCycle

cl::opt< bool > SinkInstsIntoCycle("sink-insts-to-avoid-spills", cl::desc("Sink instructions into cycles to avoid " "register spills"), cl::init(false), cl::Hidden) ( "sink-insts-to-avoid-spills"  ,
cl::desc("Sink instructions into cycles to avoid " "register spills")  ,
cl::init(false)  ,
cl::Hidden   
)
static

◆ SinkIntoCycleLimit

cl::opt< unsigned > SinkIntoCycleLimit("machine-sink-cycle-limit", cl::desc("The maximum number of instructions considered for cycle sinking."), cl::init(50), cl::Hidden) ( "machine-sink-cycle-limit"  ,
cl::desc("The maximum number of instructions considered for cycle sinking.")  ,
cl::init(50)  ,
cl::Hidden   
)
static

◆ SinkLoadBlocksThreshold

cl::opt< unsigned > SinkLoadBlocksThreshold("machine-sink-load-blocks-threshold", cl::desc("Do not try to find alias store for a load if the block number in " "the straight line is higher than this threshold."), cl::init(20), cl::Hidden) ( "machine-sink-load-blocks-threshold"  ,
cl::desc("Do not try to find alias store for a load if the block number in " "the straight line is higher than this threshold.")  ,
cl::init(20)  ,
cl::Hidden   
)
static

◆ SinkLoadInstsPerBlockThreshold

cl::opt< unsigned > SinkLoadInstsPerBlockThreshold("machine-sink-load-instrs-threshold", cl::desc("Do not try to find alias store for a load if there is a in-path " "block whose instruction number is higher than this threshold."), cl::init(2000), cl::Hidden) ( "machine-sink-load-instrs-threshold"  ,
cl::desc("Do not try to find alias store for a load if there is a in-path " "block whose instruction number is higher than this threshold.")  ,
cl::init(2000)  ,
cl::Hidden   
)
static

◆ SplitEdgeProbabilityThreshold

cl::opt< unsigned > SplitEdgeProbabilityThreshold("machine-sink-split-probability-threshold", cl::desc( "Percentage threshold for splitting single-instruction critical edge. " "If the branch threshold is higher than this threshold, we allow " "speculative execution of up to 1 instruction to avoid branching to " "splitted critical edge"), cl::init(40), cl::Hidden) ( "machine-sink-split-probability-threshold"  ,
cl::desc( "Percentage threshold for splitting single-instruction critical edge. " "If the branch threshold is higher than this threshold, we allow " "speculative execution of up to 1 instruction to avoid branching to " "splitted critical edge")  ,
cl::init(40)  ,
cl::Hidden   
)
static

◆ SplitEdges

cl::opt< bool > SplitEdges("machine-sink-split", cl::desc("Split critical edges during machine sinking"), cl::init(true), cl::Hidden) ( "machine-sink-split"  ,
cl::desc("Split critical edges during machine sinking")  ,
cl::init(true ,
cl::Hidden   
)
static

◆ TRI

Initial value:
{
LiveRegUnits LiveInRegUnits(*TRI)
unsigned const TargetRegisterInfo * TRI
A set of register units used to track register liveness.
Definition: LiveRegUnits.h:30

Definition at line 1875 of file MachineSink.cpp.

Referenced by llvm::AArch64RegisterBankInfo::AArch64RegisterBankInfo(), llvm::AArch64Subtarget::AArch64Subtarget(), llvm::LiveRegUnits::accumulateUsedDefed(), llvm::DwarfCompileUnit::addAddress(), llvm::DwarfCompileUnit::addComplexAddress(), llvm::SIMachineFunctionInfo::addDispatchID(), llvm::SIMachineFunctionInfo::addDispatchPtr(), llvm::ARMBaseInstrInfo::AddDReg(), addExclusiveRegPair(), llvm::SIMachineFunctionInfo::addFlatScratchInit(), llvm::SITargetLowering::AddIMGInit(), llvm::SIMachineFunctionInfo::addImplicitBufferPtr(), llvm::SIMachineFunctionInfo::addKernargSegmentPtr(), llvm::addLiveIns(), llvm::DwarfExpression::addMachineReg(), llvm::DwarfExpression::addMachineRegExpression(), llvm::SIMachineFunctionInfo::addPreloadedKernArg(), llvm::SIMachineFunctionInfo::addPrivateSegmentBuffer(), llvm::SIMachineFunctionInfo::addQueuePtr(), llvm::LivePhysRegs::addReg(), llvm::LiveRegUnits::addReg(), addRegAndItsAliases(), llvm::LiveRegUnits::addRegMasked(), addRegsToSet(), addRegUnits(), llvm::PPCFrameLowering::addScavengingSpillSlot(), AddSubReg(), llvm::LiveVariables::addVirtualRegisterDead(), llvm::LiveVariables::addVirtualRegisterKilled(), AdjustBaseAndOffset(), llvm::SITargetLowering::AdjustInstrPostInstrSelection(), llvm::GCNSubtarget::adjustSchedDependency(), llvm::RegPressureTracker::advance(), llvm::SITargetLowering::allocateHSAUserSGPRs(), allocateHSAUserSGPRs(), llvm::SITargetLowering::allocatePreloadKernArgSGPRs(), llvm::SIMachineFunctionInfo::allocateVGPRSpillToAGPR(), llvm::LiveRangeEdit::allUsesAvailableAt(), llvm::X86InstrInfo::analyzeBranchPredicate(), analyzeCompressibleUses(), llvm::AArch64InstrInfo::analyzeLoopForPipelining(), llvm::AnalyzePhysRegInBundle(), llvm::AnalyzeVirtRegLanesInBundle(), AnyAliasLiveIn(), llvm::HexagonSubtarget::CallMutation::apply(), llvm::AMDGPUCallLowering::areCalleeOutgoingArgsTailCallable(), areCFlagsAccessedBetweenInstrs(), llvm::AArch64InstrInfo::areMemAccessesTriviallyDisjoint(), llvm::LanaiInstrInfo::areMemAccessesTriviallyDisjoint(), llvm::PPCInstrInfo::areMemAccessesTriviallyDisjoint(), llvm::RISCVInstrInfo::areMemAccessesTriviallyDisjoint(), llvm::ARMRegisterBankInfo::ARMRegisterBankInfo(), llvm::HexagonFrameLowering::assignCalleeSavedSpillSlots(), llvm::M68kFrameLowering::assignCalleeSavedSpillSlots(), llvm::PPCFrameLowering::assignCalleeSavedSpillSlots(), llvm::SystemZELFFrameLowering::assignCalleeSavedSpillSlots(), llvm::SystemZXPLINKFrameLowering::assignCalleeSavedSpillSlots(), llvm::TargetFrameLowering::assignCalleeSavedSpillSlots(), llvm::LiveRegUnits::available(), llvm::CodeViewDebug::beginFunctionImpl(), blockPrologueInterferes(), llvm::CriticalAntiDepBreaker::BreakAntiDependencies(), llvm::ARMBaseInstrInfo::breakPartialRegDependency(), llvm::X86InstrInfo::breakPartialRegDependency(), buildAnyextOrCopy(), buildCallOperands(), llvm::AArch64InstrInfo::buildClearRegister(), llvm::X86InstrInfo::buildClearRegister(), buildEpilogRestore(), buildGitPtr(), buildPrologSpill(), buildScratchExecCopy(), llvm::RegPressureTracker::bumpDownwardPressure(), llvm::RegPressureTracker::bumpUpwardPressure(), llvm::LiveIntervalCalc::calculate(), llvm::calculateDbgEntityHistory(), llvm::LiveRangeEdit::calculateRegClassAndHint(), canBeFeederToNewValueJump(), canClobberPhysRegDefs(), canClobberReachingPhysRegUse(), canCmpInstrBeRemoved(), canCompareBeNewValueJump(), canInstrSubstituteCmpInstr(), canRenameMOP(), canRenameUntilSecondLoad(), canRenameUpToDef(), llvm::AArch64FrameLowering::canUseAsPrologue(), CC_X86_64_VectorCall(), llvm::AArch64TargetLowering::changeStreamingMode(), checkAndUpdateCCRKill(), checkAndUpdateCPSRKill(), checkAndUpdateEFLAGSKill(), CheckForLiveRegDef(), CheckForPhysRegDependency(), llvm::SITargetLowering::checkForPhysRegDependency(), llvm::checkVOPDRegConstraints(), clearKillFlags(), llvm::CoalescerPair::CoalescerPair(), llvm::RegisterOperands::collect(), collectRegDefs(), computeCalleeSaveRegisterPairs(), llvm::HexagonBlockRanges::computeDeadMap(), computeIndirectRegAndOffset(), computeIndirectRegIndex(), llvm::computeLiveIns(), llvm::HexagonBlockRanges::computeLiveMap(), computeLiveOuts(), llvm::TargetSchedModel::computeOutputLatency(), llvm::MachineBasicBlock::computeRegisterLiveness(), llvm::TargetLoweringBase::computeRegisterProperties(), llvm::LiveInterval::computeSubRangeUndefs(), llvm::MachineInstrBuilder::constrainAllUses(), llvm::constrainOperandRegClass(), llvm::constrainSelectedInstRegOperands(), llvm::MIRPrinter::convert(), convertArgumentInfo(), llvm::MIRPrinter::convertCallSiteObjects(), llvm::MIRPrinter::convertEntryValueObjects(), llvm::MIRPrinter::convertStackObjects(), llvm::AArch64InstrInfo::copyGPRRegTuple(), llvm::VirtRegAuxInfo::copyHint(), llvm::AArch64InstrInfo::copyPhysReg(), llvm::ARMBaseInstrInfo::copyPhysReg(), llvm::PPCInstrInfo::copyPhysReg(), llvm::SparcInstrInfo::copyPhysReg(), llvm::VEInstrInfo::copyPhysReg(), llvm::RISCVInstrInfo::copyPhysReg(), llvm::AVRInstrInfo::copyPhysReg(), llvm::X86InstrInfo::copyPhysReg(), llvm::AArch64InstrInfo::copyPhysRegTuple(), llvm::RISCVInstrInfo::copyPhysRegVector(), copyPhysSubRegs(), llvm::AllocationOrder::create(), llvm::createBURRListDAGScheduler(), llvm::createCFAOffset(), llvm::createCopyConstrainDAGMutation(), llvm::createDefCFA(), createDefCFAExpression(), llvm::MipsFunctionInfo::createEhDataRegsFI(), llvm::XCoreFunctionInfo::createEHSpillSlot(), llvm::XCoreFunctionInfo::createFPSpillSlot(), llvm::createHybridListDAGScheduler(), llvm::createILPListDAGScheduler(), llvm::MipsFunctionInfo::createISRRegFI(), llvm::createLoadClusterDAGMutation(), llvm::XCoreFunctionInfo::createLRSpillSlot(), llvm::TargetInstrInfo::createMIROperandComment(), llvm::ARMBaseInstrInfo::createMIROperandComment(), llvm::RISCVInstrInfo::createMIROperandComment(), createPostIncLoadStore(), llvm::createSourceListDAGScheduler(), llvm::createStoreClusterDAGMutation(), createTuple(), llvm::RISCVTargetLowering::decomposeSubvectorInsertExtractToSubRegs(), llvm::MachineInstr::definesRegister(), llvm::TargetInstrInfo::describeLoadedValue(), llvm::AArch64InstrInfo::describeLoadedValue(), llvm::MipsInstrInfo::describeLoadedValue(), llvm::X86InstrInfo::describeLoadedValue(), describeMOVrrLoadedValue(), describeORRLoadedValue(), llvm::AArch64FrameLowering::determineCalleeSaves(), llvm::ARMFrameLowering::determineCalleeSaves(), llvm::CSKYFrameLowering::determineCalleeSaves(), llvm::MipsSEFrameLowering::determineCalleeSaves(), llvm::SystemZELFFrameLowering::determineCalleeSaves(), llvm::TargetFrameLowering::determineCalleeSaves(), llvm::SIFrameLowering::determineCalleeSaves(), llvm::SIFrameLowering::determineCalleeSavesSGPR(), llvm::SIFrameLowering::determinePrologEpilogSGPRSaves(), llvm::MachineRegisterInfo::disableCalleeSavedRegister(), llvm::AMDGPUCallLowering::doCallerAndCalleePassArgsTheSameWay(), doesModifyCalleeSavedReg(), llvm::PressureDiff::dump(), llvm::RegisterPressure::dump(), llvm::RegisterBank::dump(), llvm::SDep::dump(), dump_registers(), llvm::TargetRegisterInfo::dumpReg(), llvm::dumpRegSetPressure(), llvm::VERegisterInfo::eliminateFrameIndex(), emitAlignedDPRCS2Restores(), emitAlignedDPRCS2Spills(), emitCalleeSavedRestores(), llvm::SIFrameLowering::emitCSRSpillRestores(), llvm::SIFrameLowering::emitCSRSpillStores(), llvm::DwarfDebug::emitDebugLocValue(), emitDefineCFAWithFP(), llvm::PPCTargetLowering::emitEHSjLjSetJmp(), llvm::VETargetLowering::emitEHSjLjSetJmp(), llvm::SIFrameLowering::emitEntryFunctionPrologue(), llvm::SIFrameLowering::emitEpilogue(), emitFrameOffsetAdj(), emitIndirectDst(), emitIndirectSrc(), llvm::SITargetLowering::EmitInstrWithCustomInserter(), llvm::ARMTargetLowering::EmitInstrWithCustomInserter(), llvm::X86TargetLowering::EmitInstrWithCustomInserter(), emitLoadM0FromVGPRLoop(), emitLoadScalarOpsFromVGPRLoop(), llvm::AArch64FrameLowering::emitPrologue(), llvm::SIFrameLowering::emitPrologue(), llvm::CSKYFrameLowering::emitPrologue(), emitSCSPrologue(), emitVFROUND_NOEXCEPT_MASK(), estimateRSStackSizeLimit(), llvm::MipsFrameLowering::estimateStackSize(), llvm::examineCFlagsUse(), llvm::execMayBeModifiedBeforeAnyUse(), llvm::execMayBeModifiedBeforeUse(), llvm::GIMatchTableExecutor::executeMatchTable(), llvm::M68kInstrInfo::ExpandMOVSZX_RR(), llvm::M68kInstrInfo::ExpandMOVX_RR(), expandNOVLXLoad(), expandNOVLXStore(), llvm::AArch64InstrInfo::expandPostRAPseudo(), llvm::SIInstrInfo::expandPostRAPseudo(), llvm::ARMBaseInstrInfo::expandPostRAPseudo(), llvm::VEInstrInfo::expandPostRAPseudo(), llvm::X86InstrInfo::expandPostRAPseudo(), llvm::HexagonBlockRanges::expandToSubRegs(), expandXorFP(), llvm::finalizeBundle(), llvm::PPCInstrInfo::finalizeInsInstrs(), llvm::SITargetLowering::finalizeLowering(), FindAllMemoryUses(), llvm::findCMPToFoldIntoCBZ(), findDeadCallerSavedReg(), findHoistingInsertPosAndDeps(), findIncDecAfter(), findNextInsertLocation(), findRedundantFlagInstr(), llvm::MachineInstr::findRegisterDefOperand(), llvm::MachineInstr::findRegisterDefOperandIdx(), llvm::MachineInstr::findRegisterUseOperand(), llvm::MachineInstr::findRegisterUseOperandIdx(), findRenameRegForSameLdStRegPair(), llvm::TargetLoweringBase::findRepresentativeClass(), llvm::ARMTargetLowering::findRepresentativeClass(), llvm::X86TargetLowering::findRepresentativeClass(), findScratchNonCalleeSaveRegister(), findSurvivorBackwards(), findUseBetween(), findVCMPToFoldIntoVPST(), firstCommonClass(), llvm::TargetInstrInfo::foldMemoryOperand(), llvm::AArch64InstrInfo::foldMemoryOperandImpl(), llvm::SystemZInstrInfo::foldMemoryOperandImpl(), llvm::X86InstrInfo::foldMemoryOperandImpl(), foldVGPRCopyIntoRegSequence(), forAllMIsUntilDef(), foreachUnit(), llvm::MipsInstrInfo::genInstrWithNewOpc(), llvm::AArch64InstrInfo::getAddrModeFromMemoryOp(), llvm::MachineBasicBlock::getBeginClobberMask(), getBundledDefMI(), getBundledUseMI(), llvm::TargetFrameLowering::getCalleeSaves(), getCopyRegClasses(), getCorrespondingDRegAndLane(), GetCostForDef(), llvm::PPCInstrInfo::getDefMIPostRA(), GetDSubRegs(), getDwarfRegNum(), llvm::MachineBasicBlock::getEndClobberMask(), llvm::PPCInstrInfo::getFMAPatterns(), getImplicitSPRUseForDPRUse(), llvm::AArch64RegisterBankInfo::getInstrAlternativeMappings(), llvm::X86RegisterBankInfo::getInstrAlternativeMappings(), llvm::AArch64RegisterBankInfo::getInstrMapping(), llvm::PPCRegisterBankInfo::getInstrMapping(), llvm::RISCVRegisterBankInfo::getInstrMapping(), llvm::RegisterBankInfo::getInstrMappingImpl(), llvm::AVRRegisterInfo::getLargestLegalSuperClass(), llvm::RegisterClassInfo::getLastCalleeSavedAlias(), getMaskForArgs(), getMax32BitSubRegister(), getMaxCalleeSavedReg(), llvm::RegPressureTracker::getMaxUpwardPressureDelta(), getMemcpyLoadsAndStores(), getMemmoveLoadsAndStores(), llvm::SIInstrInfo::getMemOperandsWithOffsetWidth(), llvm::LanaiInstrInfo::getMemOperandsWithOffsetWidth(), llvm::PPCInstrInfo::getMemOperandsWithOffsetWidth(), llvm::AArch64InstrInfo::getMemOperandsWithOffsetWidth(), llvm::RISCVInstrInfo::getMemOperandsWithOffsetWidth(), llvm::TargetInstrInfo::getMemOperandWithOffset(), getMemsetStores(), llvm::RegisterBankInfo::getMinimalPhysRegClass(), llvm::MipsFunctionInfo::getMoveF64ViaSpillFI(), getOperandSize(), llvm::MipsTargetLowering::getOpndList(), llvm::ARMBaseInstrInfo::getOutliningCandidateInfo(), llvm::RISCVInstrInfo::getOutliningCandidateInfo(), llvm::RISCVInstrInfo::getOutliningTypeImpl(), llvm::ARMBaseInstrInfo::getOutliningTypeImpl(), llvm::ARMBaseInstrInfo::getPartialRegUpdateClearance(), llvm::X86InstrInfo::getPartialRegUpdateClearance(), llvm::MachineFrameInfo::getPristineRegs(), llvm::SystemZRegisterInfo::getRegAllocationHints(), llvm::RegisterBankInfo::getRegBank(), llvm::RegisterBankInfo::getRegBankFromConstraints(), llvm::TargetInstrInfo::getRegClass(), llvm::X86InstrInfo::getRegClass(), llvm::MachineInstr::getRegClassConstraint(), llvm::MachineInstr::getRegClassConstraintEffect(), llvm::MachineInstr::getRegClassConstraintEffectForVReg(), getRegClassesForCopy(), llvm::SITargetLowering::getRegClassFor(), llvm::SITargetLowering::getRegForInlineAsmConstraint(), llvm::ARMTargetLowering::getRegForInlineAsmConstraint(), llvm::BPFTargetLowering::getRegForInlineAsmConstraint(), llvm::HexagonTargetLowering::getRegForInlineAsmConstraint(), llvm::LanaiTargetLowering::getRegForInlineAsmConstraint(), llvm::M68kTargetLowering::getRegForInlineAsmConstraint(), llvm::MSP430TargetLowering::getRegForInlineAsmConstraint(), llvm::NVPTXTargetLowering::getRegForInlineAsmConstraint(), llvm::PPCTargetLowering::getRegForInlineAsmConstraint(), llvm::RISCVTargetLowering::getRegForInlineAsmConstraint(), llvm::SparcTargetLowering::getRegForInlineAsmConstraint(), llvm::SystemZTargetLowering::getRegForInlineAsmConstraint(), llvm::VETargetLowering::getRegForInlineAsmConstraint(), llvm::X86TargetLowering::getRegForInlineAsmConstraint(), llvm::SparcTargetLowering::getRegisterByName(), getRegisterName(), getRegistersForValue(), getRegisterSize(), getRegOpRC(), getRegTy(), llvm::WebAssemblyAsmPrinter::getRegType(), llvm::SIMachineFunctionInfo::getScavengeFI(), getSingleLiveInSuccBB(), llvm::RegisterBankInfo::getSizeInBits(), llvm::TargetInstrInfo::getStackSlotRange(), getSubRegForClass(), getTag(), llvm::VirtRegMap::getTargetRegInfo(), getVectorRegSpillRestoreOpcode(), getVectorRegSpillSaveOpcode(), getVGPRSpillLaneOrTempRegister(), llvm::LiveIntervals::handleMove(), llvm::LiveIntervals::handleMoveIntoNewBundle(), llvm::LoongArchFrameLowering::hasBP(), llvm::MipsFrameLowering::hasBP(), llvm::RISCVFrameLowering::hasBP(), llvm::VEFrameLowering::hasBP(), llvm::M68kFrameLowering::hasFP(), llvm::MipsFrameLowering::hasFP(), llvm::hash_value(), hasRAWHazard(), hasWriteToReadDep(), llvm::LiveIntervals::HMEditor::HMEditor(), hoistAndMergeSGPRInits(), llvm::GCNRegPressure::inc(), llvm::LiveRegSet::init(), llvm::LivePhysRegs::init(), llvm::LiveRegUnits::init(), INITIALIZE_PASS(), initLiveUnits(), llvm::VEInstrInfo::insertBranch(), llvm::AArch64TargetLowering::insertCopiesSplitCSR(), llvm::SITargetLowering::insertCopiesSplitCSR(), insertCSRRestores(), insertCSRSaves(), llvm::SIInstrInfo::insertIndirectBranch(), llvm::LoongArchInstrInfo::insertIndirectBranch(), llvm::RISCVInstrInfo::insertIndirectBranch(), llvm::X86InstrInfo::insertSelect(), InstReorderLimit(), llvm::rdf::CopyPropagation::interpretAsCopy(), interpretValues(), invalidateRegisterPairing(), invalidateWindowsRegisterPairing(), isACalleeSavedRegister(), isAGPRCopy(), isAnyArgRegReserved(), llvm::outliner::Candidate::isAnyUnavailableAcrossOrOutOfSeq(), llvm::X86RegisterInfo::isArgumentRegister(), llvm::outliner::Candidate::isAvailableAcrossAndOutOfSeq(), llvm::outliner::Candidate::isAvailableInsideSeq(), isCallerPreservedOrConstPhysReg(), llvm::AArch64InstrInfo::isCandidateToMergeOrPair(), llvm::CoalescerPair::isCoalescable(), llvm::MachineRegisterInfo::isConstantPhysReg(), isConvertibleToVMV_V_V(), isCopyFeedingInvariantStore(), IsCopyFromSGPR(), isCrossCopy(), llvm::isCycleInvariant(), isDefBetween(), isEFLAGSLive(), llvm::AMDGPUCallLowering::isEligibleForTailCallOptimization(), llvm::SITargetLowering::isEligibleForTailCallOptimization(), llvm::X86RegisterInfo::isFixedRegister(), llvm::MachineOperand::isIdenticalTo(), llvm::GCNTTIImpl::isInlineAsmSourceOfDivergence(), isInvariantStore(), isLdStSafeToCluster(), llvm::TargetLoweringBase::isLegalRC(), llvm::MachineLoop::isLoopInvariant(), isLRAvailable(), isNonFoldablePartialRegisterLoad(), isNopCopy(), llvm::isNZCVTouchedInInstructionRange(), llvm::isOfRegClass(), IsOperandAMemoryOperand(), llvm::MachineRegisterInfo::isPhysRegModified(), llvm::MachineRegisterInfo::isPhysRegUsed(), llvm::ARMBaseInstrInfo::isProfitableToIfCvt(), isRegOtherThanSPAndFP(), llvm::MachineRegisterInfo::isReservedRegUnit(), IsSafeAndProfitableToMove(), llvm::TargetInstrInfo::isSchedulingBoundary(), llvm::SITargetLowering::isSDNodeSourceOfDivergence(), llvm::AMDGPU::isSGPR(), isSGPRToVGPRCopy(), isSubRegOf(), isUnsafeToMoveAcross(), llvm::HexagonInstrInfo::isValidOffset(), isValidRegDefOf(), isValidRegUseOf(), isVGPRToSGPRCopy(), isVRegCompatibleReg(), llvm::MachineInstr::killsRegister(), llvm::AMDGPULegalizerInfo::legalizeIntrinsic(), llvm::MipsLegalizerInfo::legalizeIntrinsic(), llvm::LivePhysRegs::LivePhysRegs(), llvm::LiveRegUnits::LiveRegUnits(), loadM0FromVGPR(), loadMBUFScalarOperandsFromVGPR(), llvm::MipsSEInstrInfo::loadRegFromStack(), llvm::AArch64InstrInfo::loadRegFromStackSlot(), llvm::ARMBaseInstrInfo::loadRegFromStackSlot(), llvm::Thumb2InstrInfo::loadRegFromStackSlot(), llvm::MipsInstrInfo::loadRegFromStackSlot(), llvm::PPCInstrInfo::loadRegFromStackSlot(), llvm::LoongArchInstrInfo::loadRegFromStackSlot(), llvm::RISCVInstrInfo::loadRegFromStackSlot(), llvm::SIInstrInfo::loadRegFromStackSlot(), llvm::ARCInstrInfo::loadRegFromStackSlot(), llvm::AVRInstrInfo::loadRegFromStackSlot(), llvm::M68kInstrInfo::loadRegFromStackSlot(), llvm::X86InstrInfo::loadRegFromStackSlot(), loadRegPairFromStackSlot(), lookupCandidateBaseReg(), llvm::SITargetLowering::LowerCall(), llvm::SystemZTargetLowering::LowerCall(), llvm::AArch64CallLowering::lowerCall(), llvm::AMDGPUCallLowering::lowerCall(), llvm::ARMCallLowering::lowerCall(), llvm::M68kCallLowering::lowerCall(), llvm::MipsCallLowering::lowerCall(), llvm::RISCVCallLowering::lowerCall(), llvm::X86CallLowering::lowerCall(), llvm::LoongArchTargetLowering::LowerCall(), llvm::RISCVTargetLowering::LowerCall(), llvm::VETargetLowering::LowerCall(), llvm::SparcTargetLowering::LowerCall_32(), llvm::SparcTargetLowering::LowerCall_64(), llvm::TargetInstrInfo::lowerCopy(), llvm::PPCRegisterInfo::lowerCRBitSpilling(), llvm::AMDGPUCallLowering::lowerFormalArguments(), llvm::SITargetLowering::LowerFormalArguments(), llvm::AMDGPUCallLowering::lowerFormalArgumentsKernel(), llvm::InlineAsmLowering::lowerInlineAsm(), llvm::SITargetLowering::LowerReturn(), lowerRISCVVMachineInstrToMCInst(), llvm::AMDGPUCallLowering::lowerTailCall(), llvm::RISCVRegisterInfo::lowerVRELOAD(), llvm::RISCVRegisterInfo::lowerVSPILL(), lowerWaveReduce(), llvm::GenericUniformityAnalysisImpl< ContextT >::markDefsDivergent(), llvm::MipsRegInfoRecord::MipsRegInfoRecord(), llvm::MachineInstr::modifiesRegister(), onlyAllocateTileRegisters(), llvm::ARMBaseInstrInfo::optimizeCompareInstr(), llvm::LanaiInstrInfo::optimizeCompareInstr(), llvm::X86InstrInfo::optimizeCompareInstr(), llvm::PPCInstrInfo::optimizeCompareInstr(), llvm::TargetLowering::ParseConstraints(), llvm::SITargetLowering::passSpecialInputs(), patchMatchingInput(), performCopyPropagation(), llvm::X86InstrInfo::preservesZeroValueInReg(), llvm::print(), llvm::MIPrinter::print(), llvm::RegisterBankInfo::OperandsMapper::print(), llvm::RegisterBank::print(), llvm::PhysicalRegisterUsageInfo::print(), llvm::MachineFunction::print(), llvm::LiveIntervalUnion::print(), llvm::MachineOperand::print(), llvm::MachineInstr::print(), llvm::MachineBasicBlock::print(), llvm::HexagonAsmPrinter::PrintAsmOperand(), llvm::ARMAsmPrinter::PrintAsmOperand(), llvm::AVRAsmPrinter::PrintAsmOperand(), printCFI(), printCFIRegister(), printCustomRegMask(), PrintNodeInfo(), llvm::ARMAsmPrinter::printOperand(), llvm::printReg(), llvm::printRegClassOrBank(), printRegClassOrBank(), printRegMIR(), llvm::printRegUnit(), llvm::MipsAsmPrinter::printSavedRegsBitmask(), llvm::MachineOperand::printSubRegIdx(), llvm::printVRegOrUnit(), llvm::SIFrameLowering::processFunctionBeforeFrameFinalized(), llvm::PPCFrameLowering::processFunctionBeforeFrameFinalized(), llvm::XCoreFrameLowering::processFunctionBeforeFrameFinalized(), llvm::SIFrameLowering::processFunctionBeforeFrameIndicesReplaced(), llvm::PrologEpilogSGPRSpillBuilder::PrologEpilogSGPRSpillBuilder(), llvm::PSetIterator::PSetIterator(), llvm::MachineInstr::readsRegister(), llvm::TargetInstrInfo::reassociateOps(), llvm::RegPressureTracker::recede(), llvm::recomputeLivenessFlags(), reduceDbgValsForwardScan(), llvm::LiveInterval::refineSubRanges(), llvm::registerDefinedBetween(), llvm::MachineInstr::registerDefIsDead(), regToString(), llvm::TargetInstrInfo::reMaterialize(), llvm::ARMBaseInstrInfo::reMaterialize(), llvm::X86InstrInfo::reMaterialize(), llvm::LiveIntervals::removeAllRegUnitsForPhysReg(), llvm::LiveIntervals::removePhysRegDefAt(), llvm::LivePhysRegs::removeReg(), llvm::LiveRegUnits::removeReg(), llvm::LiveIntervals::repairIntervalsInRange(), replaceFrameIndex(), llvm::PPCInstrInfo::replaceInstrOperandWithImm(), llvm::MachineRegisterInfo::replaceRegWith(), llvm::reportMismatch(), llvm::R600InstrInfo::reserveIndirectRegisters(), reservePrivateMemoryRegs(), llvm::MachineRegisterInfo::reserveReg(), llvm::AArch64FrameLowering::resetCFIToInitialState(), llvm::SystemZELFFrameLowering::restoreCalleeSavedRegisters(), llvm::SystemZXPLINKFrameLowering::restoreCalleeSavedRegisters(), llvm::AArch64FrameLowering::restoreCalleeSavedRegisters(), llvm::ARMFrameLowering::restoreCalleeSavedRegisters(), llvm::AVRFrameLowering::restoreCalleeSavedRegisters(), llvm::CSKYFrameLowering::restoreCalleeSavedRegisters(), llvm::M68kFrameLowering::restoreCalleeSavedRegisters(), llvm::PPCFrameLowering::restoreCalleeSavedRegisters(), llvm::RISCVFrameLowering::restoreCalleeSavedRegisters(), llvm::XCoreFrameLowering::restoreCalleeSavedRegisters(), llvm::rewriteT2FrameIndex(), llvm::RISCVTargetLowering::RISCVTargetLowering(), llvm::rdf::CopyPropagation::run(), llvm::InstructionSelect::runOnMachineFunction(), llvm::SelectionDAGISel::runOnMachineFunction(), llvm::VirtRegMap::runOnMachineFunction(), llvm::GCNRegPressurePrinter::runOnMachineFunction(), llvm::MachineFunction::salvageCopySSAImpl(), scavengeFrameVirtualRegsInBlock(), scavengeVReg(), llvm::RISCVDAGToDAGISel::Select(), selectCopy(), selectMergeValues(), selectUnmergeValues(), llvm::FunctionLoweringInfo::set(), setAliasRegs(), llvm::ARMBaseInstrInfo::setExecutionDomain(), llvm::MachineInstr::setPhysRegsDeadExcept(), llvm::CoalescerPair::setRegisters(), llvm::MIRParserImpl::setupRegisterInfo(), shareSameRegisterFile(), llvm::SIMachineFunctionInfo::shiftSpillPhysVGPRsToLowestRange(), llvm::PPCInstrInfo::shouldClusterMemOps(), llvm::PPCInstrInfo::shouldReduceRegisterPressure(), shouldUseFrameHelper(), llvm::yaml::SIMachineFunctionInfo::SIMachineFunctionInfo(), SinkingPreventsImplicitNullCheck(), llvm::SITargetLowering::SITargetLowering(), llvm::SystemZELFFrameLowering::spillCalleeSavedRegisters(), llvm::SystemZXPLINKFrameLowering::spillCalleeSavedRegisters(), llvm::AArch64FrameLowering::spillCalleeSavedRegisters(), llvm::ARMFrameLowering::spillCalleeSavedRegisters(), llvm::AVRFrameLowering::spillCalleeSavedRegisters(), llvm::CSKYFrameLowering::spillCalleeSavedRegisters(), llvm::LoongArchFrameLowering::spillCalleeSavedRegisters(), llvm::M68kFrameLowering::spillCalleeSavedRegisters(), llvm::MipsSEFrameLowering::spillCalleeSavedRegisters(), llvm::PPCFrameLowering::spillCalleeSavedRegisters(), llvm::RISCVFrameLowering::spillCalleeSavedRegisters(), llvm::XCoreFrameLowering::spillCalleeSavedRegisters(), spillVGPRtoAGPR(), llvm::MachineBasicBlock::SplitCriticalEdge(), llvm::stableHashValue(), STATISTIC(), storeRegPairToStackSlot(), llvm::MipsSEInstrInfo::storeRegToStack(), llvm::AArch64InstrInfo::storeRegToStackSlot(), llvm::ARMBaseInstrInfo::storeRegToStackSlot(), llvm::Thumb2InstrInfo::storeRegToStackSlot(), llvm::LoongArchInstrInfo::storeRegToStackSlot(), llvm::MipsInstrInfo::storeRegToStackSlot(), llvm::PPCInstrInfo::storeRegToStackSlot(), llvm::RISCVInstrInfo::storeRegToStackSlot(), llvm::SIInstrInfo::storeRegToStackSlot(), llvm::ARCInstrInfo::storeRegToStackSlot(), llvm::AVRInstrInfo::storeRegToStackSlot(), llvm::M68kInstrInfo::storeRegToStackSlot(), llvm::X86InstrInfo::storeRegToStackSlot(), stripValuesNotDefiningMask(), llvm::MachineOperand::substPhysReg(), llvm::MachineOperand::substVirtReg(), TrackDefUses(), transferImplicitOperands(), tryChangeVGPRtoSGPRinCopy(), llvm::tryFoldSPUpdateIntoPushPop(), llvm::tryPressure(), tryToFindRegisterToRename(), tryToGetTargetInfo(), llvm::X86InstrInfo::unfoldMemoryOperand(), unsupportedBinOp(), llvm::LiveIntervals::HMEditor::updateAllRanges(), updateLiveIn(), UpdateOperandRegClass(), updateOperandRegConstraints(), updatePhysDepsDownwards(), updatePhysDepsUpwards(), UpdatePredRedefs(), llvm::RegisterBank::verify(), llvm::RegisterBankInfo::verify(), llvm::VirtRegAuxInfo::weightCalcHelper(), and llvm::X86RegisterBankInfo::X86RegisterBankInfo().

◆ UseBlockFreqInfo

cl::opt< bool > UseBlockFreqInfo("machine-sink-bfi", cl::desc("Use block frequency info to find successors to sink"), cl::init(true), cl::Hidden) ( "machine-sink-bfi"  ,
cl::desc("Use block frequency info to find successors to sink")  ,
cl::init(true ,
cl::Hidden   
)
static