LLVM  15.0.0git
Macros | Typedefs | Functions | Variables
MachineSink.cpp File Reference
#include "llvm/ADT/DenseSet.h"
#include "llvm/ADT/DepthFirstIterator.h"
#include "llvm/ADT/MapVector.h"
#include "llvm/ADT/PointerIntPair.h"
#include "llvm/ADT/PostOrderIterator.h"
#include "llvm/ADT/SetVector.h"
#include "llvm/ADT/SmallSet.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/Analysis/AliasAnalysis.h"
#include "llvm/Analysis/CFG.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineBlockFrequencyInfo.h"
#include "llvm/CodeGen/MachineBranchProbabilityInfo.h"
#include "llvm/CodeGen/MachineDominators.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineLoopInfo.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachinePostDominators.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/RegisterClassInfo.h"
#include "llvm/CodeGen/RegisterPressure.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/IR/BasicBlock.h"
#include "llvm/IR/DebugInfoMetadata.h"
#include "llvm/IR/LLVMContext.h"
#include "llvm/InitializePasses.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/Pass.h"
#include "llvm/Support/BranchProbability.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
#include <algorithm>
#include <cassert>
#include <cstdint>
#include <map>
#include <utility>
#include <vector>
Include dependency graph for MachineSink.cpp:

Go to the source code of this file.

Macros

#define DEBUG_TYPE   "machine-sink"
 

Typedefs

using MIRegs = std::pair< MachineInstr *, SmallVector< unsigned, 2 > >
 

Functions

 STATISTIC (NumSunk, "Number of machine instructions sunk")
 
 STATISTIC (NumLoopSunk, "Number of machine instructions sunk into a loop")
 
 STATISTIC (NumSplit, "Number of critical edges split")
 
 STATISTIC (NumCoalesces, "Number of copies coalesced")
 
 STATISTIC (NumPostRACopySink, "Number of copies sunk after RA")
 
 INITIALIZE_PASS_BEGIN (MachineSinking, DEBUG_TYPE, "Machine code sinking", false, false) INITIALIZE_PASS_END(MachineSinking
 
static bool mayLoadFromGOTOrConstantPool (MachineInstr &MI)
 Return true if this machine instruction loads from global offset table or constant pool. More...
 
static bool SinkingPreventsImplicitNullCheck (MachineInstr &MI, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI)
 Return true if MI is likely to be usable as a memory operation by the implicit null check optimization. More...
 
static bool attemptDebugCopyProp (MachineInstr &SinkInst, MachineInstr &DbgMI, Register Reg)
 If the sunk instruction is a copy, try to forward the copy instead of leaving an 'undef' DBG_VALUE in the original location. More...
 
static void performSink (MachineInstr &MI, MachineBasicBlock &SuccToSinkTo, MachineBasicBlock::iterator InsertPos, ArrayRef< MIRegs > DbgValuesToSink)
 Sink an instruction and its associated debug instructions. More...
 
static bool blockPrologueInterferes (MachineBasicBlock *BB, MachineBasicBlock::iterator End, MachineInstr &MI, const TargetRegisterInfo *TRI, const TargetInstrInfo *TII, const MachineRegisterInfo *MRI)
 Return true if a target defined block prologue instruction interferes with a sink candidate. More...
 
 INITIALIZE_PASS (PostRAMachineSinking, "postra-machine-sink", "PostRA Machine Sink", false, false) static bool aliasWithRegsInLiveIn(MachineBasicBlock &MBB
 
LiveInRegUnits addLiveIns (MBB)
 
return !LiveInRegUnits available (Reg)
 
static MachineBasicBlockgetSingleLiveInSuccBB (MachineBasicBlock &CurBB, const SmallPtrSetImpl< MachineBasicBlock * > &SinkableBBs, unsigned Reg, const TargetRegisterInfo *TRI)
 
static MachineBasicBlockgetSingleLiveInSuccBB (MachineBasicBlock &CurBB, const SmallPtrSetImpl< MachineBasicBlock * > &SinkableBBs, ArrayRef< unsigned > DefedRegsInCopy, const TargetRegisterInfo *TRI)
 
static void clearKillFlags (MachineInstr *MI, MachineBasicBlock &CurBB, SmallVectorImpl< unsigned > &UsedOpsInCopy, LiveRegUnits &UsedRegUnits, const TargetRegisterInfo *TRI)
 
static void updateLiveIn (MachineInstr *MI, MachineBasicBlock *SuccBB, SmallVectorImpl< unsigned > &UsedOpsInCopy, SmallVectorImpl< unsigned > &DefedRegsInCopy)
 
static bool hasRegisterDependency (MachineInstr *MI, SmallVectorImpl< unsigned > &UsedOpsInCopy, SmallVectorImpl< unsigned > &DefedRegsInCopy, LiveRegUnits &ModifiedRegUnits, LiveRegUnits &UsedRegUnits)
 

Variables

static cl::opt< bool > SplitEdges ("machine-sink-split", cl::desc("Split critical edges during machine sinking"), cl::init(true), cl::Hidden)
 
static cl::opt< bool > UseBlockFreqInfo ("machine-sink-bfi", cl::desc("Use block frequency info to find successors to sink"), cl::init(true), cl::Hidden)
 
static cl::opt< unsigned > SplitEdgeProbabilityThreshold ("machine-sink-split-probability-threshold", cl::desc("Percentage threshold for splitting single-instruction critical edge. " "If the branch threshold is higher than this threshold, we allow " "speculative execution of up to 1 instruction to avoid branching to " "splitted critical edge"), cl::init(40), cl::Hidden)
 
static cl::opt< unsigned > SinkLoadInstsPerBlockThreshold ("machine-sink-load-instrs-threshold", cl::desc("Do not try to find alias store for a load if there is a in-path " "block whose instruction number is higher than this threshold."), cl::init(2000), cl::Hidden)
 
static cl::opt< unsigned > SinkLoadBlocksThreshold ("machine-sink-load-blocks-threshold", cl::desc("Do not try to find alias store for a load if the block number in " "the straight line is higher than this threshold."), cl::init(20), cl::Hidden)
 
static cl::opt< bool > SinkInstsIntoLoop ("sink-insts-to-avoid-spills", cl::desc("Sink instructions into loops to avoid " "register spills"), cl::init(false), cl::Hidden)
 
static cl::opt< unsigned > SinkIntoLoopLimit ("machine-sink-loop-limit", cl::desc("The maximum number of instructions considered for loop sinking."), cl::init(50), cl::Hidden)
 
 DEBUG_TYPE
 
Machine code sinking
 
Machine code false
 
unsigned Reg
 
unsigned const TargetRegisterInfoTRI
 

Macro Definition Documentation

◆ DEBUG_TYPE

#define DEBUG_TYPE   "machine-sink"

Definition at line 64 of file MachineSink.cpp.

Typedef Documentation

◆ MIRegs

using MIRegs = std::pair<MachineInstr *, SmallVector<unsigned, 2> >

Definition at line 1092 of file MachineSink.cpp.

Function Documentation

◆ addLiveIns()

LiveInRegUnits addLiveIns ( MBB  )

◆ attemptDebugCopyProp()

static bool attemptDebugCopyProp ( MachineInstr SinkInst,
MachineInstr DbgMI,
Register  Reg 
)
static

If the sunk instruction is a copy, try to forward the copy instead of leaving an 'undef' DBG_VALUE in the original location.

Don't do this if there's any subregister weirdness involved. Returns true if copy propagation occurred.

Definition at line 1042 of file MachineSink.cpp.

References llvm::MachineInstr::getDebugOperandsForReg(), llvm::TargetSubtargetInfo::getInstrInfo(), llvm::MachineInstr::getMF(), llvm::MachineRegisterInfo::getNumVirtRegs(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), llvm::MachineOperand::getSubReg(), llvm::MachineFunction::getSubtarget(), llvm::Register::isVirtual(), MRI, Reg, and TII.

Referenced by performSink().

◆ available()

return !LiveInRegUnits available ( Reg  )

◆ blockPrologueInterferes()

static bool blockPrologueInterferes ( MachineBasicBlock BB,
MachineBasicBlock::iterator  End,
MachineInstr MI,
const TargetRegisterInfo TRI,
const TargetInstrInfo TII,
const MachineRegisterInfo MRI 
)
static

Return true if a target defined block prologue instruction interferes with a sink candidate.

Definition at line 1299 of file MachineSink.cpp.

◆ clearKillFlags()

static void clearKillFlags ( MachineInstr MI,
MachineBasicBlock CurBB,
SmallVectorImpl< unsigned > &  UsedOpsInCopy,
LiveRegUnits UsedRegUnits,
const TargetRegisterInfo TRI 
)
static

◆ getSingleLiveInSuccBB() [1/2]

static MachineBasicBlock* getSingleLiveInSuccBB ( MachineBasicBlock CurBB,
const SmallPtrSetImpl< MachineBasicBlock * > &  SinkableBBs,
ArrayRef< unsigned >  DefedRegsInCopy,
const TargetRegisterInfo TRI 
)
static

Definition at line 1652 of file MachineSink.cpp.

References BB, getSingleLiveInSuccBB(), and TRI.

◆ getSingleLiveInSuccBB() [2/2]

static MachineBasicBlock* getSingleLiveInSuccBB ( MachineBasicBlock CurBB,
const SmallPtrSetImpl< MachineBasicBlock * > &  SinkableBBs,
unsigned  Reg,
const TargetRegisterInfo TRI 
)
static

Definition at line 1625 of file MachineSink.cpp.

References BB, Reg, SI, llvm::MachineBasicBlock::successors(), and TRI.

Referenced by getSingleLiveInSuccBB().

◆ hasRegisterDependency()

static bool hasRegisterDependency ( MachineInstr MI,
SmallVectorImpl< unsigned > &  UsedOpsInCopy,
SmallVectorImpl< unsigned > &  DefedRegsInCopy,
LiveRegUnits ModifiedRegUnits,
LiveRegUnits UsedRegUnits 
)
static

◆ INITIALIZE_PASS()

INITIALIZE_PASS ( PostRAMachineSinking  ,
"postra-machine-sink ,
"PostRA Machine Sink"  ,
false  ,
false   
) &

◆ INITIALIZE_PASS_BEGIN()

INITIALIZE_PASS_BEGIN ( MachineSinking  ,
DEBUG_TYPE  ,
"Machine code sinking ,
false  ,
false   
)

◆ mayLoadFromGOTOrConstantPool()

static bool mayLoadFromGOTOrConstantPool ( MachineInstr MI)
static

Return true if this machine instruction loads from global offset table or constant pool.

Definition at line 365 of file MachineSink.cpp.

References assert(), and MI.

◆ performSink()

static void performSink ( MachineInstr MI,
MachineBasicBlock SuccToSinkTo,
MachineBasicBlock::iterator  InsertPos,
ArrayRef< MIRegs DbgValuesToSink 
)
static

◆ SinkingPreventsImplicitNullCheck()

static bool SinkingPreventsImplicitNullCheck ( MachineInstr MI,
const TargetInstrInfo TII,
const TargetRegisterInfo TRI 
)
static

Return true if MI is likely to be usable as a memory operation by the implicit null check optimization.

This is a "best effort" heuristic, and should not be relied upon for correctness. This returning true does not guarantee that the implicit null check optimization is legal over MI, and this returning false does not guarantee MI cannot possibly be used to do a null check.

Definition at line 997 of file MachineSink.cpp.

References llvm::MachineOperand::getReg(), llvm::MachineOperand::isReg(), MBB, MI, llvm::MachineBasicBlock::pred_begin(), llvm::PPC::PRED_EQ, llvm::PPC::PRED_NE, llvm::MachineBasicBlock::pred_size(), TII, and TRI.

◆ STATISTIC() [1/5]

STATISTIC ( NumCoalesces  ,
"Number of copies coalesced"   
)

◆ STATISTIC() [2/5]

STATISTIC ( NumLoopSunk  ,
"Number of machine instructions sunk into a loop  
)

◆ STATISTIC() [3/5]

STATISTIC ( NumPostRACopySink  ,
"Number of copies sunk after RA  
)

◆ STATISTIC() [4/5]

STATISTIC ( NumSplit  ,
"Number of critical edges split  
)

◆ STATISTIC() [5/5]

STATISTIC ( NumSunk  ,
"Number of machine instructions sunk"   
)

◆ updateLiveIn()

static void updateLiveIn ( MachineInstr MI,
MachineBasicBlock SuccBB,
SmallVectorImpl< unsigned > &  UsedOpsInCopy,
SmallVectorImpl< unsigned > &  DefedRegsInCopy 
)
static

Variable Documentation

◆ DEBUG_TYPE

DEBUG_TYPE

Definition at line 266 of file MachineSink.cpp.

◆ false

Machine code false

Definition at line 267 of file MachineSink.cpp.

◆ Reg

unsigned Reg

◆ sinking

Machine code sinking

Definition at line 267 of file MachineSink.cpp.

◆ SinkInstsIntoLoop

cl::opt<bool> SinkInstsIntoLoop("sink-insts-to-avoid-spills", cl::desc("Sink instructions into loops to avoid " "register spills"), cl::init(false), cl::Hidden)
static

◆ SinkIntoLoopLimit

cl::opt<unsigned> SinkIntoLoopLimit("machine-sink-loop-limit", cl::desc("The maximum number of instructions considered for loop sinking."), cl::init(50), cl::Hidden)
static

◆ SinkLoadBlocksThreshold

cl::opt<unsigned> SinkLoadBlocksThreshold("machine-sink-load-blocks-threshold", cl::desc("Do not try to find alias store for a load if the block number in " "the straight line is higher than this threshold."), cl::init(20), cl::Hidden)
static

◆ SinkLoadInstsPerBlockThreshold

cl::opt<unsigned> SinkLoadInstsPerBlockThreshold("machine-sink-load-instrs-threshold", cl::desc("Do not try to find alias store for a load if there is a in-path " "block whose instruction number is higher than this threshold."), cl::init(2000), cl::Hidden)
static

◆ SplitEdgeProbabilityThreshold

cl::opt<unsigned> SplitEdgeProbabilityThreshold("machine-sink-split-probability-threshold", cl::desc( "Percentage threshold for splitting single-instruction critical edge. " "If the branch threshold is higher than this threshold, we allow " "speculative execution of up to 1 instruction to avoid branching to " "splitted critical edge"), cl::init(40), cl::Hidden)
static

◆ SplitEdges

cl::opt<bool> SplitEdges("machine-sink-split", cl::desc("Split critical edges during machine sinking"), cl::init(true), cl::Hidden)
static

◆ TRI

unsigned const TargetRegisterInfo* TRI
Initial value:
{
LiveRegUnits LiveInRegUnits(*TRI)

Definition at line 1618 of file MachineSink.cpp.

Referenced by llvm::AArch64RegisterBankInfo::AArch64RegisterBankInfo(), llvm::LiveRegUnits::accumulateUsedDefed(), llvm::DwarfCompileUnit::addAddress(), llvm::DwarfCompileUnit::addComplexAddress(), llvm::SIMachineFunctionInfo::addDispatchID(), llvm::SIMachineFunctionInfo::addDispatchPtr(), llvm::ARMBaseInstrInfo::AddDReg(), addExclusiveRegPair(), llvm::SIMachineFunctionInfo::addFlatScratchInit(), llvm::SITargetLowering::AddIMGInit(), llvm::SIMachineFunctionInfo::addImplicitBufferPtr(), llvm::SIMachineFunctionInfo::addKernargSegmentPtr(), llvm::addLiveIns(), llvm::DwarfExpression::addMachineReg(), llvm::DwarfExpression::addMachineRegExpression(), llvm::SIMachineFunctionInfo::addPrivateSegmentBuffer(), llvm::SIMachineFunctionInfo::addQueuePtr(), llvm::LivePhysRegs::addReg(), llvm::LiveRegUnits::addReg(), addRegAndItsAliases(), llvm::LiveRegUnits::addRegMasked(), addRegsToSet(), addRegUnits(), llvm::PPCFrameLowering::addScavengingSpillSlot(), AddSubReg(), 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llvm::MachineInstr::getRegClassConstraintEffect(), llvm::MachineInstr::getRegClassConstraintEffectForVReg(), getRegClassesForCopy(), llvm::SITargetLowering::getRegClassFor(), llvm::BPFTargetLowering::getRegForInlineAsmConstraint(), llvm::SparcTargetLowering::getRegForInlineAsmConstraint(), llvm::LanaiTargetLowering::getRegForInlineAsmConstraint(), llvm::MSP430TargetLowering::getRegForInlineAsmConstraint(), llvm::M68kTargetLowering::getRegForInlineAsmConstraint(), llvm::VETargetLowering::getRegForInlineAsmConstraint(), llvm::HexagonTargetLowering::getRegForInlineAsmConstraint(), llvm::RISCVTargetLowering::getRegForInlineAsmConstraint(), llvm::SITargetLowering::getRegForInlineAsmConstraint(), llvm::SystemZTargetLowering::getRegForInlineAsmConstraint(), llvm::NVPTXTargetLowering::getRegForInlineAsmConstraint(), llvm::ARMTargetLowering::getRegForInlineAsmConstraint(), llvm::PPCTargetLowering::getRegForInlineAsmConstraint(), llvm::X86TargetLowering::getRegForInlineAsmConstraint(), getRegisterName(), getRegistersForValue(), getRegisterSize(), llvm::RegScavenger::getRegsAvailable(), getRegTy(), llvm::WebAssemblyAsmPrinter::getRegType(), llvm::SIMachineFunctionInfo::getScavengeFI(), getSingleLiveInSuccBB(), llvm::RegisterBankInfo::getSizeInBits(), llvm::TargetInstrInfo::getStackSlotRange(), getSubRegForClass(), getTag(), llvm::VirtRegMap::getTargetRegInfo(), getVGPRSpillLaneOrTempRegister(), llvm::LiveIntervals::handleMove(), llvm::LiveIntervals::handleMoveIntoNewBundle(), llvm::LoongArchFrameLowering::hasBP(), llvm::MipsFrameLowering::hasBP(), llvm::VEFrameLowering::hasBP(), llvm::RISCVFrameLowering::hasBP(), llvm::MipsFrameLowering::hasFP(), llvm::M68kFrameLowering::hasFP(), hasRAWHazard(), hasVectorOperands(), hasWriteToReadDep(), llvm::LiveIntervals::HMEditor::HMEditor(), hoistAndMergeSGPRInits(), llvm::LivePhysRegs::init(), llvm::LiveRegUnits::init(), llvm::LiveRegSet::init(), INITIALIZE_PASS(), initLiveRegs(), llvm::VEInstrInfo::insertBranch(), insertCSRRestores(), insertCSRSaves(), llvm::SIInstrInfo::insertIndirectBranch(), llvm::X86InstrInfo::insertSelect(), llvm::rdf::CopyPropagation::interpretAsCopy(), interpretValues(), isACalleeSavedRegister(), llvm::outliner::Candidate::isAnyUnavailableAcrossOrOutOfSeq(), llvm::X86RegisterInfo::isArgumentRegister(), llvm::outliner::Candidate::isAvailableAcrossAndOutOfSeq(), llvm::outliner::Candidate::isAvailableInsideSeq(), isCallerPreservedOrConstPhysReg(), llvm::AArch64InstrInfo::isCandidateToMergeOrPair(), llvm::CoalescerPair::isCoalescable(), llvm::MachineRegisterInfo::isConstantPhysReg(), isConvertibleToVMV_V_V(), isCopyFeedingInvariantStore(), IsCopyFromSGPR(), isCrossCopy(), isDefBetween(), isEFLAGSLive(), llvm::AMDGPUCallLowering::isEligibleForTailCallOptimization(), llvm::SITargetLowering::isEligibleForTailCallOptimization(), TransferTracker::isEntryValueValue(), llvm::X86RegisterInfo::isFixedRegister(), llvm::MachineOperand::isIdenticalTo(), llvm::GCNTTIImpl::isInlineAsmSourceOfDivergence(), isInvariantStore(), isLdStSafeToCluster(), llvm::TargetLoweringBase::isLegalRC(), llvm::MachineLoop::isLoopInvariant(), isLRAvailable(), isNonFoldablePartialRegisterLoad(), isNopCopy(), llvm::isNZCVTouchedInInstructionRange(), llvm::isOfRegClass(), IsOperandAMemoryOperand(), llvm::MachineRegisterInfo::isPhysRegModified(), llvm::MachineRegisterInfo::isPhysRegUsed(), llvm::ARMBaseInstrInfo::isProfitableToIfCvt(), isRegOtherThanSPAndFP(), llvm::MachineRegisterInfo::isReservedRegUnit(), IsSafeAndProfitableToMove(), llvm::TargetInstrInfo::isSchedulingBoundary(), llvm::SITargetLowering::isSDNodeSourceOfDivergence(), llvm::AMDGPU::isSGPR(), isSGPRToVGPRCopy(), isSubRegOf(), isUnsafeToMoveAcross(), llvm::HexagonInstrInfo::isValidOffset(), isValidRegDefOf(), isValidRegUseOf(), AMDGPURegBankCombinerHelper::isVgprRegBank(), isVGPRToSGPRCopy(), isVRegCompatibleReg(), llvm::MachineInstr::killsRegister(), llvm::MipsLegalizerInfo::legalizeIntrinsic(), llvm::AMDGPULegalizerInfo::legalizeIntrinsic(), llvm::LivePhysRegs::LivePhysRegs(), llvm::LiveRegUnits::LiveRegUnits(), TransferTracker::loadInlocs(), loadM0FromVGPR(), llvm::MipsSEInstrInfo::loadRegFromStack(), llvm::Thumb2InstrInfo::loadRegFromStackSlot(), llvm::RISCVInstrInfo::loadRegFromStackSlot(), llvm::ARCInstrInfo::loadRegFromStackSlot(), llvm::AVRInstrInfo::loadRegFromStackSlot(), llvm::MipsInstrInfo::loadRegFromStackSlot(), llvm::AArch64InstrInfo::loadRegFromStackSlot(), llvm::ARMBaseInstrInfo::loadRegFromStackSlot(), llvm::SIInstrInfo::loadRegFromStackSlot(), llvm::M68kInstrInfo::loadRegFromStackSlot(), llvm::X86InstrInfo::loadRegFromStackSlot(), llvm::PPCInstrInfo::loadRegFromStackSlot(), loadRegPairFromStackSlot(), lookupCandidateBaseReg(), llvm::MipsCallLowering::lowerCall(), llvm::X86CallLowering::lowerCall(), llvm::M68kCallLowering::lowerCall(), llvm::ARMCallLowering::lowerCall(), llvm::AArch64CallLowering::lowerCall(), llvm::AMDGPUCallLowering::lowerCall(), llvm::VETargetLowering::LowerCall(), llvm::SITargetLowering::LowerCall(), llvm::RISCVTargetLowering::LowerCall(), llvm::SystemZTargetLowering::LowerCall(), llvm::SparcTargetLowering::LowerCall_32(), llvm::SparcTargetLowering::LowerCall_64(), llvm::FastISel::lowerCallTo(), llvm::PPCRegisterInfo::lowerCRBitSpilling(), llvm::AMDGPUCallLowering::lowerFormalArguments(), llvm::SITargetLowering::LowerFormalArguments(), llvm::AMDGPUCallLowering::lowerFormalArgumentsKernel(), llvm::InlineAsmLowering::lowerInlineAsm(), llvm::SITargetLowering::LowerReturn(), lowerRISCVVMachineInstrToMCInst(), llvm::AMDGPUCallLowering::lowerTailCall(), llvm::MipsRegInfoRecord::MipsRegInfoRecord(), llvm::MachineInstr::modifiesRegister(), llvm::rdf::operator<<(), llvm::LanaiInstrInfo::optimizeCompareInstr(), llvm::ARMBaseInstrInfo::optimizeCompareInstr(), llvm::X86InstrInfo::optimizeCompareInstr(), llvm::PPCInstrInfo::optimizeCompareInstr(), optimizeVCMPSaveExecSequence(), llvm::TargetLowering::ParseConstraints(), llvm::SITargetLowering::passSpecialInputs(), patchMatchingInput(), performCopyPropagation(), llvm::X86InstrInfo::preservesZeroValueInReg(), llvm::PhysicalRegisterUsageInfo::print(), llvm::RegisterBank::print(), llvm::LiveIntervalUnion::print(), llvm::MIPrinter::print(), llvm::MachineOperand::print(), llvm::RegisterBankInfo::OperandsMapper::print(), llvm::MachineFunction::print(), llvm::MachineBasicBlock::print(), llvm::MachineInstr::print(), llvm::AVRAsmPrinter::PrintAsmOperand(), llvm::HexagonAsmPrinter::PrintAsmOperand(), llvm::ARMAsmPrinter::PrintAsmOperand(), printCFI(), printCFIRegister(), printCustomRegMask(), llvm::GCNRPTracker::printLiveRegs(), PrintNodeInfo(), llvm::ARMAsmPrinter::printOperand(), llvm::printReg(), llvm::printRegClassOrBank(), printRegClassOrBank(), printRegMIR(), llvm::printRegUnit(), llvm::MipsAsmPrinter::printSavedRegsBitmask(), llvm::MachineOperand::printSubRegIdx(), llvm::printVRegOrUnit(), llvm::RISCVFrameLowering::processFunctionBeforeFrameFinalized(), llvm::SIFrameLowering::processFunctionBeforeFrameFinalized(), llvm::XCoreFrameLowering::processFunctionBeforeFrameFinalized(), llvm::PPCFrameLowering::processFunctionBeforeFrameFinalized(), llvm::SIFrameLowering::processFunctionBeforeFrameIndicesReplaced(), llvm::PSetIterator::PSetIterator(), llvm::MachineInstr::readsRegister(), llvm::TargetInstrInfo::reassociateOps(), llvm::RegPressureTracker::recede(), llvm::recomputeLivenessFlags(), reduceDbgValsForwardScan(), llvm::LiveInterval::refineSubRanges(), llvm::registerDefinedBetween(), llvm::MachineInstr::registerDefIsDead(), regOverlapsSet(), regsAreCompatible(), regToString(), llvm::ARMBaseInstrInfo::reMaterialize(), llvm::X86InstrInfo::reMaterialize(), llvm::TargetInstrInfo::reMaterialize(), rematerializeCheapDef(), llvm::LiveIntervals::removeAllRegUnitsForPhysReg(), removeMapRegEntry(), llvm::LiveIntervals::removePhysRegDefAt(), llvm::LivePhysRegs::removeReg(), llvm::LiveRegUnits::removeReg(), llvm::RegBankSelect::RepairingPlacement::RepairingPlacement(), replaceFrameIndex(), llvm::PPCInstrInfo::replaceInstrOperandWithImm(), llvm::MachineRegisterInfo::replaceRegWith(), reportMismatch(), reservePrivateMemoryRegs(), llvm::AArch64FrameLowering::resetCFIToInitialState(), llvm::AVRFrameLowering::restoreCalleeSavedRegisters(), llvm::ARMFrameLowering::restoreCalleeSavedRegisters(), llvm::XCoreFrameLowering::restoreCalleeSavedRegisters(), llvm::RISCVFrameLowering::restoreCalleeSavedRegisters(), llvm::CSKYFrameLowering::restoreCalleeSavedRegisters(), llvm::AArch64FrameLowering::restoreCalleeSavedRegisters(), llvm::SystemZELFFrameLowering::restoreCalleeSavedRegisters(), llvm::M68kFrameLowering::restoreCalleeSavedRegisters(), llvm::SystemZXPLINKFrameLowering::restoreCalleeSavedRegisters(), llvm::PPCFrameLowering::restoreCalleeSavedRegisters(), llvm::rewriteT2FrameIndex(), llvm::RISCVTargetLowering::RISCVTargetLowering(), llvm::rdf::CopyPropagation::run(), llvm::InstructionSelect::runOnMachineFunction(), llvm::SelectionDAGISel::runOnMachineFunction(), llvm::VirtRegMap::runOnMachineFunction(), llvm::MachineFunction::salvageCopySSAImpl(), scavengeFrameVirtualRegsInBlock(), llvm::RegScavenger::scavengeRegister(), llvm::RegScavenger::scavengeRegisterBackwards(), scavengeVReg(), selectCopy(), selectMergeValues(), llvm::FastISel::selectPatchpoint(), selectUnmergeValues(), llvm::FunctionLoweringInfo::set(), setAliasRegs(), llvm::ARMBaseInstrInfo::setExecutionDomain(), llvm::MachineInstr::setPhysRegsDeadExcept(), llvm::CoalescerPair::setRegisters(), llvm::MIRParserImpl::setupRegisterInfo(), shareSameRegisterFile(), llvm::PPCInstrInfo::shouldClusterMemOps(), llvm::PPCInstrInfo::shouldReduceRegisterPressure(), shouldUseFrameHelper(), llvm::yaml::SIMachineFunctionInfo::SIMachineFunctionInfo(), SinkingPreventsImplicitNullCheck(), llvm::SITargetLowering::SITargetLowering(), llvm::AVRFrameLowering::spillCalleeSavedRegisters(), llvm::MipsSEFrameLowering::spillCalleeSavedRegisters(), llvm::ARMFrameLowering::spillCalleeSavedRegisters(), llvm::XCoreFrameLowering::spillCalleeSavedRegisters(), llvm::RISCVFrameLowering::spillCalleeSavedRegisters(), llvm::AArch64FrameLowering::spillCalleeSavedRegisters(), llvm::CSKYFrameLowering::spillCalleeSavedRegisters(), llvm::SystemZELFFrameLowering::spillCalleeSavedRegisters(), llvm::M68kFrameLowering::spillCalleeSavedRegisters(), llvm::SystemZXPLINKFrameLowering::spillCalleeSavedRegisters(), llvm::PPCFrameLowering::spillCalleeSavedRegisters(), spillVGPRtoAGPR(), llvm::MachineBasicBlock::SplitCriticalEdge(), storeRegPairToStackSlot(), llvm::MipsSEInstrInfo::storeRegToStack(), llvm::Thumb2InstrInfo::storeRegToStackSlot(), llvm::RISCVInstrInfo::storeRegToStackSlot(), llvm::ARCInstrInfo::storeRegToStackSlot(), llvm::AVRInstrInfo::storeRegToStackSlot(), llvm::MipsInstrInfo::storeRegToStackSlot(), llvm::AArch64InstrInfo::storeRegToStackSlot(), llvm::ARMBaseInstrInfo::storeRegToStackSlot(), llvm::SIInstrInfo::storeRegToStackSlot(), llvm::M68kInstrInfo::storeRegToStackSlot(), llvm::X86InstrInfo::storeRegToStackSlot(), llvm::PPCInstrInfo::storeRegToStackSlot(), stripValuesNotDefiningMask(), llvm::MachineOperand::substPhysReg(), llvm::MachineOperand::substVirtReg(), TrackDefUses(), tryChangeVGPRtoSGPRinCopy(), tryConstantFoldOp(), llvm::tryFoldSPUpdateIntoPushPop(), tryToFindRegisterToRename(), tryToGetTargetInfo(), llvm::X86InstrInfo::unfoldMemoryOperand(), unsupportedBinOp(), llvm::LiveIntervals::HMEditor::updateAllRanges(), updateLiveIn(), updateOperand(), UpdateOperandRegClass(), updateOperandRegConstraints(), updatePhysDepsDownwards(), updatePhysDepsUpwards(), UpdatePredRedefs(), and llvm::X86RegisterBankInfo::X86RegisterBankInfo().

◆ UseBlockFreqInfo

cl::opt<bool> UseBlockFreqInfo("machine-sink-bfi", cl::desc("Use block frequency info to find successors to sink"), cl::init(true), cl::Hidden)
static
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1618
llvm::LiveRegUnits
A set of register units used to track register liveness.
Definition: LiveRegUnits.h:30