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61 #define DEBUG_TYPE "machine-sink"
65 cl::desc(
"Split critical edges during machine sinking"),
70 cl::desc(
"Use block frequency info to find successors to sink"),
74 "machine-sink-split-probability-threshold",
76 "Percentage threshold for splitting single-instruction critical edge. "
77 "If the branch threshold is higher than this threshold, we allow "
78 "speculative execution of up to 1 instruction to avoid branching to "
79 "splitted critical edge"),
83 "machine-sink-load-instrs-threshold",
84 cl::desc(
"Do not try to find alias store for a load if there is a in-path "
85 "block whose instruction number is higher than this threshold."),
89 "machine-sink-load-blocks-threshold",
90 cl::desc(
"Do not try to find alias store for a load if the block number in "
91 "the straight line is higher than this threshold."),
96 cl::desc(
"Sink instructions into loops to avoid "
101 "machine-sink-loop-limit",
102 cl::desc(
"The maximum number of instructions considered for loop sinking."),
105 STATISTIC(NumSunk,
"Number of machine instructions sunk");
106 STATISTIC(NumLoopSunk,
"Number of machine instructions sunk into a loop");
107 STATISTIC(NumSplit,
"Number of critical edges split");
108 STATISTIC(NumCoalesces,
"Number of copies coalesced");
109 STATISTIC(NumPostRACopySink,
"Number of copies sunk after RA");
135 using AllSuccsCache =
136 std::map<MachineBasicBlock *, SmallVector<MachineBasicBlock *, 4>>;
157 std::map<std::pair<MachineBasicBlock *, MachineBasicBlock *>,
bool>
159 std::map<std::pair<MachineBasicBlock *, MachineBasicBlock *>,
160 std::vector<MachineInstr *>>
164 std::map<MachineBasicBlock *, std::vector<unsigned>> CachedRegisterPressure;
187 void releaseMemory()
override {
188 CEBCandidates.
clear();
218 AllSuccsCache &AllSuccessors);
228 bool &LocalUse)
const;
230 bool &BreakPHIEdge, AllSuccsCache &AllSuccessors);
239 AllSuccsCache &AllSuccessors);
246 AllSuccsCache &AllSuccessors)
const;
258 "Machine code sinking",
false,
false)
266 bool MachineSinking::PerformTrivialForwardCoalescing(
MachineInstr &
MI,
288 MI.eraseFromParent();
302 bool MachineSinking::AllUsesDominatedByBlock(
Register Reg,
306 bool &LocalUse)
const {
328 MachineInstr *UseInst = MO.getParent();
329 unsigned OpNo = UseInst->getOperandNo(&MO);
330 MachineBasicBlock *UseBlock = UseInst->getParent();
331 return UseBlock == MBB && UseInst->isPHI() &&
332 UseInst->getOperand(OpNo + 1).getMBB() == DefMBB;
341 unsigned OpNo = &MO - &UseInst->
getOperand(0);
343 if (UseInst->
isPHI()) {
347 }
else if (UseBlock == DefMBB) {
363 assert(
MI.mayLoad() &&
"Expected MI that loads!");
367 if (
MI.memoperands_empty())
372 if (PSV->isGOT() || PSV->isConstantPool())
380 for (
auto &
MI : *
BB) {
382 if (!
TII->shouldSink(
MI)) {
383 LLVM_DEBUG(
dbgs() <<
"LoopSink: Instruction not a candidate for this "
388 LLVM_DEBUG(
dbgs() <<
"LoopSink: Instruction is not loop invariant\n");
391 bool DontMoveAcrossStore =
true;
392 if (!
MI.isSafeToMove(AA, DontMoveAcrossStore)) {
393 LLVM_DEBUG(
dbgs() <<
"LoopSink: Instruction not safe to move.\n");
397 LLVM_DEBUG(
dbgs() <<
"LoopSink: Dont sink GOT or constant pool loads\n");
400 if (
MI.isConvergent())
409 LLVM_DEBUG(
dbgs() <<
"LoopSink: Instruction added as candidate.\n");
410 Candidates.push_back(&
MI);
423 DT = &getAnalysis<MachineDominatorTree>();
424 PDT = &getAnalysis<MachinePostDominatorTree>();
425 LI = &getAnalysis<MachineLoopInfo>();
426 MBFI =
UseBlockFreqInfo ? &getAnalysis<MachineBlockFrequencyInfo>() : nullptr;
427 MBPI = &getAnalysis<MachineBranchProbabilityInfo>();
428 AA = &getAnalysis<AAResultsWrapperPass>().getAAResults();
431 bool EverMadeChange =
false;
434 bool MadeChange =
false;
437 CEBCandidates.
clear();
443 for (
auto &Pair : ToSplit) {
444 auto NewSucc = Pair.first->SplitCriticalEdge(Pair.second, *
this);
445 if (NewSucc !=
nullptr) {
459 if (!MadeChange)
break;
460 EverMadeChange =
true;
465 for (
auto *L :
Loops) {
472 FindLoopSinkCandidates(L, Preheader, Candidates);
478 for (
auto It = Candidates.rbegin(); It != Candidates.rend(); ++It) {
480 LLVM_DEBUG(
dbgs() <<
"LoopSink: Limit reached of instructions to "
486 if (!SinkIntoLoop(L, *
I))
488 EverMadeChange =
true;
494 HasStoreCache.clear();
495 StoreInstrCache.clear();
498 for (
auto I : RegsToClearKillFlags)
500 RegsToClearKillFlags.clear();
502 return EverMadeChange;
514 bool MadeChange =
false;
517 AllSuccsCache AllSuccessors;
522 bool ProcessedBegin, SawStore =
false;
532 if (
MI.isDebugInstr()) {
533 if (
MI.isDebugValue())
538 bool Joined = PerformTrivialForwardCoalescing(
MI, &
MBB);
550 }
while (!ProcessedBegin);
552 SeenDbgUsers.
clear();
555 CachedRegisterPressure.clear();
563 assert(
MI.isDebugValue() &&
"Expected DBG_VALUE for processing");
566 MI.getDebugLoc()->getInlinedAt());
567 bool SeenBefore = SeenDbgVars.
contains(Var);
571 SeenDbgUsers[MO.
getReg()].push_back(SeenDbgUser(&
MI, SeenBefore));
577 bool MachineSinking::isWorthBreakingCriticalEdge(
MachineInstr &
MI,
585 if (!CEBCandidates.
insert(std::make_pair(
From, To)).second)
588 if (!
MI.isCopy() && !
TII->isAsCheapAsAMove(
MI))
598 for (
unsigned i = 0,
e =
MI.getNumOperands();
i !=
e; ++
i) {
632 if (!isWorthBreakingCriticalEdge(
MI, FromBB, ToBB))
693 ToSplit.insert(std::make_pair(FromBB, ToBB));
698 std::vector<unsigned> &
704 auto RP = CachedRegisterPressure.find(&
MBB);
705 if (
RP != CachedRegisterPressure.end())
719 if (
MI.isDebugValue() ||
MI.isDebugLabel())
723 RPTracker.recedeSkipDebugValues();
724 assert(&*RPTracker.getPos() == &
MI &&
"RPTracker sync error!");
725 RPTracker.recede(RegOpers);
728 RPTracker.closeRegion();
729 auto It = CachedRegisterPressure.insert(
730 std::make_pair(&
MBB, RPTracker.getPressure().MaxSetPressure));
731 return It.first->second;
738 AllSuccsCache &AllSuccessors) {
739 assert (SuccToSinkTo &&
"Invalid SinkTo Candidate BB");
741 if (
MBB == SuccToSinkTo)
754 bool NonPHIUse =
false;
757 if (UseBlock == SuccToSinkTo && !UseInst.
isPHI())
765 bool BreakPHIEdge =
false;
768 FindSuccToSinkTo(
MI, SuccToSinkTo, BreakPHIEdge, AllSuccessors))
769 return isProfitableToSinkTo(
Reg,
MI, SuccToSinkTo, MBB2, AllSuccessors);
782 std::vector<unsigned> BBRegisterPressure =
783 getBBRegisterPressure(*SuccToSinkTo);
784 for (; *PS != -1; PS++)
787 if (Weight + BBRegisterPressure[*PS] >=
795 for (
unsigned i = 0,
e =
MI.getNumOperands();
i !=
e; ++
i) {
811 bool LocalUse =
false;
812 if (!AllUsesDominatedByBlock(
Reg, SuccToSinkTo,
MBB, BreakPHIEdge,
828 LLVM_DEBUG(
dbgs() <<
"register pressure exceed limit, not profitable.");
844 AllSuccsCache &AllSuccessors)
const {
846 auto Succs = AllSuccessors.find(
MBB);
847 if (Succs != AllSuccessors.end())
848 return Succs->second;
861 if (DTChild->getIDom()->getBlock() ==
MI.getParent() &&
864 AllSuccs.push_back(DTChild->getBlock());
870 uint64_t LHSFreq = MBFI ? MBFI->
getBlockFreq(L).getFrequency() : 0;
871 uint64_t RHSFreq = MBFI ? MBFI->
getBlockFreq(R).getFrequency() : 0;
872 bool HasBlockFreq = LHSFreq != 0 && RHSFreq != 0;
873 return HasBlockFreq ? LHSFreq < RHSFreq
877 auto it = AllSuccessors.insert(std::make_pair(
MBB, AllSuccs));
879 return it.first->second;
886 AllSuccsCache &AllSuccessors) {
887 assert (
MBB &&
"Invalid MachineBasicBlock!");
895 for (
unsigned i = 0,
e =
MI.getNumOperands();
i !=
e; ++
i) {
897 if (!MO.
isReg())
continue;
900 if (
Reg == 0)
continue;
909 }
else if (!MO.
isDead()) {
915 if (MO.
isUse())
continue;
926 bool LocalUse =
false;
927 if (!AllUsesDominatedByBlock(
Reg, SuccToSinkTo,
MBB,
928 BreakPHIEdge, LocalUse))
939 GetAllSortedSuccessors(
MI,
MBB, AllSuccessors)) {
940 bool LocalUse =
false;
941 if (AllUsesDominatedByBlock(
Reg, SuccBlock,
MBB,
942 BreakPHIEdge, LocalUse)) {
943 SuccToSinkTo = SuccBlock;
954 if (!isProfitableToSinkTo(
Reg,
MI,
MBB, SuccToSinkTo, AllSuccessors))
961 if (
MBB == SuccToSinkTo)
966 if (SuccToSinkTo && SuccToSinkTo->
isEHPad())
991 auto *
MBB =
MI.getParent();
996 auto *PredBB = PredMBB->getBasicBlock();
1002 !PredBB->getTerminator()->getMetadata(LLVMContext::MD_make_implicit))
1007 bool OffsetIsScalable;
1008 if (!
TII->getMemOperandWithOffset(
MI, BaseOp,
Offset, OffsetIsScalable,
TRI))
1011 if (!BaseOp->
isReg())
1014 if (!(
MI.mayLoad() && !
MI.isPredicable()))
1017 MachineBranchPredicate MBP;
1018 if (
TII->analyzeBranchPredicate(*PredMBB, MBP,
false))
1021 return MBP.LHS.isReg() && MBP.RHS.isImm() && MBP.RHS.getImm() == 0 &&
1024 MBP.LHS.getReg() == BaseOp->
getReg();
1041 auto CopyOperands =
TII.isCopyInstr(SinkInst);
1044 SrcMO = CopyOperands->Source;
1045 DstMO = CopyOperands->Destination;
1057 if (arePhysRegs != PostRA)
1063 DbgMO.
getSubReg() != DstMO->getSubReg()))
1069 if (PostRA && DbgMO.
getReg() != DstMO->getReg())
1085 if (!SuccToSinkTo.
empty() && InsertPos != SuccToSinkTo.
end())
1087 InsertPos->getDebugLoc()));
1093 SuccToSinkTo.
splice(InsertPos, ParentBlock,
MI,
1102 SuccToSinkTo.
insert(InsertPos, NewDbgMI);
1105 DbgMI->setDebugValueUndef();
1118 auto BlockPair = std::make_pair(
From, To);
1122 if (HasStoreCache.find(BlockPair) != HasStoreCache.end())
1123 return HasStoreCache[BlockPair];
1125 if (StoreInstrCache.find(BlockPair) != StoreInstrCache.end())
1127 return I->mayAlias(AA,
MI,
false);
1130 bool SawStore =
false;
1131 bool HasAliasedStore =
false;
1150 if (!HandledDomBlocks.
count(
BB))
1157 for (
auto *DomBB : HandledDomBlocks) {
1159 HasStoreCache[std::make_pair(DomBB, To)] =
true;
1161 HasStoreCache[std::make_pair(
From, DomBB)] =
true;
1163 HasStoreCache[BlockPair] =
true;
1170 if (
I.isCall() ||
I.hasOrderedMemoryRef()) {
1171 for (
auto *DomBB : HandledDomBlocks) {
1173 HasStoreCache[std::make_pair(DomBB, To)] =
true;
1175 HasStoreCache[std::make_pair(
From, DomBB)] =
true;
1177 HasStoreCache[BlockPair] =
true;
1187 if (
I.mayAlias(AA,
MI,
false))
1188 HasAliasedStore =
true;
1189 StoreInstrCache[BlockPair].push_back(&
I);
1196 HasStoreCache[BlockPair] =
false;
1197 return HasAliasedStore;
1206 assert(Preheader &&
"Loop sink needs a preheader block");
1208 bool CanSink =
true;
1214 LLVM_DEBUG(
dbgs() <<
"LoopSink: Use not in loop, can't sink.\n");
1229 SinkBlock =
MI.getParent();
1236 LLVM_DEBUG(
dbgs() <<
"LoopSink: Can't find nearest dominator\n");
1240 LLVM_DEBUG(
dbgs() <<
"LoopSink: Setting nearest common dom block: " <<
1249 LLVM_DEBUG(
dbgs() <<
"LoopSink: Not sinking, can't find sink block.\n");
1252 if (SinkBlock == Preheader) {
1253 LLVM_DEBUG(
dbgs() <<
"LoopSink: Not sinking, sink block is the preheader\n");
1257 LLVM_DEBUG(
dbgs() <<
"LoopSink: Not Sinking, block too large to analyse.\n");
1266 assert(!
I.isDebugInstr() &&
"Should not sink debug inst");
1274 AllSuccsCache &AllSuccessors) {
1276 if (!
TII->shouldSink(
MI))
1280 if (!
MI.isSafeToMove(AA, SawStore))
1285 if (
MI.isConvergent())
1301 bool BreakPHIEdge =
false;
1304 FindSuccToSinkTo(
MI, ParentBlock, BreakPHIEdge, AllSuccessors);
1313 for (
unsigned I = 0,
E =
MI.getNumOperands();
I !=
E; ++
I) {
1315 if (!MO.
isReg())
continue;
1323 LLVM_DEBUG(
dbgs() <<
"Sink instr " <<
MI <<
"\tinto block " << *SuccToSinkTo);
1330 bool TryBreak =
false;
1332 MI.mayLoad() ? hasStoreBetween(ParentBlock, SuccToSinkTo,
MI) :
true;
1333 if (!
MI.isSafeToMove(AA,
Store)) {
1334 LLVM_DEBUG(
dbgs() <<
" *** NOTE: Won't sink load along critical edge.\n");
1340 if (!TryBreak && !DT->
dominates(ParentBlock, SuccToSinkTo)) {
1359 PostponeSplitCriticalEdge(
MI, ParentBlock, SuccToSinkTo, BreakPHIEdge);
1362 "break critical edge\n");
1372 bool Status = PostponeSplitCriticalEdge(
MI, ParentBlock,
1373 SuccToSinkTo, BreakPHIEdge);
1376 "break critical edge\n");
1383 while (InsertPos != SuccToSinkTo->
end() && InsertPos->isPHI())
1388 for (
auto &MO :
MI.operands()) {
1398 if (
User.getInt()) {
1404 DbgUsersToSink.push_back(DbgMI);
1412 if (
MI.getMF()->getFunction().getSubprogram() &&
MI.isCopy())
1413 SalvageUnsunkDebugUsersOfCopy(
MI, SuccToSinkTo);
1424 RegsToClearKillFlags.set(MO.
getReg());
1430 void MachineSinking::SalvageUnsunkDebugUsersOfCopy(
1440 for (
auto &MO :
MI.operands()) {
1448 if (
User.getParent() ==
MI.getParent())
1452 "DBG_VALUE user of vreg, but non reg operand?");
1453 DbgDefUsers.push_back(&
User);
1459 for (
auto *
User : DbgDefUsers) {
1460 User->getDebugOperand(0).setReg(
MI.getOperand(1).getReg());
1461 User->getDebugOperand(0).setSubReg(
MI.getOperand(1).getSubReg());
1507 StringRef getPassName()
const override {
return "PostRA Machine Sink"; }
1538 "PostRA Machine Sink",
false,
false)
1553 for (
auto *
SI : SinkableBBs) {
1554 if (aliasWithRegsInLiveIn(*
SI,
Reg,
TRI)) {
1568 if (!SinkableBBs.count(
SI) && aliasWithRegsInLiveIn(*
SI,
Reg,
TRI))
1580 for (
auto DefReg : DefedRegsInCopy) {
1583 if (!
BB || (SingleBB && SingleBB !=
BB))
1594 for (
auto U : UsedOpsInCopy) {
1600 if (UI.killsRegister(SrcReg,
TRI)) {
1601 UI.clearRegisterKills(SrcReg,
TRI);
1615 for (
unsigned DefReg : DefedRegsInCopy)
1618 for (
auto U : UsedOpsInCopy) {
1619 Register SrcReg =
MI->getOperand(U).getReg();
1622 Mask |= (*S).second;
1634 bool HasRegDependency =
false;
1635 for (
unsigned i = 0,
e =
MI->getNumOperands();
i !=
e; ++
i) {
1644 HasRegDependency =
true;
1647 DefedRegsInCopy.push_back(
Reg);
1653 }
else if (MO.
isUse()) {
1655 HasRegDependency =
true;
1658 UsedOpsInCopy.push_back(
i);
1661 return HasRegDependency;
1681 if (!
SI->livein_empty() &&
SI->pred_size() == 1)
1684 if (SinkableBBs.
empty())
1687 bool Changed =
false;
1691 ModifiedRegUnits.clear();
1692 UsedRegUnits.clear();
1693 SeenDbgInstrs.clear();
1706 if (
MI->isDebugValue()) {
1707 auto &MO =
MI->getDebugOperand(0);
1712 ModifiedRegUnits, UsedRegUnits))
1718 SeenDbgInstrs[
Reg].push_back(
MI);
1723 if (
MI->isDebugInstr())
1730 if (!
MI->isCopy() || !
MI->getOperand(0).isRenamable()) {
1738 ModifiedRegUnits, UsedRegUnits)) {
1743 assert((!UsedOpsInCopy.empty() && !DefedRegsInCopy.empty()) &&
1744 "Unexpect SrcReg or DefReg");
1755 "Unexpected predecessor");
1761 for (
auto &MO :
MI->operands()) {
1767 for (
auto *
MI : SeenDbgInstrs.lookup(
Reg))
1771 DbgValsToSinkSet.
end());
1781 ++NumPostRACopySink;
1786 bool PostRAMachineSinking::runOnMachineFunction(
MachineFunction &MF) {
1790 bool Changed =
false;
1794 ModifiedRegUnits.init(*
TRI);
1795 UsedRegUnits.init(*
TRI);
1797 Changed |= tryToSinkCopy(
BB, MF,
TRI,
TII);
MachineBasicBlock * findNearestCommonDominator(MachineBasicBlock *A, MachineBasicBlock *B)
findNearestCommonDominator - Find nearest common dominator basic block for basic block A and B.
unsigned succ_size() const
void setDebugValueUndef()
Sets all register debug operands in this debug value instruction to be undef.
pred_iterator pred_begin()
This class represents lattice values for constants.
void initializeMachineSinkingPass(PassRegistry &)
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
bool isLiveIn(MCPhysReg Reg, LaneBitmask LaneMask=LaneBitmask::getAll()) const
Return true if the specified register is in the live in set.
MachineLoop * getLoopFor(const MachineBasicBlock *BB) const
Return the innermost loop that BB lives in.
static const DILocation * getMergedLocation(const DILocation *LocA, const DILocation *LocB)
When two instructions are combined into a single instruction we also need to combine the original loc...
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
static void accumulateUsedDefed(const MachineInstr &MI, LiveRegUnits &ModifiedRegUnits, LiveRegUnits &UsedRegUnits, const TargetRegisterInfo *TRI)
For a machine instruction MI, adds all register units used in UsedRegUnits and defined or clobbered i...
Represents a predicate at the MachineFunction level.
List of registers defined and used by a machine instruction.
bool contains(const LoopT *L) const
Return true if the specified loop is contained within in this loop.
virtual const TargetInstrInfo * getInstrInfo() const
Reference model for inliner Oz decision policy Note this model is also referenced by test Transforms Inline ML tests if replacing it
void setIsKill(bool Val=true)
static cl::opt< unsigned > SinkIntoLoopLimit("machine-sink-loop-limit", cl::desc("The maximum number of instructions considered for loop sinking."), cl::init(50), cl::Hidden)
MachineBasicBlock * findLoopPreheader(MachineLoop *L, bool SpeculativePreheader=false) const
Find the block that either is the loop preheader, or could speculatively be used as the preheader.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Printable printMBBReference(const MachineBasicBlock &MBB)
Prints a machine basic block reference.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
bool available(MCPhysReg Reg) const
Returns true if no part of physical register Reg is live.
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
iterator_range< use_instr_nodbg_iterator > use_nodbg_instructions(Register Reg) const
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Track the current register pressure at some position in the instruction stream, and remember the high...
iterator_range< use_instr_iterator > use_instructions(Register Reg) const
A description of a memory reference used in the backend.
static bool SinkInstruction(Instruction *Inst, SmallPtrSetImpl< Instruction * > &Stores, DominatorTree &DT, LoopInfo &LI, AAResults &AA)
SinkInstruction - Determine whether it is safe to sink the specified machine instruction out of its c...
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
const MachineFunction * getMF() const
Return the function that contains the basic block that this instruction belongs to.
Properties which a MachineFunction may have at a given point in time.
llvm::DenseMapBase< SmallDenseMap< KeyT, ValueT, 4, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >, KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >::count size_type count(const_arg_type_t< KeyT > Val) const
Return 1 if the specified key is in the map, 0 otherwise.
unsigned getNumVirtRegs() const
getNumVirtRegs - Return the number of virtual registers created.
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements.
void addLiveIns(const MachineBasicBlock &MBB)
Adds registers living into block MBB.
bool dominates(const MachineDomTreeNode *A, const MachineDomTreeNode *B) const
virtual unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const =0
Get the register unit pressure limit for this dimension.
std::pair< iterator, bool > insert(const ValueT &V)
std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
size_type count(const_arg_type_t< ValueT > V) const
Return 1 if the specified key is in the set, 0 otherwise.
unsigned const TargetRegisterInfo * TRI
static void clearKillFlags(MachineInstr *MI, MachineBasicBlock &CurBB, SmallVectorImpl< unsigned > &UsedOpsInCopy, LiveRegUnits &UsedRegUnits, const TargetRegisterInfo *TRI)
INITIALIZE_PASS_END(RegBankSelect, DEBUG_TYPE, "Assign register bank of generic virtual registers", false, false) RegBankSelect
BlockFrequency getBlockFreq(const MachineBasicBlock *MBB) const
getblockFreq - Return block frequency.
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
static cl::opt< unsigned > SinkLoadInstsPerBlockThreshold("machine-sink-load-instrs-threshold", cl::desc("Do not try to find alias store for a load if there is a in-path " "block whose instruction number is higher than this threshold."), cl::init(2000), cl::Hidden)
static bool SinkingPreventsImplicitNullCheck(MachineInstr &MI, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI)
Return true if MI is likely to be usable as a memory operation by the implicit null check optimizatio...
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
unsigned pred_size() const
bool all_of(R &&range, UnaryPredicate P)
Provide wrappers to std::all_of which take ranges instead of having to pass begin/end explicitly.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
TargetInstrInfo - Interface to description of machine instruction set.
iterator_range< use_nodbg_iterator > use_nodbg_operands(Register Reg) const
iterator begin()
Get an iterator to the beginning of the SetVector.
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
MachineBlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate machine basic b...
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
const MachineOperand & getOperand(unsigned i) const
bool isReachableFromEntry(const MachineBasicBlock *A)
isReachableFromEntry - Return true if A is dominated by the entry block of the function containing it...
bool isSuccessor(const MachineBasicBlock *MBB) const
Return true if the specified MBB is a successor of this block.
static SmallSet< MCRegister, 4 > getRegUnits(MCRegister Reg, const TargetRegisterInfo *TRI)
void setSubReg(unsigned subReg)
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
Represent the analysis usage information of a pass.
virtual const int * getRegClassPressureSets(const TargetRegisterClass *RC) const =0
Get the dimensions of register pressure impacted by this register class.
iterator_range< iterator > children()
const HexagonInstrInfo * TII
MachineOperand class - Representation of each machine instruction operand.
MachineFunctionProperties & set(Property P)
STATISTIC(NumFunctions, "Total number of functions")
Special value supplied for machine level alias analysis.
A set of register units used to track register liveness.
MachineInstr * getVRegDef(Register Reg) const
getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...
static bool attemptDebugCopyProp(MachineInstr &SinkInst, MachineInstr &DbgMI)
If the sunk instruction is a copy, try to forward the copy instead of leaving an 'undef' DBG_VALUE in...
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
bool isLoopHeader(const MachineBasicBlock *BB) const
True if the block is a loop header node.
void collect(const MachineInstr &MI, const TargetRegisterInfo &TRI, const MachineRegisterInfo &MRI, bool TrackLaneMasks, bool IgnoreDead)
Analyze the given instruction MI and fill in the Uses, Defs and DeadDefs list based on the MachineOpe...
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
bool isVirtual() const
Return true if the specified register number is in the virtual register namespace.
void clearKillFlags(Register Reg) const
clearKillFlags - Iterate over all the uses of the given register and clear the kill flag from the Mac...
Implements a dense probed hash-table based set.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
INITIALIZE_PASS_BEGIN(MachineSinking, DEBUG_TYPE, "Machine code sinking", false, false) INITIALIZE_PASS_END(MachineSinking
void runOnMachineFunction(const MachineFunction &MF)
runOnFunction - Prepare to answer questions about MF.
MachineOperand & getDebugOperand(unsigned Index)
llvm::DenseMapBase< SmallDenseMap< KeyT, ValueT, 4, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >, KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >::clear void clear()
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Representation of each machine instruction.
char & MachineSinkingID
MachineSinking - This pass performs sinking on machine instructions.
MachineInstr * CloneMachineInstr(const MachineInstr *Orig)
Create a new MachineInstr which is a copy of Orig, identical in all ways except the instruction has n...
static bool mayLoadFromGOTOrConstantPool(MachineInstr &MI)
Return true if this machine instruction loads from global offset table or constant pool.
void onEdgeSplit(const MachineBasicBlock &NewPredecessor, const MachineBasicBlock &NewSuccessor, const MachineBranchProbabilityInfo &MBPI)
incrementally calculate block frequencies when we split edges, to avoid full CFG traversal.
INITIALIZE_PASS_DEPENDENCY(DominatorTreeWrapperPass)
MachineDomTreeNode * getNode(MachineBasicBlock *BB) const
getNode - return the (Post)DominatorTree node for the specified basic block.
MCRegUnitMaskIterator enumerates a list of register units and their associated lane masks for Reg.
initializer< Ty > init(const Ty &Val)
iterator getFirstNonPHI()
Returns a pointer to the first instruction in this block that is not a PHINode instruction.
Identifies a unique instance of a variable.
BlockT * getLoopPreheader() const
If there is a preheader for this loop, return it.
static cl::opt< bool > SplitEdges("machine-sink-split", cl::desc("Split critical edges during machine sinking"), cl::init(true), cl::Hidden)
std::vector< MachineBasicBlock * >::iterator pred_iterator
static MachineBasicBlock * getSingleLiveInSuccBB(MachineBasicBlock &CurBB, const SmallPtrSetImpl< MachineBasicBlock * > &SinkableBBs, unsigned Reg, const TargetRegisterInfo *TRI)
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
static cl::opt< bool > SinkInstsIntoLoop("sink-insts-to-avoid-spills", cl::desc("Sink instructions into loops to avoid " "register spills"), cl::init(false), cl::Hidden)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
Register getReg() const
getReg - Returns the register number.
bool hasOneDef(Register RegNo) const
Return true if there is exactly one operand defining the specified register.
BranchProbability getEdgeProbability(const MachineBasicBlock *Src, const MachineBasicBlock *Dst) const
instr_iterator instr_begin()
instr_iterator instr_end()
bool insert(const value_type &X)
Insert a new element into the SetVector.
bool use_nodbg_empty(Register RegNo) const
use_nodbg_empty - Return true if there are no non-Debug instructions using the specified register.
static bool hasRegisterDependency(MachineInstr *MI, SmallVectorImpl< unsigned > &UsedOpsInCopy, SmallVectorImpl< unsigned > &DefedRegsInCopy, LiveRegUnits &ModifiedRegUnits, LiveRegUnits &UsedRegUnits)
MachineBasicBlock * getMBB() const
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
iterator_range< succ_iterator > successors()
bool isEHPad() const
Returns true if the block is a landing pad.
void setPreservesCFG()
This function should be called by the pass, iff they do not:
StringRef - Represent a constant reference to a string, i.e.
reverse_iterator rbegin()
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
static cl::opt< bool > UseBlockFreqInfo("machine-sink-bfi", cl::desc("Use block frequency info to find successors to sink"), cl::init(true), cl::Hidden)
bool hasOneNonDBGUse(Register RegNo) const
hasOneNonDBGUse - Return true if there is exactly one non-Debug use of the specified register.
void removeLiveIn(MCPhysReg Reg, LaneBitmask LaneMask=LaneBitmask::getAll())
Remove the specified register from the live in set.
AnalysisUsage & addPreserved()
Add the specified Pass class to the set of analyses preserved by this pass.
bool contains(const_arg_type_t< ValueT > V) const
Check if the set contains the given element.
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
std::pair< NoneType, bool > insert(const T &V)
insert - Insert an element into the set if it isn't already there.
const MachineBasicBlock * getParent() const
Base class for the actual dominator tree node.
MachinePostDominatorTree - an analysis pass wrapper for DominatorTree used to compute the post-domina...
unsigned const MachineRegisterInfo * MRI
Wrapper class representing virtual and physical registers.
unsigned getSubReg() const
void addLiveIn(MCRegister PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
bool isConstantPhysReg(MCRegister PhysReg) const
Returns true if PhysReg is unallocatable and constant throughout the function.
void clear()
Completely clear the SetVector.
iterator_range< df_iterator< T > > depth_first(const T &G)
void replaceRegWith(Register FromReg, Register ToReg)
replaceRegWith - Replace all instances of FromReg with ToReg in the machine function.
RegisterPressure computed within a region of instructions delimited by TopPos and BottomPos.
bool dominates(const MachineDomTreeNode *A, const MachineDomTreeNode *B) const
void stable_sort(R &&Range)
static void performSink(MachineInstr &MI, MachineBasicBlock &SuccToSinkTo, MachineBasicBlock::iterator InsertPos, SmallVectorImpl< MachineInstr * > &DbgValuesToSink)
Sink an instruction and its associated debug instructions.
Function & getFunction()
Return the LLVM function that this machine code represents.
bool isCopyLike() const
Return true if the instruction behaves like a copy.
void sortUniqueLiveIns()
Sorts and uniques the LiveIns vector.
*Add support for compiling functions in both ARM and Thumb then taking the smallest *Add support for compiling individual basic blocks in thumb when in a larger ARM function This can be used for presumed cold code
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
unsigned getLoopDepth(const MachineBasicBlock *BB) const
Return the loop nesting level of the specified block.
MCSubRegIterator enumerates all sub-registers of Reg.
iterator end()
Get an iterator to the end of the SetVector.
INITIALIZE_PASS(PostRAMachineSinking, "postra-machine-sink", "PostRA Machine Sink", false, false) static bool aliasWithRegsInLiveIn(MachineBasicBlock &MBB
PointerIntPair - This class implements a pair of a pointer and small integer.
COFF::MachineTypes Machine
static cl::opt< unsigned > SinkLoadBlocksThreshold("machine-sink-load-blocks-threshold", cl::desc("Do not try to find alias store for a load if the block number in " "the straight line is higher than this threshold."), cl::init(20), cl::Hidden)
static cl::opt< unsigned > SplitEdgeProbabilityThreshold("machine-sink-split-probability-threshold", cl::desc("Percentage threshold for splitting single-instruction critical edge. " "If the branch threshold is higher than this threshold, we allow " "speculative execution of up to 1 instruction to avoid branching to " "splitted critical edge"), cl::init(40), cl::Hidden)
bool isInlineAsmBrIndirectTarget() const
Returns true if this is the indirect dest of an INLINEASM_BR.
LLVM_NODISCARD bool empty() const
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
void setReg(Register Reg)
Change the register this operand corresponds to.
static void updateLiveIn(MachineInstr *MI, MachineBasicBlock *SuccBB, SmallVectorImpl< unsigned > &UsedOpsInCopy, SmallVectorImpl< unsigned > &DefedRegsInCopy)
MachineInstrBuilder MachineInstrBuilder & DefMI
A wrapper pass to provide the legacy pass manager access to a suitably prepared AAResults object.
virtual const RegClassWeight & getRegClassWeight(const TargetRegisterClass *RC) const =0
Get the weight in units of pressure for this register class.
iv Induction Variable Users
A templated base class for SmallPtrSet which provides the typesafe interface that is common across al...
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
AnalysisUsage & addRequired()
BlockVerifier::State From
char & PostRAMachineSinkingID
This pass perform post-ra machine sink for COPY instructions.
static bool ProcessBlock(BasicBlock &BB, DominatorTree &DT, LoopInfo &LI, AAResults &AA)
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
A vector that has set insertion semantics.
bool isLoopInvariant(MachineInstr &I) const
Returns true if the instruction is loop invariant.
static constexpr LaneBitmask getAll()
Wrapper class representing physical registers. Should be passed by value.
std::pair< iterator, bool > insert(PtrType Ptr)
Inserts Ptr if and only if there is no element in the container equal to Ptr.