LLVM  15.0.0git
PPCXCOFFObjectWriter.cpp
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1 //===-- PPCXCOFFObjectWriter.cpp - PowerPC XCOFF Writer -------------------===//
2 //
3 //
4 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
5 // See https://llvm.org/LICENSE.txt for license information.
6 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //
8 //===----------------------------------------------------------------------===//
9 
13 #include "llvm/MC/MCFixup.h"
15 #include "llvm/MC/MCValue.h"
17 
18 using namespace llvm;
19 
20 namespace {
21 class PPCXCOFFObjectWriter : public MCXCOFFObjectTargetWriter {
22  static constexpr uint8_t SignBitMask = 0x80;
23 
24 public:
25  PPCXCOFFObjectWriter(bool Is64Bit);
26 
27  std::pair<uint8_t, uint8_t>
28  getRelocTypeAndSignSize(const MCValue &Target, const MCFixup &Fixup,
29  bool IsPCRel) const override;
30 };
31 } // end anonymous namespace
32 
33 PPCXCOFFObjectWriter::PPCXCOFFObjectWriter(bool Is64Bit)
34  : MCXCOFFObjectTargetWriter(Is64Bit) {}
35 
36 std::unique_ptr<MCObjectTargetWriter>
38  return std::make_unique<PPCXCOFFObjectWriter>(Is64Bit);
39 }
40 
41 std::pair<uint8_t, uint8_t> PPCXCOFFObjectWriter::getRelocTypeAndSignSize(
42  const MCValue &Target, const MCFixup &Fixup, bool IsPCRel) const {
43  const MCSymbolRefExpr::VariantKind Modifier =
44  Target.isAbsolute() ? MCSymbolRefExpr::VK_None
45  : Target.getSymA()->getKind();
46  // People from AIX OS team says AIX link editor does not care about
47  // the sign bit in the relocation entry "most" of the time.
48  // The system assembler seems to set the sign bit on relocation entry
49  // based on similar property of IsPCRel. So we will do the same here.
50  // TODO: More investigation on how assembler decides to set the sign
51  // bit, and we might want to match that.
52  const uint8_t EncodedSignednessIndicator = IsPCRel ? SignBitMask : 0u;
53 
54  // The magic number we use in SignAndSize has a strong relationship with
55  // the corresponding MCFixupKind. In most cases, it's the MCFixupKind
56  // number - 1, because SignAndSize encodes the bit length being
57  // relocated minus 1.
58  switch ((unsigned)Fixup.getKind()) {
59  default:
60  report_fatal_error("Unimplemented fixup kind.");
61  case PPC::fixup_ppc_half16: {
62  const uint8_t SignAndSizeForHalf16 = EncodedSignednessIndicator | 15;
63  switch (Modifier) {
64  default:
65  report_fatal_error("Unsupported modifier for half16 fixup.");
67  return {XCOFF::RelocationType::R_TOC, SignAndSizeForHalf16};
69  return {XCOFF::RelocationType::R_TOCU, SignAndSizeForHalf16};
71  return {XCOFF::RelocationType::R_TOCL, SignAndSizeForHalf16};
72  }
73  } break;
76  if (IsPCRel)
77  report_fatal_error("Invalid PC-relative relocation.");
78  switch (Modifier) {
79  default:
80  llvm_unreachable("Unsupported Modifier");
82  return {XCOFF::RelocationType::R_TOC, 15};
84  return {XCOFF::RelocationType::R_TOCL, 15};
85  }
86  } break;
88  // Branches are 4 byte aligned, so the 24 bits we encode in
89  // the instruction actually represents a 26 bit offset.
90  return {XCOFF::RelocationType::R_RBR, EncodedSignednessIndicator | 25};
92  return {XCOFF::RelocationType::R_RBA, EncodedSignednessIndicator | 25};
93  case FK_Data_4:
94  case FK_Data_8:
95  const uint8_t SignAndSizeForFKData =
96  EncodedSignednessIndicator |
97  ((unsigned)Fixup.getKind() == FK_Data_4 ? 31 : 63);
98  switch (Modifier) {
99  default:
100  report_fatal_error("Unsupported modifier");
102  return {XCOFF::RelocationType::R_TLS, SignAndSizeForFKData};
104  return {XCOFF::RelocationType::R_TLSM, SignAndSizeForFKData};
106  return {XCOFF::RelocationType::R_POS, SignAndSizeForFKData};
107  }
108  }
109 }
llvm::MCSymbolRefExpr::VK_PPC_AIX_TLSGDM
@ VK_PPC_AIX_TLSGDM
Definition: MCExpr.h:301
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
llvm::Target
Target - Wrapper for Target specific information.
Definition: TargetRegistry.h:145
MCFixupKindInfo.h
PPCMCTargetDesc.h
llvm::XCOFF::R_RBA
@ R_RBA
Branch absolute relocation. Similar to R_BA but references a modifiable instruction.
Definition: XCOFF.h:289
llvm::XCOFF::R_TOCU
@ R_TOCU
Relative to TOC upper. Specifies the high-order 16 bits of a large code model TOC-relative relocation...
Definition: XCOFF.h:302
llvm::MCSymbolRefExpr::VK_PPC_L
@ VK_PPC_L
Definition: MCExpr.h:266
XCOFF.h
llvm::FK_Data_4
@ FK_Data_4
A four-byte fixup.
Definition: MCFixup.h:25
llvm::XCOFF::R_TLS
@ R_TLS
General-dynamic reference to TLS symbol.
Definition: XCOFF.h:294
llvm::XCOFF::R_POS
@ R_POS
Positive relocation. Provides the address of the referenced symbol.
Definition: XCOFF.h:248
llvm::MCSymbolRefExpr::VK_PPC_U
@ VK_PPC_U
Definition: MCExpr.h:265
llvm::PPC::fixup_ppc_half16dq
@ fixup_ppc_half16dq
A 16-bit fixup corresponding to lo16(_foo) with implied 3 zero bits for instrs like 'lxv'.
Definition: PPCFixupKinds.h:56
llvm::report_fatal_error
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:145
llvm::MCXCOFFObjectTargetWriter
Definition: MCXCOFFObjectWriter.h:18
llvm::createPPCXCOFFObjectWriter
std::unique_ptr< MCObjectTargetWriter > createPPCXCOFFObjectWriter(bool Is64Bit)
Construct a PPC XCOFF object writer.
Definition: PPCXCOFFObjectWriter.cpp:37
llvm::PPC::fixup_ppc_half16
@ fixup_ppc_half16
A 16-bit fixup corresponding to lo16(_foo) or ha16(_foo) for instrs like 'li' or 'addis'.
Definition: PPCFixupKinds.h:37
llvm::MCSymbolRefExpr::VariantKind
VariantKind
Definition: MCExpr.h:194
llvm::XCOFF::R_RBR
@ R_RBR
Branch relative to self relocation. Similar to the R_BR relocation type, but references a modifiable ...
Definition: XCOFF.h:291
PPCFixupKinds.h
MCXCOFFObjectWriter.h
llvm::PPC::fixup_ppc_half16ds
@ fixup_ppc_half16ds
A 14-bit fixup corresponding to lo16(_foo) with implied 2 zero bits for instrs like 'std'.
Definition: PPCFixupKinds.h:41
Fixup
PowerPC TLS Dynamic Call Fixup
Definition: PPCTLSDynamicCall.cpp:215
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
MCFixup.h
llvm::XCOFF::R_TOC
@ R_TOC
Relative to the TOC relocation. Provides a displacement that is the difference between the address of...
Definition: XCOFF.h:259
llvm::PPC::fixup_ppc_br24abs
@ fixup_ppc_br24abs
24-bit absolute relocation for direct branches like 'ba' and 'bla'.
Definition: PPCFixupKinds.h:30
MCValue.h
llvm::FK_Data_8
@ FK_Data_8
A eight-byte fixup.
Definition: MCFixup.h:26
llvm::XCOFF::R_TOCL
@ R_TOCL
Relative to TOC lower. Specifies the low-order 16 bits of a large code model TOC-relative relocation.
Definition: XCOFF.h:304
llvm::MCValue
This represents an "assembler immediate".
Definition: MCValue.h:36
llvm::MCSymbolRefExpr::VK_None
@ VK_None
Definition: MCExpr.h:195
llvm::MCFixup
Encode information on a single operation to perform on a byte sequence (e.g., an encoded instruction)...
Definition: MCFixup.h:71
llvm::XCOFF::R_TLSM
@ R_TLSM
Module reference to TLS. Provides a handle for the module containing the referenced symbol.
Definition: XCOFF.h:298
llvm::PPC::fixup_ppc_br24
@ fixup_ppc_br24
Definition: PPCFixupKinds.h:20
llvm::MCSymbolRefExpr::VK_PPC_AIX_TLSGD
@ VK_PPC_AIX_TLSGD
Definition: MCExpr.h:300