LLVM 17.0.0git
PPCTLSDynamicCall.cpp
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1//===---------- PPCTLSDynamicCall.cpp - TLS Dynamic Call Fixup ------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This pass expands ADDItls{ld,gd}LADDR[32] machine instructions into
10// separate ADDItls[gd]L[32] and GETtlsADDR[32] instructions, both of
11// which define GPR3. A copy is added from GPR3 to the target virtual
12// register of the original instruction. The GETtlsADDR[32] is really
13// a call instruction, so its target register is constrained to be GPR3.
14// This is not true of ADDItls[gd]L[32], but there is a legacy linker
15// optimization bug that requires the target register of the addi of
16// a local- or general-dynamic TLS access sequence to be GPR3.
17//
18// This is done in a late pass so that TLS variable accesses can be
19// fully commoned by MachineCSE.
20//
21//===----------------------------------------------------------------------===//
22
23#include "PPC.h"
24#include "PPCInstrBuilder.h"
25#include "PPCInstrInfo.h"
26#include "PPCTargetMachine.h"
31#include "llvm/Support/Debug.h"
33
34using namespace llvm;
35
36#define DEBUG_TYPE "ppc-tls-dynamic-call"
37
38namespace {
39 struct PPCTLSDynamicCall : public MachineFunctionPass {
40 static char ID;
41 PPCTLSDynamicCall() : MachineFunctionPass(ID) {
43 }
44
45 const PPCInstrInfo *TII;
46
47protected:
48 bool processBlock(MachineBasicBlock &MBB) {
49 bool Changed = false;
50 bool NeedFence = true;
51 bool Is64Bit = MBB.getParent()->getSubtarget<PPCSubtarget>().isPPC64();
52 bool IsAIX = MBB.getParent()->getSubtarget<PPCSubtarget>().isAIXABI();
53 bool IsPCREL = false;
54
56 I != IE;) {
57 MachineInstr &MI = *I;
58 IsPCREL = isPCREL(MI);
59
60 if (MI.getOpcode() != PPC::ADDItlsgdLADDR &&
61 MI.getOpcode() != PPC::ADDItlsldLADDR &&
62 MI.getOpcode() != PPC::ADDItlsgdLADDR32 &&
63 MI.getOpcode() != PPC::ADDItlsldLADDR32 &&
64 MI.getOpcode() != PPC::TLSGDAIX &&
65 MI.getOpcode() != PPC::TLSGDAIX8 && !IsPCREL) {
66 // Although we create ADJCALLSTACKDOWN and ADJCALLSTACKUP
67 // as scheduling fences, we skip creating fences if we already
68 // have existing ADJCALLSTACKDOWN/UP to avoid nesting,
69 // which causes verification error with -verify-machineinstrs.
70 if (MI.getOpcode() == PPC::ADJCALLSTACKDOWN)
71 NeedFence = false;
72 else if (MI.getOpcode() == PPC::ADJCALLSTACKUP)
73 NeedFence = true;
74
75 ++I;
76 continue;
77 }
78
79 LLVM_DEBUG(dbgs() << "TLS Dynamic Call Fixup:\n " << MI);
80
81 Register OutReg = MI.getOperand(0).getReg();
82 Register InReg = PPC::NoRegister;
83 Register GPR3 = Is64Bit ? PPC::X3 : PPC::R3;
84 Register GPR4 = Is64Bit ? PPC::X4 : PPC::R4;
85 if (!IsPCREL)
86 InReg = MI.getOperand(1).getReg();
87 DebugLoc DL = MI.getDebugLoc();
88
89 unsigned Opc1, Opc2;
90 switch (MI.getOpcode()) {
91 default:
92 llvm_unreachable("Opcode inconsistency error");
93 case PPC::ADDItlsgdLADDR:
94 Opc1 = PPC::ADDItlsgdL;
95 Opc2 = PPC::GETtlsADDR;
96 break;
97 case PPC::ADDItlsldLADDR:
98 Opc1 = PPC::ADDItlsldL;
99 Opc2 = PPC::GETtlsldADDR;
100 break;
101 case PPC::ADDItlsgdLADDR32:
102 Opc1 = PPC::ADDItlsgdL32;
103 Opc2 = PPC::GETtlsADDR32;
104 break;
105 case PPC::ADDItlsldLADDR32:
106 Opc1 = PPC::ADDItlsldL32;
107 Opc2 = PPC::GETtlsldADDR32;
108 break;
109 case PPC::TLSGDAIX8:
110 // TLSGDAIX8 is expanded to two copies and GET_TLS_ADDR, so we only
111 // set Opc2 here.
112 Opc2 = PPC::GETtlsADDR64AIX;
113 break;
114 case PPC::TLSGDAIX:
115 // TLSGDAIX is expanded to two copies and GET_TLS_ADDR, so we only
116 // set Opc2 here.
117 Opc2 = PPC::GETtlsADDR32AIX;
118 break;
119 case PPC::PADDI8pc:
120 assert(IsPCREL && "Expecting General/Local Dynamic PCRel");
121 Opc1 = PPC::PADDI8pc;
122 Opc2 = MI.getOperand(2).getTargetFlags() ==
124 ? PPC::GETtlsADDRPCREL
125 : PPC::GETtlsldADDRPCREL;
126 }
127
128 // We create ADJCALLSTACKUP and ADJCALLSTACKDOWN around _tls_get_addr
129 // as scheduling fence to avoid it is scheduled before
130 // mflr in the prologue and the address in LR is clobbered (PR25839).
131 // We don't really need to save data to the stack - the clobbered
132 // registers are already saved when the SDNode (e.g. PPCaddiTlsgdLAddr)
133 // gets translated to the pseudo instruction (e.g. ADDItlsgdLADDR).
134 if (NeedFence)
135 BuildMI(MBB, I, DL, TII->get(PPC::ADJCALLSTACKDOWN)).addImm(0)
136 .addImm(0);
137
138 if (IsAIX) {
139 // The variable offset and region handle are copied in r4 and r3. The
140 // copies are followed by GETtlsADDR32AIX/GETtlsADDR64AIX.
141 BuildMI(MBB, I, DL, TII->get(TargetOpcode::COPY), GPR4)
142 .addReg(MI.getOperand(1).getReg());
143 BuildMI(MBB, I, DL, TII->get(TargetOpcode::COPY), GPR3)
144 .addReg(MI.getOperand(2).getReg());
145 BuildMI(MBB, I, DL, TII->get(Opc2), GPR3).addReg(GPR3).addReg(GPR4);
146 } else {
147 MachineInstr *Addi;
148 if (IsPCREL) {
149 Addi = BuildMI(MBB, I, DL, TII->get(Opc1), GPR3).addImm(0);
150 } else {
151 // Expand into two ops built prior to the existing instruction.
152 assert(InReg != PPC::NoRegister && "Operand must be a register");
153 Addi = BuildMI(MBB, I, DL, TII->get(Opc1), GPR3).addReg(InReg);
154 }
155
156 Addi->addOperand(MI.getOperand(2));
157
158 MachineInstr *Call =
159 (BuildMI(MBB, I, DL, TII->get(Opc2), GPR3).addReg(GPR3));
160 if (IsPCREL)
161 Call->addOperand(MI.getOperand(2));
162 else
163 Call->addOperand(MI.getOperand(3));
164 }
165 if (NeedFence)
166 BuildMI(MBB, I, DL, TII->get(PPC::ADJCALLSTACKUP)).addImm(0).addImm(0);
167
168 BuildMI(MBB, I, DL, TII->get(TargetOpcode::COPY), OutReg)
169 .addReg(GPR3);
170
171 // Move past the original instruction and remove it.
172 ++I;
173 MI.removeFromParent();
174
175 Changed = true;
176 }
177
178 return Changed;
179 }
180
181public:
182 bool isPCREL(const MachineInstr &MI) {
183 return (MI.getOpcode() == PPC::PADDI8pc) &&
184 (MI.getOperand(2).getTargetFlags() ==
186 MI.getOperand(2).getTargetFlags() ==
188 }
189
190 bool runOnMachineFunction(MachineFunction &MF) override {
191 TII = MF.getSubtarget<PPCSubtarget>().getInstrInfo();
192
193 bool Changed = false;
194
196 if (processBlock(B))
197 Changed = true;
198
199 return Changed;
200 }
201
202 void getAnalysisUsage(AnalysisUsage &AU) const override {
206 }
207 };
208}
209
211 "PowerPC TLS Dynamic Call Fixup", false, false)
215 "PowerPC TLS Dynamic Call Fixup", false, false)
216
217char PPCTLSDynamicCall::ID = 0;
219llvm::createPPCTLSDynamicCallPass() { return new PPCTLSDynamicCall(); }
MachineBasicBlock & MBB
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
#define LLVM_DEBUG(X)
Definition: Debug.h:101
const HexagonInstrInfo * TII
IRTranslator LLVM IR MI
#define I(x, y, z)
Definition: MD5.cpp:58
PowerPC TLS Dynamic Call Fixup
#define DEBUG_TYPE
#define INITIALIZE_PASS_DEPENDENCY(depName)
Definition: PassSupport.h:55
#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:59
#define INITIALIZE_PASS_BEGIN(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:52
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
Represent the analysis usage information of a pass.
AnalysisUsage & addRequired()
A debug info location.
Definition: DebugLoc.h:33
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:311
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
virtual bool runOnMachineFunction(MachineFunction &MF)=0
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Representation of each machine instruction.
Definition: MachineInstr.h:68
void addOperand(MachineFunction &MF, const MachineOperand &Op)
Add the specified operand to the instruction.
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
SlotIndexes pass.
Definition: SlotIndexes.h:319
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
@ MO_GOT_TLSLD_PCREL_FLAG
MO_GOT_TLSLD_PCREL_FLAG - A combintaion of flags, if these bits are set they should produce the reloc...
Definition: PPC.h:150
@ MO_GOT_TLSGD_PCREL_FLAG
MO_GOT_TLSGD_PCREL_FLAG - A combintaion of flags, if these bits are set they should produce the reloc...
Definition: PPC.h:145
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
void initializePPCTLSDynamicCallPass(PassRegistry &)
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
iterator_range< early_inc_iterator_impl< detail::IterOfRange< RangeT > > > make_early_inc_range(RangeT &&Range)
Make a range that does early increment to allow mutation of the underlying range without disrupting i...
Definition: STLExtras.h:748
FunctionPass * createPPCTLSDynamicCallPass()
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
@ Dynamic
Denotes mode unknown at compile time.