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LLVM 22.0.0git
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#include "llvm/MC/MCRegisterInfo.h"#include "llvm/Support/MathExtras.h"#include <cstdint>#include <memory>#include "PPCGenRegisterInfo.inc"#include "PPCGenInstrInfo.inc"#include "PPCGenSubtargetInfo.inc"Go to the source code of this file.
Namespaces | |
| namespace | llvm |
| This is an optimization pass for GlobalISel generic memory operations. | |
| namespace | llvm::PPC |
| Define some predicates that are used for node matching. | |
| namespace | llvm::PPCII |
| PPCII - This namespace holds all of the PowerPC target-specific per-instruction flags. | |
Macros | |
| #define | GET_REGINFO_ENUM |
| #define | GET_INSTRINFO_ENUM |
| #define | GET_INSTRINFO_SCHED_ENUM |
| #define | GET_INSTRINFO_MC_HELPER_DECLS |
| #define | GET_SUBTARGETINFO_ENUM |
| #define | PPC_REGS0_7(X) |
| #define | PPC_REGS0_31(X) |
| #define | PPC_REGS_EVEN0_30(X) |
| #define | PPC_REGS0_63(X) |
| #define | PPC_REGS_NO0_31(Z, X) |
| #define | PPC_REGS_LO_HI(LO, HI) |
| #define | PPC_REGS0_7(X) |
| #define | PPC_REGS0_3(X) |
| #define | DEFINE_PPC_REGCLASSES |
Typedefs | |
| using | MCPhysReg |
| An unsigned integer type large enough to represent all physical registers, but not necessarily virtual registers. | |
Enumerations | |
| enum | { llvm::PPCII::PPC970_First = 0x1 , llvm::PPCII::PPC970_Single = 0x2 , llvm::PPCII::PPC970_Cracked = 0x4 , llvm::PPCII::PPC970_Shift = 3 , llvm::PPCII::PPC970_Mask = 0x07 << PPC970_Shift } |
| enum | llvm::PPCII::PPC970_Unit { llvm::PPCII::PPC970_Pseudo = 0 << PPC970_Shift , llvm::PPCII::PPC970_FXU = 1 << PPC970_Shift , llvm::PPCII::PPC970_LSU = 2 << PPC970_Shift , llvm::PPCII::PPC970_FPU = 3 << PPC970_Shift , llvm::PPCII::PPC970_CRU = 4 << PPC970_Shift , llvm::PPCII::PPC970_VALU = 5 << PPC970_Shift , llvm::PPCII::PPC970_VPERM = 6 << PPC970_Shift , llvm::PPCII::PPC970_BRU = 7 << PPC970_Shift } |
| enum | { llvm::PPCII::NewDef_Shift = 6 , llvm::PPCII::XFormMemOp = 0x1 << NewDef_Shift , llvm::PPCII::Prefixed = 0x1 << (NewDef_Shift + 1) , llvm::PPCII::SExt32To64 = 0x1 << (NewDef_Shift + 2) , llvm::PPCII::ZExt32To64 = 0x1 << (NewDef_Shift + 3) , llvm::PPCII::MemriOp = 0x1 << (NewDef_Shift + 4) } |
| #define DEFINE_PPC_REGCLASSES |
Definition at line 258 of file PPCMCTargetDesc.h.
| #define GET_INSTRINFO_ENUM |
Definition at line 190 of file PPCMCTargetDesc.h.
| #define GET_INSTRINFO_MC_HELPER_DECLS |
Definition at line 192 of file PPCMCTargetDesc.h.
| #define GET_INSTRINFO_SCHED_ENUM |
Definition at line 191 of file PPCMCTargetDesc.h.
| #define GET_REGINFO_ENUM |
Definition at line 185 of file PPCMCTargetDesc.h.
| #define GET_SUBTARGETINFO_ENUM |
Definition at line 195 of file PPCMCTargetDesc.h.
| #define PPC_REGS0_3 | ( | X | ) |
| #define PPC_REGS0_31 | ( | X | ) |
| #define PPC_REGS0_63 | ( | X | ) |
Definition at line 216 of file PPCMCTargetDesc.h.
| #define PPC_REGS0_7 | ( | X | ) |
| #define PPC_REGS0_7 | ( | X | ) |
| #define PPC_REGS_EVEN0_30 | ( | X | ) |
| #define PPC_REGS_LO_HI | ( | LO, | |
| HI ) |
Definition at line 234 of file PPCMCTargetDesc.h.
| #define PPC_REGS_NO0_31 | ( | Z, | |
| X ) |
| using llvm::MCPhysReg |
An unsigned integer type large enough to represent all physical registers, but not necessarily virtual registers.
Definition at line 21 of file MCRegister.h.