LLVM
15.0.0git
lib
Target
RISCV
MCTargetDesc
RISCVMCTargetDesc.h
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//===-- RISCVMCTargetDesc.h - RISCV Target Descriptions ---------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file provides RISCV specific target descriptions.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVMCTARGETDESC_H
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#define LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVMCTARGETDESC_H
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#include "llvm/Config/config.h"
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#include "
llvm/MC/MCTargetOptions.h
"
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#include "
llvm/Support/DataTypes.h
"
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#include <memory>
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namespace
llvm
{
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class
MCAsmBackend;
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class
MCCodeEmitter;
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class
MCContext;
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class
MCInstrInfo;
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class
MCObjectTargetWriter;
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class
MCRegisterInfo;
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class
MCSubtargetInfo;
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class
Target
;
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MCCodeEmitter *
createRISCVMCCodeEmitter
(
const
MCInstrInfo &MCII,
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MCContext &Ctx);
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MCAsmBackend *
createRISCVAsmBackend
(
const
Target
&
T
,
const
MCSubtargetInfo &STI,
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const
MCRegisterInfo &
MRI
,
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const
MCTargetOptions &
Options
);
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std::unique_ptr<MCObjectTargetWriter>
createRISCVELFObjectWriter
(uint8_t OSABI,
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bool
Is64Bit);
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}
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// Defines symbolic names for RISC-V registers.
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#define GET_REGINFO_ENUM
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#include "RISCVGenRegisterInfo.inc"
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// Defines symbolic names for RISC-V instructions.
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#define GET_INSTRINFO_ENUM
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#include "RISCVGenInstrInfo.inc"
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#define GET_SUBTARGETINFO_ENUM
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#include "RISCVGenSubtargetInfo.inc"
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#endif
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition:
AddressRanges.h:17
MCTargetOptions.h
llvm::AMDGPU::Exp::Target
Target
Definition:
SIDefines.h:851
T
#define T
Definition:
Mips16ISelLowering.cpp:341
llvm::createRISCVMCCodeEmitter
MCCodeEmitter * createRISCVMCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx)
Definition:
RISCVMCCodeEmitter.cpp:96
llvm::createRISCVAsmBackend
MCAsmBackend * createRISCVAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
Definition:
RISCVAsmBackend.cpp:640
Options
const char LLVMTargetMachineRef LLVMPassBuilderOptionsRef Options
Definition:
PassBuilderBindings.cpp:48
llvm::createRISCVELFObjectWriter
std::unique_ptr< MCObjectTargetWriter > createRISCVELFObjectWriter(uint8_t OSABI, bool Is64Bit)
Definition:
RISCVELFObjectWriter.cpp:173
MRI
unsigned const MachineRegisterInfo * MRI
Definition:
AArch64AdvSIMDScalarPass.cpp:105
DataTypes.h
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