LLVM  14.0.0git
RISCVMCTargetDesc.h
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1 //===-- RISCVMCTargetDesc.h - RISCV Target Descriptions ---------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file provides RISCV specific target descriptions.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVMCTARGETDESC_H
14 #define LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVMCTARGETDESC_H
15 
16 #include "llvm/Config/config.h"
18 #include "llvm/Support/DataTypes.h"
19 #include <memory>
20 
21 namespace llvm {
22 class MCAsmBackend;
23 class MCCodeEmitter;
24 class MCContext;
25 class MCInstrInfo;
26 class MCObjectTargetWriter;
27 class MCRegisterInfo;
28 class MCSubtargetInfo;
29 class Target;
30 
31 MCCodeEmitter *createRISCVMCCodeEmitter(const MCInstrInfo &MCII,
32  const MCRegisterInfo &MRI,
33  MCContext &Ctx);
34 
35 MCAsmBackend *createRISCVAsmBackend(const Target &T, const MCSubtargetInfo &STI,
36  const MCRegisterInfo &MRI,
37  const MCTargetOptions &Options);
38 
39 std::unique_ptr<MCObjectTargetWriter> createRISCVELFObjectWriter(uint8_t OSABI,
40  bool Is64Bit);
41 }
42 
43 // Defines symbolic names for RISC-V registers.
44 #define GET_REGINFO_ENUM
45 #include "RISCVGenRegisterInfo.inc"
46 
47 // Defines symbolic names for RISC-V instructions.
48 #define GET_INSTRINFO_ENUM
49 #include "RISCVGenInstrInfo.inc"
50 
51 #define GET_SUBTARGETINFO_ENUM
52 #include "RISCVGenSubtargetInfo.inc"
53 
54 #endif
llvm
---------------------— PointerInfo ------------------------------------—
Definition: AllocatorList.h:23
MCTargetOptions.h
llvm::AMDGPU::Exp::Target
Target
Definition: SIDefines.h:732
T
#define T
Definition: Mips16ISelLowering.cpp:341
llvm::createRISCVAsmBackend
MCAsmBackend * createRISCVAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
Definition: RISCVAsmBackend.cpp:637
Options
const char LLVMTargetMachineRef LLVMPassBuilderOptionsRef Options
Definition: PassBuilderBindings.cpp:48
llvm::createRISCVMCCodeEmitter
MCCodeEmitter * createRISCVMCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, MCContext &Ctx)
Definition: RISCVMCCodeEmitter.cpp:95
llvm::createRISCVELFObjectWriter
std::unique_ptr< MCObjectTargetWriter > createRISCVELFObjectWriter(uint8_t OSABI, bool Is64Bit)
Definition: RISCVELFObjectWriter.cpp:173
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
DataTypes.h