LLVM 17.0.0git
RISCVAsmBackend.cpp
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1//===-- RISCVAsmBackend.cpp - RISCV Assembler Backend ---------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#include "RISCVAsmBackend.h"
10#include "RISCVMCExpr.h"
11#include "llvm/ADT/APInt.h"
12#include "llvm/MC/MCAsmInfo.h"
13#include "llvm/MC/MCAsmLayout.h"
14#include "llvm/MC/MCAssembler.h"
15#include "llvm/MC/MCContext.h"
18#include "llvm/MC/MCExpr.h"
20#include "llvm/MC/MCSymbol.h"
21#include "llvm/MC/MCValue.h"
22#include "llvm/Support/Endian.h"
25#include "llvm/Support/LEB128.h"
27
28using namespace llvm;
29
30std::optional<MCFixupKind> RISCVAsmBackend::getFixupKind(StringRef Name) const {
32 unsigned Type;
34#define ELF_RELOC(X, Y) .Case(#X, Y)
35#include "llvm/BinaryFormat/ELFRelocs/RISCV.def"
36#undef ELF_RELOC
37 .Case("BFD_RELOC_NONE", ELF::R_RISCV_NONE)
38 .Case("BFD_RELOC_32", ELF::R_RISCV_32)
39 .Case("BFD_RELOC_64", ELF::R_RISCV_64)
40 .Default(-1u);
41 if (Type != -1u)
42 return static_cast<MCFixupKind>(FirstLiteralRelocationKind + Type);
43 }
44 return std::nullopt;
45}
46
47const MCFixupKindInfo &
49 const static MCFixupKindInfo Infos[] = {
50 // This table *must* be in the order that the fixup_* kinds are defined in
51 // RISCVFixupKinds.h.
52 //
53 // name offset bits flags
54 {"fixup_riscv_hi20", 12, 20, 0},
55 {"fixup_riscv_lo12_i", 20, 12, 0},
56 {"fixup_riscv_lo12_s", 0, 32, 0},
57 {"fixup_riscv_pcrel_hi20", 12, 20,
59 {"fixup_riscv_pcrel_lo12_i", 20, 12,
61 {"fixup_riscv_pcrel_lo12_s", 0, 32,
63 {"fixup_riscv_got_hi20", 12, 20, MCFixupKindInfo::FKF_IsPCRel},
64 {"fixup_riscv_tprel_hi20", 12, 20, 0},
65 {"fixup_riscv_tprel_lo12_i", 20, 12, 0},
66 {"fixup_riscv_tprel_lo12_s", 0, 32, 0},
67 {"fixup_riscv_tprel_add", 0, 0, 0},
68 {"fixup_riscv_tls_got_hi20", 12, 20, MCFixupKindInfo::FKF_IsPCRel},
69 {"fixup_riscv_tls_gd_hi20", 12, 20, MCFixupKindInfo::FKF_IsPCRel},
70 {"fixup_riscv_jal", 12, 20, MCFixupKindInfo::FKF_IsPCRel},
71 {"fixup_riscv_branch", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
72 {"fixup_riscv_rvc_jump", 2, 11, MCFixupKindInfo::FKF_IsPCRel},
73 {"fixup_riscv_rvc_branch", 0, 16, MCFixupKindInfo::FKF_IsPCRel},
74 {"fixup_riscv_call", 0, 64, MCFixupKindInfo::FKF_IsPCRel},
75 {"fixup_riscv_call_plt", 0, 64, MCFixupKindInfo::FKF_IsPCRel},
76 {"fixup_riscv_relax", 0, 0, 0},
77 {"fixup_riscv_align", 0, 0, 0},
78
79 {"fixup_riscv_set_8", 0, 8, 0},
80 {"fixup_riscv_add_8", 0, 8, 0},
81 {"fixup_riscv_sub_8", 0, 8, 0},
82
83 {"fixup_riscv_set_16", 0, 16, 0},
84 {"fixup_riscv_add_16", 0, 16, 0},
85 {"fixup_riscv_sub_16", 0, 16, 0},
86
87 {"fixup_riscv_set_32", 0, 32, 0},
88 {"fixup_riscv_add_32", 0, 32, 0},
89 {"fixup_riscv_sub_32", 0, 32, 0},
90
91 {"fixup_riscv_add_64", 0, 64, 0},
92 {"fixup_riscv_sub_64", 0, 64, 0},
93
94 {"fixup_riscv_set_6b", 2, 6, 0},
95 {"fixup_riscv_sub_6b", 2, 6, 0},
96 };
97 static_assert((std::size(Infos)) == RISCV::NumTargetFixupKinds,
98 "Not all fixup kinds added to Infos array");
99
100 // Fixup kinds from .reloc directive are like R_RISCV_NONE. They
101 // do not require any extra processing.
102 if (Kind >= FirstLiteralRelocationKind)
104
105 if (Kind < FirstTargetFixupKind)
107
108 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
109 "Invalid kind!");
110 return Infos[Kind - FirstTargetFixupKind];
111}
112
113// If linker relaxation is enabled, or the relax option had previously been
114// enabled, always emit relocations even if the fixup can be resolved. This is
115// necessary for correctness as offsets may change during relaxation.
117 const MCFixup &Fixup,
118 const MCValue &Target) {
119 if (Fixup.getKind() >= FirstLiteralRelocationKind)
120 return true;
121 switch (Fixup.getTargetKind()) {
122 default:
123 break;
124 case FK_Data_1:
125 case FK_Data_2:
126 case FK_Data_4:
127 case FK_Data_8:
128 if (Target.isAbsolute())
129 return false;
130 break;
134 return true;
135 }
136
137 return STI.hasFeature(RISCV::FeatureRelax) || ForceRelocs;
138}
139
141 bool Resolved,
143 const MCRelaxableFragment *DF,
144 const MCAsmLayout &Layout,
145 const bool WasForced) const {
146 int64_t Offset = int64_t(Value);
147 unsigned Kind = Fixup.getTargetKind();
148
149 // We only do conditional branch relaxation when the symbol is resolved.
150 // For conditional branch, the immediate must be in the range
151 // [-4096, 4094].
152 if (Kind == RISCV::fixup_riscv_branch)
153 return Resolved && !isInt<13>(Offset);
154
155 // Return true if the symbol is actually unresolved.
156 // Resolved could be always false when shouldForceRelocation return true.
157 // We use !WasForced to indicate that the symbol is unresolved and not forced
158 // by shouldForceRelocation.
159 if (!Resolved && !WasForced)
160 return true;
161
162 switch (Kind) {
163 default:
164 return false;
166 // For compressed branch instructions the immediate must be
167 // in the range [-256, 254].
168 return Offset > 254 || Offset < -256;
170 // For compressed jump instructions the immediate must be
171 // in the range [-2048, 2046].
172 return Offset > 2046 || Offset < -2048;
173 }
174}
175
177 const MCSubtargetInfo &STI) const {
178 MCInst Res;
179 switch (Inst.getOpcode()) {
180 default:
181 llvm_unreachable("Opcode not expected!");
182 case RISCV::C_BEQZ:
183 case RISCV::C_BNEZ:
184 case RISCV::C_J:
185 case RISCV::C_JAL: {
186 bool Success = RISCVRVC::uncompress(Res, Inst, STI);
187 assert(Success && "Can't uncompress instruction");
188 (void)Success;
189 break;
190 }
191 case RISCV::BEQ:
192 case RISCV::BNE:
193 case RISCV::BLT:
194 case RISCV::BGE:
195 case RISCV::BLTU:
196 case RISCV::BGEU:
198 Res.addOperand(Inst.getOperand(0));
199 Res.addOperand(Inst.getOperand(1));
200 Res.addOperand(Inst.getOperand(2));
201 break;
202 }
203 Inst = std::move(Res);
204}
205
207 MCAsmLayout &Layout,
208 bool &WasRelaxed) const {
209 MCContext &C = Layout.getAssembler().getContext();
210
211 int64_t LineDelta = DF.getLineDelta();
212 const MCExpr &AddrDelta = DF.getAddrDelta();
213 SmallVectorImpl<char> &Data = DF.getContents();
214 SmallVectorImpl<MCFixup> &Fixups = DF.getFixups();
215 size_t OldSize = Data.size();
216
217 int64_t Value;
218 bool IsAbsolute = AddrDelta.evaluateKnownAbsolute(Value, Layout);
219 assert(IsAbsolute && "CFA with invalid expression");
220 (void)IsAbsolute;
221
222 Data.clear();
223 Fixups.clear();
225
226 // INT64_MAX is a signal that this is actually a DW_LNE_end_sequence.
227 if (LineDelta != INT64_MAX) {
228 OS << uint8_t(dwarf::DW_LNS_advance_line);
229 encodeSLEB128(LineDelta, OS);
230 }
231
232 unsigned Offset;
233 std::pair<MCFixupKind, MCFixupKind> Fixup;
234
235 // According to the DWARF specification, the `DW_LNS_fixed_advance_pc` opcode
236 // takes a single unsigned half (unencoded) operand. The maximum encodable
237 // value is therefore 65535. Set a conservative upper bound for relaxation.
238 if (Value > 60000) {
239 unsigned PtrSize = C.getAsmInfo()->getCodePointerSize();
240
241 OS << uint8_t(dwarf::DW_LNS_extended_op);
242 encodeULEB128(PtrSize + 1, OS);
243
244 OS << uint8_t(dwarf::DW_LNE_set_address);
245 Offset = OS.tell();
246 assert((PtrSize == 4 || PtrSize == 8) && "Unexpected pointer size");
248 OS.write_zeros(PtrSize);
249 } else {
250 OS << uint8_t(dwarf::DW_LNS_fixed_advance_pc);
251 Offset = OS.tell();
253 support::endian::write<uint16_t>(OS, 0, support::little);
254 }
255
256 const MCBinaryExpr &MBE = cast<MCBinaryExpr>(AddrDelta);
257 Fixups.push_back(MCFixup::create(Offset, MBE.getLHS(), std::get<0>(Fixup)));
258 Fixups.push_back(MCFixup::create(Offset, MBE.getRHS(), std::get<1>(Fixup)));
259
260 if (LineDelta == INT64_MAX) {
261 OS << uint8_t(dwarf::DW_LNS_extended_op);
262 OS << uint8_t(1);
263 OS << uint8_t(dwarf::DW_LNE_end_sequence);
264 } else {
265 OS << uint8_t(dwarf::DW_LNS_copy);
266 }
267
268 WasRelaxed = OldSize != Data.size();
269 return true;
270}
271
273 MCAsmLayout &Layout,
274 bool &WasRelaxed) const {
275
276 const MCExpr &AddrDelta = DF.getAddrDelta();
277 SmallVectorImpl<char> &Data = DF.getContents();
278 SmallVectorImpl<MCFixup> &Fixups = DF.getFixups();
279 size_t OldSize = Data.size();
280
281 int64_t Value;
282 bool IsAbsolute = AddrDelta.evaluateKnownAbsolute(Value, Layout);
283 assert(IsAbsolute && "CFA with invalid expression");
284 (void)IsAbsolute;
285
286 Data.clear();
287 Fixups.clear();
289
290 assert(
292 1 &&
293 "expected 1-byte alignment");
294 if (Value == 0) {
295 WasRelaxed = OldSize != Data.size();
296 return true;
297 }
298
299 auto AddFixups = [&Fixups, &AddrDelta](unsigned Offset,
300 std::pair<unsigned, unsigned> Fixup) {
301 const MCBinaryExpr &MBE = cast<MCBinaryExpr>(AddrDelta);
302 Fixups.push_back(MCFixup::create(
303 Offset, MBE.getLHS(), static_cast<MCFixupKind>(std::get<0>(Fixup))));
304 Fixups.push_back(MCFixup::create(
305 Offset, MBE.getRHS(), static_cast<MCFixupKind>(std::get<1>(Fixup))));
306 };
307
308 if (isUIntN(6, Value)) {
309 OS << uint8_t(dwarf::DW_CFA_advance_loc);
311 } else if (isUInt<8>(Value)) {
312 OS << uint8_t(dwarf::DW_CFA_advance_loc1);
313 support::endian::write<uint8_t>(OS, 0, support::little);
315 } else if (isUInt<16>(Value)) {
316 OS << uint8_t(dwarf::DW_CFA_advance_loc2);
317 support::endian::write<uint16_t>(OS, 0, support::little);
319 } else if (isUInt<32>(Value)) {
320 OS << uint8_t(dwarf::DW_CFA_advance_loc4);
321 support::endian::write<uint32_t>(OS, 0, support::little);
323 } else {
324 llvm_unreachable("unsupported CFA encoding");
325 }
326
327 WasRelaxed = OldSize != Data.size();
328 return true;
329}
330
331// Given a compressed control flow instruction this function returns
332// the expanded instruction.
333unsigned RISCVAsmBackend::getRelaxedOpcode(unsigned Op) const {
334 switch (Op) {
335 default:
336 return Op;
337 case RISCV::C_BEQZ:
338 return RISCV::BEQ;
339 case RISCV::C_BNEZ:
340 return RISCV::BNE;
341 case RISCV::C_J:
342 case RISCV::C_JAL: // fall through.
343 return RISCV::JAL;
344 case RISCV::BEQ:
345 return RISCV::PseudoLongBEQ;
346 case RISCV::BNE:
347 return RISCV::PseudoLongBNE;
348 case RISCV::BLT:
349 return RISCV::PseudoLongBLT;
350 case RISCV::BGE:
351 return RISCV::PseudoLongBGE;
352 case RISCV::BLTU:
353 return RISCV::PseudoLongBLTU;
354 case RISCV::BGEU:
355 return RISCV::PseudoLongBGEU;
356 }
357}
358
360 const MCSubtargetInfo &STI) const {
361 return getRelaxedOpcode(Inst.getOpcode()) != Inst.getOpcode();
362}
363
365 const MCSubtargetInfo *STI) const {
366 // We mostly follow binutils' convention here: align to even boundary with a
367 // 0-fill padding. We emit up to 1 2-byte nop, though we use c.nop if RVC is
368 // enabled or 0-fill otherwise. The remainder is now padded with 4-byte nops.
369
370 // Instructions always are at even addresses. We must be in a data area or
371 // be unaligned due to some other reason.
372 if (Count % 2) {
373 OS.write("\0", 1);
374 Count -= 1;
375 }
376
377 bool UseCompressedNop = STI->hasFeature(RISCV::FeatureStdExtC) ||
378 STI->hasFeature(RISCV::FeatureExtZca);
379 // The canonical nop on RVC is c.nop.
380 if (Count % 4 == 2) {
381 OS.write(UseCompressedNop ? "\x01\0" : "\0\0", 2);
382 Count -= 2;
383 }
384
385 // The canonical nop on RISC-V is addi x0, x0, 0.
386 for (; Count >= 4; Count -= 4)
387 OS.write("\x13\0\0\0", 4);
388
389 return true;
390}
391
393 MCContext &Ctx) {
394 switch (Fixup.getTargetKind()) {
395 default:
396 llvm_unreachable("Unknown fixup kind!");
400 llvm_unreachable("Relocation should be unconditionally forced\n");
412 case FK_Data_1:
413 case FK_Data_2:
414 case FK_Data_4:
415 case FK_Data_8:
416 case FK_Data_6b:
417 return Value;
419 return Value & 0x03;
423 return Value & 0xfff;
427 return (((Value >> 5) & 0x7f) << 25) | ((Value & 0x1f) << 7);
431 // Add 1 if bit 11 is 1, to compensate for low 12 bits being negative.
432 return ((Value + 0x800) >> 12) & 0xfffff;
434 if (!isInt<21>(Value))
435 Ctx.reportError(Fixup.getLoc(), "fixup value out of range");
436 if (Value & 0x1)
437 Ctx.reportError(Fixup.getLoc(), "fixup value must be 2-byte aligned");
438 // Need to produce imm[19|10:1|11|19:12] from the 21-bit Value.
439 unsigned Sbit = (Value >> 20) & 0x1;
440 unsigned Hi8 = (Value >> 12) & 0xff;
441 unsigned Mid1 = (Value >> 11) & 0x1;
442 unsigned Lo10 = (Value >> 1) & 0x3ff;
443 // Inst{31} = Sbit;
444 // Inst{30-21} = Lo10;
445 // Inst{20} = Mid1;
446 // Inst{19-12} = Hi8;
447 Value = (Sbit << 19) | (Lo10 << 9) | (Mid1 << 8) | Hi8;
448 return Value;
449 }
451 if (!isInt<13>(Value))
452 Ctx.reportError(Fixup.getLoc(), "fixup value out of range");
453 if (Value & 0x1)
454 Ctx.reportError(Fixup.getLoc(), "fixup value must be 2-byte aligned");
455 // Need to extract imm[12], imm[10:5], imm[4:1], imm[11] from the 13-bit
456 // Value.
457 unsigned Sbit = (Value >> 12) & 0x1;
458 unsigned Hi1 = (Value >> 11) & 0x1;
459 unsigned Mid6 = (Value >> 5) & 0x3f;
460 unsigned Lo4 = (Value >> 1) & 0xf;
461 // Inst{31} = Sbit;
462 // Inst{30-25} = Mid6;
463 // Inst{11-8} = Lo4;
464 // Inst{7} = Hi1;
465 Value = (Sbit << 31) | (Mid6 << 25) | (Lo4 << 8) | (Hi1 << 7);
466 return Value;
467 }
470 // Jalr will add UpperImm with the sign-extended 12-bit LowerImm,
471 // we need to add 0x800ULL before extract upper bits to reflect the
472 // effect of the sign extension.
473 uint64_t UpperImm = (Value + 0x800ULL) & 0xfffff000ULL;
474 uint64_t LowerImm = Value & 0xfffULL;
475 return UpperImm | ((LowerImm << 20) << 32);
476 }
478 // Need to produce offset[11|4|9:8|10|6|7|3:1|5] from the 11-bit Value.
479 unsigned Bit11 = (Value >> 11) & 0x1;
480 unsigned Bit4 = (Value >> 4) & 0x1;
481 unsigned Bit9_8 = (Value >> 8) & 0x3;
482 unsigned Bit10 = (Value >> 10) & 0x1;
483 unsigned Bit6 = (Value >> 6) & 0x1;
484 unsigned Bit7 = (Value >> 7) & 0x1;
485 unsigned Bit3_1 = (Value >> 1) & 0x7;
486 unsigned Bit5 = (Value >> 5) & 0x1;
487 Value = (Bit11 << 10) | (Bit4 << 9) | (Bit9_8 << 7) | (Bit10 << 6) |
488 (Bit6 << 5) | (Bit7 << 4) | (Bit3_1 << 1) | Bit5;
489 return Value;
490 }
492 // Need to produce offset[8|4:3], [reg 3 bit], offset[7:6|2:1|5]
493 unsigned Bit8 = (Value >> 8) & 0x1;
494 unsigned Bit7_6 = (Value >> 6) & 0x3;
495 unsigned Bit5 = (Value >> 5) & 0x1;
496 unsigned Bit4_3 = (Value >> 3) & 0x3;
497 unsigned Bit2_1 = (Value >> 1) & 0x3;
498 Value = (Bit8 << 12) | (Bit4_3 << 10) | (Bit7_6 << 5) | (Bit2_1 << 3) |
499 (Bit5 << 2);
500 return Value;
501 }
502
503 }
504}
505
507 const MCAssembler &Asm, const MCAsmLayout &Layout, const MCFixup &Fixup,
508 const MCFragment *DF, const MCValue &Target, uint64_t &Value,
509 bool &WasForced) {
510 const MCFixup *AUIPCFixup;
511 const MCFragment *AUIPCDF;
512 MCValue AUIPCTarget;
513 switch (Fixup.getTargetKind()) {
514 default:
515 llvm_unreachable("Unexpected fixup kind!");
517 AUIPCFixup = &Fixup;
518 AUIPCDF = DF;
519 AUIPCTarget = Target;
520 break;
523 AUIPCFixup = cast<RISCVMCExpr>(Fixup.getValue())->getPCRelHiFixup(&AUIPCDF);
524 if (!AUIPCFixup) {
525 Asm.getContext().reportError(Fixup.getLoc(),
526 "could not find corresponding %pcrel_hi");
527 return true;
528 }
529
530 // MCAssembler::evaluateFixup will emit an error for this case when it sees
531 // the %pcrel_hi, so don't duplicate it when also seeing the %pcrel_lo.
532 const MCExpr *AUIPCExpr = AUIPCFixup->getValue();
533 if (!AUIPCExpr->evaluateAsRelocatable(AUIPCTarget, &Layout, AUIPCFixup))
534 return true;
535 break;
536 }
537 }
538
539 if (!AUIPCTarget.getSymA() || AUIPCTarget.getSymB())
540 return false;
541
542 const MCSymbolRefExpr *A = AUIPCTarget.getSymA();
543 const MCSymbol &SA = A->getSymbol();
544 if (A->getKind() != MCSymbolRefExpr::VK_None || SA.isUndefined())
545 return false;
546
547 auto *Writer = Asm.getWriterPtr();
548 if (!Writer)
549 return false;
550
551 bool IsResolved = Writer->isSymbolRefDifferenceFullyResolvedImpl(
552 Asm, SA, *AUIPCDF, false, true);
553 if (!IsResolved)
554 return false;
555
556 Value = Layout.getSymbolOffset(SA) + AUIPCTarget.getConstant();
557 Value -= Layout.getFragmentOffset(AUIPCDF) + AUIPCFixup->getOffset();
558
559 if (shouldForceRelocation(Asm, *AUIPCFixup, AUIPCTarget)) {
560 WasForced = true;
561 return false;
562 }
563
564 return true;
565}
566
568 const MCValue &Target,
570 bool IsResolved,
571 const MCSubtargetInfo *STI) const {
572 MCFixupKind Kind = Fixup.getKind();
573 if (Kind >= FirstLiteralRelocationKind)
574 return;
575 MCContext &Ctx = Asm.getContext();
577 if (!Value)
578 return; // Doesn't change encoding.
579 // Apply any target-specific value adjustments.
581
582 // Shift the value into position.
583 Value <<= Info.TargetOffset;
584
585 unsigned Offset = Fixup.getOffset();
586 unsigned NumBytes = alignTo(Info.TargetSize + Info.TargetOffset, 8) / 8;
587
588 assert(Offset + NumBytes <= Data.size() && "Invalid fixup offset!");
589
590 // For each byte of the fragment that the fixup touches, mask in the
591 // bits from the fixup value.
592 for (unsigned i = 0; i != NumBytes; ++i) {
593 Data[Offset + i] |= uint8_t((Value >> (i * 8)) & 0xff);
594 }
595}
596
597// Linker relaxation may change code size. We have to insert Nops
598// for .align directive when linker relaxation enabled. So then Linker
599// could satisfy alignment by removing Nops.
600// The function return the total Nops Size we need to insert.
602 const MCAlignFragment &AF, unsigned &Size) {
603 // Calculate Nops Size only when linker relaxation enabled.
604 const MCSubtargetInfo *STI = AF.getSubtargetInfo();
605 if (!STI->hasFeature(RISCV::FeatureRelax))
606 return false;
607
608 bool UseCompressedNop = STI->hasFeature(RISCV::FeatureStdExtC) ||
609 STI->hasFeature(RISCV::FeatureExtZca);
610 unsigned MinNopLen = UseCompressedNop ? 2 : 4;
611
612 if (AF.getAlignment() <= MinNopLen) {
613 return false;
614 } else {
615 Size = AF.getAlignment().value() - MinNopLen;
616 return true;
617 }
618}
619
620// We need to insert R_RISCV_ALIGN relocation type to indicate the
621// position of Nops and the total bytes of the Nops have been inserted
622// when linker relaxation enabled.
623// The function insert fixup_riscv_align fixup which eventually will
624// transfer to R_RISCV_ALIGN relocation type.
626 const MCAsmLayout &Layout,
627 MCAlignFragment &AF) {
628 // Insert the fixup only when linker relaxation enabled.
629 const MCSubtargetInfo *STI = AF.getSubtargetInfo();
630 if (!STI->hasFeature(RISCV::FeatureRelax))
631 return false;
632
633 // Calculate total Nops we need to insert. If there are none to insert
634 // then simply return.
635 unsigned Count;
636 if (!shouldInsertExtraNopBytesForCodeAlign(AF, Count) || (Count == 0))
637 return false;
638
639 MCContext &Ctx = Asm.getContext();
640 const MCExpr *Dummy = MCConstantExpr::create(0, Ctx);
641 // Create fixup_riscv_align fixup.
642 MCFixup Fixup =
644
645 uint64_t FixedValue = 0;
646 MCValue NopBytes = MCValue::get(Count);
647
648 Asm.getWriter().recordRelocation(Asm, Layout, &AF, Fixup, NopBytes,
649 FixedValue);
650
651 return true;
652}
653
654std::unique_ptr<MCObjectTargetWriter>
656 return createRISCVELFObjectWriter(OSABI, Is64Bit);
657}
658
660 const MCSubtargetInfo &STI,
661 const MCRegisterInfo &MRI,
662 const MCTargetOptions &Options) {
663 const Triple &TT = STI.getTargetTriple();
664 uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TT.getOS());
665 return new RISCVAsmBackend(STI, OSABI, TT.isArch64Bit(), Options);
666}
unsigned const MachineRegisterInfo * MRI
static uint64_t adjustFixupValue(const MCFixup &Fixup, const MCValue &Target, uint64_t Value, MCContext &Ctx, const Triple &TheTriple, bool IsResolved)
#define Success
This file implements a class to represent arbitrary precision integral constant values and operations...
static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
static RegisterPass< DebugifyFunctionPass > DF("debugify-function", "Attach debug info to a function")
std::string Name
uint64_t Size
static LVOptions Options
Definition: LVOptions.cpp:25
PowerPC TLS Dynamic Call Fixup
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
raw_pwrite_stream & OS
Align getAlignment() const
Definition: MCFragment.h:322
const MCSubtargetInfo * getSubtargetInfo() const
Definition: MCFragment.h:336
Generic interface to target specific assembler backends.
Definition: MCAsmBackend.h:41
virtual const MCFixupKindInfo & getFixupKindInfo(MCFixupKind Kind) const
Get information on a fixup kind.
unsigned getMinInstAlignment() const
Definition: MCAsmInfo.h:645
Encapsulates the layout of an assembly file at a particular point in time.
Definition: MCAsmLayout.h:28
bool getSymbolOffset(const MCSymbol &S, uint64_t &Val) const
Get the offset of the given symbol, as computed in the current layout.
Definition: MCFragment.cpp:152
uint64_t getFragmentOffset(const MCFragment *F) const
Get the offset of the given fragment inside its containing section.
Definition: MCFragment.cpp:96
MCAssembler & getAssembler() const
Get the assembler object this is a layout for.
Definition: MCAsmLayout.h:50
MCContext & getContext() const
Definition: MCAssembler.h:321
Binary assembler expressions.
Definition: MCExpr.h:481
const MCExpr * getLHS() const
Get the left-hand side expression of the binary operator.
Definition: MCExpr.h:628
const MCExpr * getRHS() const
Get the right-hand side expression of the binary operator.
Definition: MCExpr.h:631
static const MCConstantExpr * create(int64_t Value, MCContext &Ctx, bool PrintInHex=false, unsigned SizeInBytes=0)
Definition: MCExpr.cpp:194
Context object for machine code objects.
Definition: MCContext.h:76
const MCAsmInfo * getAsmInfo() const
Definition: MCContext.h:446
void reportError(SMLoc L, const Twine &Msg)
Definition: MCContext.cpp:1055
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:35
bool evaluateKnownAbsolute(int64_t &Res, const MCAsmLayout &Layout) const
Definition: MCExpr.cpp:561
bool evaluateAsRelocatable(MCValue &Res, const MCAsmLayout *Layout, const MCFixup *Fixup) const
Try to evaluate the expression to a relocatable value, i.e.
Definition: MCExpr.cpp:749
Encode information on a single operation to perform on a byte sequence (e.g., an encoded instruction)...
Definition: MCFixup.h:71
const MCExpr * getValue() const
Definition: MCFixup.h:105
uint32_t getOffset() const
Definition: MCFixup.h:102
static MCFixup create(uint32_t Offset, const MCExpr *Value, MCFixupKind Kind, SMLoc Loc=SMLoc())
Definition: MCFixup.h:87
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
unsigned getOpcode() const
Definition: MCInst.h:198
void addOperand(const MCOperand Op)
Definition: MCInst.h:210
void setOpcode(unsigned Op)
Definition: MCInst.h:197
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:206
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
A relaxable fragment holds on to its MCInst, since it may need to be relaxed during the assembler lay...
Definition: MCFragment.h:270
Generic base class for all target subtargets.
bool hasFeature(unsigned Feature) const
const Triple & getTargetTriple() const
Represent a reference to a symbol from inside an expression.
Definition: MCExpr.h:192
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:41
bool isUndefined(bool SetUsed=true) const
isUndefined - Check if this symbol undefined (i.e., implicitly defined).
Definition: MCSymbol.h:257
This represents an "assembler immediate".
Definition: MCValue.h:36
int64_t getConstant() const
Definition: MCValue.h:43
static MCValue get(const MCSymbolRefExpr *SymA, const MCSymbolRefExpr *SymB=nullptr, int64_t Val=0, uint32_t RefKind=0)
Definition: MCValue.h:59
const MCSymbolRefExpr * getSymB() const
Definition: MCValue.h:45
const MCSymbolRefExpr * getSymA() const
Definition: MCValue.h:44
MutableArrayRef - Represent a mutable reference to an array (0 or more elements consecutively in memo...
Definition: ArrayRef.h:305
std::unique_ptr< MCObjectTargetWriter > createObjectTargetWriter() const override
void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup, const MCValue &Target, MutableArrayRef< char > Data, uint64_t Value, bool IsResolved, const MCSubtargetInfo *STI) const override
Apply the Value for given Fixup into the provided data fragment, at the offset specified by the fixup...
void relaxInstruction(MCInst &Inst, const MCSubtargetInfo &STI) const override
Relax the instruction in the given fragment to the next wider instruction.
bool shouldInsertFixupForCodeAlign(MCAssembler &Asm, const MCAsmLayout &Layout, MCAlignFragment &AF) override
Hook which indicates if the target requires a fixup to be generated when handling an align directive ...
bool relaxDwarfLineAddr(MCDwarfLineAddrFragment &DF, MCAsmLayout &Layout, bool &WasRelaxed) const override
bool relaxDwarfCFA(MCDwarfCallFrameFragment &DF, MCAsmLayout &Layout, bool &WasRelaxed) const override
const MCFixupKindInfo & getFixupKindInfo(MCFixupKind Kind) const override
Get information on a fixup kind.
bool shouldInsertExtraNopBytesForCodeAlign(const MCAlignFragment &AF, unsigned &Size) override
Hook to check if extra nop bytes must be inserted for alignment directive.
bool mayNeedRelaxation(const MCInst &Inst, const MCSubtargetInfo &STI) const override
Check whether the given instruction may need relaxation.
bool writeNopData(raw_ostream &OS, uint64_t Count, const MCSubtargetInfo *STI) const override
Write an (optimal) nop sequence of Count bytes to the given output.
unsigned getRelaxedOpcode(unsigned Op) const
bool evaluateTargetFixup(const MCAssembler &Asm, const MCAsmLayout &Layout, const MCFixup &Fixup, const MCFragment *DF, const MCValue &Target, uint64_t &Value, bool &WasForced) override
bool fixupNeedsRelaxationAdvanced(const MCFixup &Fixup, bool Resolved, uint64_t Value, const MCRelaxableFragment *DF, const MCAsmLayout &Layout, const bool WasForced) const override
Target specific predicate for whether a given fixup requires the associated instruction to be relaxed...
unsigned getNumFixupKinds() const override
Get the number of target specific fixup kinds.
bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup, const MCValue &Target) override
Hook to check if a relocation is needed for some target specific reason.
std::optional< MCFixupKind > getFixupKind(StringRef Name) const override
Map a relocation name used in .reloc to a fixup kind.
Represents a location in source code.
Definition: SMLoc.h:23
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:577
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
A switch()-like statement whose cases are string literals.
Definition: StringSwitch.h:44
StringSwitch & Case(StringLiteral S, T Value)
Definition: StringSwitch.h:69
R Default(T Value)
Definition: StringSwitch.h:182
Target - Wrapper for Target specific information.
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
bool isOSBinFormatELF() const
Tests whether the OS uses the ELF binary format.
Definition: Triple.h:675
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
LLVM Value Representation.
Definition: Value.h:74
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:52
raw_ostream & write_zeros(unsigned NumZeros)
write_zeros - Insert 'NumZeros' nulls.
uint64_t tell() const
tell - Return the current offset with the file.
Definition: raw_ostream.h:134
raw_ostream & write(unsigned char C)
A raw_ostream that writes to an SmallVector or SmallString.
Definition: raw_ostream.h:672
#define INT64_MAX
Definition: DataTypes.h:71
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ C
The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
bool uncompress(MCInst &OutInst, const MCInst &MI, const MCSubtargetInfo &STI)
static std::pair< MCFixupKind, MCFixupKind > getRelocPairForSize(unsigned Size)
@ fixup_riscv_tprel_lo12_s
@ fixup_riscv_tls_got_hi20
@ fixup_riscv_pcrel_lo12_i
@ fixup_riscv_pcrel_lo12_s
@ fixup_riscv_tprel_lo12_i
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
std::unique_ptr< MCObjectTargetWriter > createRISCVELFObjectWriter(uint8_t OSABI, bool Is64Bit)
@ Offset
Definition: DWP.cpp:406
bool isUIntN(unsigned N, uint64_t x)
Checks if an unsigned integer fits into the given (dynamic) bit width.
Definition: MathExtras.h:256
MCFixupKind
Extensible enumeration to represent the type of a fixup.
Definition: MCFixup.h:21
@ FirstTargetFixupKind
Definition: MCFixup.h:45
@ FK_Data_6b
A six-bits fixup.
Definition: MCFixup.h:27
@ FirstLiteralRelocationKind
The range [FirstLiteralRelocationKind, MaxTargetFixupKind) is used for relocations coming from ....
Definition: MCFixup.h:50
@ FK_Data_8
A eight-byte fixup.
Definition: MCFixup.h:26
@ FK_Data_1
A one-byte fixup.
Definition: MCFixup.h:23
@ FK_Data_4
A four-byte fixup.
Definition: MCFixup.h:25
@ FK_NONE
A no-op fixup.
Definition: MCFixup.h:22
@ FK_Data_2
A two-byte fixup.
Definition: MCFixup.h:24
MCAsmBackend * createRISCVAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
uint64_t alignTo(uint64_t Size, Align A)
Returns a multiple of A needed to store Size bytes.
Definition: Alignment.h:155
unsigned encodeSLEB128(int64_t Value, raw_ostream &OS, unsigned PadTo=0)
Utility function to encode a SLEB128 value to an output stream.
Definition: LEB128.h:23
unsigned encodeULEB128(uint64_t Value, raw_ostream &OS, unsigned PadTo=0)
Utility function to encode a ULEB128 value to an output stream.
Definition: LEB128.h:80
uint64_t value() const
This is a hole in the type system and should not be abused.
Definition: Alignment.h:85
Target independent information on a fixup kind.
@ FKF_IsTarget
Should this fixup be evaluated in a target dependent manner?
@ FKF_IsPCRel
Is this fixup kind PCrelative? This is used by the assembler backend to evaluate fixup values in a ta...