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34 #define DEBUG_TYPE "mccodeemitter"
36 STATISTIC(MCNumEmitted,
"Number of MC instructions emitted");
37 STATISTIC(MCNumFixups,
"Number of MC fixups created");
41 RISCVMCCodeEmitter(
const RISCVMCCodeEmitter &) =
delete;
42 void operator=(
const RISCVMCCodeEmitter &) =
delete;
48 : Ctx(ctx), MCII(MCII) {}
50 ~RISCVMCCodeEmitter()
override =
default;
76 unsigned getImmOpValueAsr1(
const MCInst &
MI,
unsigned OpNo,
80 unsigned getImmOpValue(
const MCInst &
MI,
unsigned OpNo,
84 unsigned getVMaskReg(
const MCInst &
MI,
unsigned OpNo,
91 verifyInstructionPredicates(
const MCInst &
MI,
98 return new RISCVMCCodeEmitter(Ctx, MCII);
115 if (
MI.getOpcode() == RISCV::PseudoTAIL) {
116 Func =
MI.getOperand(0);
118 }
else if (
MI.getOpcode() == RISCV::PseudoCALLReg) {
120 Ra =
MI.getOperand(0).getReg();
121 }
else if (
MI.getOpcode() == RISCV::PseudoCALL) {
124 }
else if (
MI.getOpcode() == RISCV::PseudoJump) {
126 Ra =
MI.getOperand(0).getReg();
130 assert(
Func.isExpr() &&
"Expected expression");
139 if (
MI.getOpcode() == RISCV::PseudoTAIL ||
140 MI.getOpcode() == RISCV::PseudoJump)
158 "Expected thread pointer as second input to TP-relative add");
162 "Expected expression as third input to TP-relative add");
166 "Expected tprel_add relocation on TP-relative symbol");
191 verifyInstructionPredicates(
MI,
201 if (
MI.getOpcode() == RISCV::PseudoCALLReg ||
202 MI.getOpcode() == RISCV::PseudoCALL ||
203 MI.getOpcode() == RISCV::PseudoTAIL ||
204 MI.getOpcode() == RISCV::PseudoJump) {
205 expandFunctionCall(
MI, OS,
Fixups, STI);
210 if (
MI.getOpcode() == RISCV::PseudoAddTPRel) {
211 expandAddTPRel(
MI, OS,
Fixups, STI);
240 return Ctx.getRegisterInfo()->getEncodingValue(MO.
getReg());
243 return static_cast<unsigned>(MO.
getImm());
250 RISCVMCCodeEmitter::getImmOpValueAsr1(
const MCInst &
MI,
unsigned OpNo,
256 unsigned Res = MO.
getImm();
257 assert((Res & 1) == 0 &&
"LSB is non-zero");
261 return getImmOpValue(
MI, OpNo,
Fixups, STI);
264 unsigned RISCVMCCodeEmitter::getImmOpValue(
const MCInst &
MI,
unsigned OpNo,
278 "getImmOpValue expects only expressions or immediates");
282 bool RelaxCandidate =
false;
284 const RISCVMCExpr *RVExpr = cast<RISCVMCExpr>(Expr);
297 "VK_RISCV_TPREL_ADD should not represent an instruction operand");
305 RelaxCandidate =
true;
309 RelaxCandidate =
true;
318 "VK_RISCV_PCREL_LO used with unexpected instruction format");
319 RelaxCandidate =
true;
323 RelaxCandidate =
true;
335 "VK_RISCV_TPREL_LO used with unexpected instruction format");
336 RelaxCandidate =
true;
340 RelaxCandidate =
true;
350 RelaxCandidate =
true;
354 RelaxCandidate =
true;
379 if (EnableRelax && RelaxCandidate) {
390 unsigned RISCVMCCodeEmitter::getVMaskReg(
const MCInst &
MI,
unsigned OpNo,
401 case RISCV::NoRegister:
406 #define ENABLE_INSTR_PREDICATE_VERIFIER
407 #include "RISCVGenMCCodeEmitter.inc"
@ fixup_riscv_pcrel_lo12_i
This is an optimization pass for GlobalISel generic memory operations.
static Lanai::Fixups FixupKind(const MCExpr *Expr)
Context object for machine code objects.
static const MCConstantExpr * create(int64_t Value, MCContext &Ctx, bool PrintInHex=false, unsigned SizeInBytes=0)
@ fixup_riscv_tls_gd_hi20
static MCFixup create(uint32_t Offset, const MCExpr *Value, MCFixupKind Kind, SMLoc Loc=SMLoc())
Container class for subtarget features.
Instances of this class represent a single low-level machine instruction.
MCCodeEmitter * createRISCVMCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx)
@ fixup_riscv_pcrel_lo12_s
unsigned getSize() const
Return the number of bytes in the encoding of this instruction, or zero if the encoding size cannot b...
MCInstBuilder & addOperand(const MCOperand &Op)
Add an operand.
@ fixup_riscv_tls_got_hi20
@ Target
Target specific expression.
Describe properties that are true of each instruction in the target description file.
const FeatureBitset & getFeatureBits() const
STATISTIC(NumFunctions, "Total number of functions")
This class implements an extremely fast bulk output stream that can only output to a stream.
void write(void *memory, value_type value, endianness endian)
Write a value to memory with a particular endianness.
static unsigned getFormat(uint64_t TSFlags)
@ fixup_riscv_tprel_lo12_s
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
@ fixup_riscv_tprel_lo12_i
MCInstBuilder & addImm(int64_t Val)
Add a new integer immediate operand.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
MCInstBuilder & addExpr(const MCExpr *Val)
Add a new MCExpr operand.
VariantKind getKind() const
Interface to description of machine instruction set.
MCCodeEmitter - Generic instruction encoding interface.
const MCExpr * getExpr() const
@ ADD
Simple integer binary arithmetic operators.
MCFixupKind
Extensible enumeration to represent the type of a fixup.
@ SymbolRef
References to labels and assigned expressions.
MCInstBuilder & addReg(unsigned Reg)
Add a new register operand.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Instances of this class represent operands of the MCInst class.
Generic base class for all target subtargets.
Base class for the full range of assembler expressions which are needed for parsing.
Wrapper class representing physical registers. Should be passed by value.
unsigned getReg() const
Returns the register number.