LLVM  14.0.0git
RISCVMCCodeEmitter.cpp
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1 //===-- RISCVMCCodeEmitter.cpp - Convert RISCV code to machine code -------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the RISCVMCCodeEmitter class.
10 //
11 //===----------------------------------------------------------------------===//
12 
17 #include "llvm/ADT/Statistic.h"
18 #include "llvm/MC/MCAsmInfo.h"
19 #include "llvm/MC/MCCodeEmitter.h"
20 #include "llvm/MC/MCContext.h"
21 #include "llvm/MC/MCExpr.h"
22 #include "llvm/MC/MCInst.h"
23 #include "llvm/MC/MCInstBuilder.h"
24 #include "llvm/MC/MCInstrInfo.h"
25 #include "llvm/MC/MCRegisterInfo.h"
26 #include "llvm/MC/MCSymbol.h"
27 #include "llvm/Support/Casting.h"
30 
31 using namespace llvm;
32 
33 #define DEBUG_TYPE "mccodeemitter"
34 
35 STATISTIC(MCNumEmitted, "Number of MC instructions emitted");
36 STATISTIC(MCNumFixups, "Number of MC fixups created");
37 
38 namespace {
39 class RISCVMCCodeEmitter : public MCCodeEmitter {
40  RISCVMCCodeEmitter(const RISCVMCCodeEmitter &) = delete;
41  void operator=(const RISCVMCCodeEmitter &) = delete;
42  MCContext &Ctx;
43  MCInstrInfo const &MCII;
44 
45 public:
46  RISCVMCCodeEmitter(MCContext &ctx, MCInstrInfo const &MCII)
47  : Ctx(ctx), MCII(MCII) {}
48 
49  ~RISCVMCCodeEmitter() override {}
50 
51  void encodeInstruction(const MCInst &MI, raw_ostream &OS,
53  const MCSubtargetInfo &STI) const override;
54 
55  void expandFunctionCall(const MCInst &MI, raw_ostream &OS,
57  const MCSubtargetInfo &STI) const;
58 
59  void expandAddTPRel(const MCInst &MI, raw_ostream &OS,
61  const MCSubtargetInfo &STI) const;
62 
63  /// TableGen'erated function for getting the binary encoding for an
64  /// instruction.
65  uint64_t getBinaryCodeForInstr(const MCInst &MI,
67  const MCSubtargetInfo &STI) const;
68 
69  /// Return binary encoding of operand. If the machine operand requires
70  /// relocation, record the relocation and return zero.
71  unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO,
73  const MCSubtargetInfo &STI) const;
74 
75  unsigned getImmOpValueAsr1(const MCInst &MI, unsigned OpNo,
77  const MCSubtargetInfo &STI) const;
78 
79  unsigned getImmOpValue(const MCInst &MI, unsigned OpNo,
81  const MCSubtargetInfo &STI) const;
82 
83  unsigned getVMaskReg(const MCInst &MI, unsigned OpNo,
85  const MCSubtargetInfo &STI) const;
86 
87 private:
88  FeatureBitset computeAvailableFeatures(const FeatureBitset &FB) const;
89  void
90  verifyInstructionPredicates(const MCInst &MI,
91  const FeatureBitset &AvailableFeatures) const;
92 };
93 } // end anonymous namespace
94 
96  const MCRegisterInfo &MRI,
97  MCContext &Ctx) {
98  return new RISCVMCCodeEmitter(Ctx, MCII);
99 }
100 
101 // Expand PseudoCALL(Reg), PseudoTAIL and PseudoJump to AUIPC and JALR with
102 // relocation types. We expand those pseudo-instructions while encoding them,
103 // meaning AUIPC and JALR won't go through RISCV MC to MC compressed
104 // instruction transformation. This is acceptable because AUIPC has no 16-bit
105 // form and C_JALR has no immediate operand field. We let linker relaxation
106 // deal with it. When linker relaxation is enabled, AUIPC and JALR have a
107 // chance to relax to JAL.
108 // If the C extension is enabled, JAL has a chance relax to C_JAL.
109 void RISCVMCCodeEmitter::expandFunctionCall(const MCInst &MI, raw_ostream &OS,
111  const MCSubtargetInfo &STI) const {
112  MCInst TmpInst;
113  MCOperand Func;
114  MCRegister Ra;
115  if (MI.getOpcode() == RISCV::PseudoTAIL) {
116  Func = MI.getOperand(0);
117  Ra = RISCV::X6;
118  } else if (MI.getOpcode() == RISCV::PseudoCALLReg) {
119  Func = MI.getOperand(1);
120  Ra = MI.getOperand(0).getReg();
121  } else if (MI.getOpcode() == RISCV::PseudoCALL) {
122  Func = MI.getOperand(0);
123  Ra = RISCV::X1;
124  } else if (MI.getOpcode() == RISCV::PseudoJump) {
125  Func = MI.getOperand(1);
126  Ra = MI.getOperand(0).getReg();
127  }
129 
130  assert(Func.isExpr() && "Expected expression");
131 
132  const MCExpr *CallExpr = Func.getExpr();
133 
134  // Emit AUIPC Ra, Func with R_RISCV_CALL relocation type.
135  TmpInst = MCInstBuilder(RISCV::AUIPC)
136  .addReg(Ra)
138  Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI);
140 
141  if (MI.getOpcode() == RISCV::PseudoTAIL ||
142  MI.getOpcode() == RISCV::PseudoJump)
143  // Emit JALR X0, Ra, 0
144  TmpInst = MCInstBuilder(RISCV::JALR).addReg(RISCV::X0).addReg(Ra).addImm(0);
145  else
146  // Emit JALR Ra, Ra, 0
147  TmpInst = MCInstBuilder(RISCV::JALR).addReg(Ra).addReg(Ra).addImm(0);
148  Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI);
150 }
151 
152 // Expand PseudoAddTPRel to a simple ADD with the correct relocation.
153 void RISCVMCCodeEmitter::expandAddTPRel(const MCInst &MI, raw_ostream &OS,
155  const MCSubtargetInfo &STI) const {
156  MCOperand DestReg = MI.getOperand(0);
157  MCOperand SrcReg = MI.getOperand(1);
158  MCOperand TPReg = MI.getOperand(2);
159  assert(TPReg.isReg() && TPReg.getReg() == RISCV::X4 &&
160  "Expected thread pointer as second input to TP-relative add");
161 
162  MCOperand SrcSymbol = MI.getOperand(3);
163  assert(SrcSymbol.isExpr() &&
164  "Expected expression as third input to TP-relative add");
165 
166  const RISCVMCExpr *Expr = dyn_cast<RISCVMCExpr>(SrcSymbol.getExpr());
167  assert(Expr && Expr->getKind() == RISCVMCExpr::VK_RISCV_TPREL_ADD &&
168  "Expected tprel_add relocation on TP-relative symbol");
169 
170  // Emit the correct tprel_add relocation for the symbol.
171  Fixups.push_back(MCFixup::create(
172  0, Expr, MCFixupKind(RISCV::fixup_riscv_tprel_add), MI.getLoc()));
173 
174  // Emit fixup_riscv_relax for tprel_add where the relax feature is enabled.
175  if (STI.getFeatureBits()[RISCV::FeatureRelax]) {
177  Fixups.push_back(MCFixup::create(
178  0, Dummy, MCFixupKind(RISCV::fixup_riscv_relax), MI.getLoc()));
179  }
180 
181  // Emit a normal ADD instruction with the given operands.
182  MCInst TmpInst = MCInstBuilder(RISCV::ADD)
183  .addOperand(DestReg)
184  .addOperand(SrcReg)
185  .addOperand(TPReg);
186  uint32_t Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI);
188 }
189 
190 void RISCVMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
192  const MCSubtargetInfo &STI) const {
193  verifyInstructionPredicates(MI,
194  computeAvailableFeatures(STI.getFeatureBits()));
195 
196  const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
197  // Get byte count of instruction.
198  unsigned Size = Desc.getSize();
199 
200  // RISCVInstrInfo::getInstSizeInBytes hard-codes the number of expanded
201  // instructions for each pseudo, and must be updated when adding new pseudos
202  // or changing existing ones.
203  if (MI.getOpcode() == RISCV::PseudoCALLReg ||
204  MI.getOpcode() == RISCV::PseudoCALL ||
205  MI.getOpcode() == RISCV::PseudoTAIL ||
206  MI.getOpcode() == RISCV::PseudoJump) {
207  expandFunctionCall(MI, OS, Fixups, STI);
208  MCNumEmitted += 2;
209  return;
210  }
211 
212  if (MI.getOpcode() == RISCV::PseudoAddTPRel) {
213  expandAddTPRel(MI, OS, Fixups, STI);
214  MCNumEmitted += 1;
215  return;
216  }
217 
218  switch (Size) {
219  default:
220  llvm_unreachable("Unhandled encodeInstruction length!");
221  case 2: {
222  uint16_t Bits = getBinaryCodeForInstr(MI, Fixups, STI);
223  support::endian::write<uint16_t>(OS, Bits, support::little);
224  break;
225  }
226  case 4: {
227  uint32_t Bits = getBinaryCodeForInstr(MI, Fixups, STI);
229  break;
230  }
231  }
232 
233  ++MCNumEmitted; // Keep track of the # of mi's emitted.
234 }
235 
236 unsigned
237 RISCVMCCodeEmitter::getMachineOpValue(const MCInst &MI, const MCOperand &MO,
239  const MCSubtargetInfo &STI) const {
240 
241  if (MO.isReg())
242  return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg());
243 
244  if (MO.isImm())
245  return static_cast<unsigned>(MO.getImm());
246 
247  llvm_unreachable("Unhandled expression!");
248  return 0;
249 }
250 
251 unsigned
252 RISCVMCCodeEmitter::getImmOpValueAsr1(const MCInst &MI, unsigned OpNo,
254  const MCSubtargetInfo &STI) const {
255  const MCOperand &MO = MI.getOperand(OpNo);
256 
257  if (MO.isImm()) {
258  unsigned Res = MO.getImm();
259  assert((Res & 1) == 0 && "LSB is non-zero");
260  return Res >> 1;
261  }
262 
263  return getImmOpValue(MI, OpNo, Fixups, STI);
264 }
265 
266 unsigned RISCVMCCodeEmitter::getImmOpValue(const MCInst &MI, unsigned OpNo,
268  const MCSubtargetInfo &STI) const {
269  bool EnableRelax = STI.getFeatureBits()[RISCV::FeatureRelax];
270  const MCOperand &MO = MI.getOperand(OpNo);
271 
272  MCInstrDesc const &Desc = MCII.get(MI.getOpcode());
273  unsigned MIFrm = RISCVII::getFormat(Desc.TSFlags);
274 
275  // If the destination is an immediate, there is nothing to do.
276  if (MO.isImm())
277  return MO.getImm();
278 
279  assert(MO.isExpr() &&
280  "getImmOpValue expects only expressions or immediates");
281  const MCExpr *Expr = MO.getExpr();
282  MCExpr::ExprKind Kind = Expr->getKind();
284  bool RelaxCandidate = false;
285  if (Kind == MCExpr::Target) {
286  const RISCVMCExpr *RVExpr = cast<RISCVMCExpr>(Expr);
287 
288  switch (RVExpr->getKind()) {
292  llvm_unreachable("Unhandled fixup kind!");
294  // tprel_add is only used to indicate that a relocation should be emitted
295  // for an add instruction used in TP-relative addressing. It should not be
296  // expanded as if representing an actual instruction operand and so to
297  // encounter it here is an error.
299  "VK_RISCV_TPREL_ADD should not represent an instruction operand");
301  if (MIFrm == RISCVII::InstFormatI)
303  else if (MIFrm == RISCVII::InstFormatS)
305  else
306  llvm_unreachable("VK_RISCV_LO used with unexpected instruction format");
307  RelaxCandidate = true;
308  break;
311  RelaxCandidate = true;
312  break;
314  if (MIFrm == RISCVII::InstFormatI)
316  else if (MIFrm == RISCVII::InstFormatS)
318  else
320  "VK_RISCV_PCREL_LO used with unexpected instruction format");
321  RelaxCandidate = true;
322  break;
325  RelaxCandidate = true;
326  break;
329  break;
331  if (MIFrm == RISCVII::InstFormatI)
333  else if (MIFrm == RISCVII::InstFormatS)
335  else
337  "VK_RISCV_TPREL_LO used with unexpected instruction format");
338  RelaxCandidate = true;
339  break;
342  RelaxCandidate = true;
343  break;
346  break;
349  break;
352  RelaxCandidate = true;
353  break;
356  RelaxCandidate = true;
357  break;
358  }
359  } else if (Kind == MCExpr::SymbolRef &&
360  cast<MCSymbolRefExpr>(Expr)->getKind() == MCSymbolRefExpr::VK_None) {
361  if (MIFrm == RISCVII::InstFormatJ) {
363  } else if (MIFrm == RISCVII::InstFormatB) {
365  } else if (MIFrm == RISCVII::InstFormatCJ) {
367  } else if (MIFrm == RISCVII::InstFormatCB) {
369  }
370  }
371 
372  assert(FixupKind != RISCV::fixup_riscv_invalid && "Unhandled expression!");
373 
374  Fixups.push_back(
375  MCFixup::create(0, Expr, MCFixupKind(FixupKind), MI.getLoc()));
376  ++MCNumFixups;
377 
378  // Ensure an R_RISCV_RELAX relocation will be emitted if linker relaxation is
379  // enabled and the current fixup will result in a relocation that may be
380  // relaxed.
381  if (EnableRelax && RelaxCandidate) {
383  Fixups.push_back(
385  MI.getLoc()));
386  ++MCNumFixups;
387  }
388 
389  return 0;
390 }
391 
392 unsigned RISCVMCCodeEmitter::getVMaskReg(const MCInst &MI, unsigned OpNo,
394  const MCSubtargetInfo &STI) const {
395  MCOperand MO = MI.getOperand(OpNo);
396  assert(MO.isReg() && "Expected a register.");
397 
398  switch (MO.getReg()) {
399  default:
400  llvm_unreachable("Invalid mask register.");
401  case RISCV::V0:
402  return 0;
403  case RISCV::NoRegister:
404  return 1;
405  }
406 }
407 
408 #define ENABLE_INSTR_PREDICATE_VERIFIER
409 #include "RISCVGenMCCodeEmitter.inc"
llvm::Check::Size
@ Size
Definition: FileCheck.h:73
llvm::RISCV::fixup_riscv_pcrel_lo12_i
@ fixup_riscv_pcrel_lo12_i
Definition: RISCVFixupKinds.h:28
llvm::RISCVMCExpr::VK_RISCV_Invalid
@ VK_RISCV_Invalid
Definition: RISCVMCExpr.h:40
llvm::RISCV::fixup_riscv_call_plt
@ fixup_riscv_call_plt
Definition: RISCVFixupKinds.h:64
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:105
llvm
This file implements support for optimizing divisions by a constant.
Definition: AllocatorList.h:23
llvm::FixupKind
static Lanai::Fixups FixupKind(const MCExpr *Expr)
Definition: LanaiMCCodeEmitter.cpp:90
llvm::RISCVII::InstFormatI
@ InstFormatI
Definition: RISCVBaseInfo.h:31
llvm::MCOperand::createExpr
static MCOperand createExpr(const MCExpr *Val)
Definition: MCInst.h:162
llvm::MCOperand::isReg
bool isReg() const
Definition: MCInst.h:61
llvm::RISCVMCExpr::VK_RISCV_TLS_GD_HI
@ VK_RISCV_TLS_GD_HI
Definition: RISCVMCExpr.h:36
llvm::MCContext
Context object for machine code objects.
Definition: MCContext.h:72
MCCodeEmitter.h
llvm::RISCVMCExpr::VK_RISCV_TPREL_ADD
@ VK_RISCV_TPREL_ADD
Definition: RISCVMCExpr.h:34
llvm::MCConstantExpr::create
static const MCConstantExpr * create(int64_t Value, MCContext &Ctx, bool PrintInHex=false, unsigned SizeInBytes=0)
Definition: MCExpr.cpp:194
Statistic.h
llvm::RISCV::fixup_riscv_tls_gd_hi20
@ fixup_riscv_tls_gd_hi20
Definition: RISCVFixupKinds.h:50
llvm::MCFixup::create
static MCFixup create(uint32_t Offset, const MCExpr *Value, MCFixupKind Kind, SMLoc Loc=SMLoc())
Definition: MCFixup.h:87
llvm::RISCV::fixup_riscv_lo12_s
@ fixup_riscv_lo12_s
Definition: RISCVFixupKinds.h:24
llvm::RISCV::fixup_riscv_call
@ fixup_riscv_call
Definition: RISCVFixupKinds.h:61
MCInstBuilder.h
llvm::RISCVII::InstFormatS
@ InstFormatS
Definition: RISCVBaseInfo.h:32
llvm::tgtok::Bits
@ Bits
Definition: TGLexer.h:50
CallExpr
Definition: ItaniumDemangle.h:1898
RISCVMCExpr.h
llvm::RISCVMCExpr::VK_RISCV_TPREL_LO
@ VK_RISCV_TPREL_LO
Definition: RISCVMCExpr.h:32
llvm::FeatureBitset
Container class for subtarget features.
Definition: SubtargetFeature.h:40
llvm::RISCVMCExpr::VK_RISCV_HI
@ VK_RISCV_HI
Definition: RISCVMCExpr.h:28
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
llvm::RISCVMCExpr::VK_RISCV_TPREL_HI
@ VK_RISCV_TPREL_HI
Definition: RISCVMCExpr.h:33
llvm::msgpack::Type::Binary
@ Binary
llvm::RISCV::fixup_riscv_pcrel_lo12_s
@ fixup_riscv_pcrel_lo12_s
Definition: RISCVFixupKinds.h:31
llvm::RISCVMCExpr::VK_RISCV_TLS_GOT_HI
@ VK_RISCV_TLS_GOT_HI
Definition: RISCVMCExpr.h:35
llvm::MCInstrDesc::TSFlags
uint64_t TSFlags
Definition: MCInstrDesc.h:203
llvm::MCInstrDesc::getSize
unsigned getSize() const
Return the number of bytes in the encoding of this instruction, or zero if the encoding size cannot b...
Definition: MCInstrDesc.h:616
llvm::MCInstBuilder::addOperand
MCInstBuilder & addOperand(const MCOperand &Op)
Add an operand.
Definition: MCInstBuilder.h:67
llvm::RISCV::fixup_riscv_jal
@ fixup_riscv_jal
Definition: RISCVFixupKinds.h:52
llvm::RISCV::fixup_riscv_hi20
@ fixup_riscv_hi20
Definition: RISCVFixupKinds.h:20
llvm::RISCVMCExpr::VK_RISCV_LO
@ VK_RISCV_LO
Definition: RISCVMCExpr.h:27
llvm::RISCV::fixup_riscv_rvc_jump
@ fixup_riscv_rvc_jump
Definition: RISCVFixupKinds.h:56
llvm::support::little
@ little
Definition: Endian.h:27
llvm::RISCV::fixup_riscv_tls_got_hi20
@ fixup_riscv_tls_got_hi20
Definition: RISCVFixupKinds.h:47
llvm::MCExpr::Target
@ Target
Target specific expression.
Definition: MCExpr.h:42
MCContext.h
llvm::RISCVII::InstFormatCB
@ InstFormatCB
Definition: RISCVBaseInfo.h:43
MCInstrInfo.h
llvm::MCOperand::getImm
int64_t getImm() const
Definition: MCInst.h:80
MCSymbol.h
llvm::RISCV::fixup_riscv_lo12_i
@ fixup_riscv_lo12_i
Definition: RISCVFixupKinds.h:22
MCInst.h
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:195
llvm::AArch64::Fixups
Fixups
Definition: AArch64FixupKinds.h:17
llvm::MCSubtargetInfo::getFeatureBits
const FeatureBitset & getFeatureBits() const
Definition: MCSubtargetInfo.h:111
llvm::RISCV::fixup_riscv_got_hi20
@ fixup_riscv_got_hi20
Definition: RISCVFixupKinds.h:34
RISCVMCTargetDesc.h
llvm::RISCVII::InstFormatJ
@ InstFormatJ
Definition: RISCVBaseInfo.h:35
llvm::STATISTIC
STATISTIC(NumFunctions, "Total number of functions")
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:53
llvm::RISCV::fixup_riscv_relax
@ fixup_riscv_relax
Definition: RISCVFixupKinds.h:67
llvm::MCExpr::getKind
ExprKind getKind() const
Definition: MCExpr.h:81
llvm::lltok::Kind
Kind
Definition: LLToken.h:18
llvm::support::endian::write
void write(void *memory, value_type value, endianness endian)
Write a value to memory with a particular endianness.
Definition: Endian.h:97
llvm::RISCVII::getFormat
static unsigned getFormat(uint64_t TSFlags)
Definition: RISCVBaseInfo.h:113
llvm::MCConstantExpr
Definition: MCExpr.h:144
llvm::RISCVMCExpr::VK_RISCV_None
@ VK_RISCV_None
Definition: RISCVMCExpr.h:26
llvm::RISCV::fixup_riscv_branch
@ fixup_riscv_branch
Definition: RISCVFixupKinds.h:54
llvm::MCOperand::isImm
bool isImm() const
Definition: MCInst.h:62
llvm::RISCVMCExpr::VK_RISCV_PCREL_HI
@ VK_RISCV_PCREL_HI
Definition: RISCVMCExpr.h:30
uint64_t
llvm::createRISCVMCCodeEmitter
MCCodeEmitter * createRISCVMCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, MCContext &Ctx)
Definition: RISCVMCCodeEmitter.cpp:95
llvm::RISCV::fixup_riscv_tprel_lo12_s
@ fixup_riscv_tprel_lo12_s
Definition: RISCVFixupKinds.h:41
MCRegisterInfo.h
llvm::MCInstBuilder
Definition: MCInstBuilder.h:21
llvm::RISCVMCExpr::VK_RISCV_PCREL_LO
@ VK_RISCV_PCREL_LO
Definition: RISCVMCExpr.h:29
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::RISCV::fixup_riscv_tprel_lo12_i
@ fixup_riscv_tprel_lo12_i
Definition: RISCVFixupKinds.h:38
llvm::RISCVII::InstFormatB
@ InstFormatB
Definition: RISCVBaseInfo.h:33
llvm::RISCVMCExpr::VK_RISCV_GOT_HI
@ VK_RISCV_GOT_HI
Definition: RISCVMCExpr.h:31
llvm::NVPTXISD::Dummy
@ Dummy
Definition: NVPTXISelLowering.h:60
MCAsmInfo.h
llvm::MCInstBuilder::addImm
MCInstBuilder & addImm(int64_t Val)
Add a new integer immediate operand.
Definition: MCInstBuilder.h:37
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:134
llvm::RISCV::fixup_riscv_pcrel_hi20
@ fixup_riscv_pcrel_hi20
Definition: RISCVFixupKinds.h:26
uint32_t
llvm::MCRegisterInfo
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Definition: MCRegisterInfo.h:135
llvm::ifs::IFSSymbolType::Func
@ Func
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::RISCVII::InstFormatCJ
@ InstFormatCJ
Definition: RISCVBaseInfo.h:44
llvm::RISCVMCExpr::getKind
VariantKind getKind() const
Definition: RISCVMCExpr.h:56
llvm::MCInstrInfo
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:25
llvm::RISCVMCExpr::VK_RISCV_32_PCREL
@ VK_RISCV_32_PCREL
Definition: RISCVMCExpr.h:39
EndianStream.h
uint16_t
llvm::MCCodeEmitter
MCCodeEmitter - Generic instruction encoding interface.
Definition: MCCodeEmitter.h:21
llvm::RISCV::fixup_riscv_tprel_add
@ fixup_riscv_tprel_add
Definition: RISCVFixupKinds.h:44
Casting.h
llvm::MCOperand::getExpr
const MCExpr * getExpr() const
Definition: MCInst.h:114
RISCVBaseInfo.h
llvm::MCOperand::isExpr
bool isExpr() const
Definition: MCInst.h:65
llvm::ISD::ADD
@ ADD
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:239
llvm::MCFixupKind
MCFixupKind
Extensible enumeration to represent the type of a fixup.
Definition: MCFixup.h:21
llvm::RISCVMCExpr::VK_RISCV_CALL
@ VK_RISCV_CALL
Definition: RISCVMCExpr.h:37
llvm::RISCV::fixup_riscv_rvc_branch
@ fixup_riscv_rvc_branch
Definition: RISCVFixupKinds.h:58
llvm::MCExpr::SymbolRef
@ SymbolRef
References to labels and assigned expressions.
Definition: MCExpr.h:40
llvm::RISCV::fixup_riscv_invalid
@ fixup_riscv_invalid
Definition: RISCVFixupKinds.h:109
llvm::MCInstBuilder::addReg
MCInstBuilder & addReg(unsigned Reg)
Add a new register operand.
Definition: MCInstBuilder.h:31
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:43
llvm::MCOperand
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:36
llvm::RISCV::Fixups
Fixups
Definition: RISCVFixupKinds.h:18
llvm::MCSymbolRefExpr::VK_None
@ VK_None
Definition: MCExpr.h:195
llvm::MCExpr::ExprKind
ExprKind
Definition: MCExpr.h:37
llvm::RISCVMCExpr::VK_RISCV_CALL_PLT
@ VK_RISCV_CALL_PLT
Definition: RISCVMCExpr.h:38
raw_ostream.h
MCExpr.h
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition: MCSubtargetInfo.h:75
llvm::RISCV::fixup_riscv_tprel_hi20
@ fixup_riscv_tprel_hi20
Definition: RISCVFixupKinds.h:36
llvm::MCExpr
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:35
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:24
llvm::MCOperand::getReg
unsigned getReg() const
Returns the register number.
Definition: MCInst.h:69
RISCVFixupKinds.h
llvm::RISCVMCExpr
Definition: RISCVMCExpr.h:23