LLVM  14.0.0git
RISCVELFObjectWriter.cpp
Go to the documentation of this file.
1 //===-- RISCVELFObjectWriter.cpp - RISCV ELF Writer -----------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
12 #include "llvm/MC/MCContext.h"
14 #include "llvm/MC/MCFixup.h"
15 #include "llvm/MC/MCObjectWriter.h"
17 
18 using namespace llvm;
19 
20 namespace {
21 class RISCVELFObjectWriter : public MCELFObjectTargetWriter {
22 public:
23  RISCVELFObjectWriter(uint8_t OSABI, bool Is64Bit);
24 
25  ~RISCVELFObjectWriter() override;
26 
27  // Return true if the given relocation must be with a symbol rather than
28  // section plus offset.
29  bool needsRelocateWithSymbol(const MCSymbol &Sym,
30  unsigned Type) const override {
31  // TODO: this is very conservative, update once RISC-V psABI requirements
32  // are clarified.
33  return true;
34  }
35 
36 protected:
37  unsigned getRelocType(MCContext &Ctx, const MCValue &Target,
38  const MCFixup &Fixup, bool IsPCRel) const override;
39 };
40 }
41 
42 RISCVELFObjectWriter::RISCVELFObjectWriter(uint8_t OSABI, bool Is64Bit)
43  : MCELFObjectTargetWriter(Is64Bit, OSABI, ELF::EM_RISCV,
44  /*HasRelocationAddend*/ true) {}
45 
46 RISCVELFObjectWriter::~RISCVELFObjectWriter() {}
47 
48 unsigned RISCVELFObjectWriter::getRelocType(MCContext &Ctx,
49  const MCValue &Target,
50  const MCFixup &Fixup,
51  bool IsPCRel) const {
52  const MCExpr *Expr = Fixup.getValue();
53  // Determine the type of the relocation
54  unsigned Kind = Fixup.getTargetKind();
57  if (IsPCRel) {
58  switch (Kind) {
59  default:
60  Ctx.reportError(Fixup.getLoc(), "Unsupported relocation type");
61  return ELF::R_RISCV_NONE;
62  case FK_Data_4:
63  case FK_PCRel_4:
64  return ELF::R_RISCV_32_PCREL;
72  return ELF::R_RISCV_GOT_HI20;
74  return ELF::R_RISCV_TLS_GOT_HI20;
76  return ELF::R_RISCV_TLS_GD_HI20;
78  return ELF::R_RISCV_JAL;
80  return ELF::R_RISCV_BRANCH;
82  return ELF::R_RISCV_RVC_JUMP;
84  return ELF::R_RISCV_RVC_BRANCH;
86  return ELF::R_RISCV_CALL;
88  return ELF::R_RISCV_CALL_PLT;
90  return ELF::R_RISCV_ADD8;
92  return ELF::R_RISCV_SUB8;
94  return ELF::R_RISCV_ADD16;
96  return ELF::R_RISCV_SUB16;
98  return ELF::R_RISCV_ADD32;
100  return ELF::R_RISCV_SUB32;
102  return ELF::R_RISCV_ADD64;
104  return ELF::R_RISCV_SUB64;
105  }
106  }
107 
108  switch (Kind) {
109  default:
110  Ctx.reportError(Fixup.getLoc(), "Unsupported relocation type");
111  return ELF::R_RISCV_NONE;
112  case FK_Data_1:
113  Ctx.reportError(Fixup.getLoc(), "1-byte data relocations not supported");
114  return ELF::R_RISCV_NONE;
115  case FK_Data_2:
116  Ctx.reportError(Fixup.getLoc(), "2-byte data relocations not supported");
117  return ELF::R_RISCV_NONE;
118  case FK_Data_4:
119  if (Expr->getKind() == MCExpr::Target &&
120  cast<RISCVMCExpr>(Expr)->getKind() == RISCVMCExpr::VK_RISCV_32_PCREL)
121  return ELF::R_RISCV_32_PCREL;
122  return ELF::R_RISCV_32;
123  case FK_Data_8:
124  return ELF::R_RISCV_64;
126  return ELF::R_RISCV_HI20;
128  return ELF::R_RISCV_LO12_I;
130  return ELF::R_RISCV_LO12_S;
132  return ELF::R_RISCV_TPREL_HI20;
134  return ELF::R_RISCV_TPREL_LO12_I;
136  return ELF::R_RISCV_TPREL_LO12_S;
138  return ELF::R_RISCV_TPREL_ADD;
140  return ELF::R_RISCV_RELAX;
142  return ELF::R_RISCV_ALIGN;
144  return ELF::R_RISCV_SET6;
146  return ELF::R_RISCV_SUB6;
148  return ELF::R_RISCV_ADD8;
150  return ELF::R_RISCV_SET8;
152  return ELF::R_RISCV_SUB8;
154  return ELF::R_RISCV_SET16;
156  return ELF::R_RISCV_ADD16;
158  return ELF::R_RISCV_SUB16;
160  return ELF::R_RISCV_SET32;
162  return ELF::R_RISCV_ADD32;
164  return ELF::R_RISCV_SUB32;
166  return ELF::R_RISCV_ADD64;
168  return ELF::R_RISCV_SUB64;
169  }
170 }
171 
172 std::unique_ptr<MCObjectTargetWriter>
173 llvm::createRISCVELFObjectWriter(uint8_t OSABI, bool Is64Bit) {
174  return std::make_unique<RISCVELFObjectWriter>(OSABI, Is64Bit);
175 }
llvm::RISCV::fixup_riscv_pcrel_lo12_i
@ fixup_riscv_pcrel_lo12_i
Definition: RISCVFixupKinds.h:28
llvm::RISCV::fixup_riscv_call_plt
@ fixup_riscv_call_plt
Definition: RISCVFixupKinds.h:64
llvm
This file implements support for optimizing divisions by a constant.
Definition: AllocatorList.h:23
llvm::MCSymbol
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:41
llvm::MCContext
Context object for machine code objects.
Definition: MCContext.h:72
llvm::Target
Target - Wrapper for Target specific information.
Definition: TargetRegistry.h:137
llvm::ELF::EM_RISCV
@ EM_RISCV
Definition: ELF.h:318
llvm::RISCV::fixup_riscv_tls_gd_hi20
@ fixup_riscv_tls_gd_hi20
Definition: RISCVFixupKinds.h:50
ErrorHandling.h
llvm::RISCV::fixup_riscv_lo12_s
@ fixup_riscv_lo12_s
Definition: RISCVFixupKinds.h:24
llvm::RISCV::fixup_riscv_call
@ fixup_riscv_call
Definition: RISCVFixupKinds.h:61
llvm::RISCV::fixup_riscv_sub_64
@ fixup_riscv_sub_64
Definition: RISCVFixupKinds.h:100
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
RISCVMCExpr.h
llvm::RISCV::fixup_riscv_add_32
@ fixup_riscv_add_32
Definition: RISCVFixupKinds.h:91
llvm::RISCV::fixup_riscv_pcrel_lo12_s
@ fixup_riscv_pcrel_lo12_s
Definition: RISCVFixupKinds.h:31
llvm::FirstLiteralRelocationKind
@ FirstLiteralRelocationKind
The range [FirstLiteralRelocationKind, MaxTargetFixupKind) is used for relocations coming from ....
Definition: MCFixup.h:50
llvm::FK_Data_4
@ FK_Data_4
A four-byte fixup.
Definition: MCFixup.h:25
llvm::RISCV::fixup_riscv_jal
@ fixup_riscv_jal
Definition: RISCVFixupKinds.h:52
llvm::RISCV::fixup_riscv_hi20
@ fixup_riscv_hi20
Definition: RISCVFixupKinds.h:20
llvm::RISCV::fixup_riscv_rvc_jump
@ fixup_riscv_rvc_jump
Definition: RISCVFixupKinds.h:56
llvm::RISCV::fixup_riscv_tls_got_hi20
@ fixup_riscv_tls_got_hi20
Definition: RISCVFixupKinds.h:47
llvm::MCExpr::Target
@ Target
Target specific expression.
Definition: MCExpr.h:42
MCContext.h
llvm::RISCV::fixup_riscv_lo12_i
@ fixup_riscv_lo12_i
Definition: RISCVFixupKinds.h:22
llvm::RISCV::fixup_riscv_got_hi20
@ fixup_riscv_got_hi20
Definition: RISCVFixupKinds.h:34
RISCVMCTargetDesc.h
llvm::MCELFObjectTargetWriter
Definition: MCELFObjectWriter.h:53
llvm::RISCV::fixup_riscv_relax
@ fixup_riscv_relax
Definition: RISCVFixupKinds.h:67
llvm::MCExpr::getKind
ExprKind getKind() const
Definition: MCExpr.h:81
llvm::lltok::Kind
Kind
Definition: LLToken.h:18
llvm::RISCV::fixup_riscv_sub_8
@ fixup_riscv_sub_8
Definition: RISCVFixupKinds.h:78
llvm::RISCV::fixup_riscv_branch
@ fixup_riscv_branch
Definition: RISCVFixupKinds.h:54
MCELFObjectWriter.h
llvm::RISCV::fixup_riscv_align
@ fixup_riscv_align
Definition: RISCVFixupKinds.h:70
llvm::RISCV::fixup_riscv_tprel_lo12_s
@ fixup_riscv_tprel_lo12_s
Definition: RISCVFixupKinds.h:41
llvm::createRISCVELFObjectWriter
std::unique_ptr< MCObjectTargetWriter > createRISCVELFObjectWriter(uint8_t OSABI, bool Is64Bit)
Definition: RISCVELFObjectWriter.cpp:173
llvm::RISCV::fixup_riscv_tprel_lo12_i
@ fixup_riscv_tprel_lo12_i
Definition: RISCVFixupKinds.h:38
llvm::RISCV::fixup_riscv_add_8
@ fixup_riscv_add_8
Definition: RISCVFixupKinds.h:75
llvm::MCContext::reportError
void reportError(SMLoc L, const Twine &Msg)
Definition: MCContext.cpp:963
llvm::FK_Data_1
@ FK_Data_1
A one-byte fixup.
Definition: MCFixup.h:23
llvm::FK_PCRel_4
@ FK_PCRel_4
A four-byte pc relative fixup.
Definition: MCFixup.h:30
Fixup
PowerPC TLS Dynamic Call Fixup
Definition: PPCTLSDynamicCall.cpp:235
llvm::RISCV::fixup_riscv_pcrel_hi20
@ fixup_riscv_pcrel_hi20
Definition: RISCVFixupKinds.h:26
llvm::RISCV::fixup_riscv_sub_16
@ fixup_riscv_sub_16
Definition: RISCVFixupKinds.h:86
MCFixup.h
llvm::RISCV::fixup_riscv_set_8
@ fixup_riscv_set_8
Definition: RISCVFixupKinds.h:72
MCObjectWriter.h
llvm::RISCVMCExpr::VK_RISCV_32_PCREL
@ VK_RISCV_32_PCREL
Definition: RISCVMCExpr.h:39
llvm::RISCV::fixup_riscv_sub_32
@ fixup_riscv_sub_32
Definition: RISCVFixupKinds.h:94
llvm::RISCV::fixup_riscv_tprel_add
@ fixup_riscv_tprel_add
Definition: RISCVFixupKinds.h:44
llvm::RISCV::fixup_riscv_add_64
@ fixup_riscv_add_64
Definition: RISCVFixupKinds.h:97
llvm::RISCV::fixup_riscv_add_16
@ fixup_riscv_add_16
Definition: RISCVFixupKinds.h:83
llvm::RISCV::fixup_riscv_sub_6b
@ fixup_riscv_sub_6b
Definition: RISCVFixupKinds.h:106
llvm::RISCV::fixup_riscv_set_16
@ fixup_riscv_set_16
Definition: RISCVFixupKinds.h:80
llvm::FK_Data_8
@ FK_Data_8
A eight-byte fixup.
Definition: MCFixup.h:26
llvm::RISCV::fixup_riscv_set_32
@ fixup_riscv_set_32
Definition: RISCVFixupKinds.h:88
llvm::RISCV::fixup_riscv_rvc_branch
@ fixup_riscv_rvc_branch
Definition: RISCVFixupKinds.h:58
llvm::MCValue
This represents an "assembler immediate".
Definition: MCValue.h:37
llvm::FK_Data_2
@ FK_Data_2
A two-byte fixup.
Definition: MCFixup.h:24
true
basic Basic Alias true
Definition: BasicAliasAnalysis.cpp:1927
llvm::RISCV::fixup_riscv_tprel_hi20
@ fixup_riscv_tprel_hi20
Definition: RISCVFixupKinds.h:36
llvm::MCFixup
Encode information on a single operation to perform on a byte sequence (e.g., an encoded instruction)...
Definition: MCFixup.h:71
llvm::MCExpr
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:35
llvm::RISCV::fixup_riscv_set_6b
@ fixup_riscv_set_6b
Definition: RISCVFixupKinds.h:103
RISCVFixupKinds.h