LLVM 19.0.0git
SIModeRegisterDefaults.cpp
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1//===-- SIModeRegisterDefaults.cpp ------------------------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
10#include "GCNSubtarget.h"
11
12using namespace llvm;
13
15 const GCNSubtarget &ST) {
16 *this = getDefaultForCallingConv(F.getCallingConv());
17
18 if (ST.hasIEEEMode()) {
19 StringRef IEEEAttr = F.getFnAttribute("amdgpu-ieee").getValueAsString();
20 if (!IEEEAttr.empty())
21 IEEE = IEEEAttr == "true";
22 }
23
24 if (ST.hasDX10ClampMode()) {
25 StringRef DX10ClampAttr =
26 F.getFnAttribute("amdgpu-dx10-clamp").getValueAsString();
27 if (!DX10ClampAttr.empty())
28 DX10Clamp = DX10ClampAttr == "true";
29 }
30
31 StringRef DenormF32Attr =
32 F.getFnAttribute("denormal-fp-math-f32").getValueAsString();
33 if (!DenormF32Attr.empty())
35
36 StringRef DenormAttr =
37 F.getFnAttribute("denormal-fp-math").getValueAsString();
38 if (!DenormAttr.empty()) {
39 DenormalMode DenormMode = parseDenormalFPAttribute(DenormAttr);
40 if (DenormF32Attr.empty())
41 FP32Denormals = DenormMode;
42 FP64FP16Denormals = DenormMode;
43 }
44}
45
46using namespace AMDGPU;
47
48/// Combine f32 and f64 rounding modes into a combined rounding mode value.
49static constexpr uint32_t getModeRegisterRoundMode(uint32_t HWFP32Val,
50 uint32_t HWFP64Val) {
51 return HWFP32Val << F32FltRoundOffset | HWFP64Val << F64FltRoundOffset;
52}
53
54static constexpr uint64_t encodeFltRoundsTable(uint32_t FltRoundsVal,
55 uint32_t HWF32Val,
56 uint32_t HWF64Val) {
57 uint32_t ModeVal = getModeRegisterRoundMode(HWF32Val, HWF64Val);
58 if (FltRoundsVal > TowardNegative)
59 FltRoundsVal -= ExtendedFltRoundOffset;
60
61 uint32_t BitIndex = ModeVal << 2;
62 return static_cast<uint64_t>(FltRoundsVal) << BitIndex;
63}
64
65// Encode FLT_ROUNDS value where the two rounding modes are the same and use a
66// standard value
67static constexpr uint64_t
69 return encodeFltRoundsTable(FltRoundsMode, HWVal, HWVal);
70}
71
72// Convert mode register encoded rounding mode to AMDGPUFltRounds
73static constexpr AMDGPUFltRounds
75 uint32_t TableRead = (FltRoundConversionTable >> (HWMode << 2)) & 0xf;
76 if (TableRead > TowardNegative)
77 TableRead += ExtendedFltRoundOffset;
78 return static_cast<AMDGPUFltRounds>(TableRead);
79}
80
85
94
101
108
110 HWTowardZero) |
115
117 HWTowardZero) |
122
123// Verify evaluation of FltRoundConversionTable
124
125// If both modes are the same, should return the standard values.
127 HWTowardZero, HWTowardZero)) == AMDGPUFltRounds::TowardZero);
130 AMDGPUFltRounds::NearestTiesToEven);
133 AMDGPUFltRounds::TowardPositive);
136 AMDGPUFltRounds::TowardNegative);
137
147
157
167
AMD GCN specific subclass of TargetSubtarget.
#define F(x, y, z)
Definition: MD5.cpp:55
#define FP_ROUND_ROUND_TO_INF
Definition: SIDefines.h:1161
#define FP_ROUND_ROUND_TO_NEAREST
Definition: SIDefines.h:1160
#define FP_ROUND_ROUND_TO_ZERO
Definition: SIDefines.h:1163
#define FP_ROUND_ROUND_TO_NEGINF
Definition: SIDefines.h:1162
static constexpr AMDGPUFltRounds decodeIndexFltRoundConversionTable(uint32_t HWMode)
static constexpr uint32_t HWTowardNegative
static constexpr uint64_t encodeFltRoundsTableSame(AMDGPUFltRounds FltRoundsMode, uint32_t HWVal)
static constexpr uint32_t HWTowardPositive
static constexpr uint32_t HWTowardZero
static constexpr uint64_t encodeFltRoundsTable(uint32_t FltRoundsVal, uint32_t HWF32Val, uint32_t HWF64Val)
static constexpr uint32_t HWNearestTiesToEven
static constexpr uint32_t getModeRegisterRoundMode(uint32_t HWFP32Val, uint32_t HWFP64Val)
Combine f32 and f64 rounding modes into a combined rounding mode value.
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
constexpr bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:134
static constexpr uint32_t F64FltRoundOffset
Offset in mode register of f64/f16 rounding mode.
static constexpr uint32_t ExtendedFltRoundOffset
Offset of nonstandard values for llvm.get.rounding results from the largest supported mode.
AMDGPUFltRounds
Return values used for llvm.get.rounding.
static constexpr uint32_t F32FltRoundOffset
Offset in mode register of f32 rounding mode.
const uint64_t FltRoundConversionTable
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ TowardNegative
roundTowardNegative.
DenormalMode parseDenormalFPAttribute(StringRef Str)
Returns the denormal mode to use for inputs and outputs.
Represent subnormal handling kind for floating point instruction inputs and outputs.
bool DX10Clamp
Used by the vector ALU to force DX10-style treatment of NaNs: when set, clamp NaN to zero; otherwise,...
DenormalMode FP64FP16Denormals
If this is set, neither input or output denormals are flushed for both f64 and f16/v2f16 instructions...
bool IEEE
Floating point opcodes that support exception flag gathering quiet and propagate signaling NaN inputs...
static SIModeRegisterDefaults getDefaultForCallingConv(CallingConv::ID CC)
DenormalMode FP32Denormals
If this is set, neither input or output denormals are flushed for most f32 instructions.