LLVM 17.0.0git
Public Member Functions | Static Public Member Functions | Public Attributes | List of all members
llvm::SIModeRegisterDefaults Struct Reference

#include "Target/AMDGPU/SIModeRegisterDefaults.h"

Public Member Functions

 SIModeRegisterDefaults ()
 
 SIModeRegisterDefaults (const Function &F)
 
bool operator== (const SIModeRegisterDefaults Other) const
 
bool allFP32Denormals () const
 
bool allFP64FP16Denormals () const
 
uint32_t fpDenormModeSPValue () const
 Get the encoding value for the FP_DENORM bits of the mode register for the FP32 denormal mode.
 
uint32_t fpDenormModeDPValue () const
 Get the encoding value for the FP_DENORM bits of the mode register for the FP64/FP16 denormal mode.
 
bool isInlineCompatible (SIModeRegisterDefaults CalleeMode) const
 

Static Public Member Functions

static SIModeRegisterDefaults getDefaultForCallingConv (CallingConv::ID CC)
 

Public Attributes

bool IEEE: 1
 Floating point opcodes that support exception flag gathering quiet and propagate signaling NaN inputs per IEEE 754-2008.
 
bool DX10Clamp: 1
 Used by the vector ALU to force DX10-style treatment of NaNs: when set, clamp NaN to zero; otherwise, pass NaN through.
 
DenormalMode FP32Denormals
 If this is set, neither input or output denormals are flushed for most f32 instructions.
 
DenormalMode FP64FP16Denormals
 If this is set, neither input or output denormals are flushed for both f64 and f16/v2f16 instructions.
 

Detailed Description

Definition at line 18 of file SIModeRegisterDefaults.h.

Constructor & Destructor Documentation

◆ SIModeRegisterDefaults() [1/2]

llvm::SIModeRegisterDefaults::SIModeRegisterDefaults ( )
inline

Definition at line 37 of file SIModeRegisterDefaults.h.

◆ SIModeRegisterDefaults() [2/2]

SIModeRegisterDefaults::SIModeRegisterDefaults ( const Function F)

Member Function Documentation

◆ allFP32Denormals()

bool llvm::SIModeRegisterDefaults::allFP32Denormals ( ) const
inline

◆ allFP64FP16Denormals()

bool llvm::SIModeRegisterDefaults::allFP64FP16Denormals ( ) const
inline

◆ fpDenormModeDPValue()

uint32_t llvm::SIModeRegisterDefaults::fpDenormModeDPValue ( ) const
inline

◆ fpDenormModeSPValue()

uint32_t llvm::SIModeRegisterDefaults::fpDenormModeSPValue ( ) const
inline

◆ getDefaultForCallingConv()

static SIModeRegisterDefaults llvm::SIModeRegisterDefaults::getDefaultForCallingConv ( CallingConv::ID  CC)
inlinestatic

Definition at line 45 of file SIModeRegisterDefaults.h.

References CC, llvm::AMDGPU::isShader(), and Mode.

Referenced by SIModeRegisterDefaults().

◆ isInlineCompatible()

bool llvm::SIModeRegisterDefaults::isInlineCompatible ( SIModeRegisterDefaults  CalleeMode) const
inline

Definition at line 91 of file SIModeRegisterDefaults.h.

References DX10Clamp, and IEEE.

Referenced by llvm::GCNTTIImpl::areInlineCompatible().

◆ operator==()

bool llvm::SIModeRegisterDefaults::operator== ( const SIModeRegisterDefaults  Other) const
inline

Definition at line 51 of file SIModeRegisterDefaults.h.

References DX10Clamp, FP32Denormals, FP64FP16Denormals, IEEE, and llvm::Other.

Member Data Documentation

◆ DX10Clamp

bool llvm::SIModeRegisterDefaults::DX10Clamp

Used by the vector ALU to force DX10-style treatment of NaNs: when set, clamp NaN to zero; otherwise, pass NaN through.

Definition at line 27 of file SIModeRegisterDefaults.h.

Referenced by isInlineCompatible(), operator==(), llvm::GCNTargetMachine::parseMachineFunctionInfo(), and SIModeRegisterDefaults().

◆ FP32Denormals

DenormalMode llvm::SIModeRegisterDefaults::FP32Denormals

If this is set, neither input or output denormals are flushed for most f32 instructions.

Definition at line 31 of file SIModeRegisterDefaults.h.

Referenced by allFP32Denormals(), fpDenormModeSPValue(), operator==(), llvm::GCNTargetMachine::parseMachineFunctionInfo(), and SIModeRegisterDefaults().

◆ FP64FP16Denormals

DenormalMode llvm::SIModeRegisterDefaults::FP64FP16Denormals

If this is set, neither input or output denormals are flushed for both f64 and f16/v2f16 instructions.

Definition at line 35 of file SIModeRegisterDefaults.h.

Referenced by allFP64FP16Denormals(), fpDenormModeDPValue(), operator==(), llvm::GCNTargetMachine::parseMachineFunctionInfo(), and SIModeRegisterDefaults().

◆ IEEE

bool llvm::SIModeRegisterDefaults::IEEE

Floating point opcodes that support exception flag gathering quiet and propagate signaling NaN inputs per IEEE 754-2008.

Min_dx10 and max_dx10 become IEEE 754- 2008 compliant due to signaling NaN propagation and quieting.

Definition at line 23 of file SIModeRegisterDefaults.h.

Referenced by isInlineCompatible(), llvm::AMDGPULegalizerInfo::legalizeFFloor(), llvm::AMDGPULegalizerInfo::legalizeMinNumMaxNum(), llvm::AMDGPULegalizerInfo::legalizeRsqClampIntrinsic(), operator==(), llvm::GCNTargetMachine::parseMachineFunctionInfo(), and SIModeRegisterDefaults().


The documentation for this struct was generated from the following files: