LLVM 18.0.0git
SIModeRegisterDefaults.h
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1//===-- SIModeRegisterDefaults.h --------------------------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#ifndef LLVM_LIB_TARGET_AMDGPU_SIMODEREGISTERDEFAULTS_H
10#define LLVM_LIB_TARGET_AMDGPU_SIMODEREGISTERDEFAULTS_H
11
14
15namespace llvm {
16
17// Track defaults for fields in the MODE register.
19 /// Floating point opcodes that support exception flag gathering quiet and
20 /// propagate signaling NaN inputs per IEEE 754-2008. Min_dx10 and max_dx10
21 /// become IEEE 754- 2008 compliant due to signaling NaN propagation and
22 /// quieting.
23 bool IEEE : 1;
24
25 /// Used by the vector ALU to force DX10-style treatment of NaNs: when set,
26 /// clamp NaN to zero; otherwise, pass NaN through.
27 bool DX10Clamp : 1;
28
29 /// If this is set, neither input or output denormals are flushed for most f32
30 /// instructions.
32
33 /// If this is set, neither input or output denormals are flushed for both f64
34 /// and f16/v2f16 instructions.
36
38 IEEE(true),
40 FP32Denormals(DenormalMode::getIEEE()),
41 FP64FP16Denormals(DenormalMode::getIEEE()) {}
42
44
47 Mode.IEEE = !AMDGPU::isShader(CC);
48 return Mode;
49 }
50
52 return IEEE == Other.IEEE && DX10Clamp == Other.DX10Clamp &&
53 FP32Denormals == Other.FP32Denormals &&
54 FP64FP16Denormals == Other.FP64FP16Denormals;
55 }
56
57 /// Get the encoding value for the FP_DENORM bits of the mode register for the
58 /// FP32 denormal mode.
65 return FP_DENORM_FLUSH_IN;
67 }
68
69 /// Get the encoding value for the FP_DENORM bits of the mode register for the
70 /// FP64/FP16 denormal mode.
77 return FP_DENORM_FLUSH_IN;
79 }
80
81 // FIXME: Inlining should be OK for dx10-clamp, since the caller's mode should
82 // be able to override.
84 return DX10Clamp == CalleeMode.DX10Clamp && IEEE == CalleeMode.IEEE;
85 }
86};
87
88namespace AMDGPU {
89
90/// Return values used for llvm.get.rounding
91///
92/// When both the F32 and F64/F16 modes are the same, returns the standard
93/// values. If they differ, returns an extended mode starting at 8.
94enum AMDGPUFltRounds : int8_t {
95 // Inherit everything from RoundingMode
96 TowardZero = static_cast<int8_t>(RoundingMode::TowardZero),
102
103 Dynamic = static_cast<int8_t>(RoundingMode::Dynamic),
104
105 // Permute the mismatched rounding mode cases. If the modes are the same, use
106 // the standard values, otherwise, these values are sorted such that higher
107 // hardware encoded values have higher enum values.
112
117
122
127
128 Invalid = static_cast<int8_t>(RoundingMode::Invalid)
130
131/// Offset of nonstandard values for llvm.get.rounding results from the largest
132/// supported mode.
133static constexpr uint32_t ExtendedFltRoundOffset = 4;
134
135/// Offset in mode register of f32 rounding mode.
136static constexpr uint32_t F32FltRoundOffset = 0;
137
138/// Offset in mode register of f64/f16 rounding mode.
139static constexpr uint32_t F64FltRoundOffset = 2;
140
141// Bit indexed table to convert from hardware rounding mode values to FLT_ROUNDS
142// values.
144
145} // end namespace AMDGPU
146
147} // end namespace llvm
148
149#endif // LLVM_LIB_TARGET_AMDGPU_SIMODEREGISTERDEFAULTS_H
basic Basic Alias true
Utilities for dealing with flags related to floating point properties and mode controls.
#define F(x, y, z)
Definition: MD5.cpp:55
static cl::opt< RegAllocEvictionAdvisorAnalysis::AdvisorMode > Mode("regalloc-enable-advisor", cl::Hidden, cl::init(RegAllocEvictionAdvisorAnalysis::AdvisorMode::Default), cl::desc("Enable regalloc advisor mode"), cl::values(clEnumValN(RegAllocEvictionAdvisorAnalysis::AdvisorMode::Default, "default", "Default"), clEnumValN(RegAllocEvictionAdvisorAnalysis::AdvisorMode::Release, "release", "precompiled"), clEnumValN(RegAllocEvictionAdvisorAnalysis::AdvisorMode::Development, "development", "for training")))
#define FP_DENORM_FLUSH_OUT
Definition: SIDefines.h:1149
#define FP_DENORM_FLUSH_NONE
Definition: SIDefines.h:1151
#define FP_DENORM_FLUSH_IN_FLUSH_OUT
Definition: SIDefines.h:1148
#define FP_DENORM_FLUSH_IN
Definition: SIDefines.h:1150
static constexpr uint32_t F64FltRoundOffset
Offset in mode register of f64/f16 rounding mode.
static constexpr uint32_t ExtendedFltRoundOffset
Offset of nonstandard values for llvm.get.rounding results from the largest supported mode.
bool isShader(CallingConv::ID cc)
AMDGPUFltRounds
Return values used for llvm.get.rounding.
static constexpr uint32_t F32FltRoundOffset
Offset in mode register of f32 rounding mode.
const uint64_t FltRoundConversionTable
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Other
Any other memory.
@ TowardZero
roundTowardZero.
@ NearestTiesToEven
roundTiesToEven.
@ Invalid
Denotes invalid value.
@ Dynamic
Denotes mode unknown at compile time.
@ TowardPositive
roundTowardPositive.
@ NearestTiesToAway
roundTiesToAway.
@ TowardNegative
roundTowardNegative.
Represent subnormal handling kind for floating point instruction inputs and outputs.
DenormalModeKind Input
Denormal treatment kind for floating point instruction inputs in the default floating-point environme...
@ PreserveSign
The sign of a flushed-to-zero number is preserved in the sign of 0.
static constexpr DenormalMode getPreserveSign()
DenormalModeKind Output
Denormal flushing mode for floating point instruction results in the default floating point environme...
bool DX10Clamp
Used by the vector ALU to force DX10-style treatment of NaNs: when set, clamp NaN to zero; otherwise,...
uint32_t fpDenormModeSPValue() const
Get the encoding value for the FP_DENORM bits of the mode register for the FP32 denormal mode.
DenormalMode FP64FP16Denormals
If this is set, neither input or output denormals are flushed for both f64 and f16/v2f16 instructions...
bool IEEE
Floating point opcodes that support exception flag gathering quiet and propagate signaling NaN inputs...
static SIModeRegisterDefaults getDefaultForCallingConv(CallingConv::ID CC)
uint32_t fpDenormModeDPValue() const
Get the encoding value for the FP_DENORM bits of the mode register for the FP64/FP16 denormal mode.
bool isInlineCompatible(SIModeRegisterDefaults CalleeMode) const
bool operator==(const SIModeRegisterDefaults Other) const
DenormalMode FP32Denormals
If this is set, neither input or output denormals are flushed for most f32 instructions.