LLVM 17.0.0git
SystemZMCTargetDesc.h
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1//===-- SystemZMCTargetDesc.h - SystemZ target descriptions -----*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#ifndef LLVM_LIB_TARGET_SYSTEMZ_MCTARGETDESC_SYSTEMZMCTARGETDESC_H
10#define LLVM_LIB_TARGET_SYSTEMZ_MCTARGETDESC_SYSTEMZMCTARGETDESC_H
11
13
14#include <memory>
15
16namespace llvm {
17
18class MCAsmBackend;
19class MCCodeEmitter;
20class MCContext;
21class MCInstrInfo;
22class MCObjectTargetWriter;
23class MCRegisterInfo;
24class MCSubtargetInfo;
25class MCTargetOptions;
26class Target;
27
28namespace SystemZMC {
29// How many bytes are in the ABI-defined, caller-allocated part of
30// a stack frame.
31const int64_t ELFCallFrameSize = 160;
32
33// The offset of the DWARF CFA from the incoming stack pointer.
35
36// Maps of asm register numbers to LLVM register numbers, with 0 indicating
37// an invalid register. In principle we could use 32-bit and 64-bit register
38// classes directly, provided that we relegated the GPR allocation order
39// in SystemZRegisterInfo.td to an AltOrder and left the default order
40// as %r0-%r15. It seems better to provide the same interface for
41// all classes though.
42extern const unsigned GR32Regs[16];
43extern const unsigned GRH32Regs[16];
44extern const unsigned GR64Regs[16];
45extern const unsigned GR128Regs[16];
46extern const unsigned FP32Regs[16];
47extern const unsigned FP64Regs[16];
48extern const unsigned FP128Regs[16];
49extern const unsigned VR32Regs[32];
50extern const unsigned VR64Regs[32];
51extern const unsigned VR128Regs[32];
52extern const unsigned AR32Regs[16];
53extern const unsigned CR64Regs[16];
54
55// Return the 0-based number of the first architectural register that
56// contains the given LLVM register. E.g. R1D -> 1.
57unsigned getFirstReg(unsigned Reg);
58
59// Return the given register as a GR64.
60inline unsigned getRegAsGR64(unsigned Reg) {
61 return GR64Regs[getFirstReg(Reg)];
62}
63
64// Return the given register as a low GR32.
65inline unsigned getRegAsGR32(unsigned Reg) {
66 return GR32Regs[getFirstReg(Reg)];
67}
68
69// Return the given register as a high GR32.
70inline unsigned getRegAsGRH32(unsigned Reg) {
71 return GRH32Regs[getFirstReg(Reg)];
72}
73
74// Return the given register as a VR128.
75inline unsigned getRegAsVR128(unsigned Reg) {
76 return VR128Regs[getFirstReg(Reg)];
77}
78} // end namespace SystemZMC
79
80MCCodeEmitter *createSystemZMCCodeEmitter(const MCInstrInfo &MCII,
81 MCContext &Ctx);
82
83MCAsmBackend *createSystemZMCAsmBackend(const Target &T,
84 const MCSubtargetInfo &STI,
85 const MCRegisterInfo &MRI,
86 const MCTargetOptions &Options);
87
88std::unique_ptr<MCObjectTargetWriter> createSystemZObjectWriter(uint8_t OSABI);
89} // end namespace llvm
90
91// Defines symbolic names for SystemZ registers.
92// This defines a mapping from register name to register number.
93#define GET_REGINFO_ENUM
94#include "SystemZGenRegisterInfo.inc"
95
96// Defines symbolic names for the SystemZ instructions.
97#define GET_INSTRINFO_ENUM
98#define GET_INSTRINFO_MC_HELPER_DECLS
99#include "SystemZGenInstrInfo.inc"
100
101#define GET_SUBTARGETINFO_ENUM
102#include "SystemZGenSubtargetInfo.inc"
103
104#endif
unsigned const MachineRegisterInfo * MRI
static LVOptions Options
Definition: LVOptions.cpp:25
unsigned Reg
unsigned getRegAsGR32(unsigned Reg)
const unsigned GR64Regs[16]
const unsigned VR128Regs[32]
unsigned getRegAsGRH32(unsigned Reg)
unsigned getRegAsVR128(unsigned Reg)
const unsigned GR128Regs[16]
const unsigned GRH32Regs[16]
const unsigned FP32Regs[16]
const unsigned GR32Regs[16]
const unsigned FP64Regs[16]
const int64_t ELFCallFrameSize
const int64_t ELFCFAOffsetFromInitialSP
const unsigned VR64Regs[32]
unsigned getFirstReg(unsigned Reg)
unsigned getRegAsGR64(unsigned Reg)
const unsigned FP128Regs[16]
const unsigned AR32Regs[16]
const unsigned VR32Regs[32]
const unsigned CR64Regs[16]
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
MCAsmBackend * createSystemZMCAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
std::unique_ptr< MCObjectTargetWriter > createSystemZObjectWriter(uint8_t OSABI)
MCCodeEmitter * createSystemZMCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx)