LLVM  15.0.0git
SystemZMCTargetDesc.cpp
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1 //===-- SystemZMCTargetDesc.cpp - SystemZ target descriptions -------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #include "SystemZMCTargetDesc.h"
10 #include "SystemZInstPrinter.h"
11 #include "SystemZMCAsmInfo.h"
12 #include "SystemZTargetStreamer.h"
14 #include "llvm/MC/MCContext.h"
15 #include "llvm/MC/MCDwarf.h"
16 #include "llvm/MC/MCInst.h"
17 #include "llvm/MC/MCInstrInfo.h"
18 #include "llvm/MC/MCRegisterInfo.h"
19 #include "llvm/MC/MCStreamer.h"
21 #include "llvm/MC/TargetRegistry.h"
22 
23 using namespace llvm;
24 
25 #define GET_INSTRINFO_MC_DESC
26 #include "SystemZGenInstrInfo.inc"
27 
28 #define GET_SUBTARGETINFO_MC_DESC
29 #include "SystemZGenSubtargetInfo.inc"
30 
31 #define GET_REGINFO_MC_DESC
32 #include "SystemZGenRegisterInfo.inc"
33 
34 const unsigned SystemZMC::GR32Regs[16] = {
35  SystemZ::R0L, SystemZ::R1L, SystemZ::R2L, SystemZ::R3L,
36  SystemZ::R4L, SystemZ::R5L, SystemZ::R6L, SystemZ::R7L,
37  SystemZ::R8L, SystemZ::R9L, SystemZ::R10L, SystemZ::R11L,
38  SystemZ::R12L, SystemZ::R13L, SystemZ::R14L, SystemZ::R15L
39 };
40 
41 const unsigned SystemZMC::GRH32Regs[16] = {
42  SystemZ::R0H, SystemZ::R1H, SystemZ::R2H, SystemZ::R3H,
43  SystemZ::R4H, SystemZ::R5H, SystemZ::R6H, SystemZ::R7H,
44  SystemZ::R8H, SystemZ::R9H, SystemZ::R10H, SystemZ::R11H,
45  SystemZ::R12H, SystemZ::R13H, SystemZ::R14H, SystemZ::R15H
46 };
47 
48 const unsigned SystemZMC::GR64Regs[16] = {
49  SystemZ::R0D, SystemZ::R1D, SystemZ::R2D, SystemZ::R3D,
50  SystemZ::R4D, SystemZ::R5D, SystemZ::R6D, SystemZ::R7D,
51  SystemZ::R8D, SystemZ::R9D, SystemZ::R10D, SystemZ::R11D,
52  SystemZ::R12D, SystemZ::R13D, SystemZ::R14D, SystemZ::R15D
53 };
54 
55 const unsigned SystemZMC::GR128Regs[16] = {
56  SystemZ::R0Q, 0, SystemZ::R2Q, 0,
57  SystemZ::R4Q, 0, SystemZ::R6Q, 0,
58  SystemZ::R8Q, 0, SystemZ::R10Q, 0,
59  SystemZ::R12Q, 0, SystemZ::R14Q, 0
60 };
61 
62 const unsigned SystemZMC::FP32Regs[16] = {
63  SystemZ::F0S, SystemZ::F1S, SystemZ::F2S, SystemZ::F3S,
64  SystemZ::F4S, SystemZ::F5S, SystemZ::F6S, SystemZ::F7S,
65  SystemZ::F8S, SystemZ::F9S, SystemZ::F10S, SystemZ::F11S,
66  SystemZ::F12S, SystemZ::F13S, SystemZ::F14S, SystemZ::F15S
67 };
68 
69 const unsigned SystemZMC::FP64Regs[16] = {
70  SystemZ::F0D, SystemZ::F1D, SystemZ::F2D, SystemZ::F3D,
71  SystemZ::F4D, SystemZ::F5D, SystemZ::F6D, SystemZ::F7D,
72  SystemZ::F8D, SystemZ::F9D, SystemZ::F10D, SystemZ::F11D,
73  SystemZ::F12D, SystemZ::F13D, SystemZ::F14D, SystemZ::F15D
74 };
75 
76 const unsigned SystemZMC::FP128Regs[16] = {
77  SystemZ::F0Q, SystemZ::F1Q, 0, 0,
78  SystemZ::F4Q, SystemZ::F5Q, 0, 0,
79  SystemZ::F8Q, SystemZ::F9Q, 0, 0,
80  SystemZ::F12Q, SystemZ::F13Q, 0, 0
81 };
82 
83 const unsigned SystemZMC::VR32Regs[32] = {
84  SystemZ::F0S, SystemZ::F1S, SystemZ::F2S, SystemZ::F3S,
85  SystemZ::F4S, SystemZ::F5S, SystemZ::F6S, SystemZ::F7S,
86  SystemZ::F8S, SystemZ::F9S, SystemZ::F10S, SystemZ::F11S,
87  SystemZ::F12S, SystemZ::F13S, SystemZ::F14S, SystemZ::F15S,
88  SystemZ::F16S, SystemZ::F17S, SystemZ::F18S, SystemZ::F19S,
89  SystemZ::F20S, SystemZ::F21S, SystemZ::F22S, SystemZ::F23S,
90  SystemZ::F24S, SystemZ::F25S, SystemZ::F26S, SystemZ::F27S,
91  SystemZ::F28S, SystemZ::F29S, SystemZ::F30S, SystemZ::F31S
92 };
93 
94 const unsigned SystemZMC::VR64Regs[32] = {
95  SystemZ::F0D, SystemZ::F1D, SystemZ::F2D, SystemZ::F3D,
96  SystemZ::F4D, SystemZ::F5D, SystemZ::F6D, SystemZ::F7D,
97  SystemZ::F8D, SystemZ::F9D, SystemZ::F10D, SystemZ::F11D,
98  SystemZ::F12D, SystemZ::F13D, SystemZ::F14D, SystemZ::F15D,
99  SystemZ::F16D, SystemZ::F17D, SystemZ::F18D, SystemZ::F19D,
100  SystemZ::F20D, SystemZ::F21D, SystemZ::F22D, SystemZ::F23D,
101  SystemZ::F24D, SystemZ::F25D, SystemZ::F26D, SystemZ::F27D,
102  SystemZ::F28D, SystemZ::F29D, SystemZ::F30D, SystemZ::F31D
103 };
104 
105 const unsigned SystemZMC::VR128Regs[32] = {
106  SystemZ::V0, SystemZ::V1, SystemZ::V2, SystemZ::V3,
107  SystemZ::V4, SystemZ::V5, SystemZ::V6, SystemZ::V7,
108  SystemZ::V8, SystemZ::V9, SystemZ::V10, SystemZ::V11,
109  SystemZ::V12, SystemZ::V13, SystemZ::V14, SystemZ::V15,
110  SystemZ::V16, SystemZ::V17, SystemZ::V18, SystemZ::V19,
111  SystemZ::V20, SystemZ::V21, SystemZ::V22, SystemZ::V23,
112  SystemZ::V24, SystemZ::V25, SystemZ::V26, SystemZ::V27,
113  SystemZ::V28, SystemZ::V29, SystemZ::V30, SystemZ::V31
114 };
115 
116 const unsigned SystemZMC::AR32Regs[16] = {
117  SystemZ::A0, SystemZ::A1, SystemZ::A2, SystemZ::A3,
118  SystemZ::A4, SystemZ::A5, SystemZ::A6, SystemZ::A7,
119  SystemZ::A8, SystemZ::A9, SystemZ::A10, SystemZ::A11,
120  SystemZ::A12, SystemZ::A13, SystemZ::A14, SystemZ::A15
121 };
122 
123 const unsigned SystemZMC::CR64Regs[16] = {
124  SystemZ::C0, SystemZ::C1, SystemZ::C2, SystemZ::C3,
125  SystemZ::C4, SystemZ::C5, SystemZ::C6, SystemZ::C7,
126  SystemZ::C8, SystemZ::C9, SystemZ::C10, SystemZ::C11,
127  SystemZ::C12, SystemZ::C13, SystemZ::C14, SystemZ::C15
128 };
129 
130 unsigned SystemZMC::getFirstReg(unsigned Reg) {
131  static unsigned Map[SystemZ::NUM_TARGET_REGS];
132  static bool Initialized = false;
133  if (!Initialized) {
134  for (unsigned I = 0; I < 16; ++I) {
135  Map[GR32Regs[I]] = I;
136  Map[GRH32Regs[I]] = I;
137  Map[GR64Regs[I]] = I;
138  Map[GR128Regs[I]] = I;
139  Map[FP128Regs[I]] = I;
140  Map[AR32Regs[I]] = I;
141  }
142  for (unsigned I = 0; I < 32; ++I) {
143  Map[VR32Regs[I]] = I;
144  Map[VR64Regs[I]] = I;
145  Map[VR128Regs[I]] = I;
146  }
147  }
148  assert(Reg < SystemZ::NUM_TARGET_REGS);
149  return Map[Reg];
150 }
151 
153  const Triple &TT,
154  const MCTargetOptions &Options) {
155  if (TT.isOSzOS())
156  return new SystemZMCAsmInfoGOFF(TT);
157 
158  MCAsmInfo *MAI = new SystemZMCAsmInfoELF(TT);
160  nullptr, MRI.getDwarfRegNum(SystemZ::R15D, true),
162  MAI->addInitialFrameState(Inst);
163  return MAI;
164 }
165 
167  MCInstrInfo *X = new MCInstrInfo();
168  InitSystemZMCInstrInfo(X);
169  return X;
170 }
171 
174  InitSystemZMCRegisterInfo(X, SystemZ::R14D);
175  return X;
176 }
177 
178 static MCSubtargetInfo *
180  return createSystemZMCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS);
181 }
182 
184  unsigned SyntaxVariant,
185  const MCAsmInfo &MAI,
186  const MCInstrInfo &MII,
187  const MCRegisterInfo &MRI) {
188  return new SystemZInstPrinter(MAI, MII, MRI);
189 }
190 
192  // Emit EXRL target instructions.
193  if (EXRLTargets2Sym.empty())
194  return;
195  // Switch to the .text section.
198  for (auto &I : EXRLTargets2Sym) {
199  Streamer.emitLabel(I.second);
200  const MCInstSTIPair &MCI_STI = I.first;
201  Streamer.emitInstruction(MCI_STI.first, *MCI_STI.second);
202  }
203  EXRLTargets2Sym.clear();
204 }
205 
206 namespace {
207 class SystemZTargetAsmStreamer : public SystemZTargetStreamer {
209 
210 public:
211  SystemZTargetAsmStreamer(MCStreamer &S, formatted_raw_ostream &OS)
212  : SystemZTargetStreamer(S), OS(OS) {}
213  void emitMachine(StringRef CPU) override {
214  OS << "\t.machine " << CPU << "\n";
215  }
216 };
217 
218 class SystemZTargetELFStreamer : public SystemZTargetStreamer {
219 public:
220  SystemZTargetELFStreamer(MCStreamer &S) : SystemZTargetStreamer(S) {}
221  void emitMachine(StringRef CPU) override {}
222 };
223 } // end namespace
224 
225 static MCTargetStreamer *
228  MCInstPrinter *InstPrint,
229  bool isVerboseAsm) {
230  return new SystemZTargetAsmStreamer(S, OS);
231 }
232 
233 static MCTargetStreamer *
235  return new SystemZTargetELFStreamer(S);
236 }
237 
239  // Register the MCAsmInfo.
242 
243  // Register the MCCodeEmitter.
246 
247  // Register the MCInstrInfo.
250 
251  // Register the MCRegisterInfo.
254 
255  // Register the MCSubtargetInfo.
258 
259  // Register the MCAsmBackend.
262 
263  // Register the MCInstPrinter.
266 
267  // Register the asm streamer.
270 
271  // Register the obj streamer
274 }
llvm::SystemZMC::GR128Regs
const unsigned GR128Regs[16]
Definition: SystemZMCTargetDesc.cpp:55
llvm::MCContext::getObjectFileInfo
const MCObjectFileInfo * getObjectFileInfo() const
Definition: MCContext.h:443
MCDwarf.h
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
T
C1
instcombine should handle this C2 when C1
Definition: README.txt:263
llvm::MCAsmInfo
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:56
llvm::SystemZMC::VR128Regs
const unsigned VR128Regs[32]
Definition: SystemZMCTargetDesc.cpp:105
llvm::SystemZMC::FP32Regs
const unsigned FP32Regs[16]
Definition: SystemZMCTargetDesc.cpp:62
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
llvm::TargetRegistry::RegisterAsmTargetStreamer
static void RegisterAsmTargetStreamer(Target &T, Target::AsmTargetStreamerCtorTy Fn)
Definition: TargetRegistry.h:993
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
createAsmTargetStreamer
static MCTargetStreamer * createAsmTargetStreamer(MCStreamer &S, formatted_raw_ostream &OS, MCInstPrinter *InstPrint, bool isVerboseAsm)
Definition: SystemZMCTargetDesc.cpp:226
llvm::SystemZMC::GR64Regs
const unsigned GR64Regs[16]
Definition: SystemZMCTargetDesc.cpp:48
llvm::SystemZTargetStreamer
Definition: SystemZTargetStreamer.h:18
SystemZMCTargetDesc.h
llvm::SystemZMC::FP128Regs
const unsigned FP128Regs[16]
Definition: SystemZMCTargetDesc.cpp:76
llvm::SystemZMC::AR32Regs
const unsigned AR32Regs[16]
Definition: SystemZMCTargetDesc.cpp:116
llvm::TargetRegistry::RegisterMCInstPrinter
static void RegisterMCInstPrinter(Target &T, Target::MCInstPrinterCtorTy Fn)
RegisterMCInstPrinter - Register a MCInstPrinter implementation for the given target.
Definition: TargetRegistry.h:947
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SystemZInstPrinter.h
SystemZTargetStreamer.h
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Streaming machine code generation interface.
Definition: MCStreamer.h:201
llvm::SystemZMC::CR64Regs
const unsigned CR64Regs[16]
Definition: SystemZMCTargetDesc.cpp:123
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MCCodeEmitter * createSystemZMCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx)
Definition: SystemZMCCodeEmitter.cpp:335
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void emitConstantPools() override
Definition: SystemZMCTargetDesc.cpp:191
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Target & getTheSystemZTarget()
Definition: SystemZTargetInfo.cpp:14
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virtual void emitLabel(MCSymbol *Symbol, SMLoc Loc=SMLoc())
Emit a label for Symbol into the current section.
Definition: MCStreamer.cpp:416
MCInstrInfo.h
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static MCRegisterInfo * createSystemZMCRegisterInfo(const Triple &TT)
Definition: SystemZMCTargetDesc.cpp:172
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const unsigned GR32Regs[16]
Definition: SystemZMCTargetDesc.cpp:34
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Definition: SystemZInstPrinter.h:24
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Definition: PassBuilderBindings.cpp:48
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Definition: SystemZMCTargetDesc.cpp:234
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Target specific streamer interface.
Definition: MCStreamer.h:93
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Definition: MCObjectFileInfo.h:267
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Definition: SystemZMCTargetDesc.cpp:166
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Definition: MCDwarf.h:472
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Definition: NVPTX.h:124
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Definition: SystemZMCTargetDesc.h:34
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static void RegisterMCAsmBackend(Target &T, Target::MCAsmBackendCtorTy Fn)
RegisterMCAsmBackend - Register a MCAsmBackend implementation for the given target.
Definition: TargetRegistry.h:894
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Definition: SystemZTargetStreamer.h:22
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Definition: MCStreamer.h:95
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Definition: MCInstPrinter.h:43
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Definition: Compiler.h:126
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Definition: MCStreamer.cpp:1091
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Definition: TargetRegistry.h:999
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Definition: FormattedStream.h:30
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static void RegisterMCAsmInfo(Target &T, Target::MCAsmInfoCtorFnTy Fn)
RegisterMCAsmInfo - Register a MCAsmInfo implementation for the given target.
Definition: TargetRegistry.h:808
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static MCCFIInstruction cfiDefCfa(MCSymbol *L, unsigned Register, int Offset)
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Definition: MCDwarf.h:526
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Definition: MCAsmInfo.cpp:86
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const unsigned FP64Regs[16]
Definition: SystemZMCTargetDesc.cpp:69
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static void RegisterMCSubtargetInfo(Target &T, Target::MCSubtargetInfoCtorFnTy Fn)
RegisterMCSubtargetInfo - Register a MCSubtargetInfo implementation for the given target.
Definition: TargetRegistry.h:867
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Definition: MCTargetOptions.h:36
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const unsigned GRH32Regs[16]
Definition: SystemZMCTargetDesc.cpp:41
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Definition: StringRef.h:58
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Definition: README.txt:210
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Definition: SystemZMCAsmInfo.h:20
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Definition: MCRegisterInfo.h:135
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Definition: AArch64AdvSIMDScalarPass.cpp:105
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Definition: NVPTX.h:123
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RegisterMCInstrInfo - Register a MCInstrInfo implementation for the given target.
Definition: TargetRegistry.h:834
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static void RegisterMCCodeEmitter(Target &T, Target::MCCodeEmitterCtorTy Fn)
RegisterMCCodeEmitter - Register a MCCodeEmitter implementation for the given target.
Definition: TargetRegistry.h:960
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Interface to description of machine instruction set.
Definition: MCInstrInfo.h:26
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Definition: SystemZMCAsmInfo.h:25
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static void RegisterMCRegInfo(Target &T, Target::MCRegInfoCtorFnTy Fn)
RegisterMCRegInfo - Register a MCRegisterInfo implementation for the given target.
Definition: TargetRegistry.h:854
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Definition: SystemZMCTargetDesc.cpp:130
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Definition: SystemZMCTargetDesc.cpp:152
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Definition: SystemZMCTargetDesc.cpp:94
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Definition: SystemZMCTargetDesc.cpp:183
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Definition: SystemZTargetStreamer.h:47
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Definition: MCStreamer.h:282
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Definition: SystemZMCAsmBackend.cpp:194
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Definition: X86.h:192
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Definition: SystemZMCTargetDesc.cpp:238
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Definition: MCStreamer.cpp:1220
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Definition: MCSubtargetInfo.h:76
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Definition: MCObjectFileInfo.h:27
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Definition: SystemZMCTargetDesc.cpp:83
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Definition: SystemZMCTargetDesc.cpp:179
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