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23 :
MCSubtargetInfo(TT, CPU, TuneCPU,
FS, PF,
PD, WPR, WL,
RA, IS,
OC,
FP) {}
This is an optimization pass for GlobalISel generic memory operations.
virtual bool enablePostRAScheduler() const
True if the subtarget should run a scheduler after register allocation.
const MCSchedModel & getSchedModel() const
Get the machine model for this subtarget's CPU.
virtual bool enableRALocalReassignment(CodeGenOpt::Level OptLevel) const
True if the subtarget should run the local reassignment heuristic of the register allocator.
Triple - Helper class for working with autoconf configuration names.
virtual void mirFileLoaded(MachineFunction &MF) const
This is called after a .mir file was loaded.
Identify one of the processor resource kinds consumed by a particular scheduling class for the specif...
~TargetSubtargetInfo() override
virtual bool enableIndirectBrExpand() const
True if the subtarget should run the indirectbr expansion pass.
virtual bool enablePostRAMachineScheduler() const
True if the subtarget should run a machine scheduler after register allocation.
Specify the latency in cpu cycles for a particular scheduling class and def index.
SI optimize exec mask operations pre RA
virtual bool useAA() const
Enable use of alias analysis during code generation (during MI scheduling, DAGCombine,...
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
StringRef - Represent a constant reference to a string, i.e.
virtual bool enableJoinGlobalCopies() const
True if the subtarget should enable joining global copies.
These values represent a non-pipelined step in the execution of an instruction.
Specify the number of cycles allowed after instruction issue before a particular use operand reads it...
TargetSubtargetInfo()=delete
Generic base class for all target subtargets.
virtual bool enableMachineScheduler() const
True if the subtarget should run MachineScheduler after aggressive coalescing.
virtual bool enableAtomicExpand() const
True if the subtarget should run the atomic expansion pass.