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LLVM 18.0.0git
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#include "AArch64MachineFunctionInfo.h"#include "AArch64TargetMachine.h"#include "MCTargetDesc/AArch64AddressingModes.h"#include "llvm/ADT/APSInt.h"#include "llvm/CodeGen/ISDOpcodes.h"#include "llvm/CodeGen/SelectionDAGISel.h"#include "llvm/IR/Function.h"#include "llvm/IR/GlobalValue.h"#include "llvm/IR/Intrinsics.h"#include "llvm/IR/IntrinsicsAArch64.h"#include "llvm/Support/Debug.h"#include "llvm/Support/ErrorHandling.h"#include "llvm/Support/KnownBits.h"#include "llvm/Support/MathExtras.h"#include "llvm/Support/raw_ostream.h"#include "AArch64GenDAGISel.inc"Go to the source code of this file.
Macros | |
| #define | DEBUG_TYPE "aarch64-isel" |
| #define | PASS_NAME "AArch64 Instruction Selection" |
Enumerations | |
| enum class | SelectTypeKind { Int1 = 0 , Int = 1 , FP = 2 , AnyType = 3 } |
Functions | |
| static bool | isIntImmediate (const SDNode *N, uint64_t &Imm) |
| isIntImmediate - This method tests to see if the node is a constant operand. | |
| static bool | isIntImmediate (SDValue N, uint64_t &Imm) |
| static bool | isOpcWithIntImmediate (const SDNode *N, unsigned Opc, uint64_t &Imm) |
| static bool | isIntImmediateEq (SDValue N, const uint64_t ImmExpected) |
| static AArch64_AM::ShiftExtendType | getShiftTypeForNode (SDValue N) |
| getShiftTypeForNode - Translate a shift node to the corresponding ShiftType value. | |
| static bool | isWorthFoldingSHL (SDValue V) |
| Determine whether it is worth it to fold SHL into the addressing mode. | |
| static AArch64_AM::ShiftExtendType | getExtendTypeForNode (SDValue N, bool IsLoadStore=false) |
| getExtendTypeForNode - Translate an extend node to the corresponding ExtendType value. | |
| static SDValue | narrowIfNeeded (SelectionDAG *CurDAG, SDValue N) |
| Instructions that accept extend modifiers like UXTW expect the register being extended to be a GPR32, but the incoming DAG might be acting on a GPR64 (either via SEXT_INREG or AND). | |
| static bool | isWorthFoldingADDlow (SDValue N) |
| If there's a use of this ADDlow that's not itself a load/store then we'll need to create a real ADD instruction from it anyway and there's no point in folding it into the mem op. | |
| static SDValue | Widen (SelectionDAG *CurDAG, SDValue N) |
| static bool | isPreferredADD (int64_t ImmOff) |
| template<SelectTypeKind Kind> | |
| static unsigned | SelectOpcodeFromVT (EVT VT, ArrayRef< unsigned > Opcodes) |
| This function selects an opcode from a list of opcodes, which is expected to be the opcode for { 8-bit, 16-bit, 32-bit, 64-bit } element types, in this order. | |
| bool | SelectSMETile (unsigned &BaseReg, unsigned TileNum) |
| static SDValue | NarrowVector (SDValue V128Reg, SelectionDAG &DAG) |
| NarrowVector - Given a value in the V128 register class, produce the equivalent value in the V64 register class. | |
| static bool | isBitfieldExtractOpFromAnd (SelectionDAG *CurDAG, SDNode *N, unsigned &Opc, SDValue &Opd0, unsigned &LSB, unsigned &MSB, unsigned NumberOfIgnoredLowBits, bool BiggerPattern) |
| static bool | isBitfieldExtractOpFromSExtInReg (SDNode *N, unsigned &Opc, SDValue &Opd0, unsigned &Immr, unsigned &Imms) |
| static bool | isSeveralBitsExtractOpFromShr (SDNode *N, unsigned &Opc, SDValue &Opd0, unsigned &LSB, unsigned &MSB) |
| static bool | isBitfieldExtractOpFromShr (SDNode *N, unsigned &Opc, SDValue &Opd0, unsigned &Immr, unsigned &Imms, bool BiggerPattern) |
| static bool | isBitfieldExtractOp (SelectionDAG *CurDAG, SDNode *N, unsigned &Opc, SDValue &Opd0, unsigned &Immr, unsigned &Imms, unsigned NumberOfIgnoredLowBits=0, bool BiggerPattern=false) |
| static bool | isBitfieldDstMask (uint64_t DstMask, const APInt &BitsToBeInserted, unsigned NumberOfIgnoredHighBits, EVT VT) |
| Does DstMask form a complementary pair with the mask provided by BitsToBeInserted, suitable for use in a BFI instruction. | |
| static void | getUsefulBits (SDValue Op, APInt &UsefulBits, unsigned Depth=0) |
| static void | getUsefulBitsFromAndWithImmediate (SDValue Op, APInt &UsefulBits, unsigned Depth) |
| static void | getUsefulBitsFromBitfieldMoveOpd (SDValue Op, APInt &UsefulBits, uint64_t Imm, uint64_t MSB, unsigned Depth) |
| static void | getUsefulBitsFromUBFM (SDValue Op, APInt &UsefulBits, unsigned Depth) |
| static void | getUsefulBitsFromOrWithShiftedReg (SDValue Op, APInt &UsefulBits, unsigned Depth) |
| static void | getUsefulBitsFromBFM (SDValue Op, SDValue Orig, APInt &UsefulBits, unsigned Depth) |
| static void | getUsefulBitsForUse (SDNode *UserNode, APInt &UsefulBits, SDValue Orig, unsigned Depth) |
| static SDValue | getLeftShift (SelectionDAG *CurDAG, SDValue Op, int ShlAmount) |
| Create a machine node performing a notional SHL of Op by ShlAmount. | |
| static bool | isBitfieldPositioningOpFromAnd (SelectionDAG *CurDAG, SDValue Op, bool BiggerPattern, const uint64_t NonZeroBits, SDValue &Src, int &DstLSB, int &Width) |
| static bool | isBitfieldPositioningOpFromShl (SelectionDAG *CurDAG, SDValue Op, bool BiggerPattern, const uint64_t NonZeroBits, SDValue &Src, int &DstLSB, int &Width) |
| static bool | isBitfieldPositioningOp (SelectionDAG *CurDAG, SDValue Op, bool BiggerPattern, SDValue &Src, int &DstLSB, int &Width) |
| Does this tree qualify as an attempt to move a bitfield into position, essentially "(and (shl VAL, N), Mask)" or (shl VAL, N). | |
| static bool | isSeveralBitsPositioningOpFromShl (const uint64_t ShlImm, SDValue Op, SDValue &Src, int &DstLSB, int &Width) |
| static bool | isShiftedMask (uint64_t Mask, EVT VT) |
| static bool | tryBitfieldInsertOpFromOrAndImm (SDNode *N, SelectionDAG *CurDAG) |
| static bool | isWorthFoldingIntoOrrWithShift (SDValue Dst, SelectionDAG *CurDAG, SDValue &ShiftedOperand, uint64_t &EncodedShiftImm) |
| static bool | tryOrrWithShift (SDNode *N, SDValue OrOpd0, SDValue OrOpd1, SDValue Src, SDValue Dst, SelectionDAG *CurDAG, const bool BiggerPattern) |
| static bool | tryBitfieldInsertOpFromOr (SDNode *N, const APInt &UsefulBits, SelectionDAG *CurDAG) |
| static bool | checkCVTFixedPointOperandWithFBits (SelectionDAG *CurDAG, SDValue N, SDValue &FixedPos, unsigned RegWidth, bool isReciprocal) |
| static int | getIntOperandFromRegisterString (StringRef RegString) |
| static EVT | getPackedVectorTypeFromPredicateType (LLVMContext &Ctx, EVT PredVT, unsigned NumVec) |
When PredVT is a scalable vector predicate in the form MVT::nx<M>xi1, it builds the correspondent scalable vector of integers MVT::nx<M>xi<bits> s.t. | |
| static EVT | getMemVTFromNode (LLVMContext &Ctx, SDNode *Root) |
Return the EVT of the data associated to a memory operation in Root. | |
| #define DEBUG_TYPE "aarch64-isel" |
Definition at line 31 of file AArch64ISelDAGToDAG.cpp.
| #define PASS_NAME "AArch64 Instruction Selection" |
Definition at line 32 of file AArch64ISelDAGToDAG.cpp.
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| Enumerator | |
|---|---|
| Int1 | |
| Int | |
| FP | |
| AnyType | |
Definition at line 1635 of file AArch64ISelDAGToDAG.cpp.
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Definition at line 3660 of file AArch64ISelDAGToDAG.cpp.
References llvm::AArch64ISD::ADDlow, llvm::APFloat::convertToInteger(), llvm::ConstantPoolSDNode::getConstVal(), llvm::APFloat::getExactInverse(), llvm::SelectionDAG::getTargetConstant(), and N.
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getExtendTypeForNode - Translate an extend node to the corresponding ExtendType value.
Definition at line 771 of file AArch64ISelDAGToDAG.cpp.
References llvm::ISD::AND, llvm::ISD::ANY_EXTEND, assert(), llvm::ConstantSDNode::getZExtValue(), llvm::AArch64_AM::InvalidShiftExtend, N, llvm::ISD::SIGN_EXTEND, llvm::ISD::SIGN_EXTEND_INREG, llvm::AArch64_AM::SXTB, llvm::AArch64_AM::SXTH, llvm::AArch64_AM::SXTW, llvm::AArch64_AM::UXTB, llvm::AArch64_AM::UXTH, llvm::AArch64_AM::UXTW, and llvm::ISD::ZERO_EXTEND.
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Definition at line 3726 of file AArch64ISelDAGToDAG.cpp.
References assert(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::SmallVectorBase< Size_T >::size(), and llvm::StringRef::split().
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Create a machine node performing a notional SHL of Op by ShlAmount.
If ShlAmount is negative, do a (logical) right-shift instead. If ShlAmount is 0, return Op unchanged.
Definition at line 2811 of file AArch64ISelDAGToDAG.cpp.
References assert(), llvm::BitWidth, llvm::SelectionDAG::getMachineNode(), llvm::EVT::getSizeInBits(), and llvm::SelectionDAG::getTargetConstant().
Referenced by isBitfieldPositioningOpFromAnd(), and isBitfieldPositioningOpFromShl().
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Return the EVT of the data associated to a memory operation in Root.
If such EVT cannot be retrived, it returns an invalid EVT.
Definition at line 6638 of file AArch64ISelDAGToDAG.cpp.
References llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), getPackedVectorTypeFromPredicateType(), llvm::SDNode::getValueType(), llvm::ISD::INTRINSIC_VOID, llvm::ISD::INTRINSIC_W_CHAIN, llvm::AArch64ISD::LD1_MERGE_ZERO, llvm::AArch64ISD::LD1S_MERGE_ZERO, llvm::AArch64ISD::LDNF1_MERGE_ZERO, llvm::AArch64ISD::LDNF1S_MERGE_ZERO, llvm::AArch64ISD::ST1_PRED, llvm::AArch64ISD::SVE_LD2_MERGE_ZERO, llvm::AArch64ISD::SVE_LD3_MERGE_ZERO, and llvm::AArch64ISD::SVE_LD4_MERGE_ZERO.
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When PredVT is a scalable vector predicate in the form MVT::nx<M>xi1, it builds the correspondent scalable vector of integers MVT::nx<M>xi<bits> s.t.
M x bits = 128. When targeting structured vectors (NumVec >1), the output data type is MVT::nx<M*NumVec>xi<bits> s.t. M x bits = 128. If the input PredVT is not in the form MVT::nx<M>xi1, it returns an invalid EVT.
Definition at line 6618 of file AArch64ISelDAGToDAG.cpp.
References assert(), llvm::EVT::getIntegerVT(), llvm::EVT::getVectorElementCount(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorVT(), llvm::EVT::isScalableVector(), and llvm::AArch64::SVEBitsPerBlock.
Referenced by getMemVTFromNode().
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getShiftTypeForNode - Translate a shift node to the corresponding ShiftType value.
Definition at line 626 of file AArch64ISelDAGToDAG.cpp.
References llvm::AArch64_AM::ASR, llvm::AArch64_AM::InvalidShiftExtend, llvm::AArch64_AM::LSL, llvm::AArch64_AM::LSR, N, llvm::AArch64_AM::ROR, llvm::ISD::ROTR, llvm::ISD::SHL, llvm::ISD::SRA, and llvm::ISD::SRL.
Definition at line 2784 of file AArch64ISelDAGToDAG.cpp.
References llvm::Depth, llvm::APInt::flipAllBits(), llvm::APInt::getBitWidth(), getUsefulBitsForUse(), and llvm::SelectionDAG::MaxRecursionDepth.
Referenced by getUsefulBitsFromAndWithImmediate(), getUsefulBitsFromBFM(), getUsefulBitsFromBitfieldMoveOpd(), and getUsefulBitsFromOrWithShiftedReg().
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Definition at line 2736 of file AArch64ISelDAGToDAG.cpp.
References llvm::Depth, llvm::APInt::getBitWidth(), llvm::SDNode::getMachineOpcode(), llvm::SDNode::getOperand(), getUsefulBitsFromAndWithImmediate(), getUsefulBitsFromBFM(), getUsefulBitsFromOrWithShiftedReg(), getUsefulBitsFromUBFM(), and llvm::SDNode::isMachineOpcode().
Referenced by getUsefulBits().
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Definition at line 2607 of file AArch64ISelDAGToDAG.cpp.
References llvm::AArch64_AM::decodeLogicalImmediate(), llvm::Depth, llvm::APInt::getBitWidth(), and getUsefulBits().
Referenced by getUsefulBitsForUse().
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Definition at line 2681 of file AArch64ISelDAGToDAG.cpp.
References llvm::Depth, llvm::APInt::flipAllBits(), llvm::APInt::getBitWidth(), and getUsefulBits().
Referenced by getUsefulBitsForUse().
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Definition at line 2616 of file AArch64ISelDAGToDAG.cpp.
References llvm::Depth, llvm::APInt::getBitWidth(), getUsefulBits(), and llvm::APInt::lshrInPlace().
Referenced by getUsefulBitsFromUBFM().
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Definition at line 2653 of file AArch64ISelDAGToDAG.cpp.
References llvm::Depth, llvm::AArch64_AM::getShiftType(), llvm::AArch64_AM::getShiftValue(), getUsefulBits(), llvm::AArch64_AM::LSL, and llvm::AArch64_AM::LSR.
Referenced by getUsefulBitsForUse().
Definition at line 2643 of file AArch64ISelDAGToDAG.cpp.
References llvm::Depth, and getUsefulBitsFromBitfieldMoveOpd().
Referenced by getUsefulBitsForUse().
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Does DstMask form a complementary pair with the mask provided by BitsToBeInserted, suitable for use in a BFI instruction.
Roughly speaking, this asks whether DstMask zeroes precisely those bits that will be set by the other half.
Definition at line 2577 of file AArch64ISelDAGToDAG.cpp.
References assert(), llvm::BitWidth, llvm::EVT::getSizeInBits(), and llvm::APInt::zextOrTrunc().
Referenced by tryBitfieldInsertOpFromOr().
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Definition at line 2504 of file AArch64ISelDAGToDAG.cpp.
References llvm::ISD::AND, isBitfieldExtractOpFromAnd(), isBitfieldExtractOpFromSExtInReg(), isBitfieldExtractOpFromShr(), N, llvm::ISD::SIGN_EXTEND_INREG, llvm::ISD::SRA, and llvm::ISD::SRL.
Referenced by tryBitfieldInsertOpFromOr().
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Definition at line 2246 of file AArch64ISelDAGToDAG.cpp.
References llvm::ISD::AND, llvm::ISD::ANY_EXTEND, assert(), llvm::dbgs(), llvm::SDValue::getNode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::EVT::getSizeInBits(), llvm::SDNode::getValueType(), isOpcWithIntImmediate(), LLVM_DEBUG, N, llvm::ISD::SRL, llvm::ISD::TRUNCATE, and Widen().
Referenced by isBitfieldExtractOp().
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Definition at line 2340 of file AArch64ISelDAGToDAG.cpp.
References assert(), llvm::BitWidth, llvm::EVT::getSizeInBits(), isOpcWithIntImmediate(), N, llvm::ISD::SIGN_EXTEND_INREG, llvm::ISD::SRA, llvm::ISD::SRL, and llvm::ISD::TRUNCATE.
Referenced by isBitfieldExtractOp().
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Definition at line 2413 of file AArch64ISelDAGToDAG.cpp.
References assert(), llvm::dbgs(), llvm::EVT::getSizeInBits(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), isIntImmediate(), isOpcWithIntImmediate(), isSeveralBitsExtractOpFromShr(), LLVM_DEBUG, N, llvm::ISD::SHL, llvm::ISD::SRA, llvm::ISD::SRL, and llvm::ISD::TRUNCATE.
Referenced by isBitfieldExtractOp().
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Does this tree qualify as an attempt to move a bitfield into position, essentially "(and (shl VAL, N), Mask)" or (shl VAL, N).
Definition at line 2855 of file AArch64ISelDAGToDAG.cpp.
References llvm::ISD::AND, assert(), llvm::BitWidth, llvm::SelectionDAG::computeKnownBits(), llvm::EVT::getSizeInBits(), isBitfieldPositioningOpFromAnd(), isBitfieldPositioningOpFromShl(), llvm::isShiftedMask_64(), and llvm::ISD::SHL.
Referenced by tryBitfieldInsertOpFromOr().
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Definition at line 2885 of file AArch64ISelDAGToDAG.cpp.
References llvm::ISD::AND, llvm::ISD::ANY_EXTEND, assert(), llvm::countr_one(), llvm::countr_zero(), llvm::dbgs(), getLeftShift(), llvm::SDValue::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getSizeInBits(), llvm::SDValue::getValueType(), llvm::SDValue::hasOneUse(), isOpcWithIntImmediate(), llvm::isShiftedMask_64(), LLVM_DEBUG, llvm::ISD::SHL, and Widen().
Referenced by isBitfieldPositioningOp().
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Definition at line 3007 of file AArch64ISelDAGToDAG.cpp.
References assert(), llvm::countr_one(), llvm::countr_zero(), getLeftShift(), isOpcWithIntImmediate(), isSeveralBitsPositioningOpFromShl(), llvm::isShiftedMask_64(), and llvm::ISD::SHL.
Referenced by isBitfieldPositioningOp().
isIntImmediate - This method tests to see if the node is a constant operand.
If so Imm will receive the 32-bit value.
Definition at line 501 of file AArch64ISelDAGToDAG.cpp.
References llvm::CallingConv::C, and N.
Referenced by isBitfieldExtractOpFromShr(), isIntImmediate(), isIntImmediateEq(), isOpcWithIntImmediate(), and isSeveralBitsExtractOpFromShr().
Definition at line 511 of file AArch64ISelDAGToDAG.cpp.
References isIntImmediate(), and N.
Definition at line 527 of file AArch64ISelDAGToDAG.cpp.
References isIntImmediate(), and N.
Referenced by isSeveralBitsPositioningOpFromShl().
Definition at line 518 of file AArch64ISelDAGToDAG.cpp.
References isIntImmediate(), and N.
Referenced by isBitfieldExtractOpFromAnd(), isBitfieldExtractOpFromSExtInReg(), isBitfieldExtractOpFromShr(), isBitfieldPositioningOpFromAnd(), isBitfieldPositioningOpFromShl(), isSeveralBitsExtractOpFromShr(), isSeveralBitsPositioningOpFromShl(), isWorthFoldingIntoOrrWithShift(), performAddCombineForShiftedOperands(), tryBitfieldInsertOpFromOr(), tryBitfieldInsertOpFromOrAndImm(), and tryOrrWithShift().
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Definition at line 1271 of file AArch64ISelDAGToDAG.cpp.
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Definition at line 2373 of file AArch64ISelDAGToDAG.cpp.
References llvm::ISD::AND, isIntImmediate(), llvm::isMask_64(), isOpcWithIntImmediate(), llvm::Log2_64(), N, and llvm::ISD::SRL.
Referenced by isBitfieldExtractOpFromShr().
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Definition at line 2975 of file AArch64ISelDAGToDAG.cpp.
References llvm::ISD::AND, assert(), llvm::countr_one(), llvm::SDValue::getNode(), llvm::SDValue::getOperand(), isIntImmediateEq(), llvm::isMask_64(), isOpcWithIntImmediate(), and llvm::ISD::SHL.
Referenced by isBitfieldPositioningOpFromShl().
Definition at line 3039 of file AArch64ISelDAGToDAG.cpp.
References assert(), llvm::isShiftedMask_32(), and llvm::isShiftedMask_64().
Referenced by tryBitfieldInsertOpFromOr(), and tryBitfieldInsertOpFromOrAndImm().
If there's a use of this ADDlow that's not itself a load/store then we'll need to create a real ADD instruction from it anyway and there's no point in folding it into the mem op.
Theoretically, it shouldn't matter, but there's a single pseudo-instruction for an ADRP/ADD pair so over-aggressive folding leads to duplicated ADRP instructions.
Definition at line 984 of file AArch64ISelDAGToDAG.cpp.
References llvm::ISD::ATOMIC_LOAD, llvm::ISD::ATOMIC_STORE, llvm::isStrongerThanMonotonic(), llvm::ISD::LOAD, N, and llvm::ISD::STORE.
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Definition at line 3136 of file AArch64ISelDAGToDAG.cpp.
References llvm::ISD::AND, assert(), llvm::countr_one(), llvm::countr_zero(), DL, llvm::SelectionDAG::getMachineNode(), llvm::SDValue::getNode(), llvm::SDValue::getOperand(), llvm::AArch64_AM::getShifterImm(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getTargetConstant(), llvm::SDValue::hasOneUse(), isOpcWithIntImmediate(), llvm::isShiftedMask_64(), llvm::AArch64_AM::LSL, llvm::AArch64_AM::LSR, llvm::ISD::SHL, and llvm::ISD::SRL.
Referenced by tryOrrWithShift().
Determine whether it is worth it to fold SHL into the addressing mode.
Definition at line 643 of file AArch64ISelDAGToDAG.cpp.
References assert(), llvm::ISD::SHL, and llvm::SDNode::uses().
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Instructions that accept extend modifiers like UXTW expect the register being extended to be a GPR32, but the incoming DAG might be acting on a GPR64 (either via SEXT_INREG or AND).
Extract the appropriate low bits if this is the case.
Definition at line 876 of file AArch64ISelDAGToDAG.cpp.
References llvm::SelectionDAG::getTargetExtractSubreg(), and N.
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NarrowVector - Given a value in the V128 register class, produce the equivalent value in the V64 register class.
Definition at line 2079 of file AArch64ISelDAGToDAG.cpp.
References llvm::EVT::getSimpleVT(), llvm::SelectionDAG::getTargetExtractSubreg(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), and llvm::MVT::getVectorVT().
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This function selects an opcode from a list of opcodes, which is expected to be the opcode for { 8-bit, 16-bit, 32-bit, 64-bit } element types, in this order.
Definition at line 1646 of file AArch64ISelDAGToDAG.cpp.
References AnyType, FP, llvm::EVT::getVectorElementType(), llvm::EVT::getVectorMinNumElements(), Int, Int1, llvm::EVT::isScalableVector(), llvm::Offset, and llvm::ArrayRef< T >::size().
Definition at line 1879 of file AArch64ISelDAGToDAG.cpp.
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Definition at line 3311 of file AArch64ISelDAGToDAG.cpp.
References llvm::ISD::AND, assert(), llvm::BitWidth, llvm::SelectionDAG::computeKnownBits(), llvm::APInt::countl_zero(), llvm::APInt::countr_zero(), llvm::countr_zero(), DL, llvm::APInt::getBitsSet(), llvm::KnownBits::getBitWidth(), llvm::SelectionDAG::getMachineNode(), llvm::SDValue::getNode(), llvm::SDNode::getOperand(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getTargetConstant(), llvm::SDValue::getValueType(), llvm::SDValue::hasOneUse(), I, isBitfieldDstMask(), isBitfieldExtractOp(), isBitfieldPositioningOp(), isOpcWithIntImmediate(), isShiftedMask(), N, llvm::ISD::OR, llvm::APInt::popcount(), llvm::SelectionDAG::SelectNodeTo(), llvm::ISD::SRL, std::swap(), tryOrrWithShift(), and llvm::KnownBits::Zero.
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Definition at line 3048 of file AArch64ISelDAGToDAG.cpp.
References llvm::And, llvm::ISD::AND, assert(), llvm::BitWidth, llvm::SelectionDAG::computeKnownBits(), llvm::countr_one(), DL, llvm::SelectionDAG::getMachineNode(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getTargetConstant(), llvm::APInt::getZExtValue(), llvm::AArch64_AM::isLogicalImmediate(), isOpcWithIntImmediate(), isShiftedMask(), N, llvm::ISD::OR, llvm::APInt::popcount(), llvm::SelectionDAG::SelectNodeTo(), and llvm::KnownBits::Zero.
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Definition at line 3211 of file AArch64ISelDAGToDAG.cpp.
References llvm::ISD::AND, assert(), DL, llvm::SDValue::getNode(), llvm::SDValue::getOperand(), llvm::AArch64_AM::getShifterImm(), llvm::SelectionDAG::getTargetConstant(), llvm::SDValue::hasOneUse(), llvm::isMask_64(), isOpcWithIntImmediate(), isWorthFoldingIntoOrrWithShift(), llvm::AArch64_AM::LSL, llvm::AArch64_AM::LSR, N, llvm::ISD::OR, llvm::SelectionDAG::SelectNodeTo(), llvm::ISD::SHL, and llvm::ISD::SRL.
Referenced by tryBitfieldInsertOpFromOr().
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Definition at line 1152 of file AArch64ISelDAGToDAG.cpp.
References llvm::SelectionDAG::getMachineNode(), llvm::SelectionDAG::getTargetInsertSubreg(), and N.
Referenced by getAVX512Node(), isBitfieldExtractOpFromAnd(), and isBitfieldPositioningOpFromAnd().
1.9.6