LLVM  10.0.0svn
LiveRangeEdit.cpp
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1 //===-- LiveRangeEdit.cpp - Basic tools for editing a register live range -===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // The LiveRangeEdit class represents changes done to a virtual register when it
10 // is spilled or split.
11 //===----------------------------------------------------------------------===//
12 
14 #include "llvm/ADT/Statistic.h"
20 #include "llvm/Support/Debug.h"
22 
23 using namespace llvm;
24 
25 #define DEBUG_TYPE "regalloc"
26 
27 STATISTIC(NumDCEDeleted, "Number of instructions deleted by DCE");
28 STATISTIC(NumDCEFoldedLoads, "Number of single use loads folded after DCE");
29 STATISTIC(NumFracRanges, "Number of live ranges fractured by DCE");
30 
31 void LiveRangeEdit::Delegate::anchor() { }
32 
33 LiveInterval &LiveRangeEdit::createEmptyIntervalFrom(unsigned OldReg,
34  bool createSubRanges) {
35  Register VReg = MRI.createVirtualRegister(MRI.getRegClass(OldReg));
36  if (VRM)
37  VRM->setIsSplitFromReg(VReg, VRM->getOriginal(OldReg));
38 
39  LiveInterval &LI = LIS.createEmptyInterval(VReg);
40  if (Parent && !Parent->isSpillable())
41  LI.markNotSpillable();
42  if (createSubRanges) {
43  // Create empty subranges if the OldReg's interval has them. Do not create
44  // the main range here---it will be constructed later after the subranges
45  // have been finalized.
46  LiveInterval &OldLI = LIS.getInterval(OldReg);
47  VNInfo::Allocator &Alloc = LIS.getVNInfoAllocator();
48  for (LiveInterval::SubRange &S : OldLI.subranges())
49  LI.createSubRange(Alloc, S.LaneMask);
50  }
51  return LI;
52 }
53 
54 unsigned LiveRangeEdit::createFrom(unsigned OldReg) {
55  Register VReg = MRI.createVirtualRegister(MRI.getRegClass(OldReg));
56  if (VRM) {
57  VRM->setIsSplitFromReg(VReg, VRM->getOriginal(OldReg));
58  }
59  // FIXME: Getting the interval here actually computes it.
60  // In theory, this may not be what we want, but in practice
61  // the createEmptyIntervalFrom API is used when this is not
62  // the case. Generally speaking we just want to annotate the
63  // LiveInterval when it gets created but we cannot do that at
64  // the moment.
65  if (Parent && !Parent->isSpillable())
66  LIS.getInterval(VReg).markNotSpillable();
67  return VReg;
68 }
69 
71  const MachineInstr *DefMI,
72  AliasAnalysis *aa) {
73  assert(DefMI && "Missing instruction");
74  ScannedRemattable = true;
75  if (!TII.isTriviallyReMaterializable(*DefMI, aa))
76  return false;
77  Remattable.insert(VNI);
78  return true;
79 }
80 
81 void LiveRangeEdit::scanRemattable(AliasAnalysis *aa) {
82  for (VNInfo *VNI : getParent().valnos) {
83  if (VNI->isUnused())
84  continue;
85  unsigned Original = VRM->getOriginal(getReg());
86  LiveInterval &OrigLI = LIS.getInterval(Original);
87  VNInfo *OrigVNI = OrigLI.getVNInfoAt(VNI->def);
88  if (!OrigVNI)
89  continue;
90  MachineInstr *DefMI = LIS.getInstructionFromIndex(OrigVNI->def);
91  if (!DefMI)
92  continue;
93  checkRematerializable(OrigVNI, DefMI, aa);
94  }
95  ScannedRemattable = true;
96 }
97 
99  if (!ScannedRemattable)
100  scanRemattable(aa);
101  return !Remattable.empty();
102 }
103 
104 /// allUsesAvailableAt - Return true if all registers used by OrigMI at
105 /// OrigIdx are also available with the same value at UseIdx.
106 bool LiveRangeEdit::allUsesAvailableAt(const MachineInstr *OrigMI,
107  SlotIndex OrigIdx,
108  SlotIndex UseIdx) const {
109  OrigIdx = OrigIdx.getRegSlot(true);
110  UseIdx = UseIdx.getRegSlot(true);
111  for (unsigned i = 0, e = OrigMI->getNumOperands(); i != e; ++i) {
112  const MachineOperand &MO = OrigMI->getOperand(i);
113  if (!MO.isReg() || !MO.getReg() || !MO.readsReg())
114  continue;
115 
116  // We can't remat physreg uses, unless it is a constant.
118  if (MRI.isConstantPhysReg(MO.getReg()))
119  continue;
120  return false;
121  }
122 
123  LiveInterval &li = LIS.getInterval(MO.getReg());
124  const VNInfo *OVNI = li.getVNInfoAt(OrigIdx);
125  if (!OVNI)
126  continue;
127 
128  // Don't allow rematerialization immediately after the original def.
129  // It would be incorrect if OrigMI redefines the register.
130  // See PR14098.
131  if (SlotIndex::isSameInstr(OrigIdx, UseIdx))
132  return false;
133 
134  if (OVNI != li.getVNInfoAt(UseIdx))
135  return false;
136  }
137  return true;
138 }
139 
141  SlotIndex UseIdx, bool cheapAsAMove) {
142  assert(ScannedRemattable && "Call anyRematerializable first");
143 
144  // Use scanRemattable info.
145  if (!Remattable.count(OrigVNI))
146  return false;
147 
148  // No defining instruction provided.
149  SlotIndex DefIdx;
150  assert(RM.OrigMI && "No defining instruction for remattable value");
151  DefIdx = LIS.getInstructionIndex(*RM.OrigMI);
152 
153  // If only cheap remats were requested, bail out early.
154  if (cheapAsAMove && !TII.isAsCheapAsAMove(*RM.OrigMI))
155  return false;
156 
157  // Verify that all used registers are available with the same values.
158  if (!allUsesAvailableAt(RM.OrigMI, DefIdx, UseIdx))
159  return false;
160 
161  return true;
162 }
163 
166  unsigned DestReg,
167  const Remat &RM,
168  const TargetRegisterInfo &tri,
169  bool Late) {
170  assert(RM.OrigMI && "Invalid remat");
171  TII.reMaterialize(MBB, MI, DestReg, 0, *RM.OrigMI, tri);
172  // DestReg of the cloned instruction cannot be Dead. Set isDead of DestReg
173  // to false anyway in case the isDead flag of RM.OrigMI's dest register
174  // is true.
175  (*--MI).getOperand(0).setIsDead(false);
176  Rematted.insert(RM.ParentVNI);
177  return LIS.getSlotIndexes()->insertMachineInstrInMaps(*MI, Late).getRegSlot();
178 }
179 
181  if (TheDelegate && TheDelegate->LRE_CanEraseVirtReg(Reg))
182  LIS.removeInterval(Reg);
183 }
184 
185 bool LiveRangeEdit::foldAsLoad(LiveInterval *LI,
187  MachineInstr *DefMI = nullptr, *UseMI = nullptr;
188 
189  // Check that there is a single def and a single use.
190  for (MachineOperand &MO : MRI.reg_nodbg_operands(LI->reg)) {
191  MachineInstr *MI = MO.getParent();
192  if (MO.isDef()) {
193  if (DefMI && DefMI != MI)
194  return false;
195  if (!MI->canFoldAsLoad())
196  return false;
197  DefMI = MI;
198  } else if (!MO.isUndef()) {
199  if (UseMI && UseMI != MI)
200  return false;
201  // FIXME: Targets don't know how to fold subreg uses.
202  if (MO.getSubReg())
203  return false;
204  UseMI = MI;
205  }
206  }
207  if (!DefMI || !UseMI)
208  return false;
209 
210  // Since we're moving the DefMI load, make sure we're not extending any live
211  // ranges.
212  if (!allUsesAvailableAt(DefMI, LIS.getInstructionIndex(*DefMI),
213  LIS.getInstructionIndex(*UseMI)))
214  return false;
215 
216  // We also need to make sure it is safe to move the load.
217  // Assume there are stores between DefMI and UseMI.
218  bool SawStore = true;
219  if (!DefMI->isSafeToMove(nullptr, SawStore))
220  return false;
221 
222  LLVM_DEBUG(dbgs() << "Try to fold single def: " << *DefMI
223  << " into single use: " << *UseMI);
224 
226  if (UseMI->readsWritesVirtualRegister(LI->reg, &Ops).second)
227  return false;
228 
229  MachineInstr *FoldMI = TII.foldMemoryOperand(*UseMI, Ops, *DefMI, &LIS);
230  if (!FoldMI)
231  return false;
232  LLVM_DEBUG(dbgs() << " folded: " << *FoldMI);
233  LIS.ReplaceMachineInstrInMaps(*UseMI, *FoldMI);
234  if (UseMI->isCall())
235  UseMI->getMF()->moveCallSiteInfo(UseMI, FoldMI);
237  DefMI->addRegisterDead(LI->reg, nullptr);
238  Dead.push_back(DefMI);
239  ++NumDCEFoldedLoads;
240  return true;
241 }
242 
243 bool LiveRangeEdit::useIsKill(const LiveInterval &LI,
244  const MachineOperand &MO) const {
245  const MachineInstr &MI = *MO.getParent();
246  SlotIndex Idx = LIS.getInstructionIndex(MI).getRegSlot();
247  if (LI.Query(Idx).isKill())
248  return true;
249  const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
250  unsigned SubReg = MO.getSubReg();
251  LaneBitmask LaneMask = TRI.getSubRegIndexLaneMask(SubReg);
252  for (const LiveInterval::SubRange &S : LI.subranges()) {
253  if ((S.LaneMask & LaneMask).any() && S.Query(Idx).isKill())
254  return true;
255  }
256  return false;
257 }
258 
259 /// Find all live intervals that need to shrink, then remove the instruction.
260 void LiveRangeEdit::eliminateDeadDef(MachineInstr *MI, ToShrinkSet &ToShrink,
261  AliasAnalysis *AA) {
262  assert(MI->allDefsAreDead() && "Def isn't really dead");
263  SlotIndex Idx = LIS.getInstructionIndex(*MI).getRegSlot();
264 
265  // Never delete a bundled instruction.
266  if (MI->isBundled()) {
267  return;
268  }
269  // Never delete inline asm.
270  if (MI->isInlineAsm()) {
271  LLVM_DEBUG(dbgs() << "Won't delete: " << Idx << '\t' << *MI);
272  return;
273  }
274 
275  // Use the same criteria as DeadMachineInstructionElim.
276  bool SawStore = false;
277  if (!MI->isSafeToMove(nullptr, SawStore)) {
278  LLVM_DEBUG(dbgs() << "Can't delete: " << Idx << '\t' << *MI);
279  return;
280  }
281 
282  LLVM_DEBUG(dbgs() << "Deleting dead def " << Idx << '\t' << *MI);
283 
284  // Collect virtual registers to be erased after MI is gone.
285  SmallVector<unsigned, 8> RegsToErase;
286  bool ReadsPhysRegs = false;
287  bool isOrigDef = false;
288  unsigned Dest;
289  // Only optimize rematerialize case when the instruction has one def, since
290  // otherwise we could leave some dead defs in the code. This case is
291  // extremely rare.
292  if (VRM && MI->getOperand(0).isReg() && MI->getOperand(0).isDef() &&
293  MI->getDesc().getNumDefs() == 1) {
294  Dest = MI->getOperand(0).getReg();
295  unsigned Original = VRM->getOriginal(Dest);
296  LiveInterval &OrigLI = LIS.getInterval(Original);
297  VNInfo *OrigVNI = OrigLI.getVNInfoAt(Idx);
298  // The original live-range may have been shrunk to
299  // an empty live-range. It happens when it is dead, but
300  // we still keep it around to be able to rematerialize
301  // other values that depend on it.
302  if (OrigVNI)
303  isOrigDef = SlotIndex::isSameInstr(OrigVNI->def, Idx);
304  }
305 
306  // Check for live intervals that may shrink
308  MOE = MI->operands_end(); MOI != MOE; ++MOI) {
309  if (!MOI->isReg())
310  continue;
311  Register Reg = MOI->getReg();
312  if (!Register::isVirtualRegister(Reg)) {
313  // Check if MI reads any unreserved physregs.
314  if (Reg && MOI->readsReg() && !MRI.isReserved(Reg))
315  ReadsPhysRegs = true;
316  else if (MOI->isDef())
317  LIS.removePhysRegDefAt(Reg, Idx);
318  continue;
319  }
320  LiveInterval &LI = LIS.getInterval(Reg);
321 
322  // Shrink read registers, unless it is likely to be expensive and
323  // unlikely to change anything. We typically don't want to shrink the
324  // PIC base register that has lots of uses everywhere.
325  // Always shrink COPY uses that probably come from live range splitting.
326  if ((MI->readsVirtualRegister(Reg) && (MI->isCopy() || MOI->isDef())) ||
327  (MOI->readsReg() && (MRI.hasOneNonDBGUse(Reg) || useIsKill(LI, *MOI))))
328  ToShrink.insert(&LI);
329 
330  // Remove defined value.
331  if (MOI->isDef()) {
332  if (TheDelegate && LI.getVNInfoAt(Idx) != nullptr)
333  TheDelegate->LRE_WillShrinkVirtReg(LI.reg);
334  LIS.removeVRegDefAt(LI, Idx);
335  if (LI.empty())
336  RegsToErase.push_back(Reg);
337  }
338  }
339 
340  // Currently, we don't support DCE of physreg live ranges. If MI reads
341  // any unreserved physregs, don't erase the instruction, but turn it into
342  // a KILL instead. This way, the physreg live ranges don't end up
343  // dangling.
344  // FIXME: It would be better to have something like shrinkToUses() for
345  // physregs. That could potentially enable more DCE and it would free up
346  // the physreg. It would not happen often, though.
347  if (ReadsPhysRegs) {
348  MI->setDesc(TII.get(TargetOpcode::KILL));
349  // Remove all operands that aren't physregs.
350  for (unsigned i = MI->getNumOperands(); i; --i) {
351  const MachineOperand &MO = MI->getOperand(i-1);
352  if (MO.isReg() && Register::isPhysicalRegister(MO.getReg()))
353  continue;
354  MI->RemoveOperand(i-1);
355  }
356  LLVM_DEBUG(dbgs() << "Converted physregs to:\t" << *MI);
357  } else {
358  // If the dest of MI is an original reg and MI is reMaterializable,
359  // don't delete the inst. Replace the dest with a new reg, and keep
360  // the inst for remat of other siblings. The inst is saved in
361  // LiveRangeEdit::DeadRemats and will be deleted after all the
362  // allocations of the func are done.
363  if (isOrigDef && DeadRemats && TII.isTriviallyReMaterializable(*MI, AA)) {
364  LiveInterval &NewLI = createEmptyIntervalFrom(Dest, false);
365  VNInfo *VNI = NewLI.getNextValue(Idx, LIS.getVNInfoAllocator());
366  NewLI.addSegment(LiveInterval::Segment(Idx, Idx.getDeadSlot(), VNI));
367  pop_back();
368  DeadRemats->insert(MI);
369  const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
370  MI->substituteRegister(Dest, NewLI.reg, 0, TRI);
371  MI->getOperand(0).setIsDead(true);
372  } else {
373  if (TheDelegate)
374  TheDelegate->LRE_WillEraseInstruction(MI);
375  LIS.RemoveMachineInstrFromMaps(*MI);
376  MI->eraseFromParent();
377  ++NumDCEDeleted;
378  }
379  }
380 
381  // Erase any virtregs that are now empty and unused. There may be <undef>
382  // uses around. Keep the empty live range in that case.
383  for (unsigned i = 0, e = RegsToErase.size(); i != e; ++i) {
384  unsigned Reg = RegsToErase[i];
385  if (LIS.hasInterval(Reg) && MRI.reg_nodbg_empty(Reg)) {
386  ToShrink.remove(&LIS.getInterval(Reg));
387  eraseVirtReg(Reg);
388  }
389  }
390 }
391 
393  ArrayRef<unsigned> RegsBeingSpilled,
394  AliasAnalysis *AA) {
395  ToShrinkSet ToShrink;
396 
397  for (;;) {
398  // Erase all dead defs.
399  while (!Dead.empty())
400  eliminateDeadDef(Dead.pop_back_val(), ToShrink, AA);
401 
402  if (ToShrink.empty())
403  break;
404 
405  // Shrink just one live interval. Then delete new dead defs.
406  LiveInterval *LI = ToShrink.back();
407  ToShrink.pop_back();
408  if (foldAsLoad(LI, Dead))
409  continue;
410  unsigned VReg = LI->reg;
411  if (TheDelegate)
412  TheDelegate->LRE_WillShrinkVirtReg(VReg);
413  if (!LIS.shrinkToUses(LI, &Dead))
414  continue;
415 
416  // Don't create new intervals for a register being spilled.
417  // The new intervals would have to be spilled anyway so its not worth it.
418  // Also they currently aren't spilled so creating them and not spilling
419  // them results in incorrect code.
420  bool BeingSpilled = false;
421  for (unsigned i = 0, e = RegsBeingSpilled.size(); i != e; ++i) {
422  if (VReg == RegsBeingSpilled[i]) {
423  BeingSpilled = true;
424  break;
425  }
426  }
427 
428  if (BeingSpilled) continue;
429 
430  // LI may have been separated, create new intervals.
431  LI->RenumberValues();
433  LIS.splitSeparateComponents(*LI, SplitLIs);
434  if (!SplitLIs.empty())
435  ++NumFracRanges;
436 
437  unsigned Original = VRM ? VRM->getOriginal(VReg) : 0;
438  for (const LiveInterval *SplitLI : SplitLIs) {
439  // If LI is an original interval that hasn't been split yet, make the new
440  // intervals their own originals instead of referring to LI. The original
441  // interval must contain all the split products, and LI doesn't.
442  if (Original != VReg && Original != 0)
443  VRM->setIsSplitFromReg(SplitLI->reg, Original);
444  if (TheDelegate)
445  TheDelegate->LRE_DidCloneVirtReg(SplitLI->reg, VReg);
446  }
447  }
448 }
449 
450 // Keep track of new virtual registers created via
451 // MachineRegisterInfo::createVirtualRegister.
452 void
453 LiveRangeEdit::MRI_NoteNewVirtualRegister(unsigned VReg)
454 {
455  if (VRM)
456  VRM->grow();
457 
458  NewRegs.push_back(VReg);
459 }
460 
461 void
463  const MachineLoopInfo &Loops,
464  const MachineBlockFrequencyInfo &MBFI) {
465  VirtRegAuxInfo VRAI(MF, LIS, VRM, Loops, MBFI);
466  for (unsigned I = 0, Size = size(); I < Size; ++I) {
467  LiveInterval &LI = LIS.getInterval(get(I));
468  if (MRI.recomputeRegClass(LI.reg))
469  LLVM_DEBUG({
471  dbgs() << "Inflated " << printReg(LI.reg) << " to "
472  << TRI->getRegClassName(MRI.getRegClass(LI.reg)) << '\n';
473  });
475  }
476 }
void RenumberValues()
RenumberValues - Renumber all values in order of appearance and remove unused values.
bool empty() const
Definition: LiveInterval.h:373
mop_iterator operands_end()
Definition: MachineInstr.h:471
Calculate auxiliary information for a virtual register such as its spill weight and allocation hint...
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
const unsigned reg
Definition: LiveInterval.h:708
bool isCall(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:656
SlotIndex def
The index of the defining instruction.
Definition: LiveInterval.h:60
const MachineFunction * getMF() const
Return the function that contains the basic block that this instruction belongs to.
This class represents lattice values for constants.
Definition: AllocatorList.h:23
bool anyRematerializable(AliasAnalysis *)
anyRematerializable - Return true if any parent values may be rematerializable.
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
void push_back(const T &Elt)
Definition: SmallVector.h:211
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:63
LiveInterval - This class represents the liveness of a register, or stack slot.
Definition: LiveInterval.h:679
void eliminateDeadDefs(SmallVectorImpl< MachineInstr *> &Dead, ArrayRef< unsigned > RegsBeingSpilled=None, AliasAnalysis *AA=nullptr)
eliminateDeadDefs - Try to delete machine instructions that are now dead (allDefsAreDead returns true...
unsigned Reg
bool addRegisterDead(Register Reg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)
We have determined MI defined a register without a use.
unsigned getSubReg() const
bool isInlineAsm() const
bool readsVirtualRegister(Register Reg) const
Return true if the MachineInstr reads the specified virtual register.
MachineBlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate machine basic b...
A live range for subregisters.
Definition: LiveInterval.h:686
This represents a simple continuous liveness interval for a value.
Definition: LiveInterval.h:161
STATISTIC(NumFunctions, "Total number of functions")
unsigned const TargetRegisterInfo * TRI
void setIsDead(bool Val=true)
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
VNInfo - Value Number Information.
Definition: LiveInterval.h:52
const T & back() const
Return the last element of the SetVector.
Definition: SetVector.h:128
bool checkRematerializable(VNInfo *VNI, const MachineInstr *DefMI, AliasAnalysis *)
checkRematerializable - Manually add VNI to the list of rematerializable values if DefMI may be remat...
const char * getRegClassName(const TargetRegisterClass *Class) const
Returns the name of the register class.
Hexagon Hardware Loops
const HexagonInstrInfo * TII
void substituteRegister(Register FromReg, Register ToReg, unsigned SubIdx, const TargetRegisterInfo &RegInfo)
Replace all occurrences of FromReg with ToReg:SubIdx, properly composing subreg indices where necessa...
std::pair< bool, bool > readsWritesVirtualRegister(Register Reg, SmallVectorImpl< unsigned > *Ops=nullptr) const
Return a pair of bools (reads, writes) indicating if this instruction reads or writes Reg...
unsigned getNumOperands() const
Retuns the total number of operands.
Definition: MachineInstr.h:413
iterator_range< subrange_iterator > subranges()
Definition: LiveInterval.h:764
void eraseFromParent()
Unlink &#39;this&#39; from the containing basic block and delete it.
unsigned SubReg
bool remove(const value_type &X)
Remove an item from the set vector.
Definition: SetVector.h:157
void pop_back()
Remove the last element of the SetVector.
Definition: SetVector.h:221
bool readsReg() const
readsReg - Returns true if this operand reads the previous value of its register. ...
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:407
bool insert(const value_type &X)
Insert a new element into the SetVector.
Definition: SetVector.h:141
SlotIndex getRegSlot(bool EC=false) const
Returns the register use/def slot in the current instruction for a normal or early-clobber def...
Definition: SlotIndexes.h:254
iterator addSegment(Segment S)
Add the specified Segment to this range, merging segments as appropriate.
bool canRematerializeAt(Remat &RM, VNInfo *OrigVNI, SlotIndex UseIdx, bool cheapAsAMove)
canRematerializeAt - Determine if ParentVNI can be rematerialized at UseIdx.
void pop_back()
pop_back - It allows LiveRangeEdit users to drop new registers.
unsigned getReg() const
bool isKill() const
Return true if the live-in value is killed by this instruction.
Definition: LiveInterval.h:111
bool allDefsAreDead() const
Return true if all the defs of this instruction are dead.
LiveQueryResult Query(SlotIndex Idx) const
Query Liveness at Idx.
Definition: LiveInterval.h:532
VNInfo * getVNInfoAt(SlotIndex Idx) const
getVNInfoAt - Return the VNInfo that is live at Idx, or NULL.
Definition: LiveInterval.h:412
unsigned createFrom(unsigned OldReg)
createFrom - Create a new virtual register based on OldReg.
SubRange * createSubRange(BumpPtrAllocator &Allocator, LaneBitmask LaneMask)
Creates a new empty subregister live range.
Definition: LiveInterval.h:774
unsigned const MachineRegisterInfo * MRI
void grow(size_t MinSize=0)
Grow the allocated memory (without initializing new elements), doubling the size of the allocated mem...
Definition: SmallVector.h:233
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Allocate memory in an ever growing pool, as if by bump-pointer.
Definition: Allocator.h:141
bool isBundled() const
Return true if this instruction part of a bundle.
Definition: MachineInstr.h:357
MachineInstrBuilder & UseMI
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:148
unsigned size() const
constexpr double e
Definition: MathExtras.h:57
bool isCopy() const
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
size_t size() const
Definition: SmallVector.h:52
LiveInterval & getParent() const
void setDesc(const MCInstrDesc &tid)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one...
static bool isSameInstr(SlotIndex A, SlotIndex B)
isSameInstr - Return true if A and B refer to the same instruction.
Definition: SlotIndexes.h:197
MachineOperand class - Representation of each machine instruction operand.
MachineInstrBuilder MachineInstrBuilder & DefMI
void calculateSpillWeightAndHint(LiveInterval &li)
(re)compute li&#39;s spill weight and allocation hint.
LLVM_NODISCARD T pop_back_val()
Definition: SmallVector.h:374
LaneBitmask getSubRegIndexLaneMask(unsigned SubIdx) const
Return a bitmask representing the parts of a register that are covered by SubIdx. ...
void markNotSpillable()
markNotSpillable - Mark interval as not spillable
Definition: LiveInterval.h:813
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
Definition: MCInstrDesc.h:241
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
Representation of each machine instruction.
Definition: MachineInstr.h:63
SlotIndex rematerializeAt(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, const Remat &RM, const TargetRegisterInfo &, bool Late=false)
rematerializeAt - Rematerialize RM.ParentVNI into DestReg by inserting an instruction into MBB before...
LLVM_NODISCARD bool empty() const
Definition: SmallVector.h:55
bool canFoldAsLoad(QueryType Type=IgnoreBundle) const
Return true for instructions that can be folded as memory operands in other instructions.
Definition: MachineInstr.h:776
#define I(x, y, z)
Definition: MD5.cpp:58
bool empty() const
Determine if the SetVector is empty or not.
Definition: SetVector.h:72
uint32_t Size
Definition: Profile.cpp:46
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Remat - Information needed to rematerialize at a specific location.
VNInfo * getNextValue(SlotIndex def, VNInfo::Allocator &VNInfoAllocator)
getNextValue - Create a new value number and return it.
Definition: LiveInterval.h:322
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool isSafeToMove(AAResults *AA, bool &SawStore) const
Return true if it is safe to move this instruction.
mop_iterator operands_begin()
Definition: MachineInstr.h:470
A vector that has set insertion semantics.
Definition: SetVector.h:40
void moveCallSiteInfo(const MachineInstr *Old, const MachineInstr *New)
Following functions update call site info.
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:69
void calculateRegClassAndHint(MachineFunction &, const MachineLoopInfo &, const MachineBlockFrequencyInfo &)
calculateRegClassAndHint - Recompute register class and hint for each new register.
IRTranslator LLVM IR MI
void RemoveOperand(unsigned OpNo)
Erase an operand from an instruction, leaving it with one fewer operand than it started with...
void eraseVirtReg(unsigned Reg)
eraseVirtReg - Notify the delegate that Reg is no longer in use, and try to erase it from LIS...
Register getReg() const
getReg - Returns the register number.
#define LLVM_DEBUG(X)
Definition: Debug.h:122
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:415
SlotIndex - An opaque wrapper around machine indexes.
Definition: SlotIndexes.h:83
Wrapper class representing virtual and physical registers.
Definition: Register.h:19