LLVM  10.0.0svn
MachineIRBuilder.cpp
Go to the documentation of this file.
1 //===-- llvm/CodeGen/GlobalISel/MachineIRBuilder.cpp - MIBuilder--*- C++ -*-==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 /// This file implements the MachineIRBuidler class.
10 //===----------------------------------------------------------------------===//
13 
22 #include "llvm/IR/DebugInfo.h"
23 
24 using namespace llvm;
25 
27  State.MF = &MF;
28  State.MBB = nullptr;
29  State.MRI = &MF.getRegInfo();
30  State.TII = MF.getSubtarget().getInstrInfo();
31  State.DL = DebugLoc();
33  State.Observer = nullptr;
34 }
35 
37  State.MBB = &MBB;
38  State.II = MBB.end();
39  assert(&getMF() == MBB.getParent() &&
40  "Basic block is in a different function");
41 }
42 
44  assert(MI.getParent() && "Instruction is not part of a basic block");
45  setMBB(*MI.getParent());
46  State.II = MI.getIterator();
47 }
48 
50 
53  assert(MBB.getParent() == &getMF() &&
54  "Basic block is in a different function");
55  State.MBB = &MBB;
56  State.II = II;
57 }
58 
59 void MachineIRBuilder::recordInsertion(MachineInstr *InsertedInstr) const {
60  if (State.Observer)
61  State.Observer->createdInstr(*InsertedInstr);
62 }
63 
65  State.Observer = &Observer;
66 }
67 
69 
70 //------------------------------------------------------------------------------
71 // Build instruction variants.
72 //------------------------------------------------------------------------------
73 
75  return insertInstr(buildInstrNoInsert(Opcode));
76 }
77 
79  MachineInstrBuilder MIB = BuildMI(getMF(), getDL(), getTII().get(Opcode));
80  return MIB;
81 }
82 
84  getMBB().insert(getInsertPt(), MIB);
85  recordInsertion(MIB);
86  return MIB;
87 }
88 
91  const MDNode *Expr) {
92  assert(isa<DILocalVariable>(Variable) && "not a variable");
93  assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
94  assert(
95  cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(getDL()) &&
96  "Expected inlined-at fields to agree");
97  return insertInstr(BuildMI(getMF(), getDL(),
98  getTII().get(TargetOpcode::DBG_VALUE),
99  /*IsIndirect*/ false, Reg, Variable, Expr));
100 }
101 
104  const MDNode *Expr) {
105  assert(isa<DILocalVariable>(Variable) && "not a variable");
106  assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
107  assert(
108  cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(getDL()) &&
109  "Expected inlined-at fields to agree");
110  return insertInstr(BuildMI(getMF(), getDL(),
111  getTII().get(TargetOpcode::DBG_VALUE),
112  /*IsIndirect*/ true, Reg, Variable, Expr));
113 }
114 
116  const MDNode *Variable,
117  const MDNode *Expr) {
118  assert(isa<DILocalVariable>(Variable) && "not a variable");
119  assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
120  assert(
121  cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(getDL()) &&
122  "Expected inlined-at fields to agree");
123  return buildInstr(TargetOpcode::DBG_VALUE)
124  .addFrameIndex(FI)
125  .addImm(0)
126  .addMetadata(Variable)
127  .addMetadata(Expr);
128 }
129 
131  const MDNode *Variable,
132  const MDNode *Expr) {
133  assert(isa<DILocalVariable>(Variable) && "not a variable");
134  assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
135  assert(
136  cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(getDL()) &&
137  "Expected inlined-at fields to agree");
138  auto MIB = buildInstr(TargetOpcode::DBG_VALUE);
139  if (auto *CI = dyn_cast<ConstantInt>(&C)) {
140  if (CI->getBitWidth() > 64)
141  MIB.addCImm(CI);
142  else
143  MIB.addImm(CI->getZExtValue());
144  } else if (auto *CFP = dyn_cast<ConstantFP>(&C)) {
145  MIB.addFPImm(CFP);
146  } else {
147  // Insert %noreg if we didn't find a usable constant and had to drop it.
148  MIB.addReg(0U);
149  }
150 
151  return MIB.addImm(0).addMetadata(Variable).addMetadata(Expr);
152 }
153 
155  assert(isa<DILabel>(Label) && "not a label");
156  assert(cast<DILabel>(Label)->isValidLocationForIntrinsic(State.DL) &&
157  "Expected inlined-at fields to agree");
158  auto MIB = buildInstr(TargetOpcode::DBG_LABEL);
159 
160  return MIB.addMetadata(Label);
161 }
162 
164  int Idx) {
165  assert(Res.getLLTTy(*getMRI()).isPointer() && "invalid operand type");
166  auto MIB = buildInstr(TargetOpcode::G_FRAME_INDEX);
167  Res.addDefToMIB(*getMRI(), MIB);
168  MIB.addFrameIndex(Idx);
169  return MIB;
170 }
171 
173  const GlobalValue *GV) {
174  assert(Res.getLLTTy(*getMRI()).isPointer() && "invalid operand type");
176  GV->getType()->getAddressSpace() &&
177  "address space mismatch");
178 
179  auto MIB = buildInstr(TargetOpcode::G_GLOBAL_VALUE);
180  Res.addDefToMIB(*getMRI(), MIB);
181  MIB.addGlobalAddress(GV);
182  return MIB;
183 }
184 
186  unsigned JTI) {
187  return buildInstr(TargetOpcode::G_JUMP_TABLE, {PtrTy}, {})
188  .addJumpTableIndex(JTI);
189 }
190 
191 void MachineIRBuilder::validateBinaryOp(const LLT &Res, const LLT &Op0,
192  const LLT &Op1) {
193  assert((Res.isScalar() || Res.isVector()) && "invalid operand type");
194  assert((Res == Op0 && Res == Op1) && "type mismatch");
195 }
196 
197 void MachineIRBuilder::validateShiftOp(const LLT &Res, const LLT &Op0,
198  const LLT &Op1) {
199  assert((Res.isScalar() || Res.isVector()) && "invalid operand type");
200  assert((Res == Op0) && "type mismatch");
201 }
202 
204  const SrcOp &Op0,
205  const SrcOp &Op1) {
206  assert(Res.getLLTTy(*getMRI()).isPointer() &&
207  Res.getLLTTy(*getMRI()) == Op0.getLLTTy(*getMRI()) && "type mismatch");
208  assert(Op1.getLLTTy(*getMRI()).isScalar() && "invalid offset type");
209 
210  auto MIB = buildInstr(TargetOpcode::G_GEP);
211  Res.addDefToMIB(*getMRI(), MIB);
212  Op0.addSrcToMIB(MIB);
213  Op1.addSrcToMIB(MIB);
214  return MIB;
215 }
216 
219  const LLT &ValueTy, uint64_t Value) {
220  assert(Res == 0 && "Res is a result argument");
221  assert(ValueTy.isScalar() && "invalid offset type");
222 
223  if (Value == 0) {
224  Res = Op0;
225  return None;
226  }
227 
229  auto Cst = buildConstant(ValueTy, Value);
230  return buildGEP(Res, Op0, Cst.getReg(0));
231 }
232 
234  const SrcOp &Op0,
235  uint32_t NumBits) {
236  assert(Res.getLLTTy(*getMRI()).isPointer() &&
237  Res.getLLTTy(*getMRI()) == Op0.getLLTTy(*getMRI()) && "type mismatch");
238 
239  auto MIB = buildInstr(TargetOpcode::G_PTR_MASK);
240  Res.addDefToMIB(*getMRI(), MIB);
241  Op0.addSrcToMIB(MIB);
242  MIB.addImm(NumBits);
243  return MIB;
244 }
245 
247  return buildInstr(TargetOpcode::G_BR).addMBB(&Dest);
248 }
249 
251  assert(getMRI()->getType(Tgt).isPointer() && "invalid branch destination");
252  return buildInstr(TargetOpcode::G_BRINDIRECT).addUse(Tgt);
253 }
254 
256  unsigned JTI,
257  Register IndexReg) {
258  assert(getMRI()->getType(TablePtr).isPointer() &&
259  "Table reg must be a pointer");
260  return buildInstr(TargetOpcode::G_BRJT)
261  .addUse(TablePtr)
262  .addJumpTableIndex(JTI)
263  .addUse(IndexReg);
264 }
265 
267  const SrcOp &Op) {
268  return buildInstr(TargetOpcode::COPY, Res, Op);
269 }
270 
272  const ConstantInt &Val) {
273  LLT Ty = Res.getLLTTy(*getMRI());
274  LLT EltTy = Ty.getScalarType();
275  assert(EltTy.getScalarSizeInBits() == Val.getBitWidth() &&
276  "creating constant with the wrong size");
277 
278  if (Ty.isVector()) {
279  auto Const = buildInstr(TargetOpcode::G_CONSTANT)
280  .addDef(getMRI()->createGenericVirtualRegister(EltTy))
281  .addCImm(&Val);
282  return buildSplatVector(Res, Const);
283  }
284 
285  auto Const = buildInstr(TargetOpcode::G_CONSTANT);
286  Res.addDefToMIB(*getMRI(), Const);
287  Const.addCImm(&Val);
288  return Const;
289 }
290 
292  int64_t Val) {
293  auto IntN = IntegerType::get(getMF().getFunction().getContext(),
295  ConstantInt *CI = ConstantInt::get(IntN, Val, true);
296  return buildConstant(Res, *CI);
297 }
298 
300  const ConstantFP &Val) {
301  LLT Ty = Res.getLLTTy(*getMRI());
302  LLT EltTy = Ty.getScalarType();
303 
305  == EltTy.getSizeInBits() &&
306  "creating fconstant with the wrong size");
307 
308  assert(!Ty.isPointer() && "invalid operand type");
309 
310  if (Ty.isVector()) {
311  auto Const = buildInstr(TargetOpcode::G_FCONSTANT)
312  .addDef(getMRI()->createGenericVirtualRegister(EltTy))
313  .addFPImm(&Val);
314 
315  return buildSplatVector(Res, Const);
316  }
317 
318  auto Const = buildInstr(TargetOpcode::G_FCONSTANT);
319  Res.addDefToMIB(*getMRI(), Const);
320  Const.addFPImm(&Val);
321  return Const;
322 }
323 
325  const APInt &Val) {
326  ConstantInt *CI = ConstantInt::get(getMF().getFunction().getContext(), Val);
327  return buildConstant(Res, *CI);
328 }
329 
331  double Val) {
332  LLT DstTy = Res.getLLTTy(*getMRI());
333  auto &Ctx = getMF().getFunction().getContext();
334  auto *CFP =
336  return buildFConstant(Res, *CFP);
337 }
338 
340  const APFloat &Val) {
341  auto &Ctx = getMF().getFunction().getContext();
342  auto *CFP = ConstantFP::get(Ctx, Val);
343  return buildFConstant(Res, *CFP);
344 }
345 
347  MachineBasicBlock &Dest) {
348  assert(getMRI()->getType(Tst).isScalar() && "invalid operand type");
349 
350  return buildInstr(TargetOpcode::G_BRCOND).addUse(Tst).addMBB(&Dest);
351 }
352 
354  const SrcOp &Addr,
355  MachineMemOperand &MMO) {
356  return buildLoadInstr(TargetOpcode::G_LOAD, Res, Addr, MMO);
357 }
358 
360  const DstOp &Res,
361  const SrcOp &Addr,
362  MachineMemOperand &MMO) {
363  assert(Res.getLLTTy(*getMRI()).isValid() && "invalid operand type");
364  assert(Addr.getLLTTy(*getMRI()).isPointer() && "invalid operand type");
365 
366  auto MIB = buildInstr(Opcode);
367  Res.addDefToMIB(*getMRI(), MIB);
368  Addr.addSrcToMIB(MIB);
369  MIB.addMemOperand(&MMO);
370  return MIB;
371 }
372 
374  const SrcOp &Addr,
375  MachineMemOperand &MMO) {
376  assert(Val.getLLTTy(*getMRI()).isValid() && "invalid operand type");
377  assert(Addr.getLLTTy(*getMRI()).isPointer() && "invalid operand type");
378 
379  auto MIB = buildInstr(TargetOpcode::G_STORE);
380  Val.addSrcToMIB(MIB);
381  Addr.addSrcToMIB(MIB);
382  MIB.addMemOperand(&MMO);
383  return MIB;
384 }
385 
387  const DstOp &CarryOut,
388  const SrcOp &Op0,
389  const SrcOp &Op1) {
390  return buildInstr(TargetOpcode::G_UADDO, {Res, CarryOut}, {Op0, Op1});
391 }
392 
394  const DstOp &CarryOut,
395  const SrcOp &Op0,
396  const SrcOp &Op1,
397  const SrcOp &CarryIn) {
398  return buildInstr(TargetOpcode::G_UADDE, {Res, CarryOut},
399  {Op0, Op1, CarryIn});
400 }
401 
403  const SrcOp &Op) {
404  return buildInstr(TargetOpcode::G_ANYEXT, Res, Op);
405 }
406 
408  const SrcOp &Op) {
409  return buildInstr(TargetOpcode::G_SEXT, Res, Op);
410 }
411 
413  const SrcOp &Op) {
414  return buildInstr(TargetOpcode::G_ZEXT, Res, Op);
415 }
416 
417 unsigned MachineIRBuilder::getBoolExtOp(bool IsVec, bool IsFP) const {
418  const auto *TLI = getMF().getSubtarget().getTargetLowering();
419  switch (TLI->getBooleanContents(IsVec, IsFP)) {
421  return TargetOpcode::G_SEXT;
423  return TargetOpcode::G_ZEXT;
424  default:
425  return TargetOpcode::G_ANYEXT;
426  }
427 }
428 
430  const SrcOp &Op,
431  bool IsFP) {
432  unsigned ExtOp = getBoolExtOp(getMRI()->getType(Op.getReg()).isVector(), IsFP);
433  return buildInstr(ExtOp, Res, Op);
434 }
435 
437  const DstOp &Res,
438  const SrcOp &Op) {
439  assert((TargetOpcode::G_ANYEXT == ExtOpc || TargetOpcode::G_ZEXT == ExtOpc ||
440  TargetOpcode::G_SEXT == ExtOpc) &&
441  "Expecting Extending Opc");
442  assert(Res.getLLTTy(*getMRI()).isScalar() ||
443  Res.getLLTTy(*getMRI()).isVector());
444  assert(Res.getLLTTy(*getMRI()).isScalar() ==
445  Op.getLLTTy(*getMRI()).isScalar());
446 
447  unsigned Opcode = TargetOpcode::COPY;
448  if (Res.getLLTTy(*getMRI()).getSizeInBits() >
449  Op.getLLTTy(*getMRI()).getSizeInBits())
450  Opcode = ExtOpc;
451  else if (Res.getLLTTy(*getMRI()).getSizeInBits() <
452  Op.getLLTTy(*getMRI()).getSizeInBits())
453  Opcode = TargetOpcode::G_TRUNC;
454  else
455  assert(Res.getLLTTy(*getMRI()) == Op.getLLTTy(*getMRI()));
456 
457  return buildInstr(Opcode, Res, Op);
458 }
459 
461  const SrcOp &Op) {
462  return buildExtOrTrunc(TargetOpcode::G_SEXT, Res, Op);
463 }
464 
466  const SrcOp &Op) {
467  return buildExtOrTrunc(TargetOpcode::G_ZEXT, Res, Op);
468 }
469 
471  const SrcOp &Op) {
472  return buildExtOrTrunc(TargetOpcode::G_ANYEXT, Res, Op);
473 }
474 
476  const SrcOp &Src) {
477  LLT SrcTy = Src.getLLTTy(*getMRI());
478  LLT DstTy = Dst.getLLTTy(*getMRI());
479  if (SrcTy == DstTy)
480  return buildCopy(Dst, Src);
481 
482  unsigned Opcode;
483  if (SrcTy.isPointer() && DstTy.isScalar())
484  Opcode = TargetOpcode::G_PTRTOINT;
485  else if (DstTy.isPointer() && SrcTy.isScalar())
486  Opcode = TargetOpcode::G_INTTOPTR;
487  else {
488  assert(!SrcTy.isPointer() && !DstTy.isPointer() && "n G_ADDRCAST yet");
489  Opcode = TargetOpcode::G_BITCAST;
490  }
491 
492  return buildInstr(Opcode, Dst, Src);
493 }
494 
496  const SrcOp &Src,
497  uint64_t Index) {
498  LLT SrcTy = Src.getLLTTy(*getMRI());
499  LLT DstTy = Dst.getLLTTy(*getMRI());
500 
501 #ifndef NDEBUG
502  assert(SrcTy.isValid() && "invalid operand type");
503  assert(DstTy.isValid() && "invalid operand type");
504  assert(Index + DstTy.getSizeInBits() <= SrcTy.getSizeInBits() &&
505  "extracting off end of register");
506 #endif
507 
508  if (DstTy.getSizeInBits() == SrcTy.getSizeInBits()) {
509  assert(Index == 0 && "insertion past the end of a register");
510  return buildCast(Dst, Src);
511  }
512 
513  auto Extract = buildInstr(TargetOpcode::G_EXTRACT);
514  Dst.addDefToMIB(*getMRI(), Extract);
515  Src.addSrcToMIB(Extract);
516  Extract.addImm(Index);
517  return Extract;
518 }
519 
521  ArrayRef<uint64_t> Indices) {
522 #ifndef NDEBUG
523  assert(Ops.size() == Indices.size() && "incompatible args");
524  assert(!Ops.empty() && "invalid trivial sequence");
525  assert(std::is_sorted(Indices.begin(), Indices.end()) &&
526  "sequence offsets must be in ascending order");
527 
528  assert(getMRI()->getType(Res).isValid() && "invalid operand type");
529  for (auto Op : Ops)
530  assert(getMRI()->getType(Op).isValid() && "invalid operand type");
531 #endif
532 
533  LLT ResTy = getMRI()->getType(Res);
534  LLT OpTy = getMRI()->getType(Ops[0]);
535  unsigned OpSize = OpTy.getSizeInBits();
536  bool MaybeMerge = true;
537  for (unsigned i = 0; i < Ops.size(); ++i) {
538  if (getMRI()->getType(Ops[i]) != OpTy || Indices[i] != i * OpSize) {
539  MaybeMerge = false;
540  break;
541  }
542  }
543 
544  if (MaybeMerge && Ops.size() * OpSize == ResTy.getSizeInBits()) {
545  buildMerge(Res, Ops);
546  return;
547  }
548 
549  Register ResIn = getMRI()->createGenericVirtualRegister(ResTy);
550  buildUndef(ResIn);
551 
552  for (unsigned i = 0; i < Ops.size(); ++i) {
553  Register ResOut = i + 1 == Ops.size()
554  ? Res
556  buildInsert(ResOut, ResIn, Ops[i], Indices[i]);
557  ResIn = ResOut;
558  }
559 }
560 
562  return buildInstr(TargetOpcode::G_IMPLICIT_DEF, {Res}, {});
563 }
564 
566  ArrayRef<Register> Ops) {
567  // Unfortunately to convert from ArrayRef<LLT> to ArrayRef<SrcOp>,
568  // we need some temporary storage for the DstOp objects. Here we use a
569  // sufficiently large SmallVector to not go through the heap.
570  SmallVector<SrcOp, 8> TmpVec(Ops.begin(), Ops.end());
571  assert(TmpVec.size() > 1);
572  return buildInstr(TargetOpcode::G_MERGE_VALUES, Res, TmpVec);
573 }
574 
576  const SrcOp &Op) {
577  // Unfortunately to convert from ArrayRef<LLT> to ArrayRef<DstOp>,
578  // we need some temporary storage for the DstOp objects. Here we use a
579  // sufficiently large SmallVector to not go through the heap.
580  SmallVector<DstOp, 8> TmpVec(Res.begin(), Res.end());
581  assert(TmpVec.size() > 1);
582  return buildInstr(TargetOpcode::G_UNMERGE_VALUES, TmpVec, Op);
583 }
584 
586  const SrcOp &Op) {
587  unsigned NumReg = Op.getLLTTy(*getMRI()).getSizeInBits() / Res.getSizeInBits();
589  for (unsigned I = 0; I != NumReg; ++I)
590  TmpVec.push_back(getMRI()->createGenericVirtualRegister(Res));
591  return buildUnmerge(TmpVec, Op);
592 }
593 
595  const SrcOp &Op) {
596  // Unfortunately to convert from ArrayRef<Register> to ArrayRef<DstOp>,
597  // we need some temporary storage for the DstOp objects. Here we use a
598  // sufficiently large SmallVector to not go through the heap.
599  SmallVector<DstOp, 8> TmpVec(Res.begin(), Res.end());
600  assert(TmpVec.size() > 1);
601  return buildInstr(TargetOpcode::G_UNMERGE_VALUES, TmpVec, Op);
602 }
603 
605  ArrayRef<Register> Ops) {
606  // Unfortunately to convert from ArrayRef<Register> to ArrayRef<SrcOp>,
607  // we need some temporary storage for the DstOp objects. Here we use a
608  // sufficiently large SmallVector to not go through the heap.
609  SmallVector<SrcOp, 8> TmpVec(Ops.begin(), Ops.end());
610  return buildInstr(TargetOpcode::G_BUILD_VECTOR, Res, TmpVec);
611 }
612 
614  const SrcOp &Src) {
615  SmallVector<SrcOp, 8> TmpVec(Res.getLLTTy(*getMRI()).getNumElements(), Src);
616  return buildInstr(TargetOpcode::G_BUILD_VECTOR, Res, TmpVec);
617 }
618 
621  ArrayRef<Register> Ops) {
622  // Unfortunately to convert from ArrayRef<Register> to ArrayRef<SrcOp>,
623  // we need some temporary storage for the DstOp objects. Here we use a
624  // sufficiently large SmallVector to not go through the heap.
625  SmallVector<SrcOp, 8> TmpVec(Ops.begin(), Ops.end());
626  return buildInstr(TargetOpcode::G_BUILD_VECTOR_TRUNC, Res, TmpVec);
627 }
628 
631  // Unfortunately to convert from ArrayRef<Register> to ArrayRef<SrcOp>,
632  // we need some temporary storage for the DstOp objects. Here we use a
633  // sufficiently large SmallVector to not go through the heap.
634  SmallVector<SrcOp, 8> TmpVec(Ops.begin(), Ops.end());
635  return buildInstr(TargetOpcode::G_CONCAT_VECTORS, Res, TmpVec);
636 }
637 
639  Register Op, unsigned Index) {
640  assert(Index + getMRI()->getType(Op).getSizeInBits() <=
641  getMRI()->getType(Res).getSizeInBits() &&
642  "insertion past the end of a register");
643 
644  if (getMRI()->getType(Res).getSizeInBits() ==
645  getMRI()->getType(Op).getSizeInBits()) {
646  return buildCast(Res, Op);
647  }
648 
649  return buildInstr(TargetOpcode::G_INSERT)
650  .addDef(Res)
651  .addUse(Src)
652  .addUse(Op)
653  .addImm(Index);
654 }
655 
657  ArrayRef<Register> ResultRegs,
658  bool HasSideEffects) {
659  auto MIB =
660  buildInstr(HasSideEffects ? TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS
661  : TargetOpcode::G_INTRINSIC);
662  for (unsigned ResultReg : ResultRegs)
663  MIB.addDef(ResultReg);
664  MIB.addIntrinsicID(ID);
665  return MIB;
666 }
667 
670  bool HasSideEffects) {
671  auto MIB =
672  buildInstr(HasSideEffects ? TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS
673  : TargetOpcode::G_INTRINSIC);
674  for (DstOp Result : Results)
675  Result.addDefToMIB(*getMRI(), MIB);
676  MIB.addIntrinsicID(ID);
677  return MIB;
678 }
679 
681  const SrcOp &Op) {
682  return buildInstr(TargetOpcode::G_TRUNC, Res, Op);
683 }
684 
686  const SrcOp &Op) {
687  return buildInstr(TargetOpcode::G_FPTRUNC, Res, Op);
688 }
689 
691  const DstOp &Res,
692  const SrcOp &Op0,
693  const SrcOp &Op1) {
694  return buildInstr(TargetOpcode::G_ICMP, Res, {Pred, Op0, Op1});
695 }
696 
698  const DstOp &Res,
699  const SrcOp &Op0,
700  const SrcOp &Op1) {
701 
702  return buildInstr(TargetOpcode::G_FCMP, Res, {Pred, Op0, Op1});
703 }
704 
706  const SrcOp &Tst,
707  const SrcOp &Op0,
708  const SrcOp &Op1) {
709 
710  return buildInstr(TargetOpcode::G_SELECT, {Res}, {Tst, Op0, Op1});
711 }
712 
715  const SrcOp &Elt, const SrcOp &Idx) {
716  return buildInstr(TargetOpcode::G_INSERT_VECTOR_ELT, Res, {Val, Elt, Idx});
717 }
718 
721  const SrcOp &Idx) {
722  return buildInstr(TargetOpcode::G_EXTRACT_VECTOR_ELT, Res, {Val, Idx});
723 }
724 
726  Register OldValRes, Register SuccessRes, Register Addr, Register CmpVal,
727  Register NewVal, MachineMemOperand &MMO) {
728 #ifndef NDEBUG
729  LLT OldValResTy = getMRI()->getType(OldValRes);
730  LLT SuccessResTy = getMRI()->getType(SuccessRes);
731  LLT AddrTy = getMRI()->getType(Addr);
732  LLT CmpValTy = getMRI()->getType(CmpVal);
733  LLT NewValTy = getMRI()->getType(NewVal);
734  assert(OldValResTy.isScalar() && "invalid operand type");
735  assert(SuccessResTy.isScalar() && "invalid operand type");
736  assert(AddrTy.isPointer() && "invalid operand type");
737  assert(CmpValTy.isValid() && "invalid operand type");
738  assert(NewValTy.isValid() && "invalid operand type");
739  assert(OldValResTy == CmpValTy && "type mismatch");
740  assert(OldValResTy == NewValTy && "type mismatch");
741 #endif
742 
743  return buildInstr(TargetOpcode::G_ATOMIC_CMPXCHG_WITH_SUCCESS)
744  .addDef(OldValRes)
745  .addDef(SuccessRes)
746  .addUse(Addr)
747  .addUse(CmpVal)
748  .addUse(NewVal)
749  .addMemOperand(&MMO);
750 }
751 
754  Register CmpVal, Register NewVal,
755  MachineMemOperand &MMO) {
756 #ifndef NDEBUG
757  LLT OldValResTy = getMRI()->getType(OldValRes);
758  LLT AddrTy = getMRI()->getType(Addr);
759  LLT CmpValTy = getMRI()->getType(CmpVal);
760  LLT NewValTy = getMRI()->getType(NewVal);
761  assert(OldValResTy.isScalar() && "invalid operand type");
762  assert(AddrTy.isPointer() && "invalid operand type");
763  assert(CmpValTy.isValid() && "invalid operand type");
764  assert(NewValTy.isValid() && "invalid operand type");
765  assert(OldValResTy == CmpValTy && "type mismatch");
766  assert(OldValResTy == NewValTy && "type mismatch");
767 #endif
768 
769  return buildInstr(TargetOpcode::G_ATOMIC_CMPXCHG)
770  .addDef(OldValRes)
771  .addUse(Addr)
772  .addUse(CmpVal)
773  .addUse(NewVal)
774  .addMemOperand(&MMO);
775 }
776 
778  Register OldValRes,
779  Register Addr,
780  Register Val,
781  MachineMemOperand &MMO) {
782 #ifndef NDEBUG
783  LLT OldValResTy = getMRI()->getType(OldValRes);
784  LLT AddrTy = getMRI()->getType(Addr);
785  LLT ValTy = getMRI()->getType(Val);
786  assert(OldValResTy.isScalar() && "invalid operand type");
787  assert(AddrTy.isPointer() && "invalid operand type");
788  assert(ValTy.isValid() && "invalid operand type");
789  assert(OldValResTy == ValTy && "type mismatch");
790 #endif
791 
792  return buildInstr(Opcode)
793  .addDef(OldValRes)
794  .addUse(Addr)
795  .addUse(Val)
796  .addMemOperand(&MMO);
797 }
798 
801  Register Val, MachineMemOperand &MMO) {
802  return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_XCHG, OldValRes, Addr, Val,
803  MMO);
804 }
807  Register Val, MachineMemOperand &MMO) {
808  return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_ADD, OldValRes, Addr, Val,
809  MMO);
810 }
813  Register Val, MachineMemOperand &MMO) {
814  return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_SUB, OldValRes, Addr, Val,
815  MMO);
816 }
819  Register Val, MachineMemOperand &MMO) {
820  return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_AND, OldValRes, Addr, Val,
821  MMO);
822 }
825  Register Val, MachineMemOperand &MMO) {
826  return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_NAND, OldValRes, Addr, Val,
827  MMO);
828 }
830  Register Addr,
831  Register Val,
832  MachineMemOperand &MMO) {
833  return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_OR, OldValRes, Addr, Val,
834  MMO);
835 }
838  Register Val, MachineMemOperand &MMO) {
839  return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_XOR, OldValRes, Addr, Val,
840  MMO);
841 }
844  Register Val, MachineMemOperand &MMO) {
845  return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_MAX, OldValRes, Addr, Val,
846  MMO);
847 }
850  Register Val, MachineMemOperand &MMO) {
851  return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_MIN, OldValRes, Addr, Val,
852  MMO);
853 }
856  Register Val, MachineMemOperand &MMO) {
857  return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_UMAX, OldValRes, Addr, Val,
858  MMO);
859 }
862  Register Val, MachineMemOperand &MMO) {
863  return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_UMIN, OldValRes, Addr, Val,
864  MMO);
865 }
866 
868 MachineIRBuilder::buildFence(unsigned Ordering, unsigned Scope) {
869  return buildInstr(TargetOpcode::G_FENCE)
870  .addImm(Ordering)
871  .addImm(Scope);
872 }
873 
876 #ifndef NDEBUG
877  assert(getMRI()->getType(Res).isPointer() && "invalid res type");
878 #endif
879 
880  return buildInstr(TargetOpcode::G_BLOCK_ADDR).addDef(Res).addBlockAddress(BA);
881 }
882 
883 void MachineIRBuilder::validateTruncExt(const LLT &DstTy, const LLT &SrcTy,
884  bool IsExtend) {
885 #ifndef NDEBUG
886  if (DstTy.isVector()) {
887  assert(SrcTy.isVector() && "mismatched cast between vector and non-vector");
888  assert(SrcTy.getNumElements() == DstTy.getNumElements() &&
889  "different number of elements in a trunc/ext");
890  } else
891  assert(DstTy.isScalar() && SrcTy.isScalar() && "invalid extend/trunc");
892 
893  if (IsExtend)
894  assert(DstTy.getSizeInBits() > SrcTy.getSizeInBits() &&
895  "invalid narrowing extend");
896  else
897  assert(DstTy.getSizeInBits() < SrcTy.getSizeInBits() &&
898  "invalid widening trunc");
899 #endif
900 }
901 
902 void MachineIRBuilder::validateSelectOp(const LLT &ResTy, const LLT &TstTy,
903  const LLT &Op0Ty, const LLT &Op1Ty) {
904 #ifndef NDEBUG
905  assert((ResTy.isScalar() || ResTy.isVector() || ResTy.isPointer()) &&
906  "invalid operand type");
907  assert((ResTy == Op0Ty && ResTy == Op1Ty) && "type mismatch");
908  if (ResTy.isScalar() || ResTy.isPointer())
909  assert(TstTy.isScalar() && "type mismatch");
910  else
911  assert((TstTy.isScalar() ||
912  (TstTy.isVector() &&
913  TstTy.getNumElements() == Op0Ty.getNumElements())) &&
914  "type mismatch");
915 #endif
916 }
917 
919  ArrayRef<DstOp> DstOps,
920  ArrayRef<SrcOp> SrcOps,
921  Optional<unsigned> Flags) {
922  switch (Opc) {
923  default:
924  break;
925  case TargetOpcode::G_SELECT: {
926  assert(DstOps.size() == 1 && "Invalid select");
927  assert(SrcOps.size() == 3 && "Invalid select");
929  DstOps[0].getLLTTy(*getMRI()), SrcOps[0].getLLTTy(*getMRI()),
930  SrcOps[1].getLLTTy(*getMRI()), SrcOps[2].getLLTTy(*getMRI()));
931  break;
932  }
933  case TargetOpcode::G_ADD:
934  case TargetOpcode::G_AND:
935  case TargetOpcode::G_MUL:
936  case TargetOpcode::G_OR:
937  case TargetOpcode::G_SUB:
938  case TargetOpcode::G_XOR:
939  case TargetOpcode::G_UDIV:
940  case TargetOpcode::G_SDIV:
941  case TargetOpcode::G_UREM:
942  case TargetOpcode::G_SREM:
943  case TargetOpcode::G_SMIN:
944  case TargetOpcode::G_SMAX:
945  case TargetOpcode::G_UMIN:
946  case TargetOpcode::G_UMAX: {
947  // All these are binary ops.
948  assert(DstOps.size() == 1 && "Invalid Dst");
949  assert(SrcOps.size() == 2 && "Invalid Srcs");
950  validateBinaryOp(DstOps[0].getLLTTy(*getMRI()),
951  SrcOps[0].getLLTTy(*getMRI()),
952  SrcOps[1].getLLTTy(*getMRI()));
953  break;
954  }
955  case TargetOpcode::G_SHL:
956  case TargetOpcode::G_ASHR:
957  case TargetOpcode::G_LSHR: {
958  assert(DstOps.size() == 1 && "Invalid Dst");
959  assert(SrcOps.size() == 2 && "Invalid Srcs");
960  validateShiftOp(DstOps[0].getLLTTy(*getMRI()),
961  SrcOps[0].getLLTTy(*getMRI()),
962  SrcOps[1].getLLTTy(*getMRI()));
963  break;
964  }
965  case TargetOpcode::G_SEXT:
966  case TargetOpcode::G_ZEXT:
967  case TargetOpcode::G_ANYEXT:
968  assert(DstOps.size() == 1 && "Invalid Dst");
969  assert(SrcOps.size() == 1 && "Invalid Srcs");
970  validateTruncExt(DstOps[0].getLLTTy(*getMRI()),
971  SrcOps[0].getLLTTy(*getMRI()), true);
972  break;
973  case TargetOpcode::G_TRUNC:
974  case TargetOpcode::G_FPTRUNC: {
975  assert(DstOps.size() == 1 && "Invalid Dst");
976  assert(SrcOps.size() == 1 && "Invalid Srcs");
977  validateTruncExt(DstOps[0].getLLTTy(*getMRI()),
978  SrcOps[0].getLLTTy(*getMRI()), false);
979  break;
980  }
981  case TargetOpcode::COPY:
982  assert(DstOps.size() == 1 && "Invalid Dst");
983  // If the caller wants to add a subreg source it has to be done separately
984  // so we may not have any SrcOps at this point yet.
985  break;
986  case TargetOpcode::G_FCMP:
987  case TargetOpcode::G_ICMP: {
988  assert(DstOps.size() == 1 && "Invalid Dst Operands");
989  assert(SrcOps.size() == 3 && "Invalid Src Operands");
990  // For F/ICMP, the first src operand is the predicate, followed by
991  // the two comparands.
992  assert(SrcOps[0].getSrcOpKind() == SrcOp::SrcType::Ty_Predicate &&
993  "Expecting predicate");
994  assert([&]() -> bool {
995  CmpInst::Predicate Pred = SrcOps[0].getPredicate();
996  return Opc == TargetOpcode::G_ICMP ? CmpInst::isIntPredicate(Pred)
997  : CmpInst::isFPPredicate(Pred);
998  }() && "Invalid predicate");
999  assert(SrcOps[1].getLLTTy(*getMRI()) == SrcOps[2].getLLTTy(*getMRI()) &&
1000  "Type mismatch");
1001  assert([&]() -> bool {
1002  LLT Op0Ty = SrcOps[1].getLLTTy(*getMRI());
1003  LLT DstTy = DstOps[0].getLLTTy(*getMRI());
1004  if (Op0Ty.isScalar() || Op0Ty.isPointer())
1005  return DstTy.isScalar();
1006  else
1007  return DstTy.isVector() &&
1008  DstTy.getNumElements() == Op0Ty.getNumElements();
1009  }() && "Type Mismatch");
1010  break;
1011  }
1012  case TargetOpcode::G_UNMERGE_VALUES: {
1013  assert(!DstOps.empty() && "Invalid trivial sequence");
1014  assert(SrcOps.size() == 1 && "Invalid src for Unmerge");
1015  assert(std::all_of(DstOps.begin(), DstOps.end(),
1016  [&, this](const DstOp &Op) {
1017  return Op.getLLTTy(*getMRI()) ==
1018  DstOps[0].getLLTTy(*getMRI());
1019  }) &&
1020  "type mismatch in output list");
1021  assert(DstOps.size() * DstOps[0].getLLTTy(*getMRI()).getSizeInBits() ==
1022  SrcOps[0].getLLTTy(*getMRI()).getSizeInBits() &&
1023  "input operands do not cover output register");
1024  break;
1025  }
1026  case TargetOpcode::G_MERGE_VALUES: {
1027  assert(!SrcOps.empty() && "invalid trivial sequence");
1028  assert(DstOps.size() == 1 && "Invalid Dst");
1029  assert(std::all_of(SrcOps.begin(), SrcOps.end(),
1030  [&, this](const SrcOp &Op) {
1031  return Op.getLLTTy(*getMRI()) ==
1032  SrcOps[0].getLLTTy(*getMRI());
1033  }) &&
1034  "type mismatch in input list");
1035  assert(SrcOps.size() * SrcOps[0].getLLTTy(*getMRI()).getSizeInBits() ==
1036  DstOps[0].getLLTTy(*getMRI()).getSizeInBits() &&
1037  "input operands do not cover output register");
1038  if (SrcOps.size() == 1)
1039  return buildCast(DstOps[0], SrcOps[0]);
1040  if (DstOps[0].getLLTTy(*getMRI()).isVector())
1041  return buildInstr(TargetOpcode::G_CONCAT_VECTORS, DstOps, SrcOps);
1042  break;
1043  }
1044  case TargetOpcode::G_EXTRACT_VECTOR_ELT: {
1045  assert(DstOps.size() == 1 && "Invalid Dst size");
1046  assert(SrcOps.size() == 2 && "Invalid Src size");
1047  assert(SrcOps[0].getLLTTy(*getMRI()).isVector() && "Invalid operand type");
1048  assert((DstOps[0].getLLTTy(*getMRI()).isScalar() ||
1049  DstOps[0].getLLTTy(*getMRI()).isPointer()) &&
1050  "Invalid operand type");
1051  assert(SrcOps[1].getLLTTy(*getMRI()).isScalar() && "Invalid operand type");
1052  assert(SrcOps[0].getLLTTy(*getMRI()).getElementType() ==
1053  DstOps[0].getLLTTy(*getMRI()) &&
1054  "Type mismatch");
1055  break;
1056  }
1057  case TargetOpcode::G_INSERT_VECTOR_ELT: {
1058  assert(DstOps.size() == 1 && "Invalid dst size");
1059  assert(SrcOps.size() == 3 && "Invalid src size");
1060  assert(DstOps[0].getLLTTy(*getMRI()).isVector() &&
1061  SrcOps[0].getLLTTy(*getMRI()).isVector() && "Invalid operand type");
1062  assert(DstOps[0].getLLTTy(*getMRI()).getElementType() ==
1063  SrcOps[1].getLLTTy(*getMRI()) &&
1064  "Type mismatch");
1065  assert(SrcOps[2].getLLTTy(*getMRI()).isScalar() && "Invalid index");
1066  assert(DstOps[0].getLLTTy(*getMRI()).getNumElements() ==
1067  SrcOps[0].getLLTTy(*getMRI()).getNumElements() &&
1068  "Type mismatch");
1069  break;
1070  }
1071  case TargetOpcode::G_BUILD_VECTOR: {
1072  assert((!SrcOps.empty() || SrcOps.size() < 2) &&
1073  "Must have at least 2 operands");
1074  assert(DstOps.size() == 1 && "Invalid DstOps");
1075  assert(DstOps[0].getLLTTy(*getMRI()).isVector() &&
1076  "Res type must be a vector");
1077  assert(std::all_of(SrcOps.begin(), SrcOps.end(),
1078  [&, this](const SrcOp &Op) {
1079  return Op.getLLTTy(*getMRI()) ==
1080  SrcOps[0].getLLTTy(*getMRI());
1081  }) &&
1082  "type mismatch in input list");
1083  assert(SrcOps.size() * SrcOps[0].getLLTTy(*getMRI()).getSizeInBits() ==
1084  DstOps[0].getLLTTy(*getMRI()).getSizeInBits() &&
1085  "input scalars do not exactly cover the output vector register");
1086  break;
1087  }
1088  case TargetOpcode::G_BUILD_VECTOR_TRUNC: {
1089  assert((!SrcOps.empty() || SrcOps.size() < 2) &&
1090  "Must have at least 2 operands");
1091  assert(DstOps.size() == 1 && "Invalid DstOps");
1092  assert(DstOps[0].getLLTTy(*getMRI()).isVector() &&
1093  "Res type must be a vector");
1094  assert(std::all_of(SrcOps.begin(), SrcOps.end(),
1095  [&, this](const SrcOp &Op) {
1096  return Op.getLLTTy(*getMRI()) ==
1097  SrcOps[0].getLLTTy(*getMRI());
1098  }) &&
1099  "type mismatch in input list");
1100  if (SrcOps[0].getLLTTy(*getMRI()).getSizeInBits() ==
1101  DstOps[0].getLLTTy(*getMRI()).getElementType().getSizeInBits())
1102  return buildInstr(TargetOpcode::G_BUILD_VECTOR, DstOps, SrcOps);
1103  break;
1104  }
1105  case TargetOpcode::G_CONCAT_VECTORS: {
1106  assert(DstOps.size() == 1 && "Invalid DstOps");
1107  assert((!SrcOps.empty() || SrcOps.size() < 2) &&
1108  "Must have at least 2 operands");
1109  assert(std::all_of(SrcOps.begin(), SrcOps.end(),
1110  [&, this](const SrcOp &Op) {
1111  return (Op.getLLTTy(*getMRI()).isVector() &&
1112  Op.getLLTTy(*getMRI()) ==
1113  SrcOps[0].getLLTTy(*getMRI()));
1114  }) &&
1115  "type mismatch in input list");
1116  assert(SrcOps.size() * SrcOps[0].getLLTTy(*getMRI()).getSizeInBits() ==
1117  DstOps[0].getLLTTy(*getMRI()).getSizeInBits() &&
1118  "input vectors do not exactly cover the output vector register");
1119  break;
1120  }
1121  case TargetOpcode::G_UADDE: {
1122  assert(DstOps.size() == 2 && "Invalid no of dst operands");
1123  assert(SrcOps.size() == 3 && "Invalid no of src operands");
1124  assert(DstOps[0].getLLTTy(*getMRI()).isScalar() && "Invalid operand");
1125  assert((DstOps[0].getLLTTy(*getMRI()) == SrcOps[0].getLLTTy(*getMRI())) &&
1126  (DstOps[0].getLLTTy(*getMRI()) == SrcOps[1].getLLTTy(*getMRI())) &&
1127  "Invalid operand");
1128  assert(DstOps[1].getLLTTy(*getMRI()).isScalar() && "Invalid operand");
1129  assert(DstOps[1].getLLTTy(*getMRI()) == SrcOps[2].getLLTTy(*getMRI()) &&
1130  "type mismatch");
1131  break;
1132  }
1133  }
1134 
1135  auto MIB = buildInstr(Opc);
1136  for (const DstOp &Op : DstOps)
1137  Op.addDefToMIB(*getMRI(), MIB);
1138  for (const SrcOp &Op : SrcOps)
1139  Op.addSrcToMIB(MIB);
1140  if (Flags)
1141  MIB->setFlags(*Flags);
1142  return MIB;
1143 }
MachineInstrBuilder buildDirectDbgValue(Register Reg, const MDNode *Variable, const MDNode *Expr)
Build and insert a DBG_VALUE instruction expressing the fact that the associated Variable lives in Re...
bool isFPPredicate() const
Definition: InstrTypes.h:824
uint64_t CallInst * C
const MachineInstrBuilder & addMetadata(const MDNode *MD) const
virtual MachineInstrBuilder buildConstant(const DstOp &Res, const ConstantInt &Val)
Build and insert Res = G_CONSTANT Val.
MachineInstrBuilder buildJumpTable(const LLT PtrTy, unsigned JTI)
Build and insert Res = G_JUMP_TABLE JTI.
void addDefToMIB(MachineRegisterInfo &MRI, MachineInstrBuilder &MIB) const
The CSE Analysis object.
Definition: CSEInfo.h:71
MachineInstrBuilder buildZExtOrTrunc(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_ZEXT Op, Res = G_TRUNC Op, or Res = COPY Op depending on the differing sizes...
MachineInstrBuilder buildBlockAddress(Register Res, const BlockAddress *BA)
Build and insert Res = G_BLOCK_ADDR BA.
MachineInstrBuilder buildUnmerge(ArrayRef< LLT > Res, const SrcOp &Op)
Build and insert Res0, ...
MachineInstrBuilder buildBrCond(Register Tst, MachineBasicBlock &Dest)
Build and insert G_BRCOND Tst, Dest.
This class represents lattice values for constants.
Definition: AllocatorList.h:23
MachineInstrBuilder buildInsert(Register Res, Register Src, Register Op, unsigned Index)
MachineInstrBuilder buildSExtOrTrunc(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_SEXT Op, Res = G_TRUNC Op, or Res = COPY Op depending on the differing sizes...
iterator begin() const
Definition: ArrayRef.h:136
unsigned getScalarSizeInBits() const
unsigned getSizeInBits(Register Reg, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI) const
Get the size in bits of Reg.
bool isScalar() const
GISelChangeObserver * Observer
MachineInstrBuilder buildCast(const DstOp &Dst, const SrcOp &Src)
Build and insert an appropriate cast between two registers of equal size.
unsigned Reg
virtual const TargetLowering * getTargetLowering() const
LLT getScalarType() const
Function Alias Analysis Results
LLT getType(unsigned Reg) const
Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register...
void addSrcToMIB(MachineInstrBuilder &MIB) const
static unsigned getSizeInBits(const fltSemantics &Sem)
Returns the size of the floating point number (in bits) in the given semantics.
Definition: APFloat.cpp:205
bool all_of(R &&range, UnaryPredicate P)
Provide wrappers to std::all_of which take ranges instead of having to pass begin/end explicitly...
Definition: STLExtras.h:1192
A debug info location.
Definition: DebugLoc.h:33
Metadata node.
Definition: Metadata.h:863
void buildSequence(Register Res, ArrayRef< Register > Ops, ArrayRef< uint64_t > Indices)
Build and insert instructions to put Ops together at the specified p Indices to form a larger registe...
const fltSemantics & getSemantics() const
Definition: APFloat.h:1165
void validateSelectOp(const LLT &ResTy, const LLT &TstTy, const LLT &Op0Ty, const LLT &Op1Ty)
MachineInstrBuilder buildUAddo(const DstOp &Res, const DstOp &CarryOut, const SrcOp &Op0, const SrcOp &Op1)
Build and insert Res, CarryOut = G_UADDO Op0, Op1.
unsigned getBitWidth() const
getBitWidth - Return the bitwidth of this constant.
Definition: Constants.h:142
LegalityPredicate isPointer(unsigned TypeIdx)
True iff the specified type index is a pointer (with any address space).
LegalityPredicate isVector(unsigned TypeIdx)
True iff the specified type index is a vector.
Optional< MachineInstrBuilder > materializeGEP(Register &Res, Register Op0, const LLT &ValueTy, uint64_t Value)
Materialize and insert Res = G_GEP Op0, (G_CONSTANT Value)
MachineInstrBuilder buildBrJT(Register TablePtr, unsigned JTI, Register IndexReg)
Build and insert G_BRJT TablePtr, JTI, IndexReg.
MachineInstrBuilder buildExtract(const DstOp &Res, const SrcOp &Src, uint64_t Index)
Build and insert `Res0, ...
MachineInstrBuilder buildAtomicRMWXor(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_XOR Addr, Val, MMO.
bool isVector() const
void setMF(MachineFunction &MF)
The address of a basic block.
Definition: Constants.h:839
A description of a memory reference used in the backend.
void setInsertPt(MachineBasicBlock &MBB, MachineBasicBlock::iterator II)
Set the insertion point before the specified position.
MachineInstrBuilder buildAnyExt(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_ANYEXT Op0.
MachineInstrBuilder buildExtOrTrunc(unsigned ExtOpc, const DstOp &Res, const SrcOp &Op)
Build and insert Res = ExtOpc, Res = G_TRUNC Op, or Res = COPY Op depending on the differing sizes of...
MachineInstrBuilder buildUAdde(const DstOp &Res, const DstOp &CarryOut, const SrcOp &Op0, const SrcOp &Op1, const SrcOp &CarryIn)
Build and insert Res, CarryOut = G_UADDE Op0, Op1, CarryIn.
const MachineInstrBuilder & addUse(unsigned RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register use operand.
void validateTruncExt(const LLT &Dst, const LLT &Src, bool IsExtend)
MachineInstrBuilder buildAnyExtOrTrunc(const DstOp &Res, const SrcOp &Op)
Res = COPY Op depending on the differing sizes of Res and Op.
MachineBasicBlock::iterator II
void recordInsertion(MachineInstr *MI) const
APFloat getAPFloatFromSize(double Val, unsigned Size)
Returns an APFloat from Val converted to the appropriate size.
Definition: Utils.cpp:309
MachineInstrBuilder buildLoadInstr(unsigned Opcode, const DstOp &Res, const SrcOp &Addr, MachineMemOperand &MMO)
Build and insert Res = <opcode> Addr, MMO.
MachineInstrBuilder buildFence(unsigned Ordering, unsigned Scope)
Build and insert G_FENCE Ordering, Scope.
MachineInstrBuilder buildBrIndirect(Register Tgt)
Build and insert G_BRINDIRECT Tgt.
MachineInstrBuilder buildInstrNoInsert(unsigned Opcode)
Build but don&#39;t insert <empty> = Opcode <empty>.
void validateBinaryOp(const LLT &Res, const LLT &Op0, const LLT &Op1)
MachineFunction & getMF()
Getter for the function we currently build.
const MachineInstrBuilder & addFPImm(const ConstantFP *Val) const
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:32
virtual const TargetInstrInfo * getInstrInfo() const
MachineInstrBuilder buildAtomicRMWUmax(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_UMAX Addr, Val, MMO.
static Function * getFunction(Constant *C)
Definition: Evaluator.cpp:258
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
MachineInstrBuilder buildExtractVectorElement(const DstOp &Res, const SrcOp &Val, const SrcOp &Idx)
Build and insert Res = G_EXTRACT_VECTOR_ELT Val, Idx.
Analysis containing CSE Info
Definition: CSEInfo.cpp:20
void setChangeObserver(GISelChangeObserver &Observer)
MachineBasicBlock::iterator getInsertPt()
Current insertion point for new instructions.
MachineInstrBuilder buildDbgLabel(const MDNode *Label)
Build and insert a DBG_LABEL instructions specifying that Label is given.
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
MachineInstrBundleIterator< MachineInstr > iterator
MachineInstrBuilder buildSExt(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_SEXT Op.
void validateShiftOp(const LLT &Res, const LLT &Op0, const LLT &Op1)
MachineRegisterInfo * getMRI()
Getter for MRI.
Abstract class that contains various methods for clients to notify about changes. ...
MachineInstrBuilder buildFPTrunc(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_FPTRUNC Op.
const MachineInstrBuilder & addBlockAddress(const BlockAddress *BA, int64_t Offset=0, unsigned char TargetFlags=0) const
const TargetInstrInfo * TII
Information used to access the description of the opcodes.
const MachineInstrBuilder & addCImm(const ConstantInt *Val) const
MachineInstrBuilder buildAtomicRMWMax(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_MAX Addr, Val, MMO.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineInstrBuilder buildInstr(unsigned Opcode)
Build and insert <empty> = Opcode <empty>.
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:148
MachineInstrBuilder buildZExt(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_ZEXT Op.
This is an important base class in LLVM.
Definition: Constant.h:41
MachineInstrBuilder buildBuildVector(const DstOp &Res, ArrayRef< Register > Ops)
Build and insert Res = G_BUILD_VECTOR Op0, ...
MachineInstrBuilder buildAtomicRMWXchg(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_XCHG Addr, Val, MMO.
virtual void createdInstr(MachineInstr &MI)=0
An instruction has been created and inserted into the function.
ConstantFP - Floating Point Values [float, double].
Definition: Constants.h:263
void setInstr(MachineInstr &MI)
Set the insertion point to before MI.
bool isValid() const
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:732
MachineInstrBuilder buildGlobalValue(const DstOp &Res, const GlobalValue *GV)
Build and insert Res = G_GLOBAL_VALUE GV.
MachineInstrBuilder buildFIDbgValue(int FI, const MDNode *Variable, const MDNode *Expr)
Build and insert a DBG_VALUE instruction expressing the fact that the associated Variable lives in th...
unsigned getAddressSpace() const
Return the address space of the Pointer type.
Definition: DerivedTypes.h:572
DebugLoc DL
Debug location to be set to any instruction we create.
self_iterator getIterator()
Definition: ilist_node.h:81
unsigned getAddressSpace() const
MachineInstrBuilder buildGEP(const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1)
Build and insert Res = G_GEP Op0, Op1.
const MachineInstrBuilder & addFrameIndex(int Idx) const
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function. ...
Definition: Function.cpp:205
MachineInstrBuilder buildCopy(const DstOp &Res, const SrcOp &Op)
Build and insert Res = COPY Op.
MachineInstrBuilder buildTrunc(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_TRUNC Op.
static wasm::ValType getType(const TargetRegisterClass *RC)
MachineInstrBuilder buildAtomicRMWAdd(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_ADD Addr, Val, MMO.
MachineInstrBuilder buildBuildVectorTrunc(const DstOp &Res, ArrayRef< Register > Ops)
Build and insert Res = G_BUILD_VECTOR_TRUNC Op0, ...
MachineInstrBuilder buildIntrinsic(Intrinsic::ID ID, ArrayRef< Register > Res, bool HasSideEffects)
Build and insert either a G_INTRINSIC (if HasSideEffects is false) or G_INTRINSIC_W_SIDE_EFFECTS inst...
const APFloat & getValueAPF() const
Definition: Constants.h:302
MachineInstrBuilder buildBr(MachineBasicBlock &Dest)
Build and insert G_BR Dest.
MachineInstrBuilder buildConstDbgValue(const Constant &C, const MDNode *Variable, const MDNode *Expr)
Build and insert a DBG_VALUE instructions specifying that Variable is given by C (suitably modified b...
static IntegerType * get(LLVMContext &C, unsigned NumBits)
This static method is the primary way of constructing an IntegerType.
Definition: Type.cpp:239
MachineInstrBuilder buildLoad(const DstOp &Res, const SrcOp &Addr, MachineMemOperand &MMO)
Build and insert Res = G_LOAD Addr, MMO.
MachineInstrBuilder buildICmp(CmpInst::Predicate Pred, const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1)
Build and insert a Res = G_ICMP Pred, Op0, Op1.
This is the shared class of boolean and integer constants.
Definition: Constants.h:83
MachineInstrBuilder buildAtomicRMWSub(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_SUB Addr, Val, MMO.
virtual MachineInstrBuilder buildFConstant(const DstOp &Res, const ConstantFP &Val)
Build and insert Res = G_FCONSTANT Val.
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:837
MachineInstrBuilder buildFrameIndex(const DstOp &Res, int Idx)
Build and insert Res = G_FRAME_INDEX Idx.
iterator end() const
Definition: ArrayRef.h:137
unsigned getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
MachineInstrBuilder buildAtomicRMWOr(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_OR Addr, Val, MMO.
MachineInstrBuilder buildAtomicRMWUmin(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_UMIN Addr, Val, MMO.
const TargetInstrInfo & getTII()
static Constant * get(Type *Ty, uint64_t V, bool isSigned=false)
If Ty is a vector type, return a Constant with a splat of the given value.
Definition: Constants.cpp:643
MachineInstrBuilder buildSelect(const DstOp &Res, const SrcOp &Tst, const SrcOp &Op0, const SrcOp &Op1)
Build and insert a Res = G_SELECT Tst, Op0, Op1.
LegalityPredicate isScalar(unsigned TypeIdx)
True iff the specified type index is a scalar.
static Constant * get(Type *Ty, double V)
This returns a ConstantFP, or a vector containing a splat of a ConstantFP, for the specified value in...
Definition: Constants.cpp:706
MachineInstrBuilder buildPtrMask(const DstOp &Res, const SrcOp &Op0, uint32_t NumBits)
Build and insert Res = G_PTR_MASK Op0, NumBits.
LLT getLLTTy(const MachineRegisterInfo &MRI) const
const Function & getFunction() const
Return the LLVM function that this machine code represents.
void setCSEInfo(GISelCSEInfo *Info)
This file declares the MachineIRBuilder class.
MachineInstrBuilder buildInsertVectorElement(const DstOp &Res, const SrcOp &Val, const SrcOp &Elt, const SrcOp &Idx)
Build and insert Res = G_INSERT_VECTOR_ELT Val, Elt, Idx.
bool isIntPredicate() const
Definition: InstrTypes.h:825
Class for arbitrary precision integers.
Definition: APInt.h:69
Register getReg() const
MachineInstrBuilder buildAtomicCmpXchgWithSuccess(Register OldValRes, Register SuccessRes, Register Addr, Register CmpVal, Register NewVal, MachineMemOperand &MMO)
Build and insert OldValRes<def>, SuccessRes<def> = G_ATOMIC_CMPXCHG_WITH_SUCCESS Addr, CmpVal, NewVal, MMO.
unsigned getBoolExtOp(bool IsVec, bool IsFP) const
LLT getLLTTy(const MachineRegisterInfo &MRI) const
bool isPointer() const
MachineInstrBuilder buildAtomicRMWAnd(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_AND Addr, Val, MMO.
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:256
MachineInstrBuilder buildAtomicRMWNand(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_NAND Addr, Val, MMO.
Representation of each machine instruction.
Definition: MachineInstr.h:64
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
MachineInstrBuilder buildFCmp(CmpInst::Predicate Pred, const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1)
Build and insert a Res = G_FCMP PredOp0, Op1.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
MachineInstrBuilder buildIndirectDbgValue(Register Reg, const MDNode *Variable, const MDNode *Expr)
Build and insert a DBG_VALUE instruction expressing the fact that the associated Variable lives in me...
const MachineBasicBlock & getMBB() const
Getter for the basic block we currently build.
MachineInstrBuilder buildBoolExt(const DstOp &Res, const SrcOp &Op, bool IsFP)
void setMBB(MachineBasicBlock &MBB)
Set the insertion point to the end of MBB.
#define I(x, y, z)
Definition: MD5.cpp:58
MachineInstrBuilder buildStore(const SrcOp &Val, const SrcOp &Addr, MachineMemOperand &MMO)
Build and insert G_STORE Val, Addr, MMO.
MachineInstrBuilder buildAtomicRMWMin(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_MIN Addr, Val, MMO.
const MachineInstrBuilder & addJumpTableIndex(unsigned Idx, unsigned char TargetFlags=0) const
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
MachineInstrBuilder buildAtomicRMW(unsigned Opcode, Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_<Opcode> Addr, Val, MMO.
MachineInstrBuilder insertInstr(MachineInstrBuilder MIB)
Insert an existing instruction at the insertion point.
LLVM Value Representation.
Definition: Value.h:72
uint16_t getNumElements() const
Returns the number of elements in a vector LLT.
MachineInstrBuilder buildMerge(const DstOp &Res, ArrayRef< Register > Ops)
Build and insert Res = G_MERGE_VALUES Op0, ...
IRTranslator LLVM IR MI
const MachineInstrBuilder & addDef(unsigned RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register definition operand.
MachineInstrBuilder buildUndef(const DstOp &Res)
Build and insert Res = IMPLICIT_DEF.
Register createGenericVirtualRegister(LLT Ty, StringRef Name="")
Create and return a new generic virtual register with low-level type Ty.
MachineFunction * MF
MachineFunction under construction.
MachineInstrBuilder buildConcatVectors(const DstOp &Res, ArrayRef< Register > Ops)
Build and insert Res = G_CONCAT_VECTORS Op0, ...
MachineInstrBuilder buildSplatVector(const DstOp &Res, const SrcOp &Src)
Build and insert Res = G_BUILD_VECTOR with Src replicated to fill the number of elements.
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned char TargetFlags=0) const
const DebugLoc & getDL()
Getter for DebugLoc.
MachineInstrBuilder buildAtomicCmpXchg(Register OldValRes, Register Addr, Register CmpVal, Register NewVal, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMIC_CMPXCHG Addr, CmpVal, NewVal, MMO.
PointerType * getType() const
Global values are always pointers.
Definition: GlobalValue.h:277
Wrapper class representing virtual and physical registers.
Definition: Register.h:18
bool empty() const
empty - Check if the array is empty.
Definition: ArrayRef.h:143
This file describes how to lower LLVM code to machine code.
MachineRegisterInfo * MRI
Information used to verify types are consistent and to create virtual registers.