LLVM  10.0.0svn
MachineIRBuilder.cpp
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1 //===-- llvm/CodeGen/GlobalISel/MachineIRBuilder.cpp - MIBuilder--*- C++ -*-==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 /// This file implements the MachineIRBuidler class.
10 //===----------------------------------------------------------------------===//
13 
22 #include "llvm/IR/DebugInfo.h"
23 
24 using namespace llvm;
25 
27  State.MF = &MF;
28  State.MBB = nullptr;
29  State.MRI = &MF.getRegInfo();
30  State.TII = MF.getSubtarget().getInstrInfo();
31  State.DL = DebugLoc();
33  State.Observer = nullptr;
34 }
35 
37  State.MBB = &MBB;
38  State.II = MBB.end();
39  assert(&getMF() == MBB.getParent() &&
40  "Basic block is in a different function");
41 }
42 
44  assert(MI.getParent() && "Instruction is not part of a basic block");
45  setMBB(*MI.getParent());
46  State.II = MI.getIterator();
47 }
48 
50 
53  assert(MBB.getParent() == &getMF() &&
54  "Basic block is in a different function");
55  State.MBB = &MBB;
56  State.II = II;
57 }
58 
59 void MachineIRBuilder::recordInsertion(MachineInstr *InsertedInstr) const {
60  if (State.Observer)
61  State.Observer->createdInstr(*InsertedInstr);
62 }
63 
65  State.Observer = &Observer;
66 }
67 
69 
70 //------------------------------------------------------------------------------
71 // Build instruction variants.
72 //------------------------------------------------------------------------------
73 
75  return insertInstr(buildInstrNoInsert(Opcode));
76 }
77 
79  MachineInstrBuilder MIB = BuildMI(getMF(), getDL(), getTII().get(Opcode));
80  return MIB;
81 }
82 
84  getMBB().insert(getInsertPt(), MIB);
85  recordInsertion(MIB);
86  return MIB;
87 }
88 
91  const MDNode *Expr) {
92  assert(isa<DILocalVariable>(Variable) && "not a variable");
93  assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
94  assert(
95  cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(getDL()) &&
96  "Expected inlined-at fields to agree");
97  return insertInstr(BuildMI(getMF(), getDL(),
98  getTII().get(TargetOpcode::DBG_VALUE),
99  /*IsIndirect*/ false, Reg, Variable, Expr));
100 }
101 
104  const MDNode *Expr) {
105  assert(isa<DILocalVariable>(Variable) && "not a variable");
106  assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
107  assert(
108  cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(getDL()) &&
109  "Expected inlined-at fields to agree");
110  return insertInstr(BuildMI(getMF(), getDL(),
111  getTII().get(TargetOpcode::DBG_VALUE),
112  /*IsIndirect*/ true, Reg, Variable, Expr));
113 }
114 
116  const MDNode *Variable,
117  const MDNode *Expr) {
118  assert(isa<DILocalVariable>(Variable) && "not a variable");
119  assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
120  assert(
121  cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(getDL()) &&
122  "Expected inlined-at fields to agree");
123  return buildInstr(TargetOpcode::DBG_VALUE)
124  .addFrameIndex(FI)
125  .addImm(0)
126  .addMetadata(Variable)
127  .addMetadata(Expr);
128 }
129 
131  const MDNode *Variable,
132  const MDNode *Expr) {
133  assert(isa<DILocalVariable>(Variable) && "not a variable");
134  assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
135  assert(
136  cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(getDL()) &&
137  "Expected inlined-at fields to agree");
138  auto MIB = buildInstr(TargetOpcode::DBG_VALUE);
139  if (auto *CI = dyn_cast<ConstantInt>(&C)) {
140  if (CI->getBitWidth() > 64)
141  MIB.addCImm(CI);
142  else
143  MIB.addImm(CI->getZExtValue());
144  } else if (auto *CFP = dyn_cast<ConstantFP>(&C)) {
145  MIB.addFPImm(CFP);
146  } else {
147  // Insert %noreg if we didn't find a usable constant and had to drop it.
148  MIB.addReg(0U);
149  }
150 
151  return MIB.addImm(0).addMetadata(Variable).addMetadata(Expr);
152 }
153 
155  assert(isa<DILabel>(Label) && "not a label");
156  assert(cast<DILabel>(Label)->isValidLocationForIntrinsic(State.DL) &&
157  "Expected inlined-at fields to agree");
158  auto MIB = buildInstr(TargetOpcode::DBG_LABEL);
159 
160  return MIB.addMetadata(Label);
161 }
162 
164  const SrcOp &Size,
165  unsigned Align) {
166  assert(Res.getLLTTy(*getMRI()).isPointer() && "expected ptr dst type");
167  auto MIB = buildInstr(TargetOpcode::G_DYN_STACKALLOC);
168  Res.addDefToMIB(*getMRI(), MIB);
169  Size.addSrcToMIB(MIB);
170  MIB.addImm(Align);
171  return MIB;
172 }
173 
175  int Idx) {
176  assert(Res.getLLTTy(*getMRI()).isPointer() && "invalid operand type");
177  auto MIB = buildInstr(TargetOpcode::G_FRAME_INDEX);
178  Res.addDefToMIB(*getMRI(), MIB);
179  MIB.addFrameIndex(Idx);
180  return MIB;
181 }
182 
184  const GlobalValue *GV) {
185  assert(Res.getLLTTy(*getMRI()).isPointer() && "invalid operand type");
187  GV->getType()->getAddressSpace() &&
188  "address space mismatch");
189 
190  auto MIB = buildInstr(TargetOpcode::G_GLOBAL_VALUE);
191  Res.addDefToMIB(*getMRI(), MIB);
192  MIB.addGlobalAddress(GV);
193  return MIB;
194 }
195 
197  unsigned JTI) {
198  return buildInstr(TargetOpcode::G_JUMP_TABLE, {PtrTy}, {})
199  .addJumpTableIndex(JTI);
200 }
201 
202 void MachineIRBuilder::validateBinaryOp(const LLT &Res, const LLT &Op0,
203  const LLT &Op1) {
204  assert((Res.isScalar() || Res.isVector()) && "invalid operand type");
205  assert((Res == Op0 && Res == Op1) && "type mismatch");
206 }
207 
208 void MachineIRBuilder::validateShiftOp(const LLT &Res, const LLT &Op0,
209  const LLT &Op1) {
210  assert((Res.isScalar() || Res.isVector()) && "invalid operand type");
211  assert((Res == Op0) && "type mismatch");
212 }
213 
215  const SrcOp &Op0,
216  const SrcOp &Op1) {
217  assert(Res.getLLTTy(*getMRI()).isPointer() &&
218  Res.getLLTTy(*getMRI()) == Op0.getLLTTy(*getMRI()) && "type mismatch");
219  assert(Op1.getLLTTy(*getMRI()).isScalar() && "invalid offset type");
220 
221  return buildInstr(TargetOpcode::G_GEP, {Res}, {Op0, Op1});
222 }
223 
226  const LLT &ValueTy, uint64_t Value) {
227  assert(Res == 0 && "Res is a result argument");
228  assert(ValueTy.isScalar() && "invalid offset type");
229 
230  if (Value == 0) {
231  Res = Op0;
232  return None;
233  }
234 
236  auto Cst = buildConstant(ValueTy, Value);
237  return buildGEP(Res, Op0, Cst.getReg(0));
238 }
239 
241  const SrcOp &Op0,
242  uint32_t NumBits) {
243  assert(Res.getLLTTy(*getMRI()).isPointer() &&
244  Res.getLLTTy(*getMRI()) == Op0.getLLTTy(*getMRI()) && "type mismatch");
245 
246  auto MIB = buildInstr(TargetOpcode::G_PTR_MASK);
247  Res.addDefToMIB(*getMRI(), MIB);
248  Op0.addSrcToMIB(MIB);
249  MIB.addImm(NumBits);
250  return MIB;
251 }
252 
254  return buildInstr(TargetOpcode::G_BR).addMBB(&Dest);
255 }
256 
258  assert(getMRI()->getType(Tgt).isPointer() && "invalid branch destination");
259  return buildInstr(TargetOpcode::G_BRINDIRECT).addUse(Tgt);
260 }
261 
263  unsigned JTI,
264  Register IndexReg) {
265  assert(getMRI()->getType(TablePtr).isPointer() &&
266  "Table reg must be a pointer");
267  return buildInstr(TargetOpcode::G_BRJT)
268  .addUse(TablePtr)
269  .addJumpTableIndex(JTI)
270  .addUse(IndexReg);
271 }
272 
274  const SrcOp &Op) {
275  return buildInstr(TargetOpcode::COPY, Res, Op);
276 }
277 
279  const ConstantInt &Val) {
280  LLT Ty = Res.getLLTTy(*getMRI());
281  LLT EltTy = Ty.getScalarType();
282  assert(EltTy.getScalarSizeInBits() == Val.getBitWidth() &&
283  "creating constant with the wrong size");
284 
285  if (Ty.isVector()) {
286  auto Const = buildInstr(TargetOpcode::G_CONSTANT)
287  .addDef(getMRI()->createGenericVirtualRegister(EltTy))
288  .addCImm(&Val);
289  return buildSplatVector(Res, Const);
290  }
291 
292  auto Const = buildInstr(TargetOpcode::G_CONSTANT);
293  Res.addDefToMIB(*getMRI(), Const);
294  Const.addCImm(&Val);
295  return Const;
296 }
297 
299  int64_t Val) {
300  auto IntN = IntegerType::get(getMF().getFunction().getContext(),
302  ConstantInt *CI = ConstantInt::get(IntN, Val, true);
303  return buildConstant(Res, *CI);
304 }
305 
307  const ConstantFP &Val) {
308  LLT Ty = Res.getLLTTy(*getMRI());
309  LLT EltTy = Ty.getScalarType();
310 
312  == EltTy.getSizeInBits() &&
313  "creating fconstant with the wrong size");
314 
315  assert(!Ty.isPointer() && "invalid operand type");
316 
317  if (Ty.isVector()) {
318  auto Const = buildInstr(TargetOpcode::G_FCONSTANT)
319  .addDef(getMRI()->createGenericVirtualRegister(EltTy))
320  .addFPImm(&Val);
321 
322  return buildSplatVector(Res, Const);
323  }
324 
325  auto Const = buildInstr(TargetOpcode::G_FCONSTANT);
326  Res.addDefToMIB(*getMRI(), Const);
327  Const.addFPImm(&Val);
328  return Const;
329 }
330 
332  const APInt &Val) {
333  ConstantInt *CI = ConstantInt::get(getMF().getFunction().getContext(), Val);
334  return buildConstant(Res, *CI);
335 }
336 
338  double Val) {
339  LLT DstTy = Res.getLLTTy(*getMRI());
340  auto &Ctx = getMF().getFunction().getContext();
341  auto *CFP =
343  return buildFConstant(Res, *CFP);
344 }
345 
347  const APFloat &Val) {
348  auto &Ctx = getMF().getFunction().getContext();
349  auto *CFP = ConstantFP::get(Ctx, Val);
350  return buildFConstant(Res, *CFP);
351 }
352 
354  MachineBasicBlock &Dest) {
355  assert(getMRI()->getType(Tst).isScalar() && "invalid operand type");
356 
357  return buildInstr(TargetOpcode::G_BRCOND).addUse(Tst).addMBB(&Dest);
358 }
359 
361  const SrcOp &Addr,
362  MachineMemOperand &MMO) {
363  return buildLoadInstr(TargetOpcode::G_LOAD, Res, Addr, MMO);
364 }
365 
367  const DstOp &Res,
368  const SrcOp &Addr,
369  MachineMemOperand &MMO) {
370  assert(Res.getLLTTy(*getMRI()).isValid() && "invalid operand type");
371  assert(Addr.getLLTTy(*getMRI()).isPointer() && "invalid operand type");
372 
373  auto MIB = buildInstr(Opcode);
374  Res.addDefToMIB(*getMRI(), MIB);
375  Addr.addSrcToMIB(MIB);
376  MIB.addMemOperand(&MMO);
377  return MIB;
378 }
379 
381  const SrcOp &Addr,
382  MachineMemOperand &MMO) {
383  assert(Val.getLLTTy(*getMRI()).isValid() && "invalid operand type");
384  assert(Addr.getLLTTy(*getMRI()).isPointer() && "invalid operand type");
385 
386  auto MIB = buildInstr(TargetOpcode::G_STORE);
387  Val.addSrcToMIB(MIB);
388  Addr.addSrcToMIB(MIB);
389  MIB.addMemOperand(&MMO);
390  return MIB;
391 }
392 
394  const DstOp &CarryOut,
395  const SrcOp &Op0,
396  const SrcOp &Op1) {
397  return buildInstr(TargetOpcode::G_UADDO, {Res, CarryOut}, {Op0, Op1});
398 }
399 
401  const DstOp &CarryOut,
402  const SrcOp &Op0,
403  const SrcOp &Op1,
404  const SrcOp &CarryIn) {
405  return buildInstr(TargetOpcode::G_UADDE, {Res, CarryOut},
406  {Op0, Op1, CarryIn});
407 }
408 
410  const SrcOp &Op) {
411  return buildInstr(TargetOpcode::G_ANYEXT, Res, Op);
412 }
413 
415  const SrcOp &Op) {
416  return buildInstr(TargetOpcode::G_SEXT, Res, Op);
417 }
418 
420  const SrcOp &Op) {
421  return buildInstr(TargetOpcode::G_ZEXT, Res, Op);
422 }
423 
424 unsigned MachineIRBuilder::getBoolExtOp(bool IsVec, bool IsFP) const {
425  const auto *TLI = getMF().getSubtarget().getTargetLowering();
426  switch (TLI->getBooleanContents(IsVec, IsFP)) {
428  return TargetOpcode::G_SEXT;
430  return TargetOpcode::G_ZEXT;
431  default:
432  return TargetOpcode::G_ANYEXT;
433  }
434 }
435 
437  const SrcOp &Op,
438  bool IsFP) {
439  unsigned ExtOp = getBoolExtOp(getMRI()->getType(Op.getReg()).isVector(), IsFP);
440  return buildInstr(ExtOp, Res, Op);
441 }
442 
444  const DstOp &Res,
445  const SrcOp &Op) {
446  assert((TargetOpcode::G_ANYEXT == ExtOpc || TargetOpcode::G_ZEXT == ExtOpc ||
447  TargetOpcode::G_SEXT == ExtOpc) &&
448  "Expecting Extending Opc");
449  assert(Res.getLLTTy(*getMRI()).isScalar() ||
450  Res.getLLTTy(*getMRI()).isVector());
451  assert(Res.getLLTTy(*getMRI()).isScalar() ==
452  Op.getLLTTy(*getMRI()).isScalar());
453 
454  unsigned Opcode = TargetOpcode::COPY;
455  if (Res.getLLTTy(*getMRI()).getSizeInBits() >
456  Op.getLLTTy(*getMRI()).getSizeInBits())
457  Opcode = ExtOpc;
458  else if (Res.getLLTTy(*getMRI()).getSizeInBits() <
459  Op.getLLTTy(*getMRI()).getSizeInBits())
460  Opcode = TargetOpcode::G_TRUNC;
461  else
462  assert(Res.getLLTTy(*getMRI()) == Op.getLLTTy(*getMRI()));
463 
464  return buildInstr(Opcode, Res, Op);
465 }
466 
468  const SrcOp &Op) {
469  return buildExtOrTrunc(TargetOpcode::G_SEXT, Res, Op);
470 }
471 
473  const SrcOp &Op) {
474  return buildExtOrTrunc(TargetOpcode::G_ZEXT, Res, Op);
475 }
476 
478  const SrcOp &Op) {
479  return buildExtOrTrunc(TargetOpcode::G_ANYEXT, Res, Op);
480 }
481 
483  const SrcOp &Src) {
484  LLT SrcTy = Src.getLLTTy(*getMRI());
485  LLT DstTy = Dst.getLLTTy(*getMRI());
486  if (SrcTy == DstTy)
487  return buildCopy(Dst, Src);
488 
489  unsigned Opcode;
490  if (SrcTy.isPointer() && DstTy.isScalar())
491  Opcode = TargetOpcode::G_PTRTOINT;
492  else if (DstTy.isPointer() && SrcTy.isScalar())
493  Opcode = TargetOpcode::G_INTTOPTR;
494  else {
495  assert(!SrcTy.isPointer() && !DstTy.isPointer() && "n G_ADDRCAST yet");
496  Opcode = TargetOpcode::G_BITCAST;
497  }
498 
499  return buildInstr(Opcode, Dst, Src);
500 }
501 
503  const SrcOp &Src,
504  uint64_t Index) {
505  LLT SrcTy = Src.getLLTTy(*getMRI());
506  LLT DstTy = Dst.getLLTTy(*getMRI());
507 
508 #ifndef NDEBUG
509  assert(SrcTy.isValid() && "invalid operand type");
510  assert(DstTy.isValid() && "invalid operand type");
511  assert(Index + DstTy.getSizeInBits() <= SrcTy.getSizeInBits() &&
512  "extracting off end of register");
513 #endif
514 
515  if (DstTy.getSizeInBits() == SrcTy.getSizeInBits()) {
516  assert(Index == 0 && "insertion past the end of a register");
517  return buildCast(Dst, Src);
518  }
519 
520  auto Extract = buildInstr(TargetOpcode::G_EXTRACT);
521  Dst.addDefToMIB(*getMRI(), Extract);
522  Src.addSrcToMIB(Extract);
523  Extract.addImm(Index);
524  return Extract;
525 }
526 
528  ArrayRef<uint64_t> Indices) {
529 #ifndef NDEBUG
530  assert(Ops.size() == Indices.size() && "incompatible args");
531  assert(!Ops.empty() && "invalid trivial sequence");
532  assert(std::is_sorted(Indices.begin(), Indices.end()) &&
533  "sequence offsets must be in ascending order");
534 
535  assert(getMRI()->getType(Res).isValid() && "invalid operand type");
536  for (auto Op : Ops)
537  assert(getMRI()->getType(Op).isValid() && "invalid operand type");
538 #endif
539 
540  LLT ResTy = getMRI()->getType(Res);
541  LLT OpTy = getMRI()->getType(Ops[0]);
542  unsigned OpSize = OpTy.getSizeInBits();
543  bool MaybeMerge = true;
544  for (unsigned i = 0; i < Ops.size(); ++i) {
545  if (getMRI()->getType(Ops[i]) != OpTy || Indices[i] != i * OpSize) {
546  MaybeMerge = false;
547  break;
548  }
549  }
550 
551  if (MaybeMerge && Ops.size() * OpSize == ResTy.getSizeInBits()) {
552  buildMerge(Res, Ops);
553  return;
554  }
555 
556  Register ResIn = getMRI()->createGenericVirtualRegister(ResTy);
557  buildUndef(ResIn);
558 
559  for (unsigned i = 0; i < Ops.size(); ++i) {
560  Register ResOut = i + 1 == Ops.size()
561  ? Res
563  buildInsert(ResOut, ResIn, Ops[i], Indices[i]);
564  ResIn = ResOut;
565  }
566 }
567 
569  return buildInstr(TargetOpcode::G_IMPLICIT_DEF, {Res}, {});
570 }
571 
573  ArrayRef<Register> Ops) {
574  // Unfortunately to convert from ArrayRef<LLT> to ArrayRef<SrcOp>,
575  // we need some temporary storage for the DstOp objects. Here we use a
576  // sufficiently large SmallVector to not go through the heap.
577  SmallVector<SrcOp, 8> TmpVec(Ops.begin(), Ops.end());
578  assert(TmpVec.size() > 1);
579  return buildInstr(TargetOpcode::G_MERGE_VALUES, Res, TmpVec);
580 }
581 
583  const SrcOp &Op) {
584  // Unfortunately to convert from ArrayRef<LLT> to ArrayRef<DstOp>,
585  // we need some temporary storage for the DstOp objects. Here we use a
586  // sufficiently large SmallVector to not go through the heap.
587  SmallVector<DstOp, 8> TmpVec(Res.begin(), Res.end());
588  assert(TmpVec.size() > 1);
589  return buildInstr(TargetOpcode::G_UNMERGE_VALUES, TmpVec, Op);
590 }
591 
593  const SrcOp &Op) {
594  unsigned NumReg = Op.getLLTTy(*getMRI()).getSizeInBits() / Res.getSizeInBits();
596  for (unsigned I = 0; I != NumReg; ++I)
597  TmpVec.push_back(getMRI()->createGenericVirtualRegister(Res));
598  return buildUnmerge(TmpVec, Op);
599 }
600 
602  const SrcOp &Op) {
603  // Unfortunately to convert from ArrayRef<Register> to ArrayRef<DstOp>,
604  // we need some temporary storage for the DstOp objects. Here we use a
605  // sufficiently large SmallVector to not go through the heap.
606  SmallVector<DstOp, 8> TmpVec(Res.begin(), Res.end());
607  assert(TmpVec.size() > 1);
608  return buildInstr(TargetOpcode::G_UNMERGE_VALUES, TmpVec, Op);
609 }
610 
612  ArrayRef<Register> Ops) {
613  // Unfortunately to convert from ArrayRef<Register> to ArrayRef<SrcOp>,
614  // we need some temporary storage for the DstOp objects. Here we use a
615  // sufficiently large SmallVector to not go through the heap.
616  SmallVector<SrcOp, 8> TmpVec(Ops.begin(), Ops.end());
617  return buildInstr(TargetOpcode::G_BUILD_VECTOR, Res, TmpVec);
618 }
619 
621  const SrcOp &Src) {
622  SmallVector<SrcOp, 8> TmpVec(Res.getLLTTy(*getMRI()).getNumElements(), Src);
623  return buildInstr(TargetOpcode::G_BUILD_VECTOR, Res, TmpVec);
624 }
625 
628  ArrayRef<Register> Ops) {
629  // Unfortunately to convert from ArrayRef<Register> to ArrayRef<SrcOp>,
630  // we need some temporary storage for the DstOp objects. Here we use a
631  // sufficiently large SmallVector to not go through the heap.
632  SmallVector<SrcOp, 8> TmpVec(Ops.begin(), Ops.end());
633  return buildInstr(TargetOpcode::G_BUILD_VECTOR_TRUNC, Res, TmpVec);
634 }
635 
638  // Unfortunately to convert from ArrayRef<Register> to ArrayRef<SrcOp>,
639  // we need some temporary storage for the DstOp objects. Here we use a
640  // sufficiently large SmallVector to not go through the heap.
641  SmallVector<SrcOp, 8> TmpVec(Ops.begin(), Ops.end());
642  return buildInstr(TargetOpcode::G_CONCAT_VECTORS, Res, TmpVec);
643 }
644 
646  Register Op, unsigned Index) {
647  assert(Index + getMRI()->getType(Op).getSizeInBits() <=
648  getMRI()->getType(Res).getSizeInBits() &&
649  "insertion past the end of a register");
650 
651  if (getMRI()->getType(Res).getSizeInBits() ==
652  getMRI()->getType(Op).getSizeInBits()) {
653  return buildCast(Res, Op);
654  }
655 
656  return buildInstr(TargetOpcode::G_INSERT)
657  .addDef(Res)
658  .addUse(Src)
659  .addUse(Op)
660  .addImm(Index);
661 }
662 
664  ArrayRef<Register> ResultRegs,
665  bool HasSideEffects) {
666  auto MIB =
667  buildInstr(HasSideEffects ? TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS
668  : TargetOpcode::G_INTRINSIC);
669  for (unsigned ResultReg : ResultRegs)
670  MIB.addDef(ResultReg);
671  MIB.addIntrinsicID(ID);
672  return MIB;
673 }
674 
677  bool HasSideEffects) {
678  auto MIB =
679  buildInstr(HasSideEffects ? TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS
680  : TargetOpcode::G_INTRINSIC);
681  for (DstOp Result : Results)
682  Result.addDefToMIB(*getMRI(), MIB);
683  MIB.addIntrinsicID(ID);
684  return MIB;
685 }
686 
688  const SrcOp &Op) {
689  return buildInstr(TargetOpcode::G_TRUNC, Res, Op);
690 }
691 
693  const SrcOp &Op) {
694  return buildInstr(TargetOpcode::G_FPTRUNC, Res, Op);
695 }
696 
698  const DstOp &Res,
699  const SrcOp &Op0,
700  const SrcOp &Op1) {
701  return buildInstr(TargetOpcode::G_ICMP, Res, {Pred, Op0, Op1});
702 }
703 
705  const DstOp &Res,
706  const SrcOp &Op0,
707  const SrcOp &Op1,
708  Optional<unsigned> Flags) {
709 
710  return buildInstr(TargetOpcode::G_FCMP, Res, {Pred, Op0, Op1}, Flags);
711 }
712 
714  const SrcOp &Tst,
715  const SrcOp &Op0,
716  const SrcOp &Op1,
717  Optional<unsigned> Flags) {
718 
719  return buildInstr(TargetOpcode::G_SELECT, {Res}, {Tst, Op0, Op1}, Flags);
720 }
721 
724  const SrcOp &Elt, const SrcOp &Idx) {
725  return buildInstr(TargetOpcode::G_INSERT_VECTOR_ELT, Res, {Val, Elt, Idx});
726 }
727 
730  const SrcOp &Idx) {
731  return buildInstr(TargetOpcode::G_EXTRACT_VECTOR_ELT, Res, {Val, Idx});
732 }
733 
735  Register OldValRes, Register SuccessRes, Register Addr, Register CmpVal,
736  Register NewVal, MachineMemOperand &MMO) {
737 #ifndef NDEBUG
738  LLT OldValResTy = getMRI()->getType(OldValRes);
739  LLT SuccessResTy = getMRI()->getType(SuccessRes);
740  LLT AddrTy = getMRI()->getType(Addr);
741  LLT CmpValTy = getMRI()->getType(CmpVal);
742  LLT NewValTy = getMRI()->getType(NewVal);
743  assert(OldValResTy.isScalar() && "invalid operand type");
744  assert(SuccessResTy.isScalar() && "invalid operand type");
745  assert(AddrTy.isPointer() && "invalid operand type");
746  assert(CmpValTy.isValid() && "invalid operand type");
747  assert(NewValTy.isValid() && "invalid operand type");
748  assert(OldValResTy == CmpValTy && "type mismatch");
749  assert(OldValResTy == NewValTy && "type mismatch");
750 #endif
751 
752  return buildInstr(TargetOpcode::G_ATOMIC_CMPXCHG_WITH_SUCCESS)
753  .addDef(OldValRes)
754  .addDef(SuccessRes)
755  .addUse(Addr)
756  .addUse(CmpVal)
757  .addUse(NewVal)
758  .addMemOperand(&MMO);
759 }
760 
763  Register CmpVal, Register NewVal,
764  MachineMemOperand &MMO) {
765 #ifndef NDEBUG
766  LLT OldValResTy = getMRI()->getType(OldValRes);
767  LLT AddrTy = getMRI()->getType(Addr);
768  LLT CmpValTy = getMRI()->getType(CmpVal);
769  LLT NewValTy = getMRI()->getType(NewVal);
770  assert(OldValResTy.isScalar() && "invalid operand type");
771  assert(AddrTy.isPointer() && "invalid operand type");
772  assert(CmpValTy.isValid() && "invalid operand type");
773  assert(NewValTy.isValid() && "invalid operand type");
774  assert(OldValResTy == CmpValTy && "type mismatch");
775  assert(OldValResTy == NewValTy && "type mismatch");
776 #endif
777 
778  return buildInstr(TargetOpcode::G_ATOMIC_CMPXCHG)
779  .addDef(OldValRes)
780  .addUse(Addr)
781  .addUse(CmpVal)
782  .addUse(NewVal)
783  .addMemOperand(&MMO);
784 }
785 
787  unsigned Opcode, const DstOp &OldValRes,
788  const SrcOp &Addr, const SrcOp &Val,
789  MachineMemOperand &MMO) {
790 
791 #ifndef NDEBUG
792  LLT OldValResTy = OldValRes.getLLTTy(*getMRI());
793  LLT AddrTy = Addr.getLLTTy(*getMRI());
794  LLT ValTy = Val.getLLTTy(*getMRI());
795  assert(OldValResTy.isScalar() && "invalid operand type");
796  assert(AddrTy.isPointer() && "invalid operand type");
797  assert(ValTy.isValid() && "invalid operand type");
798  assert(OldValResTy == ValTy && "type mismatch");
799  assert(MMO.isAtomic() && "not atomic mem operand");
800 #endif
801 
802  auto MIB = buildInstr(Opcode);
803  OldValRes.addDefToMIB(*getMRI(), MIB);
804  Addr.addSrcToMIB(MIB);
805  Val.addSrcToMIB(MIB);
806  MIB.addMemOperand(&MMO);
807  return MIB;
808 }
809 
812  Register Val, MachineMemOperand &MMO) {
813  return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_XCHG, OldValRes, Addr, Val,
814  MMO);
815 }
818  Register Val, MachineMemOperand &MMO) {
819  return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_ADD, OldValRes, Addr, Val,
820  MMO);
821 }
824  Register Val, MachineMemOperand &MMO) {
825  return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_SUB, OldValRes, Addr, Val,
826  MMO);
827 }
830  Register Val, MachineMemOperand &MMO) {
831  return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_AND, OldValRes, Addr, Val,
832  MMO);
833 }
836  Register Val, MachineMemOperand &MMO) {
837  return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_NAND, OldValRes, Addr, Val,
838  MMO);
839 }
841  Register Addr,
842  Register Val,
843  MachineMemOperand &MMO) {
844  return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_OR, OldValRes, Addr, Val,
845  MMO);
846 }
849  Register Val, MachineMemOperand &MMO) {
850  return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_XOR, OldValRes, Addr, Val,
851  MMO);
852 }
855  Register Val, MachineMemOperand &MMO) {
856  return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_MAX, OldValRes, Addr, Val,
857  MMO);
858 }
861  Register Val, MachineMemOperand &MMO) {
862  return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_MIN, OldValRes, Addr, Val,
863  MMO);
864 }
867  Register Val, MachineMemOperand &MMO) {
868  return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_UMAX, OldValRes, Addr, Val,
869  MMO);
870 }
873  Register Val, MachineMemOperand &MMO) {
874  return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_UMIN, OldValRes, Addr, Val,
875  MMO);
876 }
877 
880  const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val,
881  MachineMemOperand &MMO) {
882  return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_FADD, OldValRes, Addr, Val,
883  MMO);
884 }
885 
887 MachineIRBuilder::buildAtomicRMWFSub(const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val,
888  MachineMemOperand &MMO) {
889  return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_FSUB, OldValRes, Addr, Val,
890  MMO);
891 }
892 
894 MachineIRBuilder::buildFence(unsigned Ordering, unsigned Scope) {
895  return buildInstr(TargetOpcode::G_FENCE)
896  .addImm(Ordering)
897  .addImm(Scope);
898 }
899 
902 #ifndef NDEBUG
903  assert(getMRI()->getType(Res).isPointer() && "invalid res type");
904 #endif
905 
906  return buildInstr(TargetOpcode::G_BLOCK_ADDR).addDef(Res).addBlockAddress(BA);
907 }
908 
909 void MachineIRBuilder::validateTruncExt(const LLT &DstTy, const LLT &SrcTy,
910  bool IsExtend) {
911 #ifndef NDEBUG
912  if (DstTy.isVector()) {
913  assert(SrcTy.isVector() && "mismatched cast between vector and non-vector");
914  assert(SrcTy.getNumElements() == DstTy.getNumElements() &&
915  "different number of elements in a trunc/ext");
916  } else
917  assert(DstTy.isScalar() && SrcTy.isScalar() && "invalid extend/trunc");
918 
919  if (IsExtend)
920  assert(DstTy.getSizeInBits() > SrcTy.getSizeInBits() &&
921  "invalid narrowing extend");
922  else
923  assert(DstTy.getSizeInBits() < SrcTy.getSizeInBits() &&
924  "invalid widening trunc");
925 #endif
926 }
927 
928 void MachineIRBuilder::validateSelectOp(const LLT &ResTy, const LLT &TstTy,
929  const LLT &Op0Ty, const LLT &Op1Ty) {
930 #ifndef NDEBUG
931  assert((ResTy.isScalar() || ResTy.isVector() || ResTy.isPointer()) &&
932  "invalid operand type");
933  assert((ResTy == Op0Ty && ResTy == Op1Ty) && "type mismatch");
934  if (ResTy.isScalar() || ResTy.isPointer())
935  assert(TstTy.isScalar() && "type mismatch");
936  else
937  assert((TstTy.isScalar() ||
938  (TstTy.isVector() &&
939  TstTy.getNumElements() == Op0Ty.getNumElements())) &&
940  "type mismatch");
941 #endif
942 }
943 
945  ArrayRef<DstOp> DstOps,
946  ArrayRef<SrcOp> SrcOps,
947  Optional<unsigned> Flags) {
948  switch (Opc) {
949  default:
950  break;
951  case TargetOpcode::G_SELECT: {
952  assert(DstOps.size() == 1 && "Invalid select");
953  assert(SrcOps.size() == 3 && "Invalid select");
955  DstOps[0].getLLTTy(*getMRI()), SrcOps[0].getLLTTy(*getMRI()),
956  SrcOps[1].getLLTTy(*getMRI()), SrcOps[2].getLLTTy(*getMRI()));
957  break;
958  }
959  case TargetOpcode::G_ADD:
960  case TargetOpcode::G_AND:
961  case TargetOpcode::G_MUL:
962  case TargetOpcode::G_OR:
963  case TargetOpcode::G_SUB:
964  case TargetOpcode::G_XOR:
965  case TargetOpcode::G_UDIV:
966  case TargetOpcode::G_SDIV:
967  case TargetOpcode::G_UREM:
968  case TargetOpcode::G_SREM:
969  case TargetOpcode::G_SMIN:
970  case TargetOpcode::G_SMAX:
971  case TargetOpcode::G_UMIN:
972  case TargetOpcode::G_UMAX: {
973  // All these are binary ops.
974  assert(DstOps.size() == 1 && "Invalid Dst");
975  assert(SrcOps.size() == 2 && "Invalid Srcs");
976  validateBinaryOp(DstOps[0].getLLTTy(*getMRI()),
977  SrcOps[0].getLLTTy(*getMRI()),
978  SrcOps[1].getLLTTy(*getMRI()));
979  break;
980  }
981  case TargetOpcode::G_SHL:
982  case TargetOpcode::G_ASHR:
983  case TargetOpcode::G_LSHR: {
984  assert(DstOps.size() == 1 && "Invalid Dst");
985  assert(SrcOps.size() == 2 && "Invalid Srcs");
986  validateShiftOp(DstOps[0].getLLTTy(*getMRI()),
987  SrcOps[0].getLLTTy(*getMRI()),
988  SrcOps[1].getLLTTy(*getMRI()));
989  break;
990  }
991  case TargetOpcode::G_SEXT:
992  case TargetOpcode::G_ZEXT:
993  case TargetOpcode::G_ANYEXT:
994  assert(DstOps.size() == 1 && "Invalid Dst");
995  assert(SrcOps.size() == 1 && "Invalid Srcs");
996  validateTruncExt(DstOps[0].getLLTTy(*getMRI()),
997  SrcOps[0].getLLTTy(*getMRI()), true);
998  break;
999  case TargetOpcode::G_TRUNC:
1000  case TargetOpcode::G_FPTRUNC: {
1001  assert(DstOps.size() == 1 && "Invalid Dst");
1002  assert(SrcOps.size() == 1 && "Invalid Srcs");
1003  validateTruncExt(DstOps[0].getLLTTy(*getMRI()),
1004  SrcOps[0].getLLTTy(*getMRI()), false);
1005  break;
1006  }
1007  case TargetOpcode::COPY:
1008  assert(DstOps.size() == 1 && "Invalid Dst");
1009  // If the caller wants to add a subreg source it has to be done separately
1010  // so we may not have any SrcOps at this point yet.
1011  break;
1012  case TargetOpcode::G_FCMP:
1013  case TargetOpcode::G_ICMP: {
1014  assert(DstOps.size() == 1 && "Invalid Dst Operands");
1015  assert(SrcOps.size() == 3 && "Invalid Src Operands");
1016  // For F/ICMP, the first src operand is the predicate, followed by
1017  // the two comparands.
1018  assert(SrcOps[0].getSrcOpKind() == SrcOp::SrcType::Ty_Predicate &&
1019  "Expecting predicate");
1020  assert([&]() -> bool {
1021  CmpInst::Predicate Pred = SrcOps[0].getPredicate();
1022  return Opc == TargetOpcode::G_ICMP ? CmpInst::isIntPredicate(Pred)
1023  : CmpInst::isFPPredicate(Pred);
1024  }() && "Invalid predicate");
1025  assert(SrcOps[1].getLLTTy(*getMRI()) == SrcOps[2].getLLTTy(*getMRI()) &&
1026  "Type mismatch");
1027  assert([&]() -> bool {
1028  LLT Op0Ty = SrcOps[1].getLLTTy(*getMRI());
1029  LLT DstTy = DstOps[0].getLLTTy(*getMRI());
1030  if (Op0Ty.isScalar() || Op0Ty.isPointer())
1031  return DstTy.isScalar();
1032  else
1033  return DstTy.isVector() &&
1034  DstTy.getNumElements() == Op0Ty.getNumElements();
1035  }() && "Type Mismatch");
1036  break;
1037  }
1038  case TargetOpcode::G_UNMERGE_VALUES: {
1039  assert(!DstOps.empty() && "Invalid trivial sequence");
1040  assert(SrcOps.size() == 1 && "Invalid src for Unmerge");
1041  assert(std::all_of(DstOps.begin(), DstOps.end(),
1042  [&, this](const DstOp &Op) {
1043  return Op.getLLTTy(*getMRI()) ==
1044  DstOps[0].getLLTTy(*getMRI());
1045  }) &&
1046  "type mismatch in output list");
1047  assert(DstOps.size() * DstOps[0].getLLTTy(*getMRI()).getSizeInBits() ==
1048  SrcOps[0].getLLTTy(*getMRI()).getSizeInBits() &&
1049  "input operands do not cover output register");
1050  break;
1051  }
1052  case TargetOpcode::G_MERGE_VALUES: {
1053  assert(!SrcOps.empty() && "invalid trivial sequence");
1054  assert(DstOps.size() == 1 && "Invalid Dst");
1055  assert(std::all_of(SrcOps.begin(), SrcOps.end(),
1056  [&, this](const SrcOp &Op) {
1057  return Op.getLLTTy(*getMRI()) ==
1058  SrcOps[0].getLLTTy(*getMRI());
1059  }) &&
1060  "type mismatch in input list");
1061  assert(SrcOps.size() * SrcOps[0].getLLTTy(*getMRI()).getSizeInBits() ==
1062  DstOps[0].getLLTTy(*getMRI()).getSizeInBits() &&
1063  "input operands do not cover output register");
1064  if (SrcOps.size() == 1)
1065  return buildCast(DstOps[0], SrcOps[0]);
1066  if (DstOps[0].getLLTTy(*getMRI()).isVector())
1067  return buildInstr(TargetOpcode::G_CONCAT_VECTORS, DstOps, SrcOps);
1068  break;
1069  }
1070  case TargetOpcode::G_EXTRACT_VECTOR_ELT: {
1071  assert(DstOps.size() == 1 && "Invalid Dst size");
1072  assert(SrcOps.size() == 2 && "Invalid Src size");
1073  assert(SrcOps[0].getLLTTy(*getMRI()).isVector() && "Invalid operand type");
1074  assert((DstOps[0].getLLTTy(*getMRI()).isScalar() ||
1075  DstOps[0].getLLTTy(*getMRI()).isPointer()) &&
1076  "Invalid operand type");
1077  assert(SrcOps[1].getLLTTy(*getMRI()).isScalar() && "Invalid operand type");
1078  assert(SrcOps[0].getLLTTy(*getMRI()).getElementType() ==
1079  DstOps[0].getLLTTy(*getMRI()) &&
1080  "Type mismatch");
1081  break;
1082  }
1083  case TargetOpcode::G_INSERT_VECTOR_ELT: {
1084  assert(DstOps.size() == 1 && "Invalid dst size");
1085  assert(SrcOps.size() == 3 && "Invalid src size");
1086  assert(DstOps[0].getLLTTy(*getMRI()).isVector() &&
1087  SrcOps[0].getLLTTy(*getMRI()).isVector() && "Invalid operand type");
1088  assert(DstOps[0].getLLTTy(*getMRI()).getElementType() ==
1089  SrcOps[1].getLLTTy(*getMRI()) &&
1090  "Type mismatch");
1091  assert(SrcOps[2].getLLTTy(*getMRI()).isScalar() && "Invalid index");
1092  assert(DstOps[0].getLLTTy(*getMRI()).getNumElements() ==
1093  SrcOps[0].getLLTTy(*getMRI()).getNumElements() &&
1094  "Type mismatch");
1095  break;
1096  }
1097  case TargetOpcode::G_BUILD_VECTOR: {
1098  assert((!SrcOps.empty() || SrcOps.size() < 2) &&
1099  "Must have at least 2 operands");
1100  assert(DstOps.size() == 1 && "Invalid DstOps");
1101  assert(DstOps[0].getLLTTy(*getMRI()).isVector() &&
1102  "Res type must be a vector");
1103  assert(std::all_of(SrcOps.begin(), SrcOps.end(),
1104  [&, this](const SrcOp &Op) {
1105  return Op.getLLTTy(*getMRI()) ==
1106  SrcOps[0].getLLTTy(*getMRI());
1107  }) &&
1108  "type mismatch in input list");
1109  assert(SrcOps.size() * SrcOps[0].getLLTTy(*getMRI()).getSizeInBits() ==
1110  DstOps[0].getLLTTy(*getMRI()).getSizeInBits() &&
1111  "input scalars do not exactly cover the output vector register");
1112  break;
1113  }
1114  case TargetOpcode::G_BUILD_VECTOR_TRUNC: {
1115  assert((!SrcOps.empty() || SrcOps.size() < 2) &&
1116  "Must have at least 2 operands");
1117  assert(DstOps.size() == 1 && "Invalid DstOps");
1118  assert(DstOps[0].getLLTTy(*getMRI()).isVector() &&
1119  "Res type must be a vector");
1120  assert(std::all_of(SrcOps.begin(), SrcOps.end(),
1121  [&, this](const SrcOp &Op) {
1122  return Op.getLLTTy(*getMRI()) ==
1123  SrcOps[0].getLLTTy(*getMRI());
1124  }) &&
1125  "type mismatch in input list");
1126  if (SrcOps[0].getLLTTy(*getMRI()).getSizeInBits() ==
1127  DstOps[0].getLLTTy(*getMRI()).getElementType().getSizeInBits())
1128  return buildInstr(TargetOpcode::G_BUILD_VECTOR, DstOps, SrcOps);
1129  break;
1130  }
1131  case TargetOpcode::G_CONCAT_VECTORS: {
1132  assert(DstOps.size() == 1 && "Invalid DstOps");
1133  assert((!SrcOps.empty() || SrcOps.size() < 2) &&
1134  "Must have at least 2 operands");
1135  assert(std::all_of(SrcOps.begin(), SrcOps.end(),
1136  [&, this](const SrcOp &Op) {
1137  return (Op.getLLTTy(*getMRI()).isVector() &&
1138  Op.getLLTTy(*getMRI()) ==
1139  SrcOps[0].getLLTTy(*getMRI()));
1140  }) &&
1141  "type mismatch in input list");
1142  assert(SrcOps.size() * SrcOps[0].getLLTTy(*getMRI()).getSizeInBits() ==
1143  DstOps[0].getLLTTy(*getMRI()).getSizeInBits() &&
1144  "input vectors do not exactly cover the output vector register");
1145  break;
1146  }
1147  case TargetOpcode::G_UADDE: {
1148  assert(DstOps.size() == 2 && "Invalid no of dst operands");
1149  assert(SrcOps.size() == 3 && "Invalid no of src operands");
1150  assert(DstOps[0].getLLTTy(*getMRI()).isScalar() && "Invalid operand");
1151  assert((DstOps[0].getLLTTy(*getMRI()) == SrcOps[0].getLLTTy(*getMRI())) &&
1152  (DstOps[0].getLLTTy(*getMRI()) == SrcOps[1].getLLTTy(*getMRI())) &&
1153  "Invalid operand");
1154  assert(DstOps[1].getLLTTy(*getMRI()).isScalar() && "Invalid operand");
1155  assert(DstOps[1].getLLTTy(*getMRI()) == SrcOps[2].getLLTTy(*getMRI()) &&
1156  "type mismatch");
1157  break;
1158  }
1159  }
1160 
1161  auto MIB = buildInstr(Opc);
1162  for (const DstOp &Op : DstOps)
1163  Op.addDefToMIB(*getMRI(), MIB);
1164  for (const SrcOp &Op : SrcOps)
1165  Op.addSrcToMIB(MIB);
1166  if (Flags)
1167  MIB->setFlags(*Flags);
1168  return MIB;
1169 }
MachineInstrBuilder buildDirectDbgValue(Register Reg, const MDNode *Variable, const MDNode *Expr)
Build and insert a DBG_VALUE instruction expressing the fact that the associated Variable lives in Re...
bool isFPPredicate() const
Definition: InstrTypes.h:824
uint64_t CallInst * C
const MachineInstrBuilder & addMetadata(const MDNode *MD) const
virtual MachineInstrBuilder buildConstant(const DstOp &Res, const ConstantInt &Val)
Build and insert Res = G_CONSTANT Val.
MachineInstrBuilder buildAtomicRMWFAdd(const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_FADD Addr, Val, MMO.
MachineInstrBuilder buildJumpTable(const LLT PtrTy, unsigned JTI)
Build and insert Res = G_JUMP_TABLE JTI.
void addDefToMIB(MachineRegisterInfo &MRI, MachineInstrBuilder &MIB) const
The CSE Analysis object.
Definition: CSEInfo.h:71
MachineInstrBuilder buildZExtOrTrunc(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_ZEXT Op, Res = G_TRUNC Op, or Res = COPY Op depending on the differing sizes...
MachineInstrBuilder buildBlockAddress(Register Res, const BlockAddress *BA)
Build and insert Res = G_BLOCK_ADDR BA.
MachineInstrBuilder buildUnmerge(ArrayRef< LLT > Res, const SrcOp &Op)
Build and insert Res0, ...
MachineInstrBuilder buildBrCond(Register Tst, MachineBasicBlock &Dest)
Build and insert G_BRCOND Tst, Dest.
This class represents lattice values for constants.
Definition: AllocatorList.h:23
MachineInstrBuilder buildInsert(Register Res, Register Src, Register Op, unsigned Index)
MachineInstrBuilder buildSExtOrTrunc(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_SEXT Op, Res = G_TRUNC Op, or Res = COPY Op depending on the differing sizes...
iterator begin() const
Definition: ArrayRef.h:136
unsigned getScalarSizeInBits() const
unsigned getSizeInBits(Register Reg, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI) const
Get the size in bits of Reg.
bool isScalar() const
GISelChangeObserver * Observer
MachineInstrBuilder buildCast(const DstOp &Dst, const SrcOp &Src)
Build and insert an appropriate cast between two registers of equal size.
unsigned Reg
const MachineInstrBuilder & addJumpTableIndex(unsigned Idx, unsigned TargetFlags=0) const
virtual const TargetLowering * getTargetLowering() const
LLT getScalarType() const
Function Alias Analysis Results
LLT getType(unsigned Reg) const
Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register...
void addSrcToMIB(MachineInstrBuilder &MIB) const
static unsigned getSizeInBits(const fltSemantics &Sem)
Returns the size of the floating point number (in bits) in the given semantics.
Definition: APFloat.cpp:205
bool all_of(R &&range, UnaryPredicate P)
Provide wrappers to std::all_of which take ranges instead of having to pass begin/end explicitly...
Definition: STLExtras.h:1165
A debug info location.
Definition: DebugLoc.h:33
Metadata node.
Definition: Metadata.h:863
void buildSequence(Register Res, ArrayRef< Register > Ops, ArrayRef< uint64_t > Indices)
Build and insert instructions to put Ops together at the specified p Indices to form a larger registe...
const fltSemantics & getSemantics() const
Definition: APFloat.h:1170
MachineInstrBuilder buildAtomicRMW(unsigned Opcode, const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_<Opcode> Addr, Val, MMO.
MachineInstrBuilder buildDynStackAlloc(const DstOp &Res, const SrcOp &Size, unsigned Align)
Build and insert Res = G_DYN_STACKALLOC Size, Align.
void validateSelectOp(const LLT &ResTy, const LLT &TstTy, const LLT &Op0Ty, const LLT &Op1Ty)
MachineInstrBuilder buildUAddo(const DstOp &Res, const DstOp &CarryOut, const SrcOp &Op0, const SrcOp &Op1)
Build and insert Res, CarryOut = G_UADDO Op0, Op1.
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
unsigned getBitWidth() const
getBitWidth - Return the bitwidth of this constant.
Definition: Constants.h:142
LegalityPredicate isPointer(unsigned TypeIdx)
True iff the specified type index is a pointer (with any address space).
LegalityPredicate isVector(unsigned TypeIdx)
True iff the specified type index is a vector.
Optional< MachineInstrBuilder > materializeGEP(Register &Res, Register Op0, const LLT &ValueTy, uint64_t Value)
Materialize and insert Res = G_GEP Op0, (G_CONSTANT Value)
MachineInstrBuilder buildBrJT(Register TablePtr, unsigned JTI, Register IndexReg)
Build and insert G_BRJT TablePtr, JTI, IndexReg.
MachineInstrBuilder buildExtract(const DstOp &Res, const SrcOp &Src, uint64_t Index)
Build and insert `Res0, ...
bool isAtomic() const
Returns true if this operation has an atomic ordering requirement of unordered or higher...
MachineInstrBuilder buildAtomicRMWXor(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_XOR Addr, Val, MMO.
bool isVector() const
void setMF(MachineFunction &MF)
The address of a basic block.
Definition: Constants.h:839
A description of a memory reference used in the backend.
void setInsertPt(MachineBasicBlock &MBB, MachineBasicBlock::iterator II)
Set the insertion point before the specified position.
MachineInstrBuilder buildAnyExt(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_ANYEXT Op0.
MachineInstrBuilder buildExtOrTrunc(unsigned ExtOpc, const DstOp &Res, const SrcOp &Op)
Build and insert Res = ExtOpc, Res = G_TRUNC Op, or Res = COPY Op depending on the differing sizes of...
MachineInstrBuilder buildUAdde(const DstOp &Res, const DstOp &CarryOut, const SrcOp &Op0, const SrcOp &Op1, const SrcOp &CarryIn)
Build and insert Res, CarryOut = G_UADDE Op0, Op1, CarryIn.
void validateTruncExt(const LLT &Dst, const LLT &Src, bool IsExtend)
MachineInstrBuilder buildAnyExtOrTrunc(const DstOp &Res, const SrcOp &Op)
Res = COPY Op depending on the differing sizes of Res and Op.
MachineBasicBlock::iterator II
const MachineInstrBuilder & addDef(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register definition operand.
void recordInsertion(MachineInstr *MI) const
APFloat getAPFloatFromSize(double Val, unsigned Size)
Returns an APFloat from Val converted to the appropriate size.
Definition: Utils.cpp:306
MachineInstrBuilder buildLoadInstr(unsigned Opcode, const DstOp &Res, const SrcOp &Addr, MachineMemOperand &MMO)
Build and insert Res = <opcode> Addr, MMO.
MachineInstrBuilder buildFence(unsigned Ordering, unsigned Scope)
Build and insert G_FENCE Ordering, Scope.
MachineInstrBuilder buildBrIndirect(Register Tgt)
Build and insert G_BRINDIRECT Tgt.
MachineInstrBuilder buildSelect(const DstOp &Res, const SrcOp &Tst, const SrcOp &Op0, const SrcOp &Op1, Optional< unsigned > Flags=None)
Build and insert a Res = G_SELECT Tst, Op0, Op1.
MachineInstrBuilder buildInstrNoInsert(unsigned Opcode)
Build but don&#39;t insert <empty> = Opcode <empty>.
void validateBinaryOp(const LLT &Res, const LLT &Op0, const LLT &Op1)
MachineFunction & getMF()
Getter for the function we currently build.
const MachineInstrBuilder & addFPImm(const ConstantFP *Val) const
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:32
virtual const TargetInstrInfo * getInstrInfo() const
MachineInstrBuilder buildAtomicRMWUmax(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_UMAX Addr, Val, MMO.
static Function * getFunction(Constant *C)
Definition: Evaluator.cpp:258
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
MachineInstrBuilder buildAtomicRMWFSub(const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_FSUB Addr, Val, MMO.
MachineInstrBuilder buildExtractVectorElement(const DstOp &Res, const SrcOp &Val, const SrcOp &Idx)
Build and insert Res = G_EXTRACT_VECTOR_ELT Val, Idx.
Analysis containing CSE Info
Definition: CSEInfo.cpp:20
void setChangeObserver(GISelChangeObserver &Observer)
MachineBasicBlock::iterator getInsertPt()
Current insertion point for new instructions.
MachineInstrBuilder buildDbgLabel(const MDNode *Label)
Build and insert a DBG_LABEL instructions specifying that Label is given.
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
const MachineInstrBuilder & addUse(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register use operand.
MachineInstrBundleIterator< MachineInstr > iterator
MachineInstrBuilder buildSExt(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_SEXT Op.
void validateShiftOp(const LLT &Res, const LLT &Op0, const LLT &Op1)
MachineRegisterInfo * getMRI()
Getter for MRI.
Abstract class that contains various methods for clients to notify about changes. ...
MachineInstrBuilder buildFPTrunc(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_FPTRUNC Op.
const TargetInstrInfo * TII
Information used to access the description of the opcodes.
const MachineInstrBuilder & addCImm(const ConstantInt *Val) const
MachineInstrBuilder buildAtomicRMWMax(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_MAX Addr, Val, MMO.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineInstrBuilder buildInstr(unsigned Opcode)
Build and insert <empty> = Opcode <empty>.
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:148
MachineInstrBuilder buildZExt(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_ZEXT Op.
This is an important base class in LLVM.
Definition: Constant.h:41
MachineInstrBuilder buildBuildVector(const DstOp &Res, ArrayRef< Register > Ops)
Build and insert Res = G_BUILD_VECTOR Op0, ...
MachineInstrBuilder buildAtomicRMWXchg(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_XCHG Addr, Val, MMO.
virtual void createdInstr(MachineInstr &MI)=0
An instruction has been created and inserted into the function.
ConstantFP - Floating Point Values [float, double].
Definition: Constants.h:263
void setInstr(MachineInstr &MI)
Set the insertion point to before MI.
bool isValid() const
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:732
MachineInstrBuilder buildGlobalValue(const DstOp &Res, const GlobalValue *GV)
Build and insert Res = G_GLOBAL_VALUE GV.
MachineInstrBuilder buildFIDbgValue(int FI, const MDNode *Variable, const MDNode *Expr)
Build and insert a DBG_VALUE instruction expressing the fact that the associated Variable lives in th...
unsigned getAddressSpace() const
Return the address space of the Pointer type.
Definition: DerivedTypes.h:572
DebugLoc DL
Debug location to be set to any instruction we create.
self_iterator getIterator()
Definition: ilist_node.h:81
unsigned getAddressSpace() const
MachineInstrBuilder buildGEP(const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1)
Build and insert Res = G_GEP Op0, Op1.
const MachineInstrBuilder & addFrameIndex(int Idx) const
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function. ...
Definition: Function.cpp:205
MachineInstrBuilder buildCopy(const DstOp &Res, const SrcOp &Op)
Build and insert Res = COPY Op.
MachineInstrBuilder buildTrunc(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_TRUNC Op.
static wasm::ValType getType(const TargetRegisterClass *RC)
MachineInstrBuilder buildAtomicRMWAdd(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_ADD Addr, Val, MMO.
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:40
MachineInstrBuilder buildBuildVectorTrunc(const DstOp &Res, ArrayRef< Register > Ops)
Build and insert Res = G_BUILD_VECTOR_TRUNC Op0, ...
MachineInstrBuilder buildIntrinsic(Intrinsic::ID ID, ArrayRef< Register > Res, bool HasSideEffects)
Build and insert either a G_INTRINSIC (if HasSideEffects is false) or G_INTRINSIC_W_SIDE_EFFECTS inst...
const APFloat & getValueAPF() const
Definition: Constants.h:302
MachineInstrBuilder buildBr(MachineBasicBlock &Dest)
Build and insert G_BR Dest.
MachineInstrBuilder buildConstDbgValue(const Constant &C, const MDNode *Variable, const MDNode *Expr)
Build and insert a DBG_VALUE instructions specifying that Variable is given by C (suitably modified b...
static IntegerType * get(LLVMContext &C, unsigned NumBits)
This static method is the primary way of constructing an IntegerType.
Definition: Type.cpp:239
MachineInstrBuilder buildLoad(const DstOp &Res, const SrcOp &Addr, MachineMemOperand &MMO)
Build and insert Res = G_LOAD Addr, MMO.
MachineInstrBuilder buildICmp(CmpInst::Predicate Pred, const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1)
Build and insert a Res = G_ICMP Pred, Op0, Op1.
This is the shared class of boolean and integer constants.
Definition: Constants.h:83
MachineInstrBuilder buildAtomicRMWSub(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_SUB Addr, Val, MMO.
virtual MachineInstrBuilder buildFConstant(const DstOp &Res, const ConstantFP &Val)
Build and insert Res = G_FCONSTANT Val.
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:837
MachineInstrBuilder buildFrameIndex(const DstOp &Res, int Idx)
Build and insert Res = G_FRAME_INDEX Idx.
iterator end() const
Definition: ArrayRef.h:137
unsigned getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
MachineInstrBuilder buildAtomicRMWOr(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_OR Addr, Val, MMO.
MachineInstrBuilder buildAtomicRMWUmin(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_UMIN Addr, Val, MMO.
const TargetInstrInfo & getTII()
static Constant * get(Type *Ty, uint64_t V, bool isSigned=false)
If Ty is a vector type, return a Constant with a splat of the given value.
Definition: Constants.cpp:653
LegalityPredicate isScalar(unsigned TypeIdx)
True iff the specified type index is a scalar.
static Constant * get(Type *Ty, double V)
This returns a ConstantFP, or a vector containing a splat of a ConstantFP, for the specified value in...
Definition: Constants.cpp:716
MachineInstrBuilder buildPtrMask(const DstOp &Res, const SrcOp &Op0, uint32_t NumBits)
Build and insert Res = G_PTR_MASK Op0, NumBits.
LLT getLLTTy(const MachineRegisterInfo &MRI) const
const Function & getFunction() const
Return the LLVM function that this machine code represents.
void setCSEInfo(GISelCSEInfo *Info)
This file declares the MachineIRBuilder class.
MachineInstrBuilder buildFCmp(CmpInst::Predicate Pred, const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1, Optional< unsigned > Flags=None)
Build and insert a Res = G_FCMP PredOp0, Op1.
MachineInstrBuilder buildInsertVectorElement(const DstOp &Res, const SrcOp &Val, const SrcOp &Elt, const SrcOp &Idx)
Build and insert Res = G_INSERT_VECTOR_ELT Val, Elt, Idx.
bool isIntPredicate() const
Definition: InstrTypes.h:825
Class for arbitrary precision integers.
Definition: APInt.h:69
Register getReg() const
MachineInstrBuilder buildAtomicCmpXchgWithSuccess(Register OldValRes, Register SuccessRes, Register Addr, Register CmpVal, Register NewVal, MachineMemOperand &MMO)
Build and insert OldValRes<def>, SuccessRes<def> = G_ATOMIC_CMPXCHG_WITH_SUCCESS Addr, CmpVal, NewVal, MMO.
unsigned getBoolExtOp(bool IsVec, bool IsFP) const
LLT getLLTTy(const MachineRegisterInfo &MRI) const
bool isPointer() const
MachineInstrBuilder buildAtomicRMWAnd(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_AND Addr, Val, MMO.
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:256
MachineInstrBuilder buildAtomicRMWNand(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_NAND Addr, Val, MMO.
Representation of each machine instruction.
Definition: MachineInstr.h:64
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
MachineInstrBuilder buildIndirectDbgValue(Register Reg, const MDNode *Variable, const MDNode *Expr)
Build and insert a DBG_VALUE instruction expressing the fact that the associated Variable lives in me...
const MachineBasicBlock & getMBB() const
Getter for the basic block we currently build.
MachineInstrBuilder buildBoolExt(const DstOp &Res, const SrcOp &Op, bool IsFP)
void setMBB(MachineBasicBlock &MBB)
Set the insertion point to the end of MBB.
#define I(x, y, z)
Definition: MD5.cpp:58
MachineInstrBuilder buildStore(const SrcOp &Val, const SrcOp &Addr, MachineMemOperand &MMO)
Build and insert G_STORE Val, Addr, MMO.
uint32_t Size
Definition: Profile.cpp:46
MachineInstrBuilder buildAtomicRMWMin(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_MIN Addr, Val, MMO.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
MachineInstrBuilder insertInstr(MachineInstrBuilder MIB)
Insert an existing instruction at the insertion point.
LLVM Value Representation.
Definition: Value.h:73
uint16_t getNumElements() const
Returns the number of elements in a vector LLT.
MachineInstrBuilder buildMerge(const DstOp &Res, ArrayRef< Register > Ops)
Build and insert Res = G_MERGE_VALUES Op0, ...
IRTranslator LLVM IR MI
MachineInstrBuilder buildUndef(const DstOp &Res)
Build and insert Res = IMPLICIT_DEF.
Register createGenericVirtualRegister(LLT Ty, StringRef Name="")
Create and return a new generic virtual register with low-level type Ty.
MachineFunction * MF
MachineFunction under construction.
MachineInstrBuilder buildConcatVectors(const DstOp &Res, ArrayRef< Register > Ops)
Build and insert Res = G_CONCAT_VECTORS Op0, ...
MachineInstrBuilder buildSplatVector(const DstOp &Res, const SrcOp &Src)
Build and insert Res = G_BUILD_VECTOR with Src replicated to fill the number of elements.
const DebugLoc & getDL()
Getter for DebugLoc.
MachineInstrBuilder buildAtomicCmpXchg(Register OldValRes, Register Addr, Register CmpVal, Register NewVal, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMIC_CMPXCHG Addr, CmpVal, NewVal, MMO.
PointerType * getType() const
Global values are always pointers.
Definition: GlobalValue.h:277
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
bool empty() const
empty - Check if the array is empty.
Definition: ArrayRef.h:143
This file describes how to lower LLVM code to machine code.
const MachineInstrBuilder & addBlockAddress(const BlockAddress *BA, int64_t Offset=0, unsigned TargetFlags=0) const
MachineRegisterInfo * MRI
Information used to verify types are consistent and to create virtual registers.