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MipsSEISelDAGToDAG.cpp
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1 //===-- MipsSEISelDAGToDAG.cpp - A Dag to Dag Inst Selector for MipsSE ----===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // Subclass of MipsDAGToDAGISel specialized for mips32/64.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "MipsSEISelDAGToDAG.h"
15 #include "Mips.h"
16 #include "MipsAnalyzeImmediate.h"
17 #include "MipsMachineFunction.h"
18 #include "MipsRegisterInfo.h"
25 #include "llvm/IR/CFG.h"
26 #include "llvm/IR/Dominators.h"
27 #include "llvm/IR/GlobalValue.h"
28 #include "llvm/IR/Instructions.h"
29 #include "llvm/IR/Intrinsics.h"
30 #include "llvm/IR/Type.h"
31 #include "llvm/Support/Debug.h"
35 using namespace llvm;
36 
37 #define DEBUG_TYPE "mips-isel"
38 
39 bool MipsSEDAGToDAGISel::runOnMachineFunction(MachineFunction &MF) {
40  Subtarget = &static_cast<const MipsSubtarget &>(MF.getSubtarget());
41  if (Subtarget->inMips16Mode())
42  return false;
44 }
45 
46 void MipsSEDAGToDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
49 }
50 
51 void MipsSEDAGToDAGISel::addDSPCtrlRegOperands(bool IsDef, MachineInstr &MI,
53  MachineInstrBuilder MIB(MF, &MI);
54  unsigned Mask = MI.getOperand(1).getImm();
55  unsigned Flag =
57 
58  if (Mask & 1)
59  MIB.addReg(Mips::DSPPos, Flag);
60 
61  if (Mask & 2)
62  MIB.addReg(Mips::DSPSCount, Flag);
63 
64  if (Mask & 4)
65  MIB.addReg(Mips::DSPCarry, Flag);
66 
67  if (Mask & 8)
68  MIB.addReg(Mips::DSPOutFlag, Flag);
69 
70  if (Mask & 16)
71  MIB.addReg(Mips::DSPCCond, Flag);
72 
73  if (Mask & 32)
74  MIB.addReg(Mips::DSPEFI, Flag);
75 }
76 
77 unsigned MipsSEDAGToDAGISel::getMSACtrlReg(const SDValue RegIdx) const {
78  uint64_t RegNum = cast<ConstantSDNode>(RegIdx)->getZExtValue();
79  return Mips::MSACtrlRegClass.getRegister(RegNum);
80 }
81 
82 bool MipsSEDAGToDAGISel::replaceUsesWithZeroReg(MachineRegisterInfo *MRI,
83  const MachineInstr& MI) {
84  unsigned DstReg = 0, ZeroReg = 0;
85 
86  // Check if MI is "addiu $dst, $zero, 0" or "daddiu $dst, $zero, 0".
87  if ((MI.getOpcode() == Mips::ADDiu) &&
88  (MI.getOperand(1).getReg() == Mips::ZERO) &&
89  (MI.getOperand(2).isImm()) &&
90  (MI.getOperand(2).getImm() == 0)) {
91  DstReg = MI.getOperand(0).getReg();
92  ZeroReg = Mips::ZERO;
93  } else if ((MI.getOpcode() == Mips::DADDiu) &&
94  (MI.getOperand(1).getReg() == Mips::ZERO_64) &&
95  (MI.getOperand(2).isImm()) &&
96  (MI.getOperand(2).getImm() == 0)) {
97  DstReg = MI.getOperand(0).getReg();
98  ZeroReg = Mips::ZERO_64;
99  }
100 
101  if (!DstReg)
102  return false;
103 
104  // Replace uses with ZeroReg.
105  for (MachineRegisterInfo::use_iterator U = MRI->use_begin(DstReg),
106  E = MRI->use_end(); U != E;) {
107  MachineOperand &MO = *U;
108  unsigned OpNo = U.getOperandNo();
109  MachineInstr *MI = MO.getParent();
110  ++U;
111 
112  // Do not replace if it is a phi's operand or is tied to def operand.
113  if (MI->isPHI() || MI->isRegTiedToDefOperand(OpNo) || MI->isPseudo())
114  continue;
115 
116  // Also, we have to check that the register class of the operand
117  // contains the zero register.
118  if (!MRI->getRegClass(MO.getReg())->contains(ZeroReg))
119  continue;
120 
121  MO.setReg(ZeroReg);
122  }
123 
124  return true;
125 }
126 
127 void MipsSEDAGToDAGISel::processFunctionAfterISel(MachineFunction &MF) {
128  MF.getInfo<MipsFunctionInfo>()->initGlobalBaseReg();
129 
130  MachineRegisterInfo *MRI = &MF.getRegInfo();
131 
132  for (auto &MBB: MF) {
133  for (auto &MI: MBB) {
134  switch (MI.getOpcode()) {
135  case Mips::RDDSP:
136  addDSPCtrlRegOperands(false, MI, MF);
137  break;
138  case Mips::WRDSP:
139  addDSPCtrlRegOperands(true, MI, MF);
140  break;
141  case Mips::BuildPairF64_64:
142  case Mips::ExtractElementF64_64:
143  if (!Subtarget->useOddSPReg()) {
144  MI.addOperand(MachineOperand::CreateReg(Mips::SP, false, true));
145  break;
146  }
148  case Mips::BuildPairF64:
150  if (Subtarget->isABI_FPXX() && !Subtarget->hasMTHC1())
151  MI.addOperand(MachineOperand::CreateReg(Mips::SP, false, true));
152  break;
153  default:
154  replaceUsesWithZeroReg(MRI, MI);
155  }
156  }
157  }
158 }
159 
160 void MipsSEDAGToDAGISel::selectAddE(SDNode *Node, const SDLoc &DL) const {
161  SDValue InFlag = Node->getOperand(2);
162  unsigned Opc = InFlag.getOpcode();
163  SDValue LHS = Node->getOperand(0), RHS = Node->getOperand(1);
164  EVT VT = LHS.getValueType();
165 
166  // In the base case, we can rely on the carry bit from the addsc
167  // instruction.
168  if (Opc == ISD::ADDC) {
169  SDValue Ops[3] = {LHS, RHS, InFlag};
170  CurDAG->SelectNodeTo(Node, Mips::ADDWC, VT, MVT::Glue, Ops);
171  return;
172  }
173 
174  assert(Opc == ISD::ADDE && "ISD::ADDE not in a chain of ADDE nodes!");
175 
176  // The more complex case is when there is a chain of ISD::ADDE nodes like:
177  // (adde (adde (adde (addc a b) c) d) e).
178  //
179  // The addwc instruction does not write to the carry bit, instead it writes
180  // to bit 20 of the dsp control register. To match this series of nodes, each
181  // intermediate adde node must be expanded to write the carry bit before the
182  // addition.
183 
184  // Start by reading the overflow field for addsc and moving the value to the
185  // carry field. The usage of 1 here with MipsISD::RDDSP / Mips::WRDSP
186  // corresponds to reading/writing the entire control register to/from a GPR.
187 
188  SDValue CstOne = CurDAG->getTargetConstant(1, DL, MVT::i32);
189 
190  SDValue OuFlag = CurDAG->getTargetConstant(20, DL, MVT::i32);
191 
192  SDNode *DSPCtrlField =
193  CurDAG->getMachineNode(Mips::RDDSP, DL, MVT::i32, MVT::Glue, CstOne, InFlag);
194 
195  SDNode *Carry = CurDAG->getMachineNode(
196  Mips::EXT, DL, MVT::i32, SDValue(DSPCtrlField, 0), OuFlag, CstOne);
197 
198  SDValue Ops[4] = {SDValue(DSPCtrlField, 0),
199  CurDAG->getTargetConstant(6, DL, MVT::i32), CstOne,
200  SDValue(Carry, 0)};
201  SDNode *DSPCFWithCarry = CurDAG->getMachineNode(Mips::INS, DL, MVT::i32, Ops);
202 
203  // My reading of the MIPS DSP 3.01 specification isn't as clear as I
204  // would like about whether bit 20 always gets overwritten by addwc.
205  // Hence take an extremely conservative view and presume it's sticky. We
206  // therefore need to clear it.
207 
208  SDValue Zero = CurDAG->getRegister(Mips::ZERO, MVT::i32);
209 
210  SDValue InsOps[4] = {Zero, OuFlag, CstOne, SDValue(DSPCFWithCarry, 0)};
211  SDNode *DSPCtrlFinal = CurDAG->getMachineNode(Mips::INS, DL, MVT::i32, InsOps);
212 
213  SDNode *WrDSP = CurDAG->getMachineNode(Mips::WRDSP, DL, MVT::Glue,
214  SDValue(DSPCtrlFinal, 0), CstOne);
215 
216  SDValue Operands[3] = {LHS, RHS, SDValue(WrDSP, 0)};
217  CurDAG->SelectNodeTo(Node, Mips::ADDWC, VT, MVT::Glue, Operands);
218 }
219 
220 /// Match frameindex
221 bool MipsSEDAGToDAGISel::selectAddrFrameIndex(SDValue Addr, SDValue &Base,
222  SDValue &Offset) const {
223  if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
224  EVT ValTy = Addr.getValueType();
225 
226  Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
227  Offset = CurDAG->getTargetConstant(0, SDLoc(Addr), ValTy);
228  return true;
229  }
230  return false;
231 }
232 
233 /// Match frameindex+offset and frameindex|offset
234 bool MipsSEDAGToDAGISel::selectAddrFrameIndexOffset(
235  SDValue Addr, SDValue &Base, SDValue &Offset, unsigned OffsetBits,
236  unsigned ShiftAmount = 0) const {
237  if (CurDAG->isBaseWithConstantOffset(Addr)) {
239  if (isIntN(OffsetBits + ShiftAmount, CN->getSExtValue())) {
240  EVT ValTy = Addr.getValueType();
241 
242  // If the first operand is a FI, get the TargetFI Node
243  if (FrameIndexSDNode *FIN =
244  dyn_cast<FrameIndexSDNode>(Addr.getOperand(0)))
245  Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
246  else {
247  Base = Addr.getOperand(0);
248  // If base is a FI, additional offset calculation is done in
249  // eliminateFrameIndex, otherwise we need to check the alignment
250  const llvm::Align Align(1ULL << ShiftAmount);
251  if (!isAligned(Align, CN->getZExtValue()))
252  return false;
253  }
254 
255  Offset = CurDAG->getTargetConstant(CN->getZExtValue(), SDLoc(Addr),
256  ValTy);
257  return true;
258  }
259  }
260  return false;
261 }
262 
263 /// ComplexPattern used on MipsInstrInfo
264 /// Used on Mips Load/Store instructions
265 bool MipsSEDAGToDAGISel::selectAddrRegImm(SDValue Addr, SDValue &Base,
266  SDValue &Offset) const {
267  // if Address is FI, get the TargetFrameIndex.
268  if (selectAddrFrameIndex(Addr, Base, Offset))
269  return true;
270 
271  // on PIC code Load GA
272  if (Addr.getOpcode() == MipsISD::Wrapper) {
273  Base = Addr.getOperand(0);
274  Offset = Addr.getOperand(1);
275  return true;
276  }
277 
278  if (!TM.isPositionIndependent()) {
279  if ((Addr.getOpcode() == ISD::TargetExternalSymbol ||
281  return false;
282  }
283 
284  // Addresses of the form FI+const or FI|const
285  if (selectAddrFrameIndexOffset(Addr, Base, Offset, 16))
286  return true;
287 
288  // Operand is a result from an ADD.
289  if (Addr.getOpcode() == ISD::ADD) {
290  // When loading from constant pools, load the lower address part in
291  // the instruction itself. Example, instead of:
292  // lui $2, %hi($CPI1_0)
293  // addiu $2, $2, %lo($CPI1_0)
294  // lwc1 $f0, 0($2)
295  // Generate:
296  // lui $2, %hi($CPI1_0)
297  // lwc1 $f0, %lo($CPI1_0)($2)
298  if (Addr.getOperand(1).getOpcode() == MipsISD::Lo ||
299  Addr.getOperand(1).getOpcode() == MipsISD::GPRel) {
300  SDValue Opnd0 = Addr.getOperand(1).getOperand(0);
301  if (isa<ConstantPoolSDNode>(Opnd0) || isa<GlobalAddressSDNode>(Opnd0) ||
302  isa<JumpTableSDNode>(Opnd0)) {
303  Base = Addr.getOperand(0);
304  Offset = Opnd0;
305  return true;
306  }
307  }
308  }
309 
310  return false;
311 }
312 
313 /// ComplexPattern used on MipsInstrInfo
314 /// Used on Mips Load/Store instructions
315 bool MipsSEDAGToDAGISel::selectAddrDefault(SDValue Addr, SDValue &Base,
316  SDValue &Offset) const {
317  Base = Addr;
318  Offset = CurDAG->getTargetConstant(0, SDLoc(Addr), Addr.getValueType());
319  return true;
320 }
321 
322 bool MipsSEDAGToDAGISel::selectIntAddr(SDValue Addr, SDValue &Base,
323  SDValue &Offset) const {
324  return selectAddrRegImm(Addr, Base, Offset) ||
325  selectAddrDefault(Addr, Base, Offset);
326 }
327 
328 bool MipsSEDAGToDAGISel::selectAddrRegImm9(SDValue Addr, SDValue &Base,
329  SDValue &Offset) const {
330  if (selectAddrFrameIndex(Addr, Base, Offset))
331  return true;
332 
333  if (selectAddrFrameIndexOffset(Addr, Base, Offset, 9))
334  return true;
335 
336  return false;
337 }
338 
339 /// Used on microMIPS LWC2, LDC2, SWC2 and SDC2 instructions (11-bit offset)
340 bool MipsSEDAGToDAGISel::selectAddrRegImm11(SDValue Addr, SDValue &Base,
341  SDValue &Offset) const {
342  if (selectAddrFrameIndex(Addr, Base, Offset))
343  return true;
344 
345  if (selectAddrFrameIndexOffset(Addr, Base, Offset, 11))
346  return true;
347 
348  return false;
349 }
350 
351 /// Used on microMIPS Load/Store unaligned instructions (12-bit offset)
352 bool MipsSEDAGToDAGISel::selectAddrRegImm12(SDValue Addr, SDValue &Base,
353  SDValue &Offset) const {
354  if (selectAddrFrameIndex(Addr, Base, Offset))
355  return true;
356 
357  if (selectAddrFrameIndexOffset(Addr, Base, Offset, 12))
358  return true;
359 
360  return false;
361 }
362 
363 bool MipsSEDAGToDAGISel::selectAddrRegImm16(SDValue Addr, SDValue &Base,
364  SDValue &Offset) const {
365  if (selectAddrFrameIndex(Addr, Base, Offset))
366  return true;
367 
368  if (selectAddrFrameIndexOffset(Addr, Base, Offset, 16))
369  return true;
370 
371  return false;
372 }
373 
374 bool MipsSEDAGToDAGISel::selectIntAddr11MM(SDValue Addr, SDValue &Base,
375  SDValue &Offset) const {
376  return selectAddrRegImm11(Addr, Base, Offset) ||
377  selectAddrDefault(Addr, Base, Offset);
378 }
379 
380 bool MipsSEDAGToDAGISel::selectIntAddr12MM(SDValue Addr, SDValue &Base,
381  SDValue &Offset) const {
382  return selectAddrRegImm12(Addr, Base, Offset) ||
383  selectAddrDefault(Addr, Base, Offset);
384 }
385 
386 bool MipsSEDAGToDAGISel::selectIntAddr16MM(SDValue Addr, SDValue &Base,
387  SDValue &Offset) const {
388  return selectAddrRegImm16(Addr, Base, Offset) ||
389  selectAddrDefault(Addr, Base, Offset);
390 }
391 
392 bool MipsSEDAGToDAGISel::selectIntAddrLSL2MM(SDValue Addr, SDValue &Base,
393  SDValue &Offset) const {
394  if (selectAddrFrameIndexOffset(Addr, Base, Offset, 7)) {
395  if (isa<FrameIndexSDNode>(Base))
396  return false;
397 
398  if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Offset)) {
399  unsigned CnstOff = CN->getZExtValue();
400  return (CnstOff == (CnstOff & 0x3c));
401  }
402 
403  return false;
404  }
405 
406  // For all other cases where "lw" would be selected, don't select "lw16"
407  // because it would result in additional instructions to prepare operands.
408  if (selectAddrRegImm(Addr, Base, Offset))
409  return false;
410 
411  return selectAddrDefault(Addr, Base, Offset);
412 }
413 
414 bool MipsSEDAGToDAGISel::selectIntAddrSImm10(SDValue Addr, SDValue &Base,
415  SDValue &Offset) const {
416 
417  if (selectAddrFrameIndex(Addr, Base, Offset))
418  return true;
419 
420  if (selectAddrFrameIndexOffset(Addr, Base, Offset, 10))
421  return true;
422 
423  return selectAddrDefault(Addr, Base, Offset);
424 }
425 
426 bool MipsSEDAGToDAGISel::selectIntAddrSImm10Lsl1(SDValue Addr, SDValue &Base,
427  SDValue &Offset) const {
428  if (selectAddrFrameIndex(Addr, Base, Offset))
429  return true;
430 
431  if (selectAddrFrameIndexOffset(Addr, Base, Offset, 10, 1))
432  return true;
433 
434  return selectAddrDefault(Addr, Base, Offset);
435 }
436 
437 bool MipsSEDAGToDAGISel::selectIntAddrSImm10Lsl2(SDValue Addr, SDValue &Base,
438  SDValue &Offset) const {
439  if (selectAddrFrameIndex(Addr, Base, Offset))
440  return true;
441 
442  if (selectAddrFrameIndexOffset(Addr, Base, Offset, 10, 2))
443  return true;
444 
445  return selectAddrDefault(Addr, Base, Offset);
446 }
447 
448 bool MipsSEDAGToDAGISel::selectIntAddrSImm10Lsl3(SDValue Addr, SDValue &Base,
449  SDValue &Offset) const {
450  if (selectAddrFrameIndex(Addr, Base, Offset))
451  return true;
452 
453  if (selectAddrFrameIndexOffset(Addr, Base, Offset, 10, 3))
454  return true;
455 
456  return selectAddrDefault(Addr, Base, Offset);
457 }
458 
459 // Select constant vector splats.
460 //
461 // Returns true and sets Imm if:
462 // * MSA is enabled
463 // * N is a ISD::BUILD_VECTOR representing a constant splat
464 bool MipsSEDAGToDAGISel::selectVSplat(SDNode *N, APInt &Imm,
465  unsigned MinSizeInBits) const {
466  if (!Subtarget->hasMSA())
467  return false;
468 
470 
471  if (!Node)
472  return false;
473 
474  APInt SplatValue, SplatUndef;
475  unsigned SplatBitSize;
476  bool HasAnyUndefs;
477 
478  if (!Node->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs,
479  MinSizeInBits, !Subtarget->isLittle()))
480  return false;
481 
482  Imm = SplatValue;
483 
484  return true;
485 }
486 
487 // Select constant vector splats.
488 //
489 // In addition to the requirements of selectVSplat(), this function returns
490 // true and sets Imm if:
491 // * The splat value is the same width as the elements of the vector
492 // * The splat value fits in an integer with the specified signed-ness and
493 // width.
494 //
495 // This function looks through ISD::BITCAST nodes.
496 // TODO: This might not be appropriate for big-endian MSA since BITCAST is
497 // sometimes a shuffle in big-endian mode.
498 //
499 // It's worth noting that this function is not used as part of the selection
500 // of ldi.[bhwd] since it does not permit using the wrong-typed ldi.[bhwd]
501 // instruction to achieve the desired bit pattern. ldi.[bhwd] is selected in
502 // MipsSEDAGToDAGISel::selectNode.
503 bool MipsSEDAGToDAGISel::
504 selectVSplatCommon(SDValue N, SDValue &Imm, bool Signed,
505  unsigned ImmBitSize) const {
506  APInt ImmValue;
507  EVT EltTy = N->getValueType(0).getVectorElementType();
508 
509  if (N->getOpcode() == ISD::BITCAST)
510  N = N->getOperand(0);
511 
512  if (selectVSplat(N.getNode(), ImmValue, EltTy.getSizeInBits()) &&
513  ImmValue.getBitWidth() == EltTy.getSizeInBits()) {
514 
515  if (( Signed && ImmValue.isSignedIntN(ImmBitSize)) ||
516  (!Signed && ImmValue.isIntN(ImmBitSize))) {
517  Imm = CurDAG->getTargetConstant(ImmValue, SDLoc(N), EltTy);
518  return true;
519  }
520  }
521 
522  return false;
523 }
524 
525 // Select constant vector splats.
526 bool MipsSEDAGToDAGISel::
527 selectVSplatUimm1(SDValue N, SDValue &Imm) const {
528  return selectVSplatCommon(N, Imm, false, 1);
529 }
530 
531 bool MipsSEDAGToDAGISel::
532 selectVSplatUimm2(SDValue N, SDValue &Imm) const {
533  return selectVSplatCommon(N, Imm, false, 2);
534 }
535 
536 bool MipsSEDAGToDAGISel::
537 selectVSplatUimm3(SDValue N, SDValue &Imm) const {
538  return selectVSplatCommon(N, Imm, false, 3);
539 }
540 
541 // Select constant vector splats.
542 bool MipsSEDAGToDAGISel::
543 selectVSplatUimm4(SDValue N, SDValue &Imm) const {
544  return selectVSplatCommon(N, Imm, false, 4);
545 }
546 
547 // Select constant vector splats.
548 bool MipsSEDAGToDAGISel::
549 selectVSplatUimm5(SDValue N, SDValue &Imm) const {
550  return selectVSplatCommon(N, Imm, false, 5);
551 }
552 
553 // Select constant vector splats.
554 bool MipsSEDAGToDAGISel::
555 selectVSplatUimm6(SDValue N, SDValue &Imm) const {
556  return selectVSplatCommon(N, Imm, false, 6);
557 }
558 
559 // Select constant vector splats.
560 bool MipsSEDAGToDAGISel::
561 selectVSplatUimm8(SDValue N, SDValue &Imm) const {
562  return selectVSplatCommon(N, Imm, false, 8);
563 }
564 
565 // Select constant vector splats.
566 bool MipsSEDAGToDAGISel::
567 selectVSplatSimm5(SDValue N, SDValue &Imm) const {
568  return selectVSplatCommon(N, Imm, true, 5);
569 }
570 
571 // Select constant vector splats whose value is a power of 2.
572 //
573 // In addition to the requirements of selectVSplat(), this function returns
574 // true and sets Imm if:
575 // * The splat value is the same width as the elements of the vector
576 // * The splat value is a power of two.
577 //
578 // This function looks through ISD::BITCAST nodes.
579 // TODO: This might not be appropriate for big-endian MSA since BITCAST is
580 // sometimes a shuffle in big-endian mode.
581 bool MipsSEDAGToDAGISel::selectVSplatUimmPow2(SDValue N, SDValue &Imm) const {
582  APInt ImmValue;
583  EVT EltTy = N->getValueType(0).getVectorElementType();
584 
585  if (N->getOpcode() == ISD::BITCAST)
586  N = N->getOperand(0);
587 
588  if (selectVSplat(N.getNode(), ImmValue, EltTy.getSizeInBits()) &&
589  ImmValue.getBitWidth() == EltTy.getSizeInBits()) {
590  int32_t Log2 = ImmValue.exactLogBase2();
591 
592  if (Log2 != -1) {
593  Imm = CurDAG->getTargetConstant(Log2, SDLoc(N), EltTy);
594  return true;
595  }
596  }
597 
598  return false;
599 }
600 
601 // Select constant vector splats whose value only has a consecutive sequence
602 // of left-most bits set (e.g. 0b11...1100...00).
603 //
604 // In addition to the requirements of selectVSplat(), this function returns
605 // true and sets Imm if:
606 // * The splat value is the same width as the elements of the vector
607 // * The splat value is a consecutive sequence of left-most bits.
608 //
609 // This function looks through ISD::BITCAST nodes.
610 // TODO: This might not be appropriate for big-endian MSA since BITCAST is
611 // sometimes a shuffle in big-endian mode.
612 bool MipsSEDAGToDAGISel::selectVSplatMaskL(SDValue N, SDValue &Imm) const {
613  APInt ImmValue;
614  EVT EltTy = N->getValueType(0).getVectorElementType();
615 
616  if (N->getOpcode() == ISD::BITCAST)
617  N = N->getOperand(0);
618 
619  if (selectVSplat(N.getNode(), ImmValue, EltTy.getSizeInBits()) &&
620  ImmValue.getBitWidth() == EltTy.getSizeInBits()) {
621  // Extract the run of set bits starting with bit zero from the bitwise
622  // inverse of ImmValue, and test that the inverse of this is the same
623  // as the original value.
624  if (ImmValue == ~(~ImmValue & ~(~ImmValue + 1))) {
625 
626  Imm = CurDAG->getTargetConstant(ImmValue.countPopulation() - 1, SDLoc(N),
627  EltTy);
628  return true;
629  }
630  }
631 
632  return false;
633 }
634 
635 // Select constant vector splats whose value only has a consecutive sequence
636 // of right-most bits set (e.g. 0b00...0011...11).
637 //
638 // In addition to the requirements of selectVSplat(), this function returns
639 // true and sets Imm if:
640 // * The splat value is the same width as the elements of the vector
641 // * The splat value is a consecutive sequence of right-most bits.
642 //
643 // This function looks through ISD::BITCAST nodes.
644 // TODO: This might not be appropriate for big-endian MSA since BITCAST is
645 // sometimes a shuffle in big-endian mode.
646 bool MipsSEDAGToDAGISel::selectVSplatMaskR(SDValue N, SDValue &Imm) const {
647  APInt ImmValue;
648  EVT EltTy = N->getValueType(0).getVectorElementType();
649 
650  if (N->getOpcode() == ISD::BITCAST)
651  N = N->getOperand(0);
652 
653  if (selectVSplat(N.getNode(), ImmValue, EltTy.getSizeInBits()) &&
654  ImmValue.getBitWidth() == EltTy.getSizeInBits()) {
655  // Extract the run of set bits starting with bit zero, and test that the
656  // result is the same as the original value
657  if (ImmValue == (ImmValue & ~(ImmValue + 1))) {
658  Imm = CurDAG->getTargetConstant(ImmValue.countPopulation() - 1, SDLoc(N),
659  EltTy);
660  return true;
661  }
662  }
663 
664  return false;
665 }
666 
667 bool MipsSEDAGToDAGISel::selectVSplatUimmInvPow2(SDValue N,
668  SDValue &Imm) const {
669  APInt ImmValue;
670  EVT EltTy = N->getValueType(0).getVectorElementType();
671 
672  if (N->getOpcode() == ISD::BITCAST)
673  N = N->getOperand(0);
674 
675  if (selectVSplat(N.getNode(), ImmValue, EltTy.getSizeInBits()) &&
676  ImmValue.getBitWidth() == EltTy.getSizeInBits()) {
677  int32_t Log2 = (~ImmValue).exactLogBase2();
678 
679  if (Log2 != -1) {
680  Imm = CurDAG->getTargetConstant(Log2, SDLoc(N), EltTy);
681  return true;
682  }
683  }
684 
685  return false;
686 }
687 
688 bool MipsSEDAGToDAGISel::trySelect(SDNode *Node) {
689  unsigned Opcode = Node->getOpcode();
690  SDLoc DL(Node);
691 
692  ///
693  // Instruction Selection not handled by the auto-generated
694  // tablegen selection should be handled here.
695  ///
696  switch(Opcode) {
697  default: break;
698 
699  case Mips::PseudoD_SELECT_I:
700  case Mips::PseudoD_SELECT_I64: {
702  SDValue cond = Node->getOperand(0);
703  SDValue Hi1 = Node->getOperand(1);
704  SDValue Lo1 = Node->getOperand(2);
705  SDValue Hi2 = Node->getOperand(3);
706  SDValue Lo2 = Node->getOperand(4);
707 
708  SDValue ops[] = {cond, Hi1, Lo1, Hi2, Lo2};
709  EVT NodeTys[] = {VT, VT};
711  ? Mips::PseudoD_SELECT_I64
712  : Mips::PseudoD_SELECT_I,
713  DL, NodeTys, ops));
714  return true;
715  }
716 
717  case ISD::ADDE: {
718  selectAddE(Node, DL);
719  return true;
720  }
721 
722  case ISD::ConstantFP: {
724  if (Node->getValueType(0) == MVT::f64 && CN->isExactlyValue(+0.0)) {
725  if (Subtarget->isGP64bit()) {
727  Mips::ZERO_64, MVT::i64);
728  ReplaceNode(Node,
729  CurDAG->getMachineNode(Mips::DMTC1, DL, MVT::f64, Zero));
730  } else if (Subtarget->isFP64bit()) {
732  Mips::ZERO, MVT::i32);
733  ReplaceNode(Node, CurDAG->getMachineNode(Mips::BuildPairF64_64, DL,
734  MVT::f64, Zero, Zero));
735  } else {
737  Mips::ZERO, MVT::i32);
739  MVT::f64, Zero, Zero));
740  }
741  return true;
742  }
743  break;
744  }
745 
746  case ISD::Constant: {
747  const ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Node);
748  int64_t Imm = CN->getSExtValue();
749  unsigned Size = CN->getValueSizeInBits(0);
750 
751  if (isInt<32>(Imm))
752  break;
753 
754  MipsAnalyzeImmediate AnalyzeImm;
755 
756  const MipsAnalyzeImmediate::InstSeq &Seq =
757  AnalyzeImm.Analyze(Imm, Size, false);
758 
760  SDLoc DL(CN);
761  SDNode *RegOpnd;
762  SDValue ImmOpnd = CurDAG->getTargetConstant(SignExtend64<16>(Inst->ImmOpnd),
763  DL, MVT::i64);
764 
765  // The first instruction can be a LUi which is different from other
766  // instructions (ADDiu, ORI and SLL) in that it does not have a register
767  // operand.
768  if (Inst->Opc == Mips::LUi64)
769  RegOpnd = CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64, ImmOpnd);
770  else
771  RegOpnd =
772  CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64,
773  CurDAG->getRegister(Mips::ZERO_64, MVT::i64),
774  ImmOpnd);
775 
776  // The remaining instructions in the sequence are handled here.
777  for (++Inst; Inst != Seq.end(); ++Inst) {
778  ImmOpnd = CurDAG->getTargetConstant(SignExtend64<16>(Inst->ImmOpnd), DL,
779  MVT::i64);
780  RegOpnd = CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64,
781  SDValue(RegOpnd, 0), ImmOpnd);
782  }
783 
784  ReplaceNode(Node, RegOpnd);
785  return true;
786  }
787 
788  case ISD::INTRINSIC_W_CHAIN: {
789  switch (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
790  default:
791  break;
792 
793  case Intrinsic::mips_cfcmsa: {
794  SDValue ChainIn = Node->getOperand(0);
795  SDValue RegIdx = Node->getOperand(2);
796  SDValue Reg = CurDAG->getCopyFromReg(ChainIn, DL,
797  getMSACtrlReg(RegIdx), MVT::i32);
798  ReplaceNode(Node, Reg.getNode());
799  return true;
800  }
801  }
802  break;
803  }
804 
806  switch (cast<ConstantSDNode>(Node->getOperand(0))->getZExtValue()) {
807  default:
808  break;
809 
810  case Intrinsic::mips_move_v:
811  // Like an assignment but will always produce a move.v even if
812  // unnecessary.
813  ReplaceNode(Node, CurDAG->getMachineNode(Mips::MOVE_V, DL,
814  Node->getValueType(0),
815  Node->getOperand(1)));
816  return true;
817  }
818  break;
819  }
820 
821  case ISD::INTRINSIC_VOID: {
822  switch (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
823  default:
824  break;
825 
826  case Intrinsic::mips_ctcmsa: {
827  SDValue ChainIn = Node->getOperand(0);
828  SDValue RegIdx = Node->getOperand(2);
829  SDValue Value = Node->getOperand(3);
830  SDValue ChainOut = CurDAG->getCopyToReg(ChainIn, DL,
831  getMSACtrlReg(RegIdx), Value);
832  ReplaceNode(Node, ChainOut.getNode());
833  return true;
834  }
835  }
836  break;
837  }
838 
839  // Manually match MipsISD::Ins nodes to get the correct instruction. It has
840  // to be done in this fashion so that we respect the differences between
841  // dins and dinsm, as the difference is that the size operand has the range
842  // 0 < size <= 32 for dins while dinsm has the range 2 <= size <= 64 which
843  // means SelectionDAGISel would have to test all the operands at once to
844  // match the instruction.
845  case MipsISD::Ins: {
846 
847  // Sanity checking for the node operands.
848  if (Node->getValueType(0) != MVT::i32 && Node->getValueType(0) != MVT::i64)
849  return false;
850 
851  if (Node->getNumOperands() != 4)
852  return false;
853 
854  if (Node->getOperand(1)->getOpcode() != ISD::Constant ||
855  Node->getOperand(2)->getOpcode() != ISD::Constant)
856  return false;
857 
858  MVT ResTy = Node->getSimpleValueType(0);
859  uint64_t Pos = Node->getConstantOperandVal(1);
860  uint64_t Size = Node->getConstantOperandVal(2);
861 
862  // Size has to be >0 for 'ins', 'dins' and 'dinsu'.
863  if (!Size)
864  return false;
865 
866  if (Pos + Size > 64)
867  return false;
868 
869  if (ResTy != MVT::i32 && ResTy != MVT::i64)
870  return false;
871 
872  unsigned Opcode = 0;
873  if (ResTy == MVT::i32) {
874  if (Pos + Size <= 32)
875  Opcode = Mips::INS;
876  } else {
877  if (Pos + Size <= 32)
878  Opcode = Mips::DINS;
879  else if (Pos < 32 && 1 < Size)
880  Opcode = Mips::DINSM;
881  else
882  Opcode = Mips::DINSU;
883  }
884 
885  if (Opcode) {
886  SDValue Ops[4] = {
887  Node->getOperand(0), CurDAG->getTargetConstant(Pos, DL, MVT::i32),
888  CurDAG->getTargetConstant(Size, DL, MVT::i32), Node->getOperand(3)};
889 
890  ReplaceNode(Node, CurDAG->getMachineNode(Opcode, DL, ResTy, Ops));
891  return true;
892  }
893 
894  return false;
895  }
896 
897  case MipsISD::ThreadPointer: {
899  unsigned RdhwrOpc, DestReg;
900 
901  if (PtrVT == MVT::i32) {
902  RdhwrOpc = Mips::RDHWR;
903  DestReg = Mips::V1;
904  } else {
905  RdhwrOpc = Mips::RDHWR64;
906  DestReg = Mips::V1_64;
907  }
908 
909  SDNode *Rdhwr =
910  CurDAG->getMachineNode(RdhwrOpc, DL, Node->getValueType(0),
911  CurDAG->getRegister(Mips::HWR29, MVT::i32),
913  SDValue Chain = CurDAG->getCopyToReg(CurDAG->getEntryNode(), DL, DestReg,
914  SDValue(Rdhwr, 0));
915  SDValue ResNode = CurDAG->getCopyFromReg(Chain, DL, DestReg, PtrVT);
916  ReplaceNode(Node, ResNode.getNode());
917  return true;
918  }
919 
920  case ISD::BUILD_VECTOR: {
921  // Select appropriate ldi.[bhwd] instructions for constant splats of
922  // 128-bit when MSA is enabled. Fixup any register class mismatches that
923  // occur as a result.
924  //
925  // This allows the compiler to use a wider range of immediates than would
926  // otherwise be allowed. If, for example, v4i32 could only use ldi.h then
927  // it would not be possible to load { 0x01010101, 0x01010101, 0x01010101,
928  // 0x01010101 } without using a constant pool. This would be sub-optimal
929  // when // 'ldi.b wd, 1' is capable of producing that bit-pattern in the
930  // same set/ of registers. Similarly, ldi.h isn't capable of producing {
931  // 0x00000000, 0x00000001, 0x00000000, 0x00000001 } but 'ldi.d wd, 1' can.
932 
933  const MipsABIInfo &ABI =
934  static_cast<const MipsTargetMachine &>(TM).getABI();
935 
936  BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Node);
937  APInt SplatValue, SplatUndef;
938  unsigned SplatBitSize;
939  bool HasAnyUndefs;
940  unsigned LdiOp;
941  EVT ResVecTy = BVN->getValueType(0);
942  EVT ViaVecTy;
943 
944  if (!Subtarget->hasMSA() || !BVN->getValueType(0).is128BitVector())
945  return false;
946 
947  if (!BVN->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
948  HasAnyUndefs, 8,
949  !Subtarget->isLittle()))
950  return false;
951 
952  switch (SplatBitSize) {
953  default:
954  return false;
955  case 8:
956  LdiOp = Mips::LDI_B;
957  ViaVecTy = MVT::v16i8;
958  break;
959  case 16:
960  LdiOp = Mips::LDI_H;
961  ViaVecTy = MVT::v8i16;
962  break;
963  case 32:
964  LdiOp = Mips::LDI_W;
965  ViaVecTy = MVT::v4i32;
966  break;
967  case 64:
968  LdiOp = Mips::LDI_D;
969  ViaVecTy = MVT::v2i64;
970  break;
971  }
972 
973  SDNode *Res;
974 
975  // If we have a signed 10 bit integer, we can splat it directly.
976  //
977  // If we have something bigger we can synthesize the value into a GPR and
978  // splat from there.
979  if (SplatValue.isSignedIntN(10)) {
980  SDValue Imm = CurDAG->getTargetConstant(SplatValue, DL,
981  ViaVecTy.getVectorElementType());
982 
983  Res = CurDAG->getMachineNode(LdiOp, DL, ViaVecTy, Imm);
984  } else if (SplatValue.isSignedIntN(16) &&
985  ((ABI.IsO32() && SplatBitSize < 64) ||
986  (ABI.IsN32() || ABI.IsN64()))) {
987  // Only handle signed 16 bit values when the element size is GPR width.
988  // MIPS64 can handle all the cases but MIPS32 would need to handle
989  // negative cases specifically here. Instead, handle those cases as
990  // 64bit values.
991 
992  bool Is32BitSplat = ABI.IsO32() || SplatBitSize < 64;
993  const unsigned ADDiuOp = Is32BitSplat ? Mips::ADDiu : Mips::DADDiu;
994  const MVT SplatMVT = Is32BitSplat ? MVT::i32 : MVT::i64;
995  SDValue ZeroVal = CurDAG->getRegister(
996  Is32BitSplat ? Mips::ZERO : Mips::ZERO_64, SplatMVT);
997 
998  const unsigned FILLOp =
999  SplatBitSize == 16
1000  ? Mips::FILL_H
1001  : (SplatBitSize == 32 ? Mips::FILL_W
1002  : (SplatBitSize == 64 ? Mips::FILL_D : 0));
1003 
1004  assert(FILLOp != 0 && "Unknown FILL Op for splat synthesis!");
1005  assert((!ABI.IsO32() || (FILLOp != Mips::FILL_D)) &&
1006  "Attempting to use fill.d on MIPS32!");
1007 
1008  const unsigned Lo = SplatValue.getLoBits(16).getZExtValue();
1009  SDValue LoVal = CurDAG->getTargetConstant(Lo, DL, SplatMVT);
1010 
1011  Res = CurDAG->getMachineNode(ADDiuOp, DL, SplatMVT, ZeroVal, LoVal);
1012  Res = CurDAG->getMachineNode(FILLOp, DL, ViaVecTy, SDValue(Res, 0));
1013 
1014  } else if (SplatValue.isSignedIntN(32) && SplatBitSize == 32) {
1015  // Only handle the cases where the splat size agrees with the size
1016  // of the SplatValue here.
1017  const unsigned Lo = SplatValue.getLoBits(16).getZExtValue();
1018  const unsigned Hi = SplatValue.lshr(16).getLoBits(16).getZExtValue();
1019  SDValue ZeroVal = CurDAG->getRegister(Mips::ZERO, MVT::i32);
1020 
1021  SDValue LoVal = CurDAG->getTargetConstant(Lo, DL, MVT::i32);
1022  SDValue HiVal = CurDAG->getTargetConstant(Hi, DL, MVT::i32);
1023 
1024  if (Hi)
1025  Res = CurDAG->getMachineNode(Mips::LUi, DL, MVT::i32, HiVal);
1026 
1027  if (Lo)
1028  Res = CurDAG->getMachineNode(Mips::ORi, DL, MVT::i32,
1029  Hi ? SDValue(Res, 0) : ZeroVal, LoVal);
1030 
1031  assert((Hi || Lo) && "Zero case reached 32 bit case splat synthesis!");
1032  Res = CurDAG->getMachineNode(Mips::FILL_W, DL, MVT::v4i32, SDValue(Res, 0));
1033 
1034  } else if (SplatValue.isSignedIntN(32) && SplatBitSize == 64 &&
1035  (ABI.IsN32() || ABI.IsN64())) {
1036  // N32 and N64 can perform some tricks that O32 can't for signed 32 bit
1037  // integers due to having 64bit registers. lui will cause the necessary
1038  // zero/sign extension.
1039  const unsigned Lo = SplatValue.getLoBits(16).getZExtValue();
1040  const unsigned Hi = SplatValue.lshr(16).getLoBits(16).getZExtValue();
1041  SDValue ZeroVal = CurDAG->getRegister(Mips::ZERO, MVT::i32);
1042 
1043  SDValue LoVal = CurDAG->getTargetConstant(Lo, DL, MVT::i32);
1044  SDValue HiVal = CurDAG->getTargetConstant(Hi, DL, MVT::i32);
1045 
1046  if (Hi)
1047  Res = CurDAG->getMachineNode(Mips::LUi, DL, MVT::i32, HiVal);
1048 
1049  if (Lo)
1050  Res = CurDAG->getMachineNode(Mips::ORi, DL, MVT::i32,
1051  Hi ? SDValue(Res, 0) : ZeroVal, LoVal);
1052 
1053  Res = CurDAG->getMachineNode(
1054  Mips::SUBREG_TO_REG, DL, MVT::i64,
1055  CurDAG->getTargetConstant(((Hi >> 15) & 0x1), DL, MVT::i64),
1056  SDValue(Res, 0),
1057  CurDAG->getTargetConstant(Mips::sub_32, DL, MVT::i64));
1058 
1059  Res =
1060  CurDAG->getMachineNode(Mips::FILL_D, DL, MVT::v2i64, SDValue(Res, 0));
1061 
1062  } else if (SplatValue.isSignedIntN(64)) {
1063  // If we have a 64 bit Splat value, we perform a similar sequence to the
1064  // above:
1065  //
1066  // MIPS32: MIPS64:
1067  // lui $res, %highest(val) lui $res, %highest(val)
1068  // ori $res, $res, %higher(val) ori $res, $res, %higher(val)
1069  // lui $res2, %hi(val) lui $res2, %hi(val)
1070  // ori $res2, %res2, %lo(val) ori $res2, %res2, %lo(val)
1071  // $res3 = fill $res2 dinsu $res, $res2, 0, 32
1072  // $res4 = insert.w $res3[1], $res fill.d $res
1073  // splat.d $res4, 0
1074  //
1075  // The ability to use dinsu is guaranteed as MSA requires MIPSR5. This saves
1076  // having to materialize the value by shifts and ors.
1077  //
1078  // FIXME: Implement the preferred sequence for MIPS64R6:
1079  //
1080  // MIPS64R6:
1081  // ori $res, $zero, %lo(val)
1082  // daui $res, $res, %hi(val)
1083  // dahi $res, $res, %higher(val)
1084  // dati $res, $res, %highest(cal)
1085  // fill.d $res
1086  //
1087 
1088  const unsigned Lo = SplatValue.getLoBits(16).getZExtValue();
1089  const unsigned Hi = SplatValue.lshr(16).getLoBits(16).getZExtValue();
1090  const unsigned Higher = SplatValue.lshr(32).getLoBits(16).getZExtValue();
1091  const unsigned Highest = SplatValue.lshr(48).getLoBits(16).getZExtValue();
1092 
1093  SDValue LoVal = CurDAG->getTargetConstant(Lo, DL, MVT::i32);
1094  SDValue HiVal = CurDAG->getTargetConstant(Hi, DL, MVT::i32);
1095  SDValue HigherVal = CurDAG->getTargetConstant(Higher, DL, MVT::i32);
1096  SDValue HighestVal = CurDAG->getTargetConstant(Highest, DL, MVT::i32);
1097  SDValue ZeroVal = CurDAG->getRegister(Mips::ZERO, MVT::i32);
1098 
1099  // Independent of whether we're targeting MIPS64 or not, the basic
1100  // operations are the same. Also, directly use the $zero register if
1101  // the 16 bit chunk is zero.
1102  //
1103  // For optimization purposes we always synthesize the splat value as
1104  // an i32 value, then if we're targetting MIPS64, use SUBREG_TO_REG
1105  // just before combining the values with dinsu to produce an i64. This
1106  // enables SelectionDAG to aggressively share components of splat values
1107  // where possible.
1108  //
1109  // FIXME: This is the general constant synthesis problem. This code
1110  // should be factored out into a class shared between all the
1111  // classes that need it. Specifically, for a splat size of 64
1112  // bits that's a negative number we can do better than LUi/ORi
1113  // for the upper 32bits.
1114 
1115  if (Hi)
1116  Res = CurDAG->getMachineNode(Mips::LUi, DL, MVT::i32, HiVal);
1117 
1118  if (Lo)
1119  Res = CurDAG->getMachineNode(Mips::ORi, DL, MVT::i32,
1120  Hi ? SDValue(Res, 0) : ZeroVal, LoVal);
1121 
1122  SDNode *HiRes;
1123  if (Highest)
1124  HiRes = CurDAG->getMachineNode(Mips::LUi, DL, MVT::i32, HighestVal);
1125 
1126  if (Higher)
1127  HiRes = CurDAG->getMachineNode(Mips::ORi, DL, MVT::i32,
1128  Highest ? SDValue(HiRes, 0) : ZeroVal,
1129  HigherVal);
1130 
1131 
1132  if (ABI.IsO32()) {
1133  Res = CurDAG->getMachineNode(Mips::FILL_W, DL, MVT::v4i32,
1134  (Hi || Lo) ? SDValue(Res, 0) : ZeroVal);
1135 
1136  Res = CurDAG->getMachineNode(
1137  Mips::INSERT_W, DL, MVT::v4i32, SDValue(Res, 0),
1138  (Highest || Higher) ? SDValue(HiRes, 0) : ZeroVal,
1139  CurDAG->getTargetConstant(1, DL, MVT::i32));
1140 
1142  const TargetRegisterClass *RC =
1143  TLI->getRegClassFor(ViaVecTy.getSimpleVT());
1144 
1145  Res = CurDAG->getMachineNode(
1146  Mips::COPY_TO_REGCLASS, DL, ViaVecTy, SDValue(Res, 0),
1147  CurDAG->getTargetConstant(RC->getID(), DL, MVT::i32));
1148 
1149  Res = CurDAG->getMachineNode(
1150  Mips::SPLATI_D, DL, MVT::v2i64, SDValue(Res, 0),
1151  CurDAG->getTargetConstant(0, DL, MVT::i32));
1152  } else if (ABI.IsN64() || ABI.IsN32()) {
1153 
1154  SDValue Zero64Val = CurDAG->getRegister(Mips::ZERO_64, MVT::i64);
1155  const bool HiResNonZero = Highest || Higher;
1156  const bool ResNonZero = Hi || Lo;
1157 
1158  if (HiResNonZero)
1159  HiRes = CurDAG->getMachineNode(
1160  Mips::SUBREG_TO_REG, DL, MVT::i64,
1161  CurDAG->getTargetConstant(((Highest >> 15) & 0x1), DL, MVT::i64),
1162  SDValue(HiRes, 0),
1163  CurDAG->getTargetConstant(Mips::sub_32, DL, MVT::i64));
1164 
1165  if (ResNonZero)
1166  Res = CurDAG->getMachineNode(
1167  Mips::SUBREG_TO_REG, DL, MVT::i64,
1168  CurDAG->getTargetConstant(((Hi >> 15) & 0x1), DL, MVT::i64),
1169  SDValue(Res, 0),
1170  CurDAG->getTargetConstant(Mips::sub_32, DL, MVT::i64));
1171 
1172  // We have 3 cases:
1173  // The HiRes is nonzero but Res is $zero => dsll32 HiRes, 0
1174  // The Res is nonzero but HiRes is $zero => dinsu Res, $zero, 32, 32
1175  // Both are non zero => dinsu Res, HiRes, 32, 32
1176  //
1177  // The obvious "missing" case is when both are zero, but that case is
1178  // handled by the ldi case.
1179  if (ResNonZero) {
1180  IntegerType *Int32Ty =
1182  const ConstantInt *Const32 = ConstantInt::get(Int32Ty, 32);
1183  SDValue Ops[4] = {HiResNonZero ? SDValue(HiRes, 0) : Zero64Val,
1184  CurDAG->getConstant(*Const32, DL, MVT::i32),
1185  CurDAG->getConstant(*Const32, DL, MVT::i32),
1186  SDValue(Res, 0)};
1187 
1188  Res = CurDAG->getMachineNode(Mips::DINSU, DL, MVT::i64, Ops);
1189  } else if (HiResNonZero) {
1190  Res = CurDAG->getMachineNode(
1191  Mips::DSLL32, DL, MVT::i64, SDValue(HiRes, 0),
1192  CurDAG->getTargetConstant(0, DL, MVT::i32));
1193  } else
1195  "Zero splat value handled by non-zero 64bit splat synthesis!");
1196 
1197  Res = CurDAG->getMachineNode(Mips::FILL_D, DL, MVT::v2i64, SDValue(Res, 0));
1198  } else
1199  llvm_unreachable("Unknown ABI in MipsISelDAGToDAG!");
1200 
1201  } else
1202  return false;
1203 
1204  if (ResVecTy != ViaVecTy) {
1205  // If LdiOp is writing to a different register class to ResVecTy, then
1206  // fix it up here. This COPY_TO_REGCLASS should never cause a move.v
1207  // since the source and destination register sets contain the same
1208  // registers.
1210  MVT ResVecTySimple = ResVecTy.getSimpleVT();
1211  const TargetRegisterClass *RC = TLI->getRegClassFor(ResVecTySimple);
1212  Res = CurDAG->getMachineNode(Mips::COPY_TO_REGCLASS, DL,
1213  ResVecTy, SDValue(Res, 0),
1214  CurDAG->getTargetConstant(RC->getID(), DL,
1215  MVT::i32));
1216  }
1217 
1218  ReplaceNode(Node, Res);
1219  return true;
1220  }
1221 
1222  }
1223 
1224  return false;
1225 }
1226 
1227 bool MipsSEDAGToDAGISel::
1228 SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
1229  std::vector<SDValue> &OutOps) {
1230  SDValue Base, Offset;
1231 
1232  switch(ConstraintID) {
1233  default:
1234  llvm_unreachable("Unexpected asm memory constraint");
1235  // All memory constraints can at least accept raw pointers.
1237  OutOps.push_back(Op);
1238  OutOps.push_back(CurDAG->getTargetConstant(0, SDLoc(Op), MVT::i32));
1239  return false;
1242  if (selectAddrRegImm16(Op, Base, Offset)) {
1243  OutOps.push_back(Base);
1244  OutOps.push_back(Offset);
1245  return false;
1246  }
1247  OutOps.push_back(Op);
1248  OutOps.push_back(CurDAG->getTargetConstant(0, SDLoc(Op), MVT::i32));
1249  return false;
1251  // The 'R' constraint is supposed to be much more complicated than this.
1252  // However, it's becoming less useful due to architectural changes and
1253  // ought to be replaced by other constraints such as 'ZC'.
1254  // For now, support 9-bit signed offsets which is supportable by all
1255  // subtargets for all instructions.
1256  if (selectAddrRegImm9(Op, Base, Offset)) {
1257  OutOps.push_back(Base);
1258  OutOps.push_back(Offset);
1259  return false;
1260  }
1261  OutOps.push_back(Op);
1262  OutOps.push_back(CurDAG->getTargetConstant(0, SDLoc(Op), MVT::i32));
1263  return false;
1265  // ZC matches whatever the pref, ll, and sc instructions can handle for the
1266  // given subtarget.
1267  if (Subtarget->inMicroMipsMode()) {
1268  // On microMIPS, they can handle 12-bit offsets.
1269  if (selectAddrRegImm12(Op, Base, Offset)) {
1270  OutOps.push_back(Base);
1271  OutOps.push_back(Offset);
1272  return false;
1273  }
1274  } else if (Subtarget->hasMips32r6()) {
1275  // On MIPS32r6/MIPS64r6, they can only handle 9-bit offsets.
1276  if (selectAddrRegImm9(Op, Base, Offset)) {
1277  OutOps.push_back(Base);
1278  OutOps.push_back(Offset);
1279  return false;
1280  }
1281  } else if (selectAddrRegImm16(Op, Base, Offset)) {
1282  // Prior to MIPS32r6/MIPS64r6, they can handle 16-bit offsets.
1283  OutOps.push_back(Base);
1284  OutOps.push_back(Offset);
1285  return false;
1286  }
1287  // In all cases, 0-bit offsets are acceptable.
1288  OutOps.push_back(Op);
1289  OutOps.push_back(CurDAG->getTargetConstant(0, SDLoc(Op), MVT::i32));
1290  return false;
1291  }
1292  return true;
1293 }
1294 
1297  return new MipsSEDAGToDAGISel(TM, OptLevel);
1298 }
bool isABI_FPXX() const
unsigned Log2(Align A)
Returns the log2 of the alignment.
Definition: Alignment.h:150
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
Definition: ISDOpcodes.h:595
SDNode * SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT)
These are used for target selectors to mutate the specified node to have the specified return type...
constexpr char Align[]
Key for Kernel::Arg::Metadata::mAlign.
EVT getValueType() const
Return the ValueType of the referenced return value.
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
bool hasMTHC1() const
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
typename SuperClass::const_iterator const_iterator
Definition: SmallVector.h:320
bool isConstantSplat(APInt &SplatValue, APInt &SplatUndef, unsigned &SplatBitSize, bool &HasAnyUndefs, unsigned MinSplatBits=0, bool isBigEndian=false) const
Check if this is a constant splat, and if so, find the smallest element size that splats the vector...
This class represents lattice values for constants.
Definition: AllocatorList.h:23
FunctionPass * createMipsSEISelDag(MipsTargetMachine &TM, CodeGenOpt::Level OptLevel)
bool inMips16Mode() const
Carry-setting nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:222
EVT getValueType(unsigned ResNo) const
Return the type of a specified result.
unsigned Reg
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
Definition: ValueTypes.h:252
TargetGlobalAddress - Like GlobalAddress, but the DAG does no folding or anything else with this node...
Definition: ISDOpcodes.h:130
unsigned getValueSizeInBits(unsigned ResNo) const
Returns MVT::getSizeInBits(getValueType(ResNo)).
MVT getSimpleValueType(unsigned ResNo) const
Return the type of a specified result as a simple type.
SDNode * getNode() const
get the SDNode which holds the desired result
bool isPHI() const
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
MachineFunction * MF
unsigned getBitWidth() const
Return the number of bits in the APInt.
Definition: APInt.h:1517
return AArch64::GPR64RegClass contains(Reg)
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
RESULT,OUTCHAIN = INTRINSIC_W_CHAIN(INCHAIN, INTRINSICID, arg1, ...) This node represents a target in...
Definition: ISDOpcodes.h:158
AnalysisUsage & addRequired()
static use_iterator use_end()
This file declares the MachineConstantPool class which is an abstract constant pool to keep track of ...
bool inMicroMipsMode() const
MachineSDNode * getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT)
These are used for target selectors to create a new node with specified return type(s), MachineInstr opcode, and operands.
const TargetLowering * TLI
bool isGP64bit() const
bool hasMips32r6() const
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:411
SDValue getEntryNode() const
Return the token chain corresponding to the entry of the function.
Definition: SelectionDAG.h:477
const DataLayout & getDataLayout() const
Definition: SelectionDAG.h:417
bool IsN32() const
Definition: MipsABIInfo.h:42
mir Rename Register Operands
unsigned getID() const
Return the register class ID number.
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
int64_t getSExtValue() const
bool IsN64() const
Definition: MipsABIInfo.h:43
unsigned getSizeInBits() const
Return the size of the specified value type in bits.
Definition: ValueTypes.h:291
virtual const TargetRegisterClass * getRegClassFor(MVT VT, bool isDivergent=false) const
Return the register class that should be used for the specified value type.
SDValue getTargetFrameIndex(int FI, EVT VT)
Definition: SelectionDAG.h:647
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:200
int32_t exactLogBase2() const
Definition: APInt.h:1796
const InstSeq & Analyze(uint64_t Imm, unsigned Size, bool LastInstrIsADDiu)
Analyze - Get an instruction sequence to load immediate Imm.
void setReg(Register Reg)
Change the register this operand corresponds to.
SDValue getTargetConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isOpaque=false)
Definition: SelectionDAG.h:596
RESULT = INTRINSIC_WO_CHAIN(INTRINSICID, arg1, arg2, ...) This node represents a target intrinsic fun...
Definition: ISDOpcodes.h:150
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:131
BUILD_VECTOR(ELT0, ELT1, ELT2, ELT3,...) - Return a vector with the specified, possibly variable...
Definition: ISDOpcodes.h:358
OUTCHAIN = INTRINSIC_VOID(INCHAIN, INTRINSICID, arg1, arg2, ...) This node represents a target intrin...
Definition: ISDOpcodes.h:165
CodeGenOpt::Level OptLevel
unsigned const MachineRegisterInfo * MRI
unsigned countPopulation() const
Count the number of bits set.
Definition: APInt.h:1666
const MipsSubtarget * Subtarget
Keep a pointer to the MipsSubtarget around so that we can make the right decision when generating cod...
Machine Value Type.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
bool isPseudo(QueryType Type=IgnoreBundle) const
Return true if this is a pseudo instruction that doesn&#39;t correspond to a real machine instruction...
Definition: MachineInstr.h:637
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
const SDValue & getOperand(unsigned Num) const
Carry-using nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:231
Represent the analysis usage information of a pass.
bool isExactlyValue(double V) const
We don&#39;t rely on operator== working on double values, as it returns true for things that are clearly ...
bool isBaseWithConstantOffset(SDValue Op) const
Return true if the specified operand is an ISD::ADD with a ConstantSDNode on the right-hand side...
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:284
bool isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx=nullptr) const
Return true if the use operand of the specified index is tied to a def operand.
bool IsO32() const
Definition: MipsABIInfo.h:41
Class to represent integer types.
Definition: DerivedTypes.h:40
bool isIntN(unsigned N) const
Check if this APInt has an N-bits unsigned integer value.
Definition: APInt.h:449
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function. ...
Definition: Function.cpp:205
static MachineOperand CreateReg(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)
virtual MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
Extended Value Type.
Definition: ValueTypes.h:33
bool isIntN(unsigned N, int64_t x)
Checks if an signed integer fits into the given (dynamic) bit width.
Definition: MathExtras.h:397
unsigned getNumOperands() const
Return the number of values used by this operation.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:40
static IntegerType * get(LLVMContext &C, unsigned NumBits)
This static method is the primary way of constructing an IntegerType.
Definition: Type.cpp:239
This is the shared class of boolean and integer constants.
Definition: Constants.h:83
constexpr bool isInt< 32 >(int64_t x)
Definition: MathExtras.h:308
void addOperand(MachineFunction &MF, const MachineOperand &Op)
Add the specified operand to the instruction.
bool isLittle() const
EVT getVectorElementType() const
Given a vector type, return the type of each element.
Definition: ValueTypes.h:264
MachineOperand class - Representation of each machine instruction operand.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
static Constant * get(Type *Ty, uint64_t V, bool isSigned=false)
If Ty is a vector type, return a Constant with a splat of the given value.
Definition: Constants.cpp:653
Represents one node in the SelectionDAG.
bool isAligned(Align Lhs, uint64_t SizeInBytes)
Checks that SizeInBytes is a multiple of the alignment.
Definition: Alignment.h:121
int64_t getImm() const
SDValue getCopyToReg(SDValue Chain, const SDLoc &dl, unsigned Reg, SDValue N)
Definition: SelectionDAG.h:695
const Function & getFunction() const
Return the LLVM function that this machine code represents.
Class for arbitrary precision integers.
Definition: APInt.h:69
A "pseudo-class" with methods for operating on BUILD_VECTORs.
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
Definition: MachineInstr.h:64
This file provides various utilities for inspecting and working with the control flow graph in LLVM I...
SDValue getCopyFromReg(SDValue Chain, const SDLoc &dl, unsigned Reg, EVT VT)
Definition: SelectionDAG.h:721
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
use_iterator use_begin(unsigned RegNo) const
xray Insert XRay ops
bool is128BitVector() const
Return true if this is a 128-bit vector type.
Definition: ValueTypes.h:181
bool isPositionIndependent() const
#define N
MipsFunctionInfo - This class is derived from MachineFunction private Mips target-specific informatio...
LLVM_NODISCARD std::enable_if<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:332
uint32_t Size
Definition: Profile.cpp:46
bool useOddSPReg() const
MipsSEDAGToDAGISel(MipsTargetMachine &TM, CodeGenOpt::Level OL)
unsigned getOpcode() const
bool isSignedIntN(unsigned N) const
Check if this APInt has an N-bits signed integer value.
Definition: APInt.h:455
SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
Create a ConstantSDNode wrapping a constant value.
const TargetLowering * getTargetLowering() const
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
LLVM Value Representation.
Definition: Value.h:73
uint64_t getConstantOperandVal(unsigned Num) const
Helper method returns the integer value of a ConstantSDNode operand.
SDValue getRegister(unsigned Reg, EVT VT)
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:265
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:80
IRTranslator LLVM IR MI
void ReplaceNode(SDNode *F, SDNode *T)
Replace all uses of F with T, then remove F from the DAG.
Legacy analysis pass which computes a DominatorTree.
Definition: Dominators.h:259
Register getReg() const
getReg - Returns the register number.
const SDValue & getOperand(unsigned i) const
uint64_t getZExtValue() const
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:416
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
reg_begin/reg_end - Provide iteration support to walk over all definitions and uses of a register wit...
bool isFP64bit() const
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
bool runOnMachineFunction(MachineFunction &MF) override
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
bool hasMSA() const
IntegerType * Int32Ty