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MipsSEISelDAGToDAG.cpp
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1 //===-- MipsSEISelDAGToDAG.cpp - A Dag to Dag Inst Selector for MipsSE ----===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // Subclass of MipsDAGToDAGISel specialized for mips32/64.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "MipsSEISelDAGToDAG.h"
15 #include "Mips.h"
16 #include "MipsAnalyzeImmediate.h"
17 #include "MipsMachineFunction.h"
18 #include "MipsRegisterInfo.h"
25 #include "llvm/IR/CFG.h"
26 #include "llvm/IR/Dominators.h"
27 #include "llvm/IR/GlobalValue.h"
28 #include "llvm/IR/Instructions.h"
29 #include "llvm/IR/Intrinsics.h"
30 #include "llvm/IR/Type.h"
31 #include "llvm/Support/Debug.h"
35 using namespace llvm;
36 
37 #define DEBUG_TYPE "mips-isel"
38 
39 bool MipsSEDAGToDAGISel::runOnMachineFunction(MachineFunction &MF) {
40  Subtarget = &static_cast<const MipsSubtarget &>(MF.getSubtarget());
41  if (Subtarget->inMips16Mode())
42  return false;
44 }
45 
46 void MipsSEDAGToDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
49 }
50 
51 void MipsSEDAGToDAGISel::addDSPCtrlRegOperands(bool IsDef, MachineInstr &MI,
53  MachineInstrBuilder MIB(MF, &MI);
54  unsigned Mask = MI.getOperand(1).getImm();
55  unsigned Flag =
57 
58  if (Mask & 1)
59  MIB.addReg(Mips::DSPPos, Flag);
60 
61  if (Mask & 2)
62  MIB.addReg(Mips::DSPSCount, Flag);
63 
64  if (Mask & 4)
65  MIB.addReg(Mips::DSPCarry, Flag);
66 
67  if (Mask & 8)
68  MIB.addReg(Mips::DSPOutFlag, Flag);
69 
70  if (Mask & 16)
71  MIB.addReg(Mips::DSPCCond, Flag);
72 
73  if (Mask & 32)
74  MIB.addReg(Mips::DSPEFI, Flag);
75 }
76 
77 unsigned MipsSEDAGToDAGISel::getMSACtrlReg(const SDValue RegIdx) const {
78  uint64_t RegNum = cast<ConstantSDNode>(RegIdx)->getZExtValue();
79  return Mips::MSACtrlRegClass.getRegister(RegNum);
80 }
81 
82 bool MipsSEDAGToDAGISel::replaceUsesWithZeroReg(MachineRegisterInfo *MRI,
83  const MachineInstr& MI) {
84  unsigned DstReg = 0, ZeroReg = 0;
85 
86  // Check if MI is "addiu $dst, $zero, 0" or "daddiu $dst, $zero, 0".
87  if ((MI.getOpcode() == Mips::ADDiu) &&
88  (MI.getOperand(1).getReg() == Mips::ZERO) &&
89  (MI.getOperand(2).isImm()) &&
90  (MI.getOperand(2).getImm() == 0)) {
91  DstReg = MI.getOperand(0).getReg();
92  ZeroReg = Mips::ZERO;
93  } else if ((MI.getOpcode() == Mips::DADDiu) &&
94  (MI.getOperand(1).getReg() == Mips::ZERO_64) &&
95  (MI.getOperand(2).isImm()) &&
96  (MI.getOperand(2).getImm() == 0)) {
97  DstReg = MI.getOperand(0).getReg();
98  ZeroReg = Mips::ZERO_64;
99  }
100 
101  if (!DstReg)
102  return false;
103 
104  // Replace uses with ZeroReg.
105  for (MachineRegisterInfo::use_iterator U = MRI->use_begin(DstReg),
106  E = MRI->use_end(); U != E;) {
107  MachineOperand &MO = *U;
108  unsigned OpNo = U.getOperandNo();
109  MachineInstr *MI = MO.getParent();
110  ++U;
111 
112  // Do not replace if it is a phi's operand or is tied to def operand.
113  if (MI->isPHI() || MI->isRegTiedToDefOperand(OpNo) || MI->isPseudo())
114  continue;
115 
116  // Also, we have to check that the register class of the operand
117  // contains the zero register.
118  if (!MRI->getRegClass(MO.getReg())->contains(ZeroReg))
119  continue;
120 
121  MO.setReg(ZeroReg);
122  }
123 
124  return true;
125 }
126 
127 void MipsSEDAGToDAGISel::emitMCountABI(MachineInstr &MI, MachineBasicBlock &MBB,
128  MachineFunction &MF) {
129  MachineInstrBuilder MIB(MF, &MI);
130  if (!Subtarget->isABI_O32()) { // N32, N64
131  // Save current return address.
132  BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(Mips::OR64))
133  .addDef(Mips::AT_64)
134  .addUse(Mips::RA_64, RegState::Undef)
135  .addUse(Mips::ZERO_64);
136  // Stops instruction above from being removed later on.
137  MIB.addUse(Mips::AT_64, RegState::Implicit);
138  } else { // O32
139  // Save current return address.
140  BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(Mips::OR))
141  .addDef(Mips::AT)
143  .addUse(Mips::ZERO);
144  // _mcount pops 2 words from stack.
145  BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(Mips::ADDiu))
146  .addDef(Mips::SP)
147  .addUse(Mips::SP)
148  .addImm(-8);
149  // Stops first instruction above from being removed later on.
150  MIB.addUse(Mips::AT, RegState::Implicit);
151  }
152 }
153 
154 void MipsSEDAGToDAGISel::processFunctionAfterISel(MachineFunction &MF) {
155  MF.getInfo<MipsFunctionInfo>()->initGlobalBaseReg();
156 
157  MachineRegisterInfo *MRI = &MF.getRegInfo();
158 
159  for (auto &MBB: MF) {
160  for (auto &MI: MBB) {
161  switch (MI.getOpcode()) {
162  case Mips::RDDSP:
163  addDSPCtrlRegOperands(false, MI, MF);
164  break;
165  case Mips::WRDSP:
166  addDSPCtrlRegOperands(true, MI, MF);
167  break;
168  case Mips::BuildPairF64_64:
169  case Mips::ExtractElementF64_64:
170  if (!Subtarget->useOddSPReg()) {
171  MI.addOperand(MachineOperand::CreateReg(Mips::SP, false, true));
172  break;
173  }
175  case Mips::BuildPairF64:
177  if (Subtarget->isABI_FPXX() && !Subtarget->hasMTHC1())
178  MI.addOperand(MachineOperand::CreateReg(Mips::SP, false, true));
179  break;
180  case Mips::JAL:
181  case Mips::JAL_MM:
182  if (MI.getOperand(0).isGlobal() &&
183  MI.getOperand(0).getGlobal()->getGlobalIdentifier() == "_mcount")
184  emitMCountABI(MI, MBB, MF);
185  break;
186  case Mips::JALRPseudo:
187  case Mips::JALR64Pseudo:
188  case Mips::JALR16_MM:
189  if (MI.getOperand(2).isMCSymbol() &&
190  MI.getOperand(2).getMCSymbol()->getName() == "_mcount")
191  emitMCountABI(MI, MBB, MF);
192  break;
193  case Mips::JALR:
194  if (MI.getOperand(3).isMCSymbol() &&
195  MI.getOperand(3).getMCSymbol()->getName() == "_mcount")
196  emitMCountABI(MI, MBB, MF);
197  break;
198  default:
199  replaceUsesWithZeroReg(MRI, MI);
200  }
201  }
202  }
203 }
204 
205 void MipsSEDAGToDAGISel::selectAddE(SDNode *Node, const SDLoc &DL) const {
206  SDValue InFlag = Node->getOperand(2);
207  unsigned Opc = InFlag.getOpcode();
208  SDValue LHS = Node->getOperand(0), RHS = Node->getOperand(1);
209  EVT VT = LHS.getValueType();
210 
211  // In the base case, we can rely on the carry bit from the addsc
212  // instruction.
213  if (Opc == ISD::ADDC) {
214  SDValue Ops[3] = {LHS, RHS, InFlag};
215  CurDAG->SelectNodeTo(Node, Mips::ADDWC, VT, MVT::Glue, Ops);
216  return;
217  }
218 
219  assert(Opc == ISD::ADDE && "ISD::ADDE not in a chain of ADDE nodes!");
220 
221  // The more complex case is when there is a chain of ISD::ADDE nodes like:
222  // (adde (adde (adde (addc a b) c) d) e).
223  //
224  // The addwc instruction does not write to the carry bit, instead it writes
225  // to bit 20 of the dsp control register. To match this series of nodes, each
226  // intermediate adde node must be expanded to write the carry bit before the
227  // addition.
228 
229  // Start by reading the overflow field for addsc and moving the value to the
230  // carry field. The usage of 1 here with MipsISD::RDDSP / Mips::WRDSP
231  // corresponds to reading/writing the entire control register to/from a GPR.
232 
233  SDValue CstOne = CurDAG->getTargetConstant(1, DL, MVT::i32);
234 
235  SDValue OuFlag = CurDAG->getTargetConstant(20, DL, MVT::i32);
236 
237  SDNode *DSPCtrlField =
238  CurDAG->getMachineNode(Mips::RDDSP, DL, MVT::i32, MVT::Glue, CstOne, InFlag);
239 
240  SDNode *Carry = CurDAG->getMachineNode(
241  Mips::EXT, DL, MVT::i32, SDValue(DSPCtrlField, 0), OuFlag, CstOne);
242 
243  SDValue Ops[4] = {SDValue(DSPCtrlField, 0),
244  CurDAG->getTargetConstant(6, DL, MVT::i32), CstOne,
245  SDValue(Carry, 0)};
246  SDNode *DSPCFWithCarry = CurDAG->getMachineNode(Mips::INS, DL, MVT::i32, Ops);
247 
248  // My reading of the MIPS DSP 3.01 specification isn't as clear as I
249  // would like about whether bit 20 always gets overwritten by addwc.
250  // Hence take an extremely conservative view and presume it's sticky. We
251  // therefore need to clear it.
252 
253  SDValue Zero = CurDAG->getRegister(Mips::ZERO, MVT::i32);
254 
255  SDValue InsOps[4] = {Zero, OuFlag, CstOne, SDValue(DSPCFWithCarry, 0)};
256  SDNode *DSPCtrlFinal = CurDAG->getMachineNode(Mips::INS, DL, MVT::i32, InsOps);
257 
258  SDNode *WrDSP = CurDAG->getMachineNode(Mips::WRDSP, DL, MVT::Glue,
259  SDValue(DSPCtrlFinal, 0), CstOne);
260 
261  SDValue Operands[3] = {LHS, RHS, SDValue(WrDSP, 0)};
262  CurDAG->SelectNodeTo(Node, Mips::ADDWC, VT, MVT::Glue, Operands);
263 }
264 
265 /// Match frameindex
266 bool MipsSEDAGToDAGISel::selectAddrFrameIndex(SDValue Addr, SDValue &Base,
267  SDValue &Offset) const {
268  if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
269  EVT ValTy = Addr.getValueType();
270 
271  Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
272  Offset = CurDAG->getTargetConstant(0, SDLoc(Addr), ValTy);
273  return true;
274  }
275  return false;
276 }
277 
278 /// Match frameindex+offset and frameindex|offset
279 bool MipsSEDAGToDAGISel::selectAddrFrameIndexOffset(
280  SDValue Addr, SDValue &Base, SDValue &Offset, unsigned OffsetBits,
281  unsigned ShiftAmount = 0) const {
282  if (CurDAG->isBaseWithConstantOffset(Addr)) {
284  if (isIntN(OffsetBits + ShiftAmount, CN->getSExtValue())) {
285  EVT ValTy = Addr.getValueType();
286 
287  // If the first operand is a FI, get the TargetFI Node
288  if (FrameIndexSDNode *FIN =
289  dyn_cast<FrameIndexSDNode>(Addr.getOperand(0)))
290  Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
291  else {
292  Base = Addr.getOperand(0);
293  // If base is a FI, additional offset calculation is done in
294  // eliminateFrameIndex, otherwise we need to check the alignment
295  const Align Alignment(1ULL << ShiftAmount);
296  if (!isAligned(Alignment, CN->getZExtValue()))
297  return false;
298  }
299 
300  Offset = CurDAG->getTargetConstant(CN->getZExtValue(), SDLoc(Addr),
301  ValTy);
302  return true;
303  }
304  }
305  return false;
306 }
307 
308 /// ComplexPattern used on MipsInstrInfo
309 /// Used on Mips Load/Store instructions
310 bool MipsSEDAGToDAGISel::selectAddrRegImm(SDValue Addr, SDValue &Base,
311  SDValue &Offset) const {
312  // if Address is FI, get the TargetFrameIndex.
313  if (selectAddrFrameIndex(Addr, Base, Offset))
314  return true;
315 
316  // on PIC code Load GA
317  if (Addr.getOpcode() == MipsISD::Wrapper) {
318  Base = Addr.getOperand(0);
319  Offset = Addr.getOperand(1);
320  return true;
321  }
322 
323  if (!TM.isPositionIndependent()) {
324  if ((Addr.getOpcode() == ISD::TargetExternalSymbol ||
326  return false;
327  }
328 
329  // Addresses of the form FI+const or FI|const
330  if (selectAddrFrameIndexOffset(Addr, Base, Offset, 16))
331  return true;
332 
333  // Operand is a result from an ADD.
334  if (Addr.getOpcode() == ISD::ADD) {
335  // When loading from constant pools, load the lower address part in
336  // the instruction itself. Example, instead of:
337  // lui $2, %hi($CPI1_0)
338  // addiu $2, $2, %lo($CPI1_0)
339  // lwc1 $f0, 0($2)
340  // Generate:
341  // lui $2, %hi($CPI1_0)
342  // lwc1 $f0, %lo($CPI1_0)($2)
343  if (Addr.getOperand(1).getOpcode() == MipsISD::Lo ||
344  Addr.getOperand(1).getOpcode() == MipsISD::GPRel) {
345  SDValue Opnd0 = Addr.getOperand(1).getOperand(0);
346  if (isa<ConstantPoolSDNode>(Opnd0) || isa<GlobalAddressSDNode>(Opnd0) ||
347  isa<JumpTableSDNode>(Opnd0)) {
348  Base = Addr.getOperand(0);
349  Offset = Opnd0;
350  return true;
351  }
352  }
353  }
354 
355  return false;
356 }
357 
358 /// ComplexPattern used on MipsInstrInfo
359 /// Used on Mips Load/Store instructions
360 bool MipsSEDAGToDAGISel::selectAddrDefault(SDValue Addr, SDValue &Base,
361  SDValue &Offset) const {
362  Base = Addr;
363  Offset = CurDAG->getTargetConstant(0, SDLoc(Addr), Addr.getValueType());
364  return true;
365 }
366 
367 bool MipsSEDAGToDAGISel::selectIntAddr(SDValue Addr, SDValue &Base,
368  SDValue &Offset) const {
369  return selectAddrRegImm(Addr, Base, Offset) ||
370  selectAddrDefault(Addr, Base, Offset);
371 }
372 
373 bool MipsSEDAGToDAGISel::selectAddrRegImm9(SDValue Addr, SDValue &Base,
374  SDValue &Offset) const {
375  if (selectAddrFrameIndex(Addr, Base, Offset))
376  return true;
377 
378  if (selectAddrFrameIndexOffset(Addr, Base, Offset, 9))
379  return true;
380 
381  return false;
382 }
383 
384 /// Used on microMIPS LWC2, LDC2, SWC2 and SDC2 instructions (11-bit offset)
385 bool MipsSEDAGToDAGISel::selectAddrRegImm11(SDValue Addr, SDValue &Base,
386  SDValue &Offset) const {
387  if (selectAddrFrameIndex(Addr, Base, Offset))
388  return true;
389 
390  if (selectAddrFrameIndexOffset(Addr, Base, Offset, 11))
391  return true;
392 
393  return false;
394 }
395 
396 /// Used on microMIPS Load/Store unaligned instructions (12-bit offset)
397 bool MipsSEDAGToDAGISel::selectAddrRegImm12(SDValue Addr, SDValue &Base,
398  SDValue &Offset) const {
399  if (selectAddrFrameIndex(Addr, Base, Offset))
400  return true;
401 
402  if (selectAddrFrameIndexOffset(Addr, Base, Offset, 12))
403  return true;
404 
405  return false;
406 }
407 
408 bool MipsSEDAGToDAGISel::selectAddrRegImm16(SDValue Addr, SDValue &Base,
409  SDValue &Offset) const {
410  if (selectAddrFrameIndex(Addr, Base, Offset))
411  return true;
412 
413  if (selectAddrFrameIndexOffset(Addr, Base, Offset, 16))
414  return true;
415 
416  return false;
417 }
418 
419 bool MipsSEDAGToDAGISel::selectIntAddr11MM(SDValue Addr, SDValue &Base,
420  SDValue &Offset) const {
421  return selectAddrRegImm11(Addr, Base, Offset) ||
422  selectAddrDefault(Addr, Base, Offset);
423 }
424 
425 bool MipsSEDAGToDAGISel::selectIntAddr12MM(SDValue Addr, SDValue &Base,
426  SDValue &Offset) const {
427  return selectAddrRegImm12(Addr, Base, Offset) ||
428  selectAddrDefault(Addr, Base, Offset);
429 }
430 
431 bool MipsSEDAGToDAGISel::selectIntAddr16MM(SDValue Addr, SDValue &Base,
432  SDValue &Offset) const {
433  return selectAddrRegImm16(Addr, Base, Offset) ||
434  selectAddrDefault(Addr, Base, Offset);
435 }
436 
437 bool MipsSEDAGToDAGISel::selectIntAddrLSL2MM(SDValue Addr, SDValue &Base,
438  SDValue &Offset) const {
439  if (selectAddrFrameIndexOffset(Addr, Base, Offset, 7)) {
440  if (isa<FrameIndexSDNode>(Base))
441  return false;
442 
443  if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Offset)) {
444  unsigned CnstOff = CN->getZExtValue();
445  return (CnstOff == (CnstOff & 0x3c));
446  }
447 
448  return false;
449  }
450 
451  // For all other cases where "lw" would be selected, don't select "lw16"
452  // because it would result in additional instructions to prepare operands.
453  if (selectAddrRegImm(Addr, Base, Offset))
454  return false;
455 
456  return selectAddrDefault(Addr, Base, Offset);
457 }
458 
459 bool MipsSEDAGToDAGISel::selectIntAddrSImm10(SDValue Addr, SDValue &Base,
460  SDValue &Offset) const {
461 
462  if (selectAddrFrameIndex(Addr, Base, Offset))
463  return true;
464 
465  if (selectAddrFrameIndexOffset(Addr, Base, Offset, 10))
466  return true;
467 
468  return selectAddrDefault(Addr, Base, Offset);
469 }
470 
471 bool MipsSEDAGToDAGISel::selectIntAddrSImm10Lsl1(SDValue Addr, SDValue &Base,
472  SDValue &Offset) const {
473  if (selectAddrFrameIndex(Addr, Base, Offset))
474  return true;
475 
476  if (selectAddrFrameIndexOffset(Addr, Base, Offset, 10, 1))
477  return true;
478 
479  return selectAddrDefault(Addr, Base, Offset);
480 }
481 
482 bool MipsSEDAGToDAGISel::selectIntAddrSImm10Lsl2(SDValue Addr, SDValue &Base,
483  SDValue &Offset) const {
484  if (selectAddrFrameIndex(Addr, Base, Offset))
485  return true;
486 
487  if (selectAddrFrameIndexOffset(Addr, Base, Offset, 10, 2))
488  return true;
489 
490  return selectAddrDefault(Addr, Base, Offset);
491 }
492 
493 bool MipsSEDAGToDAGISel::selectIntAddrSImm10Lsl3(SDValue Addr, SDValue &Base,
494  SDValue &Offset) const {
495  if (selectAddrFrameIndex(Addr, Base, Offset))
496  return true;
497 
498  if (selectAddrFrameIndexOffset(Addr, Base, Offset, 10, 3))
499  return true;
500 
501  return selectAddrDefault(Addr, Base, Offset);
502 }
503 
504 // Select constant vector splats.
505 //
506 // Returns true and sets Imm if:
507 // * MSA is enabled
508 // * N is a ISD::BUILD_VECTOR representing a constant splat
509 bool MipsSEDAGToDAGISel::selectVSplat(SDNode *N, APInt &Imm,
510  unsigned MinSizeInBits) const {
511  if (!Subtarget->hasMSA())
512  return false;
513 
515 
516  if (!Node)
517  return false;
518 
519  APInt SplatValue, SplatUndef;
520  unsigned SplatBitSize;
521  bool HasAnyUndefs;
522 
523  if (!Node->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs,
524  MinSizeInBits, !Subtarget->isLittle()))
525  return false;
526 
527  Imm = SplatValue;
528 
529  return true;
530 }
531 
532 // Select constant vector splats.
533 //
534 // In addition to the requirements of selectVSplat(), this function returns
535 // true and sets Imm if:
536 // * The splat value is the same width as the elements of the vector
537 // * The splat value fits in an integer with the specified signed-ness and
538 // width.
539 //
540 // This function looks through ISD::BITCAST nodes.
541 // TODO: This might not be appropriate for big-endian MSA since BITCAST is
542 // sometimes a shuffle in big-endian mode.
543 //
544 // It's worth noting that this function is not used as part of the selection
545 // of ldi.[bhwd] since it does not permit using the wrong-typed ldi.[bhwd]
546 // instruction to achieve the desired bit pattern. ldi.[bhwd] is selected in
547 // MipsSEDAGToDAGISel::selectNode.
548 bool MipsSEDAGToDAGISel::
549 selectVSplatCommon(SDValue N, SDValue &Imm, bool Signed,
550  unsigned ImmBitSize) const {
551  APInt ImmValue;
552  EVT EltTy = N->getValueType(0).getVectorElementType();
553 
554  if (N->getOpcode() == ISD::BITCAST)
555  N = N->getOperand(0);
556 
557  if (selectVSplat(N.getNode(), ImmValue, EltTy.getSizeInBits()) &&
558  ImmValue.getBitWidth() == EltTy.getSizeInBits()) {
559 
560  if (( Signed && ImmValue.isSignedIntN(ImmBitSize)) ||
561  (!Signed && ImmValue.isIntN(ImmBitSize))) {
562  Imm = CurDAG->getTargetConstant(ImmValue, SDLoc(N), EltTy);
563  return true;
564  }
565  }
566 
567  return false;
568 }
569 
570 // Select constant vector splats.
571 bool MipsSEDAGToDAGISel::
572 selectVSplatUimm1(SDValue N, SDValue &Imm) const {
573  return selectVSplatCommon(N, Imm, false, 1);
574 }
575 
576 bool MipsSEDAGToDAGISel::
577 selectVSplatUimm2(SDValue N, SDValue &Imm) const {
578  return selectVSplatCommon(N, Imm, false, 2);
579 }
580 
581 bool MipsSEDAGToDAGISel::
582 selectVSplatUimm3(SDValue N, SDValue &Imm) const {
583  return selectVSplatCommon(N, Imm, false, 3);
584 }
585 
586 // Select constant vector splats.
587 bool MipsSEDAGToDAGISel::
588 selectVSplatUimm4(SDValue N, SDValue &Imm) const {
589  return selectVSplatCommon(N, Imm, false, 4);
590 }
591 
592 // Select constant vector splats.
593 bool MipsSEDAGToDAGISel::
594 selectVSplatUimm5(SDValue N, SDValue &Imm) const {
595  return selectVSplatCommon(N, Imm, false, 5);
596 }
597 
598 // Select constant vector splats.
599 bool MipsSEDAGToDAGISel::
600 selectVSplatUimm6(SDValue N, SDValue &Imm) const {
601  return selectVSplatCommon(N, Imm, false, 6);
602 }
603 
604 // Select constant vector splats.
605 bool MipsSEDAGToDAGISel::
606 selectVSplatUimm8(SDValue N, SDValue &Imm) const {
607  return selectVSplatCommon(N, Imm, false, 8);
608 }
609 
610 // Select constant vector splats.
611 bool MipsSEDAGToDAGISel::
612 selectVSplatSimm5(SDValue N, SDValue &Imm) const {
613  return selectVSplatCommon(N, Imm, true, 5);
614 }
615 
616 // Select constant vector splats whose value is a power of 2.
617 //
618 // In addition to the requirements of selectVSplat(), this function returns
619 // true and sets Imm if:
620 // * The splat value is the same width as the elements of the vector
621 // * The splat value is a power of two.
622 //
623 // This function looks through ISD::BITCAST nodes.
624 // TODO: This might not be appropriate for big-endian MSA since BITCAST is
625 // sometimes a shuffle in big-endian mode.
626 bool MipsSEDAGToDAGISel::selectVSplatUimmPow2(SDValue N, SDValue &Imm) const {
627  APInt ImmValue;
628  EVT EltTy = N->getValueType(0).getVectorElementType();
629 
630  if (N->getOpcode() == ISD::BITCAST)
631  N = N->getOperand(0);
632 
633  if (selectVSplat(N.getNode(), ImmValue, EltTy.getSizeInBits()) &&
634  ImmValue.getBitWidth() == EltTy.getSizeInBits()) {
635  int32_t Log2 = ImmValue.exactLogBase2();
636 
637  if (Log2 != -1) {
638  Imm = CurDAG->getTargetConstant(Log2, SDLoc(N), EltTy);
639  return true;
640  }
641  }
642 
643  return false;
644 }
645 
646 // Select constant vector splats whose value only has a consecutive sequence
647 // of left-most bits set (e.g. 0b11...1100...00).
648 //
649 // In addition to the requirements of selectVSplat(), this function returns
650 // true and sets Imm if:
651 // * The splat value is the same width as the elements of the vector
652 // * The splat value is a consecutive sequence of left-most bits.
653 //
654 // This function looks through ISD::BITCAST nodes.
655 // TODO: This might not be appropriate for big-endian MSA since BITCAST is
656 // sometimes a shuffle in big-endian mode.
657 bool MipsSEDAGToDAGISel::selectVSplatMaskL(SDValue N, SDValue &Imm) const {
658  APInt ImmValue;
659  EVT EltTy = N->getValueType(0).getVectorElementType();
660 
661  if (N->getOpcode() == ISD::BITCAST)
662  N = N->getOperand(0);
663 
664  if (selectVSplat(N.getNode(), ImmValue, EltTy.getSizeInBits()) &&
665  ImmValue.getBitWidth() == EltTy.getSizeInBits()) {
666  // Extract the run of set bits starting with bit zero from the bitwise
667  // inverse of ImmValue, and test that the inverse of this is the same
668  // as the original value.
669  if (ImmValue == ~(~ImmValue & ~(~ImmValue + 1))) {
670 
671  Imm = CurDAG->getTargetConstant(ImmValue.countPopulation() - 1, SDLoc(N),
672  EltTy);
673  return true;
674  }
675  }
676 
677  return false;
678 }
679 
680 // Select constant vector splats whose value only has a consecutive sequence
681 // of right-most bits set (e.g. 0b00...0011...11).
682 //
683 // In addition to the requirements of selectVSplat(), this function returns
684 // true and sets Imm if:
685 // * The splat value is the same width as the elements of the vector
686 // * The splat value is a consecutive sequence of right-most bits.
687 //
688 // This function looks through ISD::BITCAST nodes.
689 // TODO: This might not be appropriate for big-endian MSA since BITCAST is
690 // sometimes a shuffle in big-endian mode.
691 bool MipsSEDAGToDAGISel::selectVSplatMaskR(SDValue N, SDValue &Imm) const {
692  APInt ImmValue;
693  EVT EltTy = N->getValueType(0).getVectorElementType();
694 
695  if (N->getOpcode() == ISD::BITCAST)
696  N = N->getOperand(0);
697 
698  if (selectVSplat(N.getNode(), ImmValue, EltTy.getSizeInBits()) &&
699  ImmValue.getBitWidth() == EltTy.getSizeInBits()) {
700  // Extract the run of set bits starting with bit zero, and test that the
701  // result is the same as the original value
702  if (ImmValue == (ImmValue & ~(ImmValue + 1))) {
703  Imm = CurDAG->getTargetConstant(ImmValue.countPopulation() - 1, SDLoc(N),
704  EltTy);
705  return true;
706  }
707  }
708 
709  return false;
710 }
711 
712 bool MipsSEDAGToDAGISel::selectVSplatUimmInvPow2(SDValue N,
713  SDValue &Imm) const {
714  APInt ImmValue;
715  EVT EltTy = N->getValueType(0).getVectorElementType();
716 
717  if (N->getOpcode() == ISD::BITCAST)
718  N = N->getOperand(0);
719 
720  if (selectVSplat(N.getNode(), ImmValue, EltTy.getSizeInBits()) &&
721  ImmValue.getBitWidth() == EltTy.getSizeInBits()) {
722  int32_t Log2 = (~ImmValue).exactLogBase2();
723 
724  if (Log2 != -1) {
725  Imm = CurDAG->getTargetConstant(Log2, SDLoc(N), EltTy);
726  return true;
727  }
728  }
729 
730  return false;
731 }
732 
733 bool MipsSEDAGToDAGISel::trySelect(SDNode *Node) {
734  unsigned Opcode = Node->getOpcode();
735  SDLoc DL(Node);
736 
737  ///
738  // Instruction Selection not handled by the auto-generated
739  // tablegen selection should be handled here.
740  ///
741  switch(Opcode) {
742  default: break;
743 
744  case Mips::PseudoD_SELECT_I:
745  case Mips::PseudoD_SELECT_I64: {
747  SDValue cond = Node->getOperand(0);
748  SDValue Hi1 = Node->getOperand(1);
749  SDValue Lo1 = Node->getOperand(2);
750  SDValue Hi2 = Node->getOperand(3);
751  SDValue Lo2 = Node->getOperand(4);
752 
753  SDValue ops[] = {cond, Hi1, Lo1, Hi2, Lo2};
754  EVT NodeTys[] = {VT, VT};
756  ? Mips::PseudoD_SELECT_I64
757  : Mips::PseudoD_SELECT_I,
758  DL, NodeTys, ops));
759  return true;
760  }
761 
762  case ISD::ADDE: {
763  selectAddE(Node, DL);
764  return true;
765  }
766 
767  case ISD::ConstantFP: {
768  auto *CN = cast<ConstantFPSDNode>(Node);
769  if (Node->getValueType(0) == MVT::f64 && CN->isExactlyValue(+0.0)) {
770  if (Subtarget->isGP64bit()) {
772  Mips::ZERO_64, MVT::i64);
773  ReplaceNode(Node,
774  CurDAG->getMachineNode(Mips::DMTC1, DL, MVT::f64, Zero));
775  } else if (Subtarget->isFP64bit()) {
777  Mips::ZERO, MVT::i32);
778  ReplaceNode(Node, CurDAG->getMachineNode(Mips::BuildPairF64_64, DL,
779  MVT::f64, Zero, Zero));
780  } else {
782  Mips::ZERO, MVT::i32);
784  MVT::f64, Zero, Zero));
785  }
786  return true;
787  }
788  break;
789  }
790 
791  case ISD::Constant: {
792  auto *CN = cast<ConstantSDNode>(Node);
793  int64_t Imm = CN->getSExtValue();
794  unsigned Size = CN->getValueSizeInBits(0);
795 
796  if (isInt<32>(Imm))
797  break;
798 
799  MipsAnalyzeImmediate AnalyzeImm;
800 
801  const MipsAnalyzeImmediate::InstSeq &Seq =
802  AnalyzeImm.Analyze(Imm, Size, false);
803 
805  SDLoc DL(CN);
806  SDNode *RegOpnd;
807  SDValue ImmOpnd = CurDAG->getTargetConstant(SignExtend64<16>(Inst->ImmOpnd),
808  DL, MVT::i64);
809 
810  // The first instruction can be a LUi which is different from other
811  // instructions (ADDiu, ORI and SLL) in that it does not have a register
812  // operand.
813  if (Inst->Opc == Mips::LUi64)
814  RegOpnd = CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64, ImmOpnd);
815  else
816  RegOpnd =
817  CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64,
818  CurDAG->getRegister(Mips::ZERO_64, MVT::i64),
819  ImmOpnd);
820 
821  // The remaining instructions in the sequence are handled here.
822  for (++Inst; Inst != Seq.end(); ++Inst) {
823  ImmOpnd = CurDAG->getTargetConstant(SignExtend64<16>(Inst->ImmOpnd), DL,
824  MVT::i64);
825  RegOpnd = CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64,
826  SDValue(RegOpnd, 0), ImmOpnd);
827  }
828 
829  ReplaceNode(Node, RegOpnd);
830  return true;
831  }
832 
833  case ISD::INTRINSIC_W_CHAIN: {
834  switch (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
835  default:
836  break;
837 
838  case Intrinsic::mips_cfcmsa: {
839  SDValue ChainIn = Node->getOperand(0);
840  SDValue RegIdx = Node->getOperand(2);
841  SDValue Reg = CurDAG->getCopyFromReg(ChainIn, DL,
842  getMSACtrlReg(RegIdx), MVT::i32);
843  ReplaceNode(Node, Reg.getNode());
844  return true;
845  }
846  }
847  break;
848  }
849 
851  switch (cast<ConstantSDNode>(Node->getOperand(0))->getZExtValue()) {
852  default:
853  break;
854 
855  case Intrinsic::mips_move_v:
856  // Like an assignment but will always produce a move.v even if
857  // unnecessary.
858  ReplaceNode(Node, CurDAG->getMachineNode(Mips::MOVE_V, DL,
859  Node->getValueType(0),
860  Node->getOperand(1)));
861  return true;
862  }
863  break;
864  }
865 
866  case ISD::INTRINSIC_VOID: {
867  switch (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
868  default:
869  break;
870 
871  case Intrinsic::mips_ctcmsa: {
872  SDValue ChainIn = Node->getOperand(0);
873  SDValue RegIdx = Node->getOperand(2);
874  SDValue Value = Node->getOperand(3);
875  SDValue ChainOut = CurDAG->getCopyToReg(ChainIn, DL,
876  getMSACtrlReg(RegIdx), Value);
877  ReplaceNode(Node, ChainOut.getNode());
878  return true;
879  }
880  }
881  break;
882  }
883 
884  // Manually match MipsISD::Ins nodes to get the correct instruction. It has
885  // to be done in this fashion so that we respect the differences between
886  // dins and dinsm, as the difference is that the size operand has the range
887  // 0 < size <= 32 for dins while dinsm has the range 2 <= size <= 64 which
888  // means SelectionDAGISel would have to test all the operands at once to
889  // match the instruction.
890  case MipsISD::Ins: {
891 
892  // Sanity checking for the node operands.
893  if (Node->getValueType(0) != MVT::i32 && Node->getValueType(0) != MVT::i64)
894  return false;
895 
896  if (Node->getNumOperands() != 4)
897  return false;
898 
899  if (Node->getOperand(1)->getOpcode() != ISD::Constant ||
900  Node->getOperand(2)->getOpcode() != ISD::Constant)
901  return false;
902 
903  MVT ResTy = Node->getSimpleValueType(0);
904  uint64_t Pos = Node->getConstantOperandVal(1);
905  uint64_t Size = Node->getConstantOperandVal(2);
906 
907  // Size has to be >0 for 'ins', 'dins' and 'dinsu'.
908  if (!Size)
909  return false;
910 
911  if (Pos + Size > 64)
912  return false;
913 
914  if (ResTy != MVT::i32 && ResTy != MVT::i64)
915  return false;
916 
917  unsigned Opcode = 0;
918  if (ResTy == MVT::i32) {
919  if (Pos + Size <= 32)
920  Opcode = Mips::INS;
921  } else {
922  if (Pos + Size <= 32)
923  Opcode = Mips::DINS;
924  else if (Pos < 32 && 1 < Size)
925  Opcode = Mips::DINSM;
926  else
927  Opcode = Mips::DINSU;
928  }
929 
930  if (Opcode) {
931  SDValue Ops[4] = {
932  Node->getOperand(0), CurDAG->getTargetConstant(Pos, DL, MVT::i32),
933  CurDAG->getTargetConstant(Size, DL, MVT::i32), Node->getOperand(3)};
934 
935  ReplaceNode(Node, CurDAG->getMachineNode(Opcode, DL, ResTy, Ops));
936  return true;
937  }
938 
939  return false;
940  }
941 
942  case MipsISD::ThreadPointer: {
944  unsigned RdhwrOpc, DestReg;
945 
946  if (PtrVT == MVT::i32) {
947  RdhwrOpc = Mips::RDHWR;
948  DestReg = Mips::V1;
949  } else {
950  RdhwrOpc = Mips::RDHWR64;
951  DestReg = Mips::V1_64;
952  }
953 
954  SDNode *Rdhwr =
955  CurDAG->getMachineNode(RdhwrOpc, DL, Node->getValueType(0),
956  CurDAG->getRegister(Mips::HWR29, MVT::i32),
958  SDValue Chain = CurDAG->getCopyToReg(CurDAG->getEntryNode(), DL, DestReg,
959  SDValue(Rdhwr, 0));
960  SDValue ResNode = CurDAG->getCopyFromReg(Chain, DL, DestReg, PtrVT);
961  ReplaceNode(Node, ResNode.getNode());
962  return true;
963  }
964 
965  case ISD::BUILD_VECTOR: {
966  // Select appropriate ldi.[bhwd] instructions for constant splats of
967  // 128-bit when MSA is enabled. Fixup any register class mismatches that
968  // occur as a result.
969  //
970  // This allows the compiler to use a wider range of immediates than would
971  // otherwise be allowed. If, for example, v4i32 could only use ldi.h then
972  // it would not be possible to load { 0x01010101, 0x01010101, 0x01010101,
973  // 0x01010101 } without using a constant pool. This would be sub-optimal
974  // when // 'ldi.b wd, 1' is capable of producing that bit-pattern in the
975  // same set/ of registers. Similarly, ldi.h isn't capable of producing {
976  // 0x00000000, 0x00000001, 0x00000000, 0x00000001 } but 'ldi.d wd, 1' can.
977 
978  const MipsABIInfo &ABI =
979  static_cast<const MipsTargetMachine &>(TM).getABI();
980 
981  BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Node);
982  APInt SplatValue, SplatUndef;
983  unsigned SplatBitSize;
984  bool HasAnyUndefs;
985  unsigned LdiOp;
986  EVT ResVecTy = BVN->getValueType(0);
987  EVT ViaVecTy;
988 
989  if (!Subtarget->hasMSA() || !BVN->getValueType(0).is128BitVector())
990  return false;
991 
992  if (!BVN->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
993  HasAnyUndefs, 8,
994  !Subtarget->isLittle()))
995  return false;
996 
997  switch (SplatBitSize) {
998  default:
999  return false;
1000  case 8:
1001  LdiOp = Mips::LDI_B;
1002  ViaVecTy = MVT::v16i8;
1003  break;
1004  case 16:
1005  LdiOp = Mips::LDI_H;
1006  ViaVecTy = MVT::v8i16;
1007  break;
1008  case 32:
1009  LdiOp = Mips::LDI_W;
1010  ViaVecTy = MVT::v4i32;
1011  break;
1012  case 64:
1013  LdiOp = Mips::LDI_D;
1014  ViaVecTy = MVT::v2i64;
1015  break;
1016  }
1017 
1018  SDNode *Res = nullptr;
1019 
1020  // If we have a signed 10 bit integer, we can splat it directly.
1021  //
1022  // If we have something bigger we can synthesize the value into a GPR and
1023  // splat from there.
1024  if (SplatValue.isSignedIntN(10)) {
1025  SDValue Imm = CurDAG->getTargetConstant(SplatValue, DL,
1026  ViaVecTy.getVectorElementType());
1027 
1028  Res = CurDAG->getMachineNode(LdiOp, DL, ViaVecTy, Imm);
1029  } else if (SplatValue.isSignedIntN(16) &&
1030  ((ABI.IsO32() && SplatBitSize < 64) ||
1031  (ABI.IsN32() || ABI.IsN64()))) {
1032  // Only handle signed 16 bit values when the element size is GPR width.
1033  // MIPS64 can handle all the cases but MIPS32 would need to handle
1034  // negative cases specifically here. Instead, handle those cases as
1035  // 64bit values.
1036 
1037  bool Is32BitSplat = ABI.IsO32() || SplatBitSize < 64;
1038  const unsigned ADDiuOp = Is32BitSplat ? Mips::ADDiu : Mips::DADDiu;
1039  const MVT SplatMVT = Is32BitSplat ? MVT::i32 : MVT::i64;
1040  SDValue ZeroVal = CurDAG->getRegister(
1041  Is32BitSplat ? Mips::ZERO : Mips::ZERO_64, SplatMVT);
1042 
1043  const unsigned FILLOp =
1044  SplatBitSize == 16
1045  ? Mips::FILL_H
1046  : (SplatBitSize == 32 ? Mips::FILL_W
1047  : (SplatBitSize == 64 ? Mips::FILL_D : 0));
1048 
1049  assert(FILLOp != 0 && "Unknown FILL Op for splat synthesis!");
1050  assert((!ABI.IsO32() || (FILLOp != Mips::FILL_D)) &&
1051  "Attempting to use fill.d on MIPS32!");
1052 
1053  const unsigned Lo = SplatValue.getLoBits(16).getZExtValue();
1054  SDValue LoVal = CurDAG->getTargetConstant(Lo, DL, SplatMVT);
1055 
1056  Res = CurDAG->getMachineNode(ADDiuOp, DL, SplatMVT, ZeroVal, LoVal);
1057  Res = CurDAG->getMachineNode(FILLOp, DL, ViaVecTy, SDValue(Res, 0));
1058 
1059  } else if (SplatValue.isSignedIntN(32) && SplatBitSize == 32) {
1060  // Only handle the cases where the splat size agrees with the size
1061  // of the SplatValue here.
1062  const unsigned Lo = SplatValue.getLoBits(16).getZExtValue();
1063  const unsigned Hi = SplatValue.lshr(16).getLoBits(16).getZExtValue();
1064  SDValue ZeroVal = CurDAG->getRegister(Mips::ZERO, MVT::i32);
1065 
1066  SDValue LoVal = CurDAG->getTargetConstant(Lo, DL, MVT::i32);
1067  SDValue HiVal = CurDAG->getTargetConstant(Hi, DL, MVT::i32);
1068 
1069  if (Hi)
1070  Res = CurDAG->getMachineNode(Mips::LUi, DL, MVT::i32, HiVal);
1071 
1072  if (Lo)
1073  Res = CurDAG->getMachineNode(Mips::ORi, DL, MVT::i32,
1074  Hi ? SDValue(Res, 0) : ZeroVal, LoVal);
1075 
1076  assert((Hi || Lo) && "Zero case reached 32 bit case splat synthesis!");
1077  Res = CurDAG->getMachineNode(Mips::FILL_W, DL, MVT::v4i32, SDValue(Res, 0));
1078 
1079  } else if (SplatValue.isSignedIntN(32) && SplatBitSize == 64 &&
1080  (ABI.IsN32() || ABI.IsN64())) {
1081  // N32 and N64 can perform some tricks that O32 can't for signed 32 bit
1082  // integers due to having 64bit registers. lui will cause the necessary
1083  // zero/sign extension.
1084  const unsigned Lo = SplatValue.getLoBits(16).getZExtValue();
1085  const unsigned Hi = SplatValue.lshr(16).getLoBits(16).getZExtValue();
1086  SDValue ZeroVal = CurDAG->getRegister(Mips::ZERO, MVT::i32);
1087 
1088  SDValue LoVal = CurDAG->getTargetConstant(Lo, DL, MVT::i32);
1089  SDValue HiVal = CurDAG->getTargetConstant(Hi, DL, MVT::i32);
1090 
1091  if (Hi)
1092  Res = CurDAG->getMachineNode(Mips::LUi, DL, MVT::i32, HiVal);
1093 
1094  if (Lo)
1095  Res = CurDAG->getMachineNode(Mips::ORi, DL, MVT::i32,
1096  Hi ? SDValue(Res, 0) : ZeroVal, LoVal);
1097 
1098  Res = CurDAG->getMachineNode(
1099  Mips::SUBREG_TO_REG, DL, MVT::i64,
1100  CurDAG->getTargetConstant(((Hi >> 15) & 0x1), DL, MVT::i64),
1101  SDValue(Res, 0),
1102  CurDAG->getTargetConstant(Mips::sub_32, DL, MVT::i64));
1103 
1104  Res =
1105  CurDAG->getMachineNode(Mips::FILL_D, DL, MVT::v2i64, SDValue(Res, 0));
1106 
1107  } else if (SplatValue.isSignedIntN(64)) {
1108  // If we have a 64 bit Splat value, we perform a similar sequence to the
1109  // above:
1110  //
1111  // MIPS32: MIPS64:
1112  // lui $res, %highest(val) lui $res, %highest(val)
1113  // ori $res, $res, %higher(val) ori $res, $res, %higher(val)
1114  // lui $res2, %hi(val) lui $res2, %hi(val)
1115  // ori $res2, %res2, %lo(val) ori $res2, %res2, %lo(val)
1116  // $res3 = fill $res2 dinsu $res, $res2, 0, 32
1117  // $res4 = insert.w $res3[1], $res fill.d $res
1118  // splat.d $res4, 0
1119  //
1120  // The ability to use dinsu is guaranteed as MSA requires MIPSR5. This saves
1121  // having to materialize the value by shifts and ors.
1122  //
1123  // FIXME: Implement the preferred sequence for MIPS64R6:
1124  //
1125  // MIPS64R6:
1126  // ori $res, $zero, %lo(val)
1127  // daui $res, $res, %hi(val)
1128  // dahi $res, $res, %higher(val)
1129  // dati $res, $res, %highest(cal)
1130  // fill.d $res
1131  //
1132 
1133  const unsigned Lo = SplatValue.getLoBits(16).getZExtValue();
1134  const unsigned Hi = SplatValue.lshr(16).getLoBits(16).getZExtValue();
1135  const unsigned Higher = SplatValue.lshr(32).getLoBits(16).getZExtValue();
1136  const unsigned Highest = SplatValue.lshr(48).getLoBits(16).getZExtValue();
1137 
1138  SDValue LoVal = CurDAG->getTargetConstant(Lo, DL, MVT::i32);
1139  SDValue HiVal = CurDAG->getTargetConstant(Hi, DL, MVT::i32);
1140  SDValue HigherVal = CurDAG->getTargetConstant(Higher, DL, MVT::i32);
1141  SDValue HighestVal = CurDAG->getTargetConstant(Highest, DL, MVT::i32);
1142  SDValue ZeroVal = CurDAG->getRegister(Mips::ZERO, MVT::i32);
1143 
1144  // Independent of whether we're targeting MIPS64 or not, the basic
1145  // operations are the same. Also, directly use the $zero register if
1146  // the 16 bit chunk is zero.
1147  //
1148  // For optimization purposes we always synthesize the splat value as
1149  // an i32 value, then if we're targetting MIPS64, use SUBREG_TO_REG
1150  // just before combining the values with dinsu to produce an i64. This
1151  // enables SelectionDAG to aggressively share components of splat values
1152  // where possible.
1153  //
1154  // FIXME: This is the general constant synthesis problem. This code
1155  // should be factored out into a class shared between all the
1156  // classes that need it. Specifically, for a splat size of 64
1157  // bits that's a negative number we can do better than LUi/ORi
1158  // for the upper 32bits.
1159 
1160  if (Hi)
1161  Res = CurDAG->getMachineNode(Mips::LUi, DL, MVT::i32, HiVal);
1162 
1163  if (Lo)
1164  Res = CurDAG->getMachineNode(Mips::ORi, DL, MVT::i32,
1165  Hi ? SDValue(Res, 0) : ZeroVal, LoVal);
1166 
1167  SDNode *HiRes;
1168  if (Highest)
1169  HiRes = CurDAG->getMachineNode(Mips::LUi, DL, MVT::i32, HighestVal);
1170 
1171  if (Higher)
1172  HiRes = CurDAG->getMachineNode(Mips::ORi, DL, MVT::i32,
1173  Highest ? SDValue(HiRes, 0) : ZeroVal,
1174  HigherVal);
1175 
1176 
1177  if (ABI.IsO32()) {
1178  Res = CurDAG->getMachineNode(Mips::FILL_W, DL, MVT::v4i32,
1179  (Hi || Lo) ? SDValue(Res, 0) : ZeroVal);
1180 
1181  Res = CurDAG->getMachineNode(
1182  Mips::INSERT_W, DL, MVT::v4i32, SDValue(Res, 0),
1183  (Highest || Higher) ? SDValue(HiRes, 0) : ZeroVal,
1184  CurDAG->getTargetConstant(1, DL, MVT::i32));
1185 
1187  const TargetRegisterClass *RC =
1188  TLI->getRegClassFor(ViaVecTy.getSimpleVT());
1189 
1190  Res = CurDAG->getMachineNode(
1191  Mips::COPY_TO_REGCLASS, DL, ViaVecTy, SDValue(Res, 0),
1192  CurDAG->getTargetConstant(RC->getID(), DL, MVT::i32));
1193 
1194  Res = CurDAG->getMachineNode(
1195  Mips::SPLATI_D, DL, MVT::v2i64, SDValue(Res, 0),
1196  CurDAG->getTargetConstant(0, DL, MVT::i32));
1197  } else if (ABI.IsN64() || ABI.IsN32()) {
1198 
1199  SDValue Zero64Val = CurDAG->getRegister(Mips::ZERO_64, MVT::i64);
1200  const bool HiResNonZero = Highest || Higher;
1201  const bool ResNonZero = Hi || Lo;
1202 
1203  if (HiResNonZero)
1204  HiRes = CurDAG->getMachineNode(
1205  Mips::SUBREG_TO_REG, DL, MVT::i64,
1206  CurDAG->getTargetConstant(((Highest >> 15) & 0x1), DL, MVT::i64),
1207  SDValue(HiRes, 0),
1208  CurDAG->getTargetConstant(Mips::sub_32, DL, MVT::i64));
1209 
1210  if (ResNonZero)
1211  Res = CurDAG->getMachineNode(
1212  Mips::SUBREG_TO_REG, DL, MVT::i64,
1213  CurDAG->getTargetConstant(((Hi >> 15) & 0x1), DL, MVT::i64),
1214  SDValue(Res, 0),
1215  CurDAG->getTargetConstant(Mips::sub_32, DL, MVT::i64));
1216 
1217  // We have 3 cases:
1218  // The HiRes is nonzero but Res is $zero => dsll32 HiRes, 0
1219  // The Res is nonzero but HiRes is $zero => dinsu Res, $zero, 32, 32
1220  // Both are non zero => dinsu Res, HiRes, 32, 32
1221  //
1222  // The obvious "missing" case is when both are zero, but that case is
1223  // handled by the ldi case.
1224  if (ResNonZero) {
1225  IntegerType *Int32Ty =
1227  const ConstantInt *Const32 = ConstantInt::get(Int32Ty, 32);
1228  SDValue Ops[4] = {HiResNonZero ? SDValue(HiRes, 0) : Zero64Val,
1229  CurDAG->getConstant(*Const32, DL, MVT::i32),
1230  CurDAG->getConstant(*Const32, DL, MVT::i32),
1231  SDValue(Res, 0)};
1232 
1233  Res = CurDAG->getMachineNode(Mips::DINSU, DL, MVT::i64, Ops);
1234  } else if (HiResNonZero) {
1235  Res = CurDAG->getMachineNode(
1236  Mips::DSLL32, DL, MVT::i64, SDValue(HiRes, 0),
1237  CurDAG->getTargetConstant(0, DL, MVT::i32));
1238  } else
1240  "Zero splat value handled by non-zero 64bit splat synthesis!");
1241 
1242  Res = CurDAG->getMachineNode(Mips::FILL_D, DL, MVT::v2i64, SDValue(Res, 0));
1243  } else
1244  llvm_unreachable("Unknown ABI in MipsISelDAGToDAG!");
1245 
1246  } else
1247  return false;
1248 
1249  if (ResVecTy != ViaVecTy) {
1250  // If LdiOp is writing to a different register class to ResVecTy, then
1251  // fix it up here. This COPY_TO_REGCLASS should never cause a move.v
1252  // since the source and destination register sets contain the same
1253  // registers.
1255  MVT ResVecTySimple = ResVecTy.getSimpleVT();
1256  const TargetRegisterClass *RC = TLI->getRegClassFor(ResVecTySimple);
1257  Res = CurDAG->getMachineNode(Mips::COPY_TO_REGCLASS, DL,
1258  ResVecTy, SDValue(Res, 0),
1259  CurDAG->getTargetConstant(RC->getID(), DL,
1260  MVT::i32));
1261  }
1262 
1263  ReplaceNode(Node, Res);
1264  return true;
1265  }
1266 
1267  }
1268 
1269  return false;
1270 }
1271 
1272 bool MipsSEDAGToDAGISel::
1273 SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
1274  std::vector<SDValue> &OutOps) {
1275  SDValue Base, Offset;
1276 
1277  switch(ConstraintID) {
1278  default:
1279  llvm_unreachable("Unexpected asm memory constraint");
1280  // All memory constraints can at least accept raw pointers.
1282  OutOps.push_back(Op);
1283  OutOps.push_back(CurDAG->getTargetConstant(0, SDLoc(Op), MVT::i32));
1284  return false;
1287  if (selectAddrRegImm16(Op, Base, Offset)) {
1288  OutOps.push_back(Base);
1289  OutOps.push_back(Offset);
1290  return false;
1291  }
1292  OutOps.push_back(Op);
1293  OutOps.push_back(CurDAG->getTargetConstant(0, SDLoc(Op), MVT::i32));
1294  return false;
1296  // The 'R' constraint is supposed to be much more complicated than this.
1297  // However, it's becoming less useful due to architectural changes and
1298  // ought to be replaced by other constraints such as 'ZC'.
1299  // For now, support 9-bit signed offsets which is supportable by all
1300  // subtargets for all instructions.
1301  if (selectAddrRegImm9(Op, Base, Offset)) {
1302  OutOps.push_back(Base);
1303  OutOps.push_back(Offset);
1304  return false;
1305  }
1306  OutOps.push_back(Op);
1307  OutOps.push_back(CurDAG->getTargetConstant(0, SDLoc(Op), MVT::i32));
1308  return false;
1310  // ZC matches whatever the pref, ll, and sc instructions can handle for the
1311  // given subtarget.
1312  if (Subtarget->inMicroMipsMode()) {
1313  // On microMIPS, they can handle 12-bit offsets.
1314  if (selectAddrRegImm12(Op, Base, Offset)) {
1315  OutOps.push_back(Base);
1316  OutOps.push_back(Offset);
1317  return false;
1318  }
1319  } else if (Subtarget->hasMips32r6()) {
1320  // On MIPS32r6/MIPS64r6, they can only handle 9-bit offsets.
1321  if (selectAddrRegImm9(Op, Base, Offset)) {
1322  OutOps.push_back(Base);
1323  OutOps.push_back(Offset);
1324  return false;
1325  }
1326  } else if (selectAddrRegImm16(Op, Base, Offset)) {
1327  // Prior to MIPS32r6/MIPS64r6, they can handle 16-bit offsets.
1328  OutOps.push_back(Base);
1329  OutOps.push_back(Offset);
1330  return false;
1331  }
1332  // In all cases, 0-bit offsets are acceptable.
1333  OutOps.push_back(Op);
1334  OutOps.push_back(CurDAG->getTargetConstant(0, SDLoc(Op), MVT::i32));
1335  return false;
1336  }
1337  return true;
1338 }
1339 
1342  return new MipsSEDAGToDAGISel(TM, OptLevel);
1343 }
bool isABI_FPXX() const
unsigned Log2(Align A)
Returns the log2 of the alignment.
Definition: Alignment.h:204
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
Definition: ISDOpcodes.h:603
SDNode * SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT)
These are used for target selectors to mutate the specified node to have the specified return type...
EVT getValueType() const
Return the ValueType of the referenced return value.
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
bool hasMTHC1() const
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
typename SuperClass::const_iterator const_iterator
Definition: SmallVector.h:320
bool isConstantSplat(APInt &SplatValue, APInt &SplatUndef, unsigned &SplatBitSize, bool &HasAnyUndefs, unsigned MinSplatBits=0, bool isBigEndian=false) const
Check if this is a constant splat, and if so, find the smallest element size that splats the vector...
This class represents lattice values for constants.
Definition: AllocatorList.h:23
FunctionPass * createMipsSEISelDag(MipsTargetMachine &TM, CodeGenOpt::Level OptLevel)
bool inMips16Mode() const
Carry-setting nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:222
EVT getValueType(unsigned ResNo) const
Return the type of a specified result.
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:384
unsigned Reg
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
Definition: ValueTypes.h:252
TargetGlobalAddress - Like GlobalAddress, but the DAG does no folding or anything else with this node...
Definition: ISDOpcodes.h:130
bool isABI_O32() const
MVT getSimpleValueType(unsigned ResNo) const
Return the type of a specified result as a simple type.
SDNode * getNode() const
get the SDNode which holds the desired result
bool isPHI() const
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
MachineFunction * MF
unsigned getBitWidth() const
Return the number of bits in the APInt.
Definition: APInt.h:1517
return AArch64::GPR64RegClass contains(Reg)
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
RESULT,OUTCHAIN = INTRINSIC_W_CHAIN(INCHAIN, INTRINSICID, arg1, ...) This node represents a target in...
Definition: ISDOpcodes.h:158
SI optimize exec mask operations pre RA
AnalysisUsage & addRequired()
static use_iterator use_end()
This file declares the MachineConstantPool class which is an abstract constant pool to keep track of ...
bool inMicroMipsMode() const
static std::string getGlobalIdentifier(StringRef Name, GlobalValue::LinkageTypes Linkage, StringRef FileName)
Return the modified name for a global value suitable to be used as the key for a global lookup (e...
Definition: Globals.cpp:136
MachineSDNode * getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT)
These are used for target selectors to create a new node with specified return type(s), MachineInstr opcode, and operands.
const TargetLowering * TLI
bool isGP64bit() const
bool hasMips32r6() const
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:410
SDValue getEntryNode() const
Return the token chain corresponding to the entry of the function.
Definition: SelectionDAG.h:477
const DataLayout & getDataLayout() const
Definition: SelectionDAG.h:417
bool IsN32() const
Definition: MipsABIInfo.h:42
mir Rename Register Operands
unsigned getID() const
Return the register class ID number.
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
int64_t getSExtValue() const
bool IsN64() const
Definition: MipsABIInfo.h:43
unsigned getSizeInBits() const
Return the size of the specified value type in bits.
Definition: ValueTypes.h:291
virtual const TargetRegisterClass * getRegClassFor(MVT VT, bool isDivergent=false) const
Return the register class that should be used for the specified value type.
SDValue getTargetFrameIndex(int FI, EVT VT)
Definition: SelectionDAG.h:647
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:200
int32_t exactLogBase2() const
Definition: APInt.h:1796
const InstSeq & Analyze(uint64_t Imm, unsigned Size, bool LastInstrIsADDiu)
Analyze - Get an instruction sequence to load immediate Imm.
void setReg(Register Reg)
Change the register this operand corresponds to.
SDValue getTargetConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isOpaque=false)
Definition: SelectionDAG.h:596
RESULT = INTRINSIC_WO_CHAIN(INTRINSICID, arg1, arg2, ...) This node represents a target intrinsic fun...
Definition: ISDOpcodes.h:150
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:131
BUILD_VECTOR(ELT0, ELT1, ELT2, ELT3,...) - Return a vector with the specified, possibly variable...
Definition: ISDOpcodes.h:359
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
const MachineInstrBuilder & addUse(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register use operand.
OUTCHAIN = INTRINSIC_VOID(INCHAIN, INTRINSICID, arg1, arg2, ...) This node represents a target intrin...
Definition: ISDOpcodes.h:165
CodeGenOpt::Level OptLevel
unsigned const MachineRegisterInfo * MRI
unsigned countPopulation() const
Count the number of bits set.
Definition: APInt.h:1666
const MipsSubtarget * Subtarget
Keep a pointer to the MipsSubtarget around so that we can make the right decision when generating cod...
Machine Value Type.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
bool isPseudo(QueryType Type=IgnoreBundle) const
Return true if this is a pseudo instruction that doesn&#39;t correspond to a real machine instruction...
Definition: MachineInstr.h:642
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
const SDValue & getOperand(unsigned Num) const
const GlobalValue * getGlobal() const
Carry-using nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:231
static ManagedStatic< OptionRegistry > OR
Definition: Options.cpp:30
Represent the analysis usage information of a pass.
bool isBaseWithConstantOffset(SDValue Op) const
Return true if the specified operand is an ISD::ADD with a ConstantSDNode on the right-hand side...
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:284
bool isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx=nullptr) const
Return true if the use operand of the specified index is tied to a def operand.
bool IsO32() const
Definition: MipsABIInfo.h:41
Class to represent integer types.
Definition: DerivedTypes.h:40
bool isIntN(unsigned N) const
Check if this APInt has an N-bits unsigned integer value.
Definition: APInt.h:449
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function. ...
Definition: Function.cpp:205
static MachineOperand CreateReg(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)
virtual MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
Extended Value Type.
Definition: ValueTypes.h:33
bool isIntN(unsigned N, int64_t x)
Checks if an signed integer fits into the given (dynamic) bit width.
Definition: MathExtras.h:434
bool isMCSymbol() const
unsigned getNumOperands() const
Return the number of values used by this operation.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:40
static IntegerType * get(LLVMContext &C, unsigned NumBits)
This static method is the primary way of constructing an IntegerType.
Definition: Type.cpp:244
This is the shared class of boolean and integer constants.
Definition: Constants.h:83
constexpr bool isInt< 32 >(int64_t x)
Definition: MathExtras.h:345
void addOperand(MachineFunction &MF, const MachineOperand &Op)
Add the specified operand to the instruction.
bool isLittle() const
bool isGlobal() const
isGlobal - Tests if this is a MO_GlobalAddress operand.
EVT getVectorElementType() const
Given a vector type, return the type of each element.
Definition: ValueTypes.h:264
MachineOperand class - Representation of each machine instruction operand.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
static Constant * get(Type *Ty, uint64_t V, bool isSigned=false)
If Ty is a vector type, return a Constant with a splat of the given value.
Definition: Constants.cpp:653
Represents one node in the SelectionDAG.
bool isAligned(Align Lhs, uint64_t SizeInBytes)
Checks that SizeInBytes is a multiple of the alignment.
Definition: Alignment.h:146
int64_t getImm() const
SDValue getCopyToReg(SDValue Chain, const SDLoc &dl, unsigned Reg, SDValue N)
Definition: SelectionDAG.h:695
const Function & getFunction() const
Return the LLVM function that this machine code represents.
Class for arbitrary precision integers.
Definition: APInt.h:69
A "pseudo-class" with methods for operating on BUILD_VECTORs.
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
Definition: MachineInstr.h:63
This file provides various utilities for inspecting and working with the control flow graph in LLVM I...
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
SDValue getCopyFromReg(SDValue Chain, const SDLoc &dl, unsigned Reg, EVT VT)
Definition: SelectionDAG.h:721
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
use_iterator use_begin(unsigned RegNo) const
xray Insert XRay ops
bool is128BitVector() const
Return true if this is a 128-bit vector type.
Definition: ValueTypes.h:181
bool isPositionIndependent() const
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
Definition: MCInstrInfo.h:44
#define N
MipsFunctionInfo - This class is derived from MachineFunction private Mips target-specific informatio...
LLVM_NODISCARD std::enable_if<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:332
uint32_t Size
Definition: Profile.cpp:46
bool useOddSPReg() const
MipsSEDAGToDAGISel(MipsTargetMachine &TM, CodeGenOpt::Level OL)
unsigned getOpcode() const
bool isSignedIntN(unsigned N) const
Check if this APInt has an N-bits signed integer value.
Definition: APInt.h:455
SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
Create a ConstantSDNode wrapping a constant value.
const TargetLowering * getTargetLowering() const
StringRef getName() const
getName - Get the symbol name.
Definition: MCSymbol.h:204
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
MCSymbol * getMCSymbol() const
LLVM Value Representation.
Definition: Value.h:74
uint64_t getConstantOperandVal(unsigned Num) const
Helper method returns the integer value of a ConstantSDNode operand.
SDValue getRegister(unsigned Reg, EVT VT)
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:273
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:80
IRTranslator LLVM IR MI
void ReplaceNode(SDNode *F, SDNode *T)
Replace all uses of F with T, then remove F from the DAG.
Legacy analysis pass which computes a DominatorTree.
Definition: Dominators.h:259
Register getReg() const
getReg - Returns the register number.
const SDValue & getOperand(unsigned i) const
uint64_t getZExtValue() const
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:415
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
const TargetInstrInfo * TII
reg_begin/reg_end - Provide iteration support to walk over all definitions and uses of a register wit...
bool isFP64bit() const
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
bool runOnMachineFunction(MachineFunction &MF) override
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
bool hasMSA() const
IntegerType * Int32Ty