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LLVM 24.0.0git
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#include "llvm/CodeGenTypes/MachineValueType.h"
Classes | |
| struct | VecVTTable |
| Lookup table for getVectorVT. More... | |
Public Types | |
| enum | SimpleValueType : uint16_t { INVALID_SIMPLE_VALUE_TYPE = 0 , VALUETYPE_SIZE = LAST_VALUETYPE + 1 } |
Public Member Functions | |
| constexpr | MVT ()=default |
| constexpr | MVT (SimpleValueType SVT) |
| bool | operator> (const MVT &S) const |
| bool | operator< (const MVT &S) const |
| bool | operator== (const MVT &S) const |
| bool | operator!= (const MVT &S) const |
| bool | operator>= (const MVT &S) const |
| bool | operator<= (const MVT &S) const |
| bool | operator== (SimpleValueType S) const |
| bool | operator!= (SimpleValueType S) const |
| LLVM_ABI void | dump () const |
| Support for debugging, callable in GDB: VT.dump() | |
| LLVM_ABI void | print (raw_ostream &OS) const |
| Implement operator<<. | |
| std::string | getString () const |
| Return the value type as a string, e.g. i32. | |
| bool | isValid () const |
| Return true if this is a valid simple valuetype. | |
| bool | isFloatingPoint () const |
| Return true if this is a FP or a vector FP type. | |
| bool | isInteger () const |
| Return true if this is an integer or a vector integer type. | |
| bool | isScalarInteger () const |
| Return true if this is an integer, not including vectors. | |
| bool | isVector () const |
| Return true if this is a vector value type. | |
| bool | isVectorOf (MVT EltVT) const |
| Return true if this is a vector with matching element type. | |
| bool | isScalableVector () const |
| Return true if this is a vector value type where the runtime length is machine dependent. | |
| bool | isScalableVectorOf (MVT EltVT) const |
| Return true if this is a scalable vector with matching element type. | |
| bool | isRISCVVectorTuple () const |
| Return true if this is a RISCV vector tuple type where the runtime length is machine dependent. | |
| bool | isScalableTargetExtVT () const |
| Return true if this is a custom target type that has a scalable size. | |
| bool | isScalableVT () const |
| Return true if the type is a scalable type. | |
| bool | isFixedLengthVector () const |
| bool | isFixedLengthVectorOf (MVT EltVT) const |
| Return true if this is a fixed length vector with matching element type. | |
| bool | is16BitVector () const |
| Return true if this is a 16-bit vector type. | |
| bool | is32BitVector () const |
| Return true if this is a 32-bit vector type. | |
| bool | is64BitVector () const |
| Return true if this is a 64-bit vector type. | |
| bool | is128BitVector () const |
| Return true if this is a 128-bit vector type. | |
| bool | is256BitVector () const |
| Return true if this is a 256-bit vector type. | |
| bool | is512BitVector () const |
| Return true if this is a 512-bit vector type. | |
| bool | is1024BitVector () const |
| Return true if this is a 1024-bit vector type. | |
| bool | is2048BitVector () const |
| Return true if this is a 2048-bit vector type. | |
| bool | isCheriCapability () const |
| Return true if this is a CHERI capability type. | |
| bool | isOverloaded () const |
| Return true if this is an overloaded type for TableGen. | |
| MVT | changeVectorElementTypeToInteger () const |
| Return a vector with the same number of elements as this vector, but with the element type converted to an integer type with the same bitwidth. | |
| MVT | changeVectorElementType (MVT EltVT) const |
| Return a VT for a vector type whose attributes match ourselves with the exception of the element type that is chosen by the caller. | |
| MVT | changeVectorElementCount (ElementCount EC) const |
| Return a VT for a vector type whose attributes match ourselves with the exception of the element count that is chosen by the caller. | |
| MVT | changeElementType (MVT EltVT) const |
| Return a VT for a type whose attributes match ourselves with the exception of the element type that is chosen by the caller. | |
| MVT | changeTypeToInteger () |
| Return the type converted to an equivalently sized integer or vector with integer element type. | |
| MVT | getHalfNumVectorElementsVT () const |
| Return a VT for a vector type with the same element type but half the number of elements. | |
| MVT | getDoubleNumVectorElementsVT () const |
| MVT | widenIntegerElementType () const |
| bool | isPow2VectorType () const |
| Returns true if the given vector is a power of 2. | |
| MVT | getPow2VectorType () const |
| Widens the length of the given vector MVT up to the nearest power of 2 and returns that type. | |
| MVT | getScalarType () const |
| If this is a vector, return the element type, otherwise return this. | |
| MVT | getVectorElementType () const |
| unsigned | getVectorMinNumElements () const |
| Given a vector type, return the minimum number of elements it contains. | |
| ElementCount | getVectorElementCount () const |
| unsigned | getVectorNumElements () const |
| TypeSize | getSizeInBits () const |
| Returns the size of the specified MVT in bits. | |
| uint64_t | getFixedSizeInBits () const |
| Return the size of the specified fixed width value type in bits. | |
| uint64_t | getScalarSizeInBits () const |
| TypeSize | getStoreSize () const |
| Return the number of bytes overwritten by a store of the specified value type. | |
| uint64_t | getScalarStoreSize () const |
| TypeSize | getStoreSizeInBits () const |
| Return the number of bits overwritten by a store of the specified value type. | |
| bool | isByteSized () const |
| Returns true if the number of bits for the type is a multiple of an 8-bit byte. | |
| bool | knownBitsGT (MVT VT) const |
| Return true if we know at compile time this has more bits than VT. | |
| bool | knownBitsGE (MVT VT) const |
| Return true if we know at compile time this has more than or the same bits as VT. | |
| bool | knownBitsLT (MVT VT) const |
| Return true if we know at compile time this has fewer bits than VT. | |
| bool | knownBitsLE (MVT VT) const |
| Return true if we know at compile time this has fewer than or the same bits as VT. | |
| bool | bitsGT (MVT VT) const |
| Return true if this has more bits than VT. | |
| bool | bitsGE (MVT VT) const |
| Return true if this has no less bits than VT. | |
| bool | bitsLT (MVT VT) const |
| Return true if this has less bits than VT. | |
| bool | bitsLE (MVT VT) const |
| Return true if this has no more bits than VT. | |
| unsigned | getRISCVVectorTupleNumFields () const |
| Given a RISC-V vector tuple type, return the num_fields. | |
| LLVM_ABI const fltSemantics & | getFltSemantics () const |
| Returns an APFloat semantics tag appropriate for the value type. | |
Public Attributes | |
| SimpleValueType | SimpleTy = INVALID_SIMPLE_VALUE_TYPE |
Static Public Attributes | |
| static LLVM_ABI const VecVTTable | VecVTs = buildVecVTTable() |
Every type that is supported natively by some processor targeted by LLVM occurs here. This means that any legal value type can be represented by an MVT.
Definition at line 36 of file MachineValueType.h.
| Enumerator | |
|---|---|
| INVALID_SIMPLE_VALUE_TYPE | |
| VALUETYPE_SIZE | |
Definition at line 38 of file MachineValueType.h.
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constexprdefault |
Referenced by bitsGE(), bitsGT(), bitsLE(), bitsLT(), changeElementType(), changeTypeToInteger(), changeVectorElementCount(), changeVectorElementType(), changeVectorElementTypeToInteger(), getDoubleNumVectorElementsVT(), getFloatingPointVT(), getHalfNumVectorElementsVT(), getIntegerVT(), getPow2VectorType(), getRISCVVectorTupleVT(), getScalableVectorVT(), getScalarType(), getVectorElementType(), getVectorVT(), getVectorVT(), getVectorVT(), getVT(), isFixedLengthVectorOf(), isScalableVectorOf(), isVectorOf(), knownBitsGE(), knownBitsGT(), knownBitsLE(), knownBitsLT(), operator!=(), operator<(), operator<=(), operator==(), operator>(), operator>=(), and widenIntegerElementType().
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inlineconstexpr |
Definition at line 58 of file MachineValueType.h.
References SimpleTy.
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inlinestatic |
SimpleValueType Iteration.
Definition at line 585 of file MachineValueType.h.
References llvm::enum_seq_inclusive(), and llvm::force_iteration_on_noniterable_enum.
Referenced by llvm::TargetLoweringBase::computeRegisterProperties(), llvm::TargetLoweringBase::initActions(), and llvm::SITargetLowering::SITargetLowering().
Return true if this has no less bits than VT.
Definition at line 473 of file MachineValueType.h.
References assert(), isScalableVector(), knownBitsGE(), and MVT().
Referenced by LowerABD(), and llvm::RISCVTargetLowering::LowerOperation().
Return true if this has more bits than VT.
Definition at line 466 of file MachineValueType.h.
References assert(), isScalableVector(), knownBitsGT(), and MVT().
Referenced by getSmallestVTForIndex(), getVRGatherIndexType(), and LowerFCOPYSIGN().
Return true if this has no more bits than VT.
Definition at line 487 of file MachineValueType.h.
References assert(), isScalableVector(), knownBitsLE(), and MVT().
Referenced by getMaskNode(), llvm::SITargetLowering::getPreferredVectorAction(), llvm::RISCVTTIImpl::getShuffleCost(), lowerBUILD_VECTOR(), lowerBuildVectorOfConstants(), lowerReductionSeq(), lowerScalarInsert(), and llvm::RISCVTargetLowering::PerformDAGCombine().
Return true if this has less bits than VT.
Definition at line 480 of file MachineValueType.h.
References assert(), isScalableVector(), knownBitsLT(), and MVT().
Referenced by getMemIntrinsicSize(), LowerABD(), LowerFCOPYSIGN(), lowerVectorIntrinsicScalars(), llvm::RISCVTargetLowering::PerformDAGCombine(), and promoteVCIXScalar().
Return a VT for a type whose attributes match ourselves with the exception of the element type that is chosen by the caller.
Definition at line 256 of file MachineValueType.h.
References changeVectorElementType(), getScalarType(), isVector(), and MVT().
Referenced by llvm::X86TargetLowering::getTgtMemIntrinsic(), getVectorMaskingNode(), LowerVectorCTLZInRegLUT(), promoteXINT_TO_FP(), and widenIntegerElementType().
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Return the type converted to an equivalently sized integer or vector with integer element type.
Similar to changeVectorElementTypeToInteger, but also handles scalars.
Definition at line 264 of file MachineValueType.h.
References changeVectorElementTypeToInteger(), getFixedSizeInBits(), getIntegerVT(), isVector(), and MVT().
Referenced by llvm::EVT::changeTypeToInteger(), combineStore(), combineX86FPLogicOp(), getConstVector(), getVRGatherIndexType(), getWideningInterleave(), getWideningSpread(), lowerShuffleAsBitMask(), lowerShuffleWithPERMV(), and matchBinaryShuffle().
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inline |
Return a VT for a vector type whose attributes match ourselves with the exception of the element count that is chosen by the caller.
Definition at line 249 of file MachineValueType.h.
References assert(), getVectorElementType(), getVectorVT(), isVector(), and MVT().
Referenced by llvm::EVT::changeVectorElementCount().
Return a VT for a vector type whose attributes match ourselves with the exception of the element type that is chosen by the caller.
Definition at line 240 of file MachineValueType.h.
References assert(), getVectorElementCount(), getVectorVT(), INVALID_SIMPLE_VALUE_TYPE, MVT(), and SimpleTy.
Referenced by llvm::AArch64TargetLowering::AArch64TargetLowering(), changeElementType(), getDeinterleaveShiftAndTrunc(), getVRGatherIndexType(), lowerBUILD_VECTOR(), LowerBUILD_VECTORvXbf16(), LowerBUILD_VECTORvXi1(), lowerBuildVectorOfConstants(), lowerBuildVectorViaDominantValues(), lowerDisjointIndicesShuffle(), LowerFLDEXP(), lowerFP_TO_INT_SAT(), llvm::RISCVTargetLowering::LowerOperation(), lowerScalarSplat(), LowerVectorAllEqual(), lowerVectorXRINT_XROUND(), LowerVSETCC(), matchUnaryShuffle(), performCONCAT_VECTORSCombine(), llvm::RISCVDAGToDAGISel::PreprocessISelDAG(), llvm::X86TargetLowering::ReplaceNodeResults(), llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(), widenVectorOpsToi8(), and llvm::X86TargetLowering::X86TargetLowering().
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inline |
Return a vector with the same number of elements as this vector, but with the element type converted to an integer type with the same bitwidth.
Definition at line 229 of file MachineValueType.h.
References assert(), getFixedSizeInBits(), getIntegerVT(), getVectorElementCount(), getVectorElementType(), getVectorVT(), INVALID_SIMPLE_VALUE_TYPE, MVT(), and SimpleTy.
Referenced by changeTypeToInteger(), llvm::EVT::changeVectorElementTypeToInteger(), combineSetCCMOVMSK(), lowerBuildVectorViaVID(), lowerShuffleAsVALIGN(), lowerVECTOR_SHUFFLE_VSHUF(), lowerVECTOR_SHUFFLE_XVSHUF(), lowerVECTOR_SHUFFLEAsVSlide1(), lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND(), lowerVectorStrictFTRUNC_FCEIL_FFLOOR_FROUND(), lowerZvzipVPAIR(), lowerZvzipVUNZIP(), lowerZvzipVZIP(), and llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode().
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inlinestatic |
Definition at line 643 of file MachineValueType.h.
References llvm::enum_seq_inclusive(), and llvm::force_iteration_on_noniterable_enum.
| void MVT::dump | ( | ) | const |
Support for debugging, callable in GDB: VT.dump()
Definition at line 385 of file ValueTypes.cpp.
References llvm::dbgs(), and print().
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inlinestatic |
Definition at line 607 of file MachineValueType.h.
References llvm::enum_seq_inclusive(), and llvm::force_iteration_on_noniterable_enum.
Referenced by llvm::AArch64TargetLowering::AArch64TargetLowering(), llvm::ARMTargetLowering::ARMTargetLowering(), llvm::HexagonTargetLowering::HexagonTargetLowering(), llvm::LoongArchTargetLowering::LoongArchTargetLowering(), llvm::MipsSETargetLowering::MipsSETargetLowering(), llvm::NVPTXTargetLowering::NVPTXTargetLowering(), llvm::PPCTargetLowering::PPCTargetLowering(), llvm::SystemZTargetLowering::SystemZTargetLowering(), llvm::WebAssemblyTargetLowering::WebAssemblyTargetLowering(), and llvm::X86TargetLowering::X86TargetLowering().
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inlinestatic |
Definition at line 625 of file MachineValueType.h.
References llvm::enum_seq_inclusive(), and llvm::force_iteration_on_noniterable_enum.
Referenced by llvm::AArch64TargetLowering::AArch64TargetLowering(), llvm::MipsTargetLowering::MipsTargetLowering(), llvm::NVPTXTargetLowering::NVPTXTargetLowering(), and llvm::RISCVTargetLowering::RISCVTargetLowering().
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inlinestatic |
Definition at line 637 of file MachineValueType.h.
References llvm::enum_seq_inclusive(), and llvm::force_iteration_on_noniterable_enum.
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inlinestatic |
Definition at line 596 of file MachineValueType.h.
References llvm::enum_seq_inclusive(), and llvm::force_iteration_on_noniterable_enum.
Referenced by llvm::AArch64TargetLowering::AArch64TargetLowering(), llvm::ARMTargetLowering::ARMTargetLowering(), llvm::HexagonTargetLowering::HexagonTargetLowering(), llvm::TargetLoweringBase::initActions(), llvm::MipsTargetLowering::MipsTargetLowering(), llvm::NVPTXTargetLowering::NVPTXTargetLowering(), llvm::PPCTargetLowering::PPCTargetLowering(), llvm::SparcTargetLowering::SparcTargetLowering(), llvm::SystemZTargetLowering::SystemZTargetLowering(), and llvm::XtensaTargetLowering::XtensaTargetLowering().
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inline |
Definition at line 281 of file MachineValueType.h.
References getVectorElementCount(), getVectorElementType(), getVectorVT(), and MVT().
Referenced by combinePTESTCC(), combineTargetShuffle(), combineX86ShuffleChain(), getSmallestVTForIndex(), isLegalVTForZvzipInterleavedOperand(), lowerShuffleAsVTRUNC(), lowerZvzipVUNZIP(), and lowerZvzipVZIP().
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Return the size of the specified fixed width value type in bits.
The function will assert if the type is scalable.
Definition at line 404 of file MachineValueType.h.
References llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::getFixedValue(), getSizeInBits(), and uint64_t.
Referenced by CC_AIX(), changeTypeToInteger(), changeVectorElementTypeToInteger(), combineINSERT_SUBVECTOR(), combineTargetShuffle(), llvm::TargetLoweringBase::computeRegisterProperties(), costShuffleViaVRegSplitting(), getCopyToPartsVector(), llvm::AArch64TargetLowering::getVectorTypeBreakdownForCallingConv(), is1024BitVector(), is128BitVector(), is16BitVector(), is2048BitVector(), is256BitVector(), is32BitVector(), is512BitVector(), is64BitVector(), lowerBUILD_VECTOR(), LowerEXTEND_VECTOR_INREG(), LowerFunnelShift(), lowerShuffleViaVRegSplitting(), LowerVSETCC(), MatchingStackOffset(), truncateScalarIntegerArg(), tryWidenMaskForShuffle(), useRVVForFixedLengthVectorVT(), and widenSubVector().
Definition at line 493 of file MachineValueType.h.
References llvm::BitWidth, llvm_unreachable, and MVT().
Referenced by combineBitcast(), combineConcatVectorOps(), combineCVTP2I_CVTTP2I(), combinePTESTCC(), combineSetCCMOVMSK(), combineVECREDUCE_LOGIC(), combineX86ShuffleChain(), combineX86ShufflesConstants(), EltsFromConsecutiveLoads(), llvm::RISCVTTIImpl::getCastInstrCost(), llvm::EVT::getFloatingPointVT(), llvm::getMVTForLLT(), lower256BitShuffle(), lowerVECTOR_SHUFFLE(), llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(), tryLowerSmallVectorExtLoad(), tryWidenMaskForShuffle(), tryWidenMaskForShuffle(), and widenShuffleMask().
| const fltSemantics & MVT::getFltSemantics | ( | ) | const |
Returns an APFloat semantics tag appropriate for the value type.
If this is a vector type, the element semantics are returned.
Definition at line 367 of file ValueTypes.cpp.
References llvm::APFloatBase::BFloat(), getScalarType(), llvm::APFloatBase::IEEEdouble(), llvm::APFloatBase::IEEEhalf(), llvm::APFloatBase::IEEEquad(), llvm::APFloatBase::IEEEsingle(), llvm_unreachable, llvm::APFloatBase::PPCDoubleDouble(), SimpleTy, and llvm::APFloatBase::x87DoubleExtended().
Referenced by CastIntSETCCtoFP(), llvm::EVT::getFltSemantics(), LowerFABSorFNEG(), LowerFCOPYSIGN(), LowerFROUND(), lowerFTRUNC_FCEIL_FFLOOR_FROUND(), lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND(), and lowerVectorStrictFTRUNC_FCEIL_FFLOOR_FROUND().
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Return a VT for a vector type with the same element type but half the number of elements.
Definition at line 272 of file MachineValueType.h.
References assert(), getVectorElementCount(), getVectorElementType(), getVectorVT(), and MVT().
Referenced by canonicalizeShuffleMaskWithHorizOp(), combineAddMulh(), combineOr(), combineSetCCMOVMSK(), combineTargetShuffle(), llvm::RISCVTargetLowering::decomposeSubvectorInsertExtractToSubRegs(), getShuffleHalfVectors(), isLegalVTForZvzipInterleavedOperand(), LowerAVXCONCAT_VECTORS(), LowerAVXExtend(), LowerCONCAT_VECTORSvXi1(), LowerEXTEND_VECTOR_INREG(), llvm::RISCVTargetLowering::LowerOperation(), lowerShuffleWithUndefHalf(), LowerSIGN_EXTEND(), LowerTruncateVecPack(), LowerTruncateVecPackWithSignBits(), lowerV2X128Shuffle(), lowerVECTOR_SHUFFLEAsPZip(), lowerZvzipVUNZIP(), llvm::RISCVTargetLowering::PerformDAGCombine(), and llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode().
Definition at line 503 of file MachineValueType.h.
References llvm::BitWidth, INVALID_SIMPLE_VALUE_TYPE, and MVT().
Referenced by changeTypeToInteger(), changeVectorElementTypeToInteger(), combineArithReduction(), combineBitcast(), combineConcatVectorOps(), combineSmallMaskReduction(), combineVectorInsert(), combineWideMaskReduction(), combineX86INT_TO_FP(), combineX86ShuffleChain(), combineX86ShufflesConstants(), llvm::computeSignatureVTs(), EltsFromConsecutiveLoads(), ExtendSrcToDst(), ExtractBitFromMaskVector(), llvm::SelectionDAG::getAtomicMemset(), llvm::RISCVTTIImpl::getCastInstrCost(), getDeinterleaveShiftAndTrunc(), getDWordFromOffset(), llvm::EVT::getIntegerVT(), getLegalMaskAndStepVector(), getMaskNode(), llvm::SelectionDAG::getMemset(), llvm::getMVTForLLT(), llvm::RISCVTargetLowering::getOptimalMemOpType(), getPermuteNode(), llvm::TargetLoweringBase::getPointerMemTy(), llvm::TargetLoweringBase::getPointerTy(), getRegistersForValue(), llvm::M68kTargetLowering::getScalarShiftAmountTy(), llvm::TargetLoweringBase::getScalarShiftAmountTy(), llvm::ARMTargetLowering::getTgtMemIntrinsic(), llvm::SelectionDAGBuilder::getValueImpl(), getVCIXISDNodeWCHAIN(), getVectorBitwiseReduce(), llvm::TargetLoweringBase::getVectorIdxTy(), getVT(), getWideningInterleave(), getWideningSpread(), llvm::TargetLoweringBase::hasFastEqualityCompare(), llvm::X86TargetLowering::hasFastEqualityCompare(), llvm::TargetLoweringBase::initActions(), insert1BitVector(), InsertBitToMaskVector(), is128BitUnpackShuffleMask(), isLegalBitRotate(), llvm::SystemZVectorConstantInfo::isVectorConstantLegal(), lower1BitShuffle(), LowerABD(), LowerBUILD_VECTORvXi1(), lowerBuildVectorAsBroadcast(), lowerBuildVectorOfConstants(), lowerBuildVectorViaPacking(), LowerCTPOP(), lowerFCOPYSIGN64(), lowerFP_TO_INT_SAT(), LowerFunnelShift(), lowerLaneOp(), LowerMINMAX(), llvm::RISCVTargetLowering::LowerOperation(), lowerPZExt(), LowerRotate(), LowerShift(), lowerShuffleAsBlend(), lowerShuffleAsPermuteAndUnpack(), lowerShuffleAsSpecificExtension(), lowerShuffleAsVTRUNC(), lowerShuffleWithEXPAND(), lowerShuffleWithPACK(), lowerShuffleWithVPMOV(), LowerTruncateVecI1(), llvm::HexagonTargetLowering::LowerUnalignedLoad(), lowerVECTOR_COMPRESS(), LowerVECTOR_SHUFFLE(), lowerVECTOR_SHUFFLE(), lowerVECTOR_SHUFFLEAsZeroOrAnyExtend(), LowerVectorCTLZInRegLUT(), LowerVectorMatch(), matchBinaryPermuteShuffle(), matchPERM(), matchShuffleAsBitRotate(), matchShuffleAsShift(), matchShuffleAsShift(), matchShuffleAsVSHLD(), matchShuffleAsVTRUNC(), matchShuffleWithPACK(), matchUnaryPermuteShuffle(), matchUnaryShuffle(), memsetStore(), mergeHighParts(), performBitcastCombine(), performCONCAT_VECTORSCombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), PerformEXTRACTCombine(), performFP_TO_INTCombine(), PerformVECREDUCE_ADDCombine(), PerformVQDMULHCombine(), processVCIXOperands(), reassociateAddSubLong(), llvm::LoongArchTargetLowering::ReplaceNodeResults(), llvm::X86TargetLowering::ReplaceNodeResults(), scaleVectorType(), llvm::AArch64TargetLowering::shouldTransformSignedTruncationCheck(), llvm::X86TargetLowering::shouldTransformSignedTruncationCheck(), ShrinkLoadReplaceStoreWithStore(), llvm::X86TargetLowering::SimplifyDemandedBitsForTargetNode(), SkipExtensionForVMULL(), llvm::HexagonDAGToDAGISel::StoreInstrForLoadIntrinsic(), TryCombineBaseUpdate(), tryLowerSmallVectorExtLoad(), trySQDMULHCombine(), tryWidenMaskForShuffle(), tryWidenMaskForShuffle(), unpackFromMemLoc(), unpackFromMemLoc(), unpackFromMemLoc(), widenBuildVector(), widenIntegerElementType(), and widenShuffleMask().
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Widens the length of the given vector MVT up to the nearest power of 2 and returns that type.
Definition at line 310 of file MachineValueType.h.
References llvm::ElementCount::get(), llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::getKnownMinValue(), getVectorElementCount(), getVectorElementType(), getVectorVT(), isPow2VectorType(), llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::isScalable(), llvm::Log2_32_Ceil(), and MVT().
Referenced by llvm::TargetLoweringBase::computeRegisterProperties().
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Given a RISC-V vector tuple type, return the num_fields.
Definition at line 532 of file MachineValueType.h.
References assert(), isRISCVVectorTuple(), and SimpleTy.
Referenced by llvm::RISCVTargetLowering::getRegClassIDForVecVT(), and llvm::RISCVTargetLowering::splitValueIntoRegisterParts().
Definition at line 521 of file MachineValueType.h.
References llvm_unreachable, and MVT().
Referenced by getVT(), lowerFixedVectorSegLoadIntrinsics(), and lowerFixedVectorSegStoreIntrinsics().
Definition at line 517 of file MachineValueType.h.
References getVectorVT(), and MVT().
Referenced by getContainerForFixedLengthVector(), llvm::AArch64TTIImpl::getIntrinsicInstrCost(), llvm::RISCVTTIImpl::getIntrinsicInstrCost(), llvm::RISCVTargetLowering::getM1VT(), llvm::RISCVTargetLowering::LowerOperation(), and llvm::RISCVTargetLowering::PerformDAGCombine().
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inline |
Definition at line 408 of file MachineValueType.h.
References llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::getFixedValue(), getScalarType(), getSizeInBits(), and uint64_t.
Referenced by buildFPVecFromScalars4(), canonicalizeBitSelect(), CC_RISCV_FastCC(), CC_RISCV_Impl(), checkSignTestSetCCCombine(), combineAndnp(), combineBitOpWithPACK(), combineBlendOfPermutes(), combineConcatVectorOps(), combineCVTP2I_CVTTP2I(), combineEXTRACT_SUBVECTOR(), combineINSERT_SUBVECTOR(), combineMOVMSK(), combineSetCCMOVMSK(), combineStore(), combineTargetShuffle(), combineTESTP(), combineToVCPOP(), combineVectorCompare(), combineVEXTRACT_STORE(), combineVPMADD(), combineVPMADD52LH(), combineX86INT_TO_FP(), combineX86ShuffleChain(), llvm::X86TargetLowering::ComputeNumSignBitsForTargetNode(), llvm::TargetLoweringBase::computeRegisterProperties(), llvm::RISCVTargetLowering::computeVLMAXBounds(), createPackShuffleMask(), createVariablePermute(), DecodePALIGNRMask(), expandFP_TO_UINT_SSE(), llvm::X86TTIImpl::getArithmeticReductionCost(), getAVX512TruncNode(), llvm::X86TTIImpl::getCmpSelInstrCost(), getConstantVector(), getConstantVector(), getConstVector(), llvm::RegsForValue::getCopyFromRegs(), getDeinterleaveShiftAndTrunc(), getFauxShuffleMask(), getFltSemantics(), llvm::AArch64TTIImpl::getIntrinsicInstrCost(), getMemCmpLoad(), llvm::X86TTIImpl::getMinMaxReductionCost(), llvm::RTLIB::getOUTLINE_ATOMIC(), getPack(), llvm::PPCTargetLowering::getPreferredVectorAction(), llvm::SystemZTargetLowering::getPreferredVectorAction(), llvm::X86TTIImpl::getReplicationShuffleCost(), getScalarValueForVectorElement(), llvm::RISCVTTIImpl::getShuffleCost(), getSmallestVTForIndex(), getTargetShuffleMask(), getTargetVShiftByConstNode(), getTargetVShiftNode(), llvm::TargetLoweringBase::getTypeToPromoteTo(), getVRGatherIndexType(), getWideningInterleave(), getWideningSpread(), is128BitLaneCrossingShuffleMask(), isHorizontalBinOp(), isInterleaveShuffle(), isLegalVTForZvzipInterleavedOperand(), isRepeatedShuffleMask(), isRepeatedShuffleMask(), isRepeatedTargetShuffleMask(), lower256BitShuffle(), LowerABD(), LowerADDSAT_SUBSAT(), LowerBITREVERSE_XOP(), lowerBUILD_VECTORAsBroadCastLoad(), lowerBuildVectorAsBroadcast(), lowerBuildVectorOfConstants(), lowerBuildVectorToBitOp(), LowerCTTZ(), LowerEXTEND_VECTOR_INREG(), LowerFABSorFNEG(), LowerFCOPYSIGN(), lowerFixedVectorSegLoadIntrinsics(), lowerFixedVectorSegStoreIntrinsics(), llvm::AMDGPUTargetLowering::LowerFP_TO_INT_SAT(), LowerFunnelShift(), LowerINTRINSIC_W_CHAIN(), LowerMGATHER(), LowerMINMAX(), LowerMLOAD(), LowerMSCATTER(), LowerMSTORE(), lowerPZExt(), LowerRotate(), LowerShift(), LowerShiftByScalarImmediate(), lowerShuffleAsBitBlend(), lowerShuffleAsBitMask(), lowerShuffleAsBitRotate(), lowerShuffleAsBlend(), lowerShuffleAsBlendAndPermute(), lowerShuffleAsBroadcast(), lowerShuffleAsByteRotateAndPermute(), lowerShuffleAsByteShiftMask(), lowerShuffleAsDecomposedShuffleMerge(), lowerShuffleAsElementInsertion(), lowerShuffleAsLanePermuteAndRepeatedMask(), lowerShuffleAsPermuteAndUnpack(), lowerShuffleAsRepeatedMaskAndLanePermute(), lowerShuffleAsShift(), lowerShuffleAsSpecificExtension(), lowerShuffleAsVALIGN(), lowerShuffleAsVTRUNC(), lowerShuffleAsZeroOrAnyExtend(), lowerShuffleOfExtractsAsVperm(), lowerShuffleWithPACK(), lowerShuffleWithPSHUFB(), lowerShuffleWithVPMOV(), LowerTruncateVecI1(), lowerV4X128Shuffle(), lowerVECTOR_SHUFFLE(), lowerVECTOR_SHUFFLEAsPSlide1(), lowerVECTOR_SHUFFLEAsShift(), lowerVECTOR_SHUFFLEAsZeroOrAnyExtend(), LowerVectorCTLZInRegLUT(), lowerVectorIntrinsicScalars(), LowerVSETCC(), LowerZERO_EXTEND_Mask(), matchBinaryPermuteShuffle(), matchBinaryShuffle(), matchShuffleAsBlend(), matchShuffleAsEXTRQ(), matchShuffleAsINSERTQ(), matchShuffleAsVTRUNC(), matchShuffleWithPACK(), matchShuffleWithSHUFPD(), matchUnaryPermuteShuffle(), matchUnaryShuffle(), llvm::X86::mayFoldLoadIntoBroadcastFromMem(), MergeBlocksConvert(), llvm::RISCVTargetLowering::PerformDAGCombine(), performDemandedBitsCombine(), performFP_TO_INTCombine(), performSHLCombine(), PerformVQDMULHCombine(), processPSInputArgs(), llvm::LoongArchTargetLowering::ReplaceNodeResults(), scaleVectorType(), llvm::RISCVDAGToDAGISel::Select(), llvm::RISCVDAGToDAGISel::selectVLXSEG(), llvm::RISCVDAGToDAGISel::selectVSXSEG(), llvm::LoongArchTargetLowering::SimplifyDemandedBitsForTargetNode(), llvm::X86TargetLowering::SimplifyDemandedBitsForTargetNode(), llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(), widenIntegerElementType(), and widenShuffleMask().
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Definition at line 425 of file MachineValueType.h.
References llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::getFixedValue(), getScalarType(), getStoreSize(), and uint64_t.
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If this is a vector, return the element type, otherwise return this.
Definition at line 321 of file MachineValueType.h.
References getVectorElementType(), isVector(), and MVT().
Referenced by llvm::AMDGPUTargetLowering::analyzeFormalArgumentsCompute(), canCombineAsMaskOperation(), CastIntSETCCtoFP(), changeElementType(), combineConcatVectorOps(), combineEXTRACT_SUBVECTOR(), combineMOVMSK(), combineStore(), combineTargetShuffle(), constructDup(), createVariablePermute(), llvm::TargetLowering::expandBSWAP(), llvm::X86TTIImpl::getArithmeticReductionCost(), getAVX512Node(), getAVX512TruncNode(), getConstantVector(), getFauxShuffleMask(), getFltSemantics(), getFpSemanticsForMVT(), llvm::NVPTXTargetLowering::getPreferredVectorAction(), llvm::SITargetLowering::getPreferredVectorAction(), llvm::SystemZTargetLowering::getPreferredVectorAction(), llvm::X86TTIImpl::getReplicationShuffleCost(), getScalarSizeInBits(), getScalarStoreSize(), getTargetShuffleMask(), getTargetVShiftNode(), getVRGatherIndexType(), isInlineableLiteralOp16(), isLegalConversion(), llvm::LoongArchTargetLowering::isShuffleMaskLegal(), llvm::RISCVTargetLowering::isShuffleMaskLegal(), llvm::X86TargetLowering::isShuffleMaskLegal(), LowerBITREVERSE(), lowerBuildVectorAsBroadcast(), lowerBuildVectorToBitOp(), LowerMLOAD(), LowerMSTORE(), LowerShift(), lowerShuffleAsBroadcast(), llvm::AMDGPUTargetLowering::LowerSIGN_EXTEND_INREG(), lowerVECTOR_SHUFFLEAsRotate(), LowerVectorCTPOP(), matchUnaryShuffle(), MergeBlocksConvert(), llvm::LoongArchTargetLowering::ReplaceNodeResults(), scalarizeVectorStore(), llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(), widenBuildVector(), widenIntegerElementType(), widenSubVector(), and widenSubVector().
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Returns the size of the specified MVT in bits.
If the value type is a scalable vector type, the scalable property will be set and the runtime size will be a positive integer multiple of the base size.
Definition at line 370 of file MachineValueType.h.
References assert(), INVALID_SIMPLE_VALUE_TYPE, llvm_unreachable, llvm::Other, SimpleTy, and VALUETYPE_SIZE.
Referenced by Analyze_CC_Sparc64_Full(), Analyze_CC_Sparc64_Half(), canonicalizeBitSelect(), CC_ARM_AAPCS_Custom_Aggregate(), CC_RISCV_FastCC(), CC_RISCV_Impl(), CC_X86_32_VectorCall(), CC_X86_64_VectorCall(), combineAVX512SetCCToKMOV(), combineConcatVectorOps(), combineEXTRACT_SUBVECTOR(), combineIntDivRem(), combineIntDivRemViaExactFPDiv(), combinePCLMULQDQ(), combinePTESTCC(), combineSetCCMOVMSK(), combineShiftRightArithmetic(), combineTargetShuffle(), combineToVCPOP(), combineVECREDUCE_LOGIC(), combineVectorHADDSUB(), combineVectorSizedSetCCEquality(), combineX86ShuffleChain(), combineX86ShuffleChainWithExtract(), combineX86ShufflesConstants(), combineX86ShufflesRecursively(), llvm::TargetLoweringBase::computeRegisterProperties(), llvm::RISCVTargetLowering::computeVLMAXBounds(), convertShiftLeftToScale(), costShuffleViaSplitting(), costShuffleViaVRegSplitting(), createPackShuffleMask(), createShuffleStride(), createVariablePermute(), createVPDPBUSD(), DecodePALIGNRMask(), emitRepstos(), llvm::TargetLowering::expandUnalignedLoad(), llvm::TargetLowering::expandUnalignedStore(), llvm::FastISel::fastEmit_ri_(), finishStackBlock(), genShuffleBland(), getAVX512Node(), getAVX512TruncNode(), getCopyFromParts(), getCopyFromPartsVector(), getCopyToParts(), getCopyToPartsVector(), getFauxShuffleMask(), getFixedSizeInBits(), getGFNICtrlMask(), llvm::RISCVTargetLowering::getLMUL(), llvm::RISCVTargetLowering::getLMULCost(), getLMULOctuple(), llvm::RISCVTargetLowering::getM1VT(), getMaskNode(), getPack(), llvm::PPCTargetLowering::getPreferredVectorAction(), getPromotedVectorElementType(), llvm::RISCVTargetLowering::getRegClassIDForVecVT(), llvm::ARMTargetLowering::getRegForInlineAsmConstraint(), llvm::HexagonTargetLowering::getRegForInlineAsmConstraint(), llvm::SITargetLowering::getRegForInlineAsmConstraint(), llvm::SystemZTargetLowering::getRegForInlineAsmConstraint(), llvm::X86TargetLowering::getRegForInlineAsmConstraint(), getRegistersForValue(), llvm::RegsForValue::getRegsAndSizes(), getScalarSizeInBits(), getScalarValueForVectorElement(), llvm::X86TargetLowering::getSetCCResultType(), llvm::TargetLoweringBase::getShiftAmountTy(), llvm::X86TTIImpl::getShuffleCost(), getStoreSize(), getSVEMultiVectorInfo(), getTargetShuffleAndZeroables(), getTargetVShiftNode(), getVectorLoweringShape(), llvm::AArch64TargetLowering::getVectorTypeBreakdownForCallingConv(), getZeroVector(), group2Shuffle(), insert1BitVector(), isByteSized(), isHorizontalBinOp(), llvm::X86TargetLowering::isShuffleMaskLegal(), isSupportedType(), isTargetShuffleEquivalent(), llvm::RISCVTargetLowering::joinRegisterPartsIntoValue(), knownBitsGE(), knownBitsGT(), knownBitsLE(), knownBitsLT(), llvm::LLT::LLT(), LowerAsSplatVectorLoad(), llvm::HexagonTargetLowering::LowerBITCAST(), LowerBITREVERSE(), LowerBITREVERSE_XOP(), llvm::HexagonTargetLowering::LowerBUILD_VECTOR(), lowerBUILD_VECTOR(), LowerBUILD_VECTORvXi1(), lowerBuildVectorAsBroadcast(), lowerBuildVectorOfConstants(), lowerBuildVectorViaPacking(), llvm::SystemZTargetLowering::LowerCall(), llvm::SparcTargetLowering::LowerCall_32(), llvm::TargetLowering::LowerCallTo(), LowerCLMUL(), llvm::HexagonTargetLowering::LowerCONCAT_VECTORS(), LowerCTLZ(), LowerEXTEND_VECTOR_INREG(), LowerEXTRACT_VECTOR_ELT_SSE4(), LowerFLDEXP(), llvm::HexagonTargetLowering::LowerFormalArguments(), lowerFP_TO_INT_SAT(), lowerFPToIntToFP(), LowerHorizontalByteSum(), LowerMGATHER(), LowerMINMAX(), LowerMLOAD(), LowerMSCATTER(), LowerMSTORE(), LowerMUL(), llvm::RISCVTargetLowering::LowerOperation(), LowerPARTIAL_REDUCE_FMLA(), LowerPARTIAL_REDUCE_MLA(), LowerSCALAR_TO_VECTOR(), LowerShift(), lowerShuffleAsBlend(), lowerShuffleAsBlendOfPSHUFBs(), lowerShuffleAsByteRotate(), lowerShuffleAsByteRotateAndPermute(), lowerShuffleAsDecomposedShuffleMerge(), lowerShuffleAsElementInsertion(), lowerShuffleAsLanePermuteAndPermute(), lowerShuffleAsLanePermuteAndRepeatedMask(), lowerShuffleAsRepeatedMaskAndLanePermute(), lowerShuffleAsSplitOrBlend(), lowerShuffleAsTruncBroadcast(), lowerShuffleAsUNPCKAndPermute(), lowerShuffleAsZeroOrAnyExtend(), lowerShuffleViaVRegSplitting(), lowerShuffleWithPACK(), lowerShuffleWithPERMV(), lowerShuffleWithPSHUFB(), lowerShuffleWithUndefHalf(), LowerSIGN_EXTEND_Mask(), llvm::LanaiTargetLowering::LowerSRL_PARTS(), LowerTruncateVecI1(), LowerTruncateVecPack(), LowerTruncateVecPackWithSignBits(), llvm::HexagonTargetLowering::LowerUnalignedLoad(), llvm::HexagonTargetLowering::LowerVECTOR_SHIFT(), llvm::HexagonTargetLowering::LowerVECTOR_SHUFFLE(), lowerVECTOR_SHUFFLE(), lowerVECTOR_SHUFFLEAsByteRotate(), lowerVECTOR_SHUFFLEAsRV32PNarrowingShift(), lowerVECTOR_SHUFFLEAsZeroOrAnyExtend(), LowerVectorAllEqual(), LowerVectorCTLZ_AVX512CDI(), LowerVectorCTPOP(), LowerVSETCC(), LowerZERO_EXTEND_Mask(), matchBinaryPermuteShuffle(), matchBinaryShuffle(), MatchingStackOffset(), matchShuffleAsBlend(), matchSplatAsGather(), matchUnaryPermuteShuffle(), MergeBlocksConvert(), mergeHighParts(), narrowExtractedVectorSelect(), performCONCAT_VECTORSCombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), performScatterStoreCombine(), PerformTruncatingStoreCombine(), PerformVCVTCombine(), PerformVMulVCTPCombine(), llvm::LoongArchTargetLowering::ReplaceNodeResults(), llvm::X86TargetLowering::ReplaceNodeResults(), llvm::RISCVDAGToDAGISel::Select(), llvm::HexagonDAGToDAGISel::SelectExtractSubvector(), llvm::HexagonDAGToDAGISel::SelectQ2V(), llvm::RISCVDAGToDAGISel::selectSExtBits(), llvm::LoongArchDAGToDAGISel::selectSExti32(), llvm::HexagonDAGToDAGISel::SelectVAlign(), llvm::RISCVDAGToDAGISel::selectZExtBits(), llvm::LoongArchDAGToDAGISel::selectZExti32(), setGroupSize(), shouldLowerTailCallStackArg(), shouldTransformMulToShiftsAddsSubs(), llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(), splitAndLowerShuffle(), llvm::RISCVTargetLowering::splitValueIntoRegisterParts(), TryCombineBaseUpdate(), llvm::RISCVDAGToDAGISel::trySignedBitfieldExtract(), llvm::RISCVDAGToDAGISel::trySignedBitfieldInsertInSign(), UnpackFromArgumentSlot(), useRVVForFixedLengthVectorVT(), widenBuildVector(), and llvm::XtensaTargetLowering::XtensaTargetLowering().
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Return the number of bytes overwritten by a store of the specified value type.
If the value type is a scalable vector type, the scalable property will be set and the runtime size will be a positive integer multiple of the base size.
Definition at line 418 of file MachineValueType.h.
References llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::getKnownMinValue(), getSizeInBits(), and llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::isScalable().
Referenced by llvm::analyzeArguments(), llvm::analyzeReturnValues(), CC_AIX(), CC_MipsO32(), CC_RISCV_FastCC(), CC_RISCV_Impl(), CC_Xtensa_Custom(), combineTargetShuffle(), ComputePTXValueVTs(), costShuffleViaSplitting(), costShuffleViaVRegSplitting(), llvm::PPCTargetLowering::emitEHSjLjLongJmp(), llvm::SystemZTargetLowering::emitEHSjLjLongJmp(), llvm::PPCTargetLowering::emitEHSjLjSetJmp(), llvm::SystemZTargetLowering::emitEHSjLjSetJmp(), llvm::BasicTTIImplBase< BasicTTIImpl >::getInterleavedMemoryOpCost(), llvm::X86TTIImpl::getInterleavedMemoryOpCostAVX512(), llvm::RISCVTargetLowering::getOptimalMemOpType(), llvm::MSP430TargetLowering::getReturnAddressFrameIndex(), getScalarStoreSize(), llvm::X86TTIImpl::getShuffleCost(), getStoreSizeInBits(), llvm::SITargetLowering::LowerCall(), llvm::RISCVTargetLowering::LowerOperation(), lowerShuffleAsBroadcast(), lowerV2X128Shuffle(), scalarizeVectorStore(), and llvm::RISCVDAGToDAGISel::Select().
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Return the number of bits overwritten by a store of the specified value type.
If the value type is a scalable vector type, the scalable property will be set and the runtime size will be a positive integer multiple of the base size.
Definition at line 435 of file MachineValueType.h.
References getStoreSize().
Referenced by llvm::HexagonTargetLowering::LowerCall(), and llvm::HexagonTargetLowering::LowerFormalArguments().
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Return the value type as a string, e.g. i32.
Definition at line 78 of file MachineValueType.h.
References print().
Referenced by ensureMatchedVecRegParts().
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Definition at line 352 of file MachineValueType.h.
References llvm::ElementCount::get(), getVectorMinNumElements(), and isScalableVector().
Referenced by changeVectorElementType(), changeVectorElementTypeToInteger(), llvm::TargetLoweringBase::computeRegisterProperties(), llvm::RISCVTargetLowering::computeVLMax(), llvm::RISCVTargetLowering::decomposeSubvectorInsertExtractToSubRegs(), getCopyToPartsVector(), getDoubleNumVectorElementsVT(), getHalfNumVectorElementsVT(), getMaskTypeFor(), getPow2VectorType(), llvm::SystemZTargetLowering::getPreferredVectorAction(), llvm::TargetLoweringBase::getPreferredVectorAction(), getQDOTXResultType(), getWideningInterleave(), getWideningSpread(), isPromotedOpNeedingSplit(), llvm::LLT::LLT(), lowerCttzElts(), lowerFP_TO_INT_SAT(), llvm::RISCVTargetLowering::LowerOperation(), lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND(), lowerVectorIntrinsicScalars(), llvm::RISCVTargetLowering::RISCVTargetLowering(), llvm::RISCVDAGToDAGISel::Select(), and splatPartsI64WithVL().
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Definition at line 325 of file MachineValueType.h.
References assert(), INVALID_SIMPLE_VALUE_TYPE, MVT(), and SimpleTy.
Referenced by allocateRVVReg(), changeVectorElementCount(), changeVectorElementTypeToInteger(), combineAVX512SetCCToKMOV(), combineBitcast(), combineEXTRACT_SUBVECTOR(), combineINSERT_SUBVECTOR(), combinePCLMULQDQ(), combineShuffleToAddSubOrFMAddSub(), combineTargetShuffle(), llvm::TargetLoweringBase::computeRegisterProperties(), convertShiftLeftToScale(), costShuffleViaSplitting(), costShuffleViaVRegSplitting(), ExtendToType(), getConstVector(), getConstVector(), getContainerForFixedLengthVector(), getDeinterleaveShiftAndTrunc(), getDoubleNumVectorElementsVT(), llvm::HexagonTargetLowering::getExtractSubvectorCost(), getGFNICtrlMask(), getHalfNumVectorElementsVT(), llvm::AArch64TTIImpl::getIntrinsicInstrCost(), llvm::RISCVTargetLowering::getLMUL(), llvm::RISCVTargetLowering::getM1VT(), getMaskNode(), getPow2VectorType(), llvm::HexagonTargetLowering::getPreferredVectorAction(), llvm::LoongArchTargetLowering::getPreferredVectorAction(), llvm::X86TargetLowering::getPreferredVectorAction(), getQDOTXResultType(), llvm::RISCVTargetLowering::getRegClassIDForVecVT(), getScalarType(), getScalarValueForVectorElement(), llvm::X86TargetLowering::getSetCCResultType(), llvm::X86TTIImpl::getShuffleCost(), getShuffleScalarElt(), getSVEMultiVectorInfo(), getTargetVShiftNode(), llvm::AArch64TargetLowering::getTgtMemIntrinsic(), llvm::X86TargetLowering::getTgtMemIntrinsic(), llvm::TargetLoweringBase::getTypeConversion(), getUnderlyingExtractedFromVec(), getVectorLoweringShape(), llvm::AArch64TargetLowering::getVectorTypeBreakdownForCallingConv(), getWideningInterleave(), getWideningSpread(), getZeroVector(), incDecVectorConstant(), isFixedLengthVectorOf(), llvm::HexagonSubtarget::isHVXVectorType(), isLegalT2AddressImmediate(), isPromotedOpNeedingSplit(), isScalableVectorOf(), isVectorOf(), llvm::RISCVTargetLowering::joinRegisterPartsIntoValue(), llvm::LLT::LLT(), LowerANY_EXTEND(), LowerAVXExtend(), LowerBITCAST(), lowerBitreverseShuffle(), lowerBUILD_VECTOR(), LowerBUILD_VECTORvXi1(), lowerBuildVectorOfConstants(), LowerBuildVectorv4x32(), lowerBuildVectorViaPacking(), llvm::HexagonTargetLowering::LowerCONCAT_VECTORS(), LowerCONCAT_VECTORS(), lowerCONVERT_FROM_ARBITRARY_FP(), LowerCTTZ(), LowerEXTEND_VECTOR_INREG(), lowerFP_TO_INT_SAT(), LowerHorizontalByteSum(), LowerIntVSETCC_AVX512(), LowerLoad(), LowerMGATHER(), LowerMLOAD(), LowerMSCATTER(), LowerMULH(), llvm::RISCVTargetLowering::LowerOperation(), LowerSCALAR_TO_VECTOR(), lowerScalarInsert(), lowerScalarSplat(), lowerShuffleAsBroadcast(), lowerShuffleAsElementInsertion(), lowerShuffleAsTruncBroadcast(), lowerShuffleViaVRegSplitting(), lowerShuffleWithUndefHalf(), LowerSIGN_EXTEND(), LowerSIGN_EXTEND_Mask(), LowerTruncateVecI1(), LowerTruncateVecPack(), LowerTruncateVecPackWithSignBits(), lowerV2X128Shuffle(), lowerV4X128Shuffle(), lowerV8I16GeneralSingleInputShuffle(), llvm::HexagonTargetLowering::LowerVECTOR_SHIFT(), llvm::HexagonTargetLowering::LowerVECTOR_SHUFFLE(), lowerVECTOR_SHUFFLE(), lowerVECTOR_SHUFFLE_IsReverse(), lowerVECTOR_SHUFFLE_VEXTRINS(), lowerVECTOR_SHUFFLE_XVEXTRINS(), lowerVECTOR_SHUFFLEAsRV32PNarrowingShift(), lowerVECTOR_SHUFFLEAsVSlide1(), LowerVectorCTLZ(), LowerVectorCTLZ_AVX512CDI(), LowerVectorCTPOP(), LowerVectorCTPOPInRegLUT(), lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND(), lowerVectorIntrinsicScalars(), lowerVectorStrictFTRUNC_FCEIL_FFLOOR_FROUND(), lowerVectorXRINT_XROUND(), LowerVSETCC(), LowerVSETCCWithSUBUS(), LowerZERO_EXTEND(), LowerZERO_EXTEND_Mask(), matchSplatAsGather(), narrowExtractedVectorSelect(), llvm::NVPTXTargetLowering::NVPTXTargetLowering(), performConcatVectorsCombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), performVWABDACombine(), performVWABDACombineWV(), llvm::RISCVDAGToDAGISel::PreprocessISelDAG(), llvm::LoongArchTargetLowering::ReplaceNodeResults(), llvm::RISCVTargetLowering::ReplaceNodeResults(), llvm::X86TargetLowering::ReplaceNodeResults(), llvm::RISCVTargetLowering::RISCVTargetLowering(), scaleVectorType(), llvm::RISCVDAGToDAGISel::Select(), llvm::HexagonDAGToDAGISel::SelectExtractSubvector(), llvm::HvxSelector::selectExtractSubvector(), llvm::X86TargetLowering::SimplifyDemandedBitsForTargetNode(), llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(), splitAndLowerShuffle(), llvm::VETargetLowering::splitPackedLoadStore(), llvm::RISCVTargetLowering::splitValueIntoRegisterParts(), llvm::splitVectorType(), tryExtendDUPToExtractHigh(), tryWidenMaskForShuffle(), useRVVForFixedLengthVectorVT(), widenMaskVectorType(), and llvm::X86TargetLowering::X86TargetLowering().
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Given a vector type, return the minimum number of elements it contains.
Definition at line 339 of file MachineValueType.h.
References assert(), and SimpleTy.
Referenced by llvm::HexagonTargetLowering::getPreferredVectorAction(), llvm::RISCVTTIImpl::getShuffleCost(), getVectorElementCount(), getVectorNumElements(), isPow2VectorType(), llvm::LLT::LLT(), lowerBUILD_VECTOR(), lowerFixedVectorSegLoadIntrinsics(), lowerFixedVectorSegStoreIntrinsics(), lowerShuffleViaVRegSplitting(), lowerZvzipVUNZIP(), matchSplatAsGather(), llvm::RISCVTargetLowering::PerformDAGCombine(), performVECTOR_INTERLEAVECombine(), llvm::RISCVDAGToDAGISel::selectVLXSEG(), llvm::RISCVDAGToDAGISel::selectVSXSEG(), and tryLowerMultiVectorStore().
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Definition at line 356 of file MachineValueType.h.
References getVectorMinNumElements(), isScalableVector(), and llvm::reportFatalInternalError().
Referenced by llvm::AMDGPUTargetLowering::analyzeFormalArgumentsCompute(), canonicalizeShuffleMaskWithHorizOp(), combineAndnp(), combineBitcast(), combineBlendOfPermutes(), combineConcatVectorOps(), combineCVTP2I_CVTTP2I(), combineEXTRACT_SUBVECTOR(), combineINSERT_SUBVECTOR(), combineMOVMSK(), combinePCLMULQDQ(), combineSetCCMOVMSK(), combineStore(), combineTargetShuffle(), combineToVCPOP(), combineVECREDUCE_LOGIC(), combineVectorCompare(), combineVEXTRACT_STORE(), combineVPMADD(), combineX86INT_TO_FP(), combineX86ShuffleChain(), llvm::X86TargetLowering::ComputeNumSignBitsForTargetNode(), convertShiftLeftToScale(), costShuffleViaSplitting(), costShuffleViaVRegSplitting(), createPackShuffleMask(), createShuffleStride(), llvm::createSplat2ShuffleMask(), createVariablePermute(), DecodePALIGNRMask(), ExtendToType(), ExtractBitFromMaskVector(), genShuffleBland(), llvm::AArch64TTIImpl::getArithmeticReductionCost(), llvm::X86TTIImpl::getArithmeticReductionCost(), getAVX512TruncNode(), getConstVector(), getConstVector(), getContainerForFixedLengthVector(), getDefaultVLOps(), getExtractedDemandedElts(), getFauxShuffleMask(), getGatherNode(), llvm::X86TTIImpl::getInterleavedMemoryOpCostAVX512(), getMaskNode(), getMemCmpLoad(), llvm::X86TTIImpl::getMinMaxReductionCost(), getPack(), llvm::LoongArchTargetLowering::getPreferredVectorAction(), llvm::NVPTXTargetLowering::getPreferredVectorAction(), llvm::PPCTargetLowering::getPreferredVectorAction(), llvm::SITargetLowering::getPreferredVectorAction(), llvm::X86TargetLowering::getPreferredVectorAction(), llvm::X86TTIImpl::getReplicationShuffleCost(), getScalarMaskingNode(), llvm::X86TTIImpl::getShuffleCost(), getShuffleHalfVectors(), getShuffleScalarElt(), getShuffleVectorZeroOrUndef(), getSingleShuffleSrc(), llvm::CallLowering::ValueHandler::getStackValueStoreType(), getTargetShuffleAndZeroables(), getTargetShuffleMask(), getTargetVShiftNode(), llvm::ARMTargetLowering::getTgtMemIntrinsic(), llvm::X86TargetLowering::getTgtMemIntrinsic(), getUnderlyingExtractedFromVec(), getVectorLoweringShape(), getVRGatherIndexType(), getZeroVector(), group2Shuffle(), incDecVectorConstant(), insert1BitVector(), InsertBitToMaskVector(), llvm::X86TargetLowering::isGuaranteedNotToBeUndefOrPoisonForTargetNode(), isHorizontalBinOp(), isInterleaveShuffle(), lower128BitShuffle(), lower1BitShuffle(), lower256BitShuffle(), lower256BitShuffle(), LowerAsSplatVectorLoad(), LowerAVXExtend(), LowerBITCAST(), LowerBITREVERSE(), LowerBITREVERSE_XOP(), lowerBitreverseShuffle(), llvm::HexagonTargetLowering::LowerBUILD_VECTOR(), llvm::VETargetLowering::lowerBUILD_VECTOR(), lowerBUILD_VECTOR(), LowerBUILD_VECTORvXi1(), lowerBuildVectorAsBlend(), lowerBuildVectorAsBroadcast(), LowerBuildVectorAsInsert(), lowerBuildVectorOfConstants(), lowerBuildVectorToBitOp(), lowerBuildVectorViaPacking(), llvm::HexagonTargetLowering::LowerCONCAT_VECTORS(), LowerCONCAT_VECTORSvXi1(), LowerEXTEND_VECTOR_INREG(), LowerFunnelShift(), LowerLoad(), LowerMGATHER(), LowerMSCATTER(), LowerMUL(), LowerMULH(), LowerMULO(), llvm::RISCVTargetLowering::LowerOperation(), lowerPZExt(), LowerRotate(), LowerSCALAR_TO_VECTOR(), LowerShift(), LowerShiftByScalarImmediate(), LowerShiftByScalarVariable(), lowerShuffleAsBlend(), lowerShuffleAsBroadcast(), lowerShuffleAsByteRotateAndPermute(), lowerShuffleAsElementInsertion(), lowerShuffleAsLanePermuteAndPermute(), lowerShuffleAsRepeatedMaskAndLanePermute(), lowerShuffleAsShift(), lowerShuffleAsSpecificExtension(), lowerShuffleAsVTRUNC(), lowerShuffleAsZeroOrAnyExtend(), lowerShuffleOfExtractsAsVperm(), lowerShufflePairAsUNPCKAndPermute(), lowerShuffleWithEXPAND(), lowerShuffleWithPERMV(), lowerShuffleWithUndefHalf(), lowerShuffleWithVPMOV(), LowerSIGN_EXTEND(), llvm::AMDGPUTargetLowering::LowerSIGN_EXTEND_INREG(), LowerSIGN_EXTEND_Mask(), LowerTruncateVecI1(), LowerTruncateVecPack(), lowerV8I16GeneralSingleInputShuffle(), lowerVECTOR_SHUFFLE(), lowerVECTOR_SHUFFLE_IsReverse(), lowerVECTOR_SHUFFLE_VEXTRINS(), lowerVECTOR_SHUFFLE_VPERMI(), lowerVECTOR_SHUFFLE_XVEXTRINS(), lowerVECTOR_SHUFFLE_XVINSVE0(), lowerVECTOR_SHUFFLE_XVPERM(), lowerVECTOR_SHUFFLE_XVPERMI(), lowerVECTOR_SHUFFLEAsPPair(), lowerVECTOR_SHUFFLEAsPSlide1(), lowerVECTOR_SHUFFLEAsPZip(), lowerVECTOR_SHUFFLEAsRV32PNarrowingShift(), lowerVECTOR_SHUFFLEAsShift(), lowerVECTOR_SHUFFLEAsVRGatherVX(), lowerVECTOR_SHUFFLEAsVSlide1(), lowerVECTOR_SHUFFLEAsVSlideup(), lowerVECTOR_SHUFFLEAsZeroOrAnyExtend(), LowerVectorCTLZ_AVX512CDI(), LowerVectorCTLZInRegLUT(), LowerVectorCTPOP(), LowerVectorCTPOPInRegLUT(), LowerVSETCC(), LowervXi8MulWithUNPCK(), LowerZERO_EXTEND_Mask(), matchShuffleAsEXTRQ(), matchShuffleAsINSERTQ(), matchShuffleWithPACK(), matchShuffleWithSHUFPD(), matchShuffleWithUNPCK(), matchUnaryShuffle(), narrowExtractedVectorSelect(), performConcatVectorsCombine(), performUADDVCombine(), llvm::LoongArchTargetLowering::ReplaceNodeResults(), llvm::RISCVTargetLowering::ReplaceNodeResults(), llvm::X86TargetLowering::ReplaceNodeResults(), scalarizeVectorStore(), scaleVectorType(), llvm::HexagonDAGToDAGISel::SelectExtractSubvector(), llvm::HvxSelector::selectExtractSubvector(), setGroupSize(), llvm::LoongArchTargetLowering::SimplifyDemandedBitsForTargetNode(), llvm::X86TargetLowering::SimplifyDemandedBitsForTargetNode(), llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(), llvm::X86TargetLowering::SimplifyMultipleUseDemandedBitsForTargetNode(), splitAndLowerShuffle(), tryExtendDUPToExtractHigh(), tryWidenMaskForShuffle(), useRVVForFixedLengthVectorVT(), widenBuildVector(), widenMaskVectorType(), and widenShuffleMask().
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Definition at line 567 of file MachineValueType.h.
References getVectorVT(), and MVT().
Definition at line 513 of file MachineValueType.h.
References getVectorVT(), and MVT().
Referenced by llvm::AArch64TargetLowering::AArch64TargetLowering(), AddCombineBUILD_VECTORToVPADDL(), canonicalizeBitSelect(), canonicalizeShuffleMaskWithHorizOp(), changeVectorElementCount(), llvm::EVT::changeVectorElementType(), changeVectorElementType(), changeVectorElementTypeToInteger(), combineArithReduction(), combineBitcast(), combineConcatVectorOps(), combineCVTP2I_CVTTP2I(), combineExtractVectorElt(), combineExtractWithShuffle(), combineFaddCFmul(), combineFMADDSUB(), combineIntDivRemViaExactFPDiv(), combineMOVMSK(), combineMulToPMADDWD(), combinePTESTCC(), combineSetCCMOVMSK(), combineStore(), combineTargetShuffle(), combineVECREDUCE_LOGIC(), combineVectorHADDSUB(), combineVectorInsert(), combineX86INT_TO_FP(), combineX86ShuffleChain(), combineX86ShufflesConstants(), ConstantBuildVector(), constructDup(), constructRetValue(), createPSADBW(), createVariablePermute(), createVPDPBUSD(), detectPMADDUBSW(), EltsFromConsecutiveLoads(), ExtractBitFromMaskVector(), llvm::X86TTIImpl::getArithmeticInstrCost(), getAVX512Node(), getAVX512TruncNode(), llvm::HvxSelector::getBoolVT(), getBuildDwordsVector(), getConstVector(), getConstVector(), getDeinterleaveShiftAndTrunc(), getDoubleNumVectorElementsVT(), getDWordFromOffset(), getGatherNode(), getHalfNumVectorElementsVT(), llvm::X86TTIImpl::getInterleavedMemoryOpCostAVX512(), llvm::getLegalVectorType(), llvm::VECustomDAG::getMaskBroadcast(), getMaskNode(), getMaskTypeFor(), llvm::getMVTForLLT(), getOnesVector(), llvm::RISCVTargetLowering::getOptimalMemOpType(), llvm::HvxSelector::getPairVT(), getPermuteNode(), getPow2VectorType(), getPrefetchNode(), getPromotedVectorElementType(), getQDOTXResultType(), llvm::SITargetLowering::getRegisterTypeForCallingConv(), llvm::SPIRVTargetLowering::getRegisterTypeForCallingConv(), getScalableVectorVT(), getScatterNode(), llvm::HvxSelector::getSingleVT(), getTargetVShiftNode(), llvm::ARMTargetLowering::getTgtMemIntrinsic(), llvm::X86TargetLowering::getTgtMemIntrinsic(), llvm::TargetLoweringBase::getTypeConversion(), getVCIXISDNodeWCHAIN(), getVectorLoweringShape(), llvm::SITargetLowering::getVectorTypeBreakdownForCallingConv(), llvm::EVT::getVectorVT(), llvm::EVT::getVectorVT(), getVectorVT(), getVectorVT(), getVT(), getWideningInterleave(), getWideningSpread(), getZeroVector(), llvm::HexagonTargetLowering::HexagonTargetLowering(), InsertBitToMaskVector(), is128BitUnpackShuffleMask(), isLegalBitRotate(), isPromotedOpNeedingSplit(), llvm::HexagonSubtarget::isTypeForHVX(), llvm::SystemZVectorConstantInfo::isVectorConstantLegal(), lower1BitShuffle(), lower256BitShuffle(), LowerBITCAST(), LowerBITREVERSE(), LowerBITREVERSE_XOP(), lowerBUILD_VECTOR(), lowerBuildVectorAsBroadcast(), lowerBuildVectorOfConstants(), lowerBuildVectorViaPacking(), LowerCLMUL(), LowerCONCAT_VECTORS_i1(), LowerCTPOP(), LowerEXTRACT_SUBVECTOR(), LowerFLDEXP(), LowerFMINIMUM_FMAXIMUM(), lowerFPToIntToFP(), LowerFunnelShift(), LowerHorizontalByteSum(), LowerI64IntToFP_AVX512DQ(), LowerINTRINSIC_W_CHAIN(), lowerLaneOp(), LowerMGATHER(), LowerMINMAX(), LowerMLOAD(), LowerMSCATTER(), LowerMSTORE(), LowerMUL(), LowerMULH(), LowerMULO(), llvm::RISCVTargetLowering::LowerOperation(), lowerPZExt(), LowerRotate(), LowerSCALAR_TO_VECTOR(), LowerShift(), LowerShiftByScalarImmediate(), LowerShiftByScalarVariable(), lowerShuffleAsBlend(), lowerShuffleAsBlendOfPSHUFBs(), lowerShuffleAsBroadcast(), lowerShuffleAsByteRotate(), lowerShuffleAsByteRotateAndPermute(), lowerShuffleAsElementInsertion(), lowerShuffleAsPermuteAndUnpack(), lowerShuffleAsSpecificExtension(), lowerShuffleAsVTRUNC(), lowerShuffleViaVRegSplitting(), lowerShuffleWithEXPAND(), lowerShuffleWithPACK(), lowerShuffleWithPSHUFB(), lowerShuffleWithVPMOV(), LowerSIGN_EXTEND_Mask(), LowerStore(), lowerSTOREVector(), LowerTruncateVecI1(), LowerTruncateVecPack(), llvm::HexagonTargetLowering::LowerUnalignedLoad(), lowerV2X128Shuffle(), lowerV4X128Shuffle(), lowerV8I16GeneralSingleInputShuffle(), lowerVECTOR_COMPRESS(), llvm::HexagonTargetLowering::LowerVECTOR_SHIFT(), LowerVECTOR_SHUFFLE(), lowerVECTOR_SHUFFLE(), lowerVECTOR_SHUFFLE_IsReverse(), lowerVECTOR_SHUFFLEAsByteRotate(), lowerVECTOR_SHUFFLEAsVRGatherVX(), lowerVECTOR_SHUFFLEAsZeroOrAnyExtend(), LowerVectorAllEqual(), LowerVectorCTLZ_AVX512CDI(), LowerVectorCTLZInRegLUT(), LowerVectorCTPOP(), lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND(), lowerVectorIntrinsicScalars(), LowerVectorMatch(), LowervXi8MulWithUNPCK(), LowerZERO_EXTEND_Mask(), matchBinaryPermuteShuffle(), matchShuffleAsBitRotate(), matchShuffleAsShift(), matchShuffleAsShift(), matchShuffleAsVSHLD(), matchShuffleAsVTRUNC(), matchShuffleWithPACK(), matchUnaryPermuteShuffle(), matchUnaryShuffle(), MergeBlocksConvert(), mergeHighParts(), llvm::MipsTargetLowering::MipsTargetLowering(), narrowExtractedVectorSelect(), NarrowVector(), performCONCAT_VECTORSCombine(), performConcatVectorsCombine(), performFP_TO_INTCombine(), PerformVQDMULHCombine(), processVCIXOperands(), replaceLoadVector(), llvm::LoongArchTargetLowering::ReplaceNodeResults(), llvm::X86TargetLowering::ReplaceNodeResults(), llvm::RISCVTargetLowering::RISCVTargetLowering(), scaleVectorType(), llvm::X86TargetLowering::SimplifyDemandedBitsForTargetNode(), llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(), SkipExtensionForVMULL(), splatPartsI64WithVL(), splitAndLowerShuffle(), llvm::splitVectorType(), TryCombineBaseUpdate(), tryExtendDUPToExtractHigh(), tryLowerSmallVectorExtLoad(), trySQDMULHCombine(), tryWidenMaskForShuffle(), tryWidenMaskForShuffle(), vectorizeExtractedCast(), widenBuildVector(), widenShuffleMask(), widenSubVector(), WidenVector(), and llvm::X86TargetLowering::X86TargetLowering().
Definition at line 560 of file MachineValueType.h.
References INVALID_SIMPLE_VALUE_TYPE, llvm::MVT::VecVTTable::MaxNumElements, MVT(), SimpleTy, and VecVTs.
Return the value type corresponding to the specified type.
If HandleUnknown is true, unknown types are returned as Other, otherwise they are invalid. NB: This includes pointer types, which require a DataLayout to convert to a concrete value type.
Definition at line 289 of file ValueTypes.cpp.
References assert(), llvm::Type::BFloatTyID, llvm::Type::ByteTyID, llvm::cast(), llvm::Type::DoubleTyID, llvm::Type::FixedVectorTyID, llvm::Type::FloatTyID, llvm::Type::FP128TyID, getBitWidth(), llvm::VectorType::getElementCount(), llvm::VectorType::getElementType(), getIntegerVT(), llvm::TargetExtType::getIntParameter(), llvm::TargetExtType::getName(), getRISCVVectorTupleVT(), llvm::TargetExtType::getTypeParameter(), getVectorVT(), getVT(), llvm::Type::HalfTyID, llvm::Type::IntegerTyID, llvm_unreachable, MVT(), llvm::Type::PPC_FP128TyID, llvm::Type::ScalableVectorTyID, llvm::StringRef::starts_with(), llvm::Type::TargetExtTyID, llvm::Type::VoidTyID, llvm::Type::X86_AMXTyID, and llvm::Type::X86_FP80TyID.
Referenced by llvm::CallLowering::checkReturn(), getAtomicMemOpSizeArg(), getConvRTLibDesc(), llvm::EVT::getEVT(), llvm::AArch64TargetLowering::getTgtMemIntrinsic(), llvm::ARMTargetLowering::getTgtMemIntrinsic(), llvm::HexagonTargetLowering::getTgtMemIntrinsic(), llvm::NVPTXTargetLowering::getTgtMemIntrinsic(), llvm::SITargetLowering::getTgtMemIntrinsic(), llvm::X86TargetLowering::getTgtMemIntrinsic(), getVT(), llvm::GCNTTIImpl::isReadRegisterSourceOfDivergence(), and performSIGN_EXTEND_INREGCombine().
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Definition at line 619 of file MachineValueType.h.
References llvm::enum_seq_inclusive(), and llvm::force_iteration_on_noniterable_enum.
Referenced by llvm::AArch64TargetLowering::AArch64TargetLowering(), llvm::AMDGPUTargetLowering::AMDGPUTargetLowering(), llvm::ARMTargetLowering::ARMTargetLowering(), llvm::NVPTXTargetLowering::NVPTXTargetLowering(), llvm::RISCVTargetLowering::RISCVTargetLowering(), llvm::SparcTargetLowering::SparcTargetLowering(), llvm::SystemZTargetLowering::SystemZTargetLowering(), and llvm::WebAssemblyTargetLowering::WebAssemblyTargetLowering().
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Definition at line 631 of file MachineValueType.h.
References llvm::enum_seq_inclusive(), and llvm::force_iteration_on_noniterable_enum.
Referenced by llvm::RISCVTargetLowering::RISCVTargetLowering().
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Definition at line 590 of file MachineValueType.h.
References llvm::enum_seq_inclusive(), and llvm::force_iteration_on_noniterable_enum.
Referenced by llvm::AArch64TargetLowering::AArch64TargetLowering(), llvm::AMDGPUTargetLowering::AMDGPUTargetLowering(), llvm::ARMTargetLowering::ARMTargetLowering(), llvm::AVRTargetLowering::AVRTargetLowering(), llvm::BPFTargetLowering::BPFTargetLowering(), findMemType(), llvm::HexagonTargetLowering::HexagonTargetLowering(), llvm::LanaiTargetLowering::LanaiTargetLowering(), llvm::M68kTargetLowering::M68kTargetLowering(), llvm::MipsTargetLowering::MipsTargetLowering(), llvm::MSP430TargetLowering::MSP430TargetLowering(), llvm::NVPTXTargetLowering::NVPTXTargetLowering(), PerformTruncatingStoreCombine(), llvm::PPCTargetLowering::PPCTargetLowering(), llvm::R600TargetLowering::R600TargetLowering(), llvm::SparcTargetLowering::SparcTargetLowering(), llvm::SystemZTargetLowering::SystemZTargetLowering(), llvm::WebAssemblyTargetLowering::WebAssemblyTargetLowering(), llvm::X86TargetLowering::X86TargetLowering(), llvm::XCoreTargetLowering::XCoreTargetLowering(), and llvm::XtensaTargetLowering::XtensaTargetLowering().
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Return true if this is a 1024-bit vector type.
Definition at line 198 of file MachineValueType.h.
References getFixedSizeInBits(), and isFixedLengthVector().
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Return true if this is a 128-bit vector type.
Definition at line 183 of file MachineValueType.h.
References getFixedSizeInBits(), and isFixedLengthVector().
Referenced by CC_AArch64_Custom_Block(), CC_LoongArch(), CC_PPC64_ELF_Shadow_GPR_Regs(), llvm::CC_XPLINK64_Shadow_Reg(), combineAndNotIntoANDNP(), combineAndNotIntoVANDN(), combineCVTP2I_CVTTP2I(), combineINSERT_SUBVECTOR(), combinePTESTCC(), combineSetCCMOVMSK(), combineTargetShuffle(), combineX86INT_TO_FP(), combineX86ShuffleChain(), llvm::X86TTIImpl::getCmpSelInstrCost(), getZeroVector(), INITIALIZE_PASS(), isHorizontalBinOp(), LowerBITREVERSE_XOP(), lowerBUILD_VECTORAsBroadCastLoad(), lowerBuildVectorAsBroadcast(), LowerBuildVectorv4x32(), LowerCLMUL(), LowerEXTEND_VECTOR_INREG(), LowerEXTRACT_VECTOR_ELT_SSE4(), LowerSCALAR_TO_VECTOR(), lowerShuffleAsBitRotate(), lowerShuffleAsByteRotate(), lowerShuffleAsByteRotateAndPermute(), lowerShuffleAsByteShiftMask(), lowerShuffleAsDecomposedShuffleMerge(), lowerShuffleAsElementInsertion(), lowerShuffleAsPermuteAndUnpack(), lowerShuffleAsSpecificExtension(), lowerShuffleAsVALIGN(), lowerShuffleAsVTRUNC(), lowerShuffleOfExtractsAsVperm(), lowerShuffleWithPSHUFB(), lowerShuffleWithUndefHalf(), LowerTruncateVecI1(), lowerVECTOR_SHUFFLE(), LowerVectorCTPOP(), LowerVSETCC(), matchBinaryPermuteShuffle(), matchBinaryShuffle(), matchShuffleAsInsertPS(), matchUnaryPermuteShuffle(), matchUnaryShuffle(), narrowExtractedVectorSelect(), performAddSubLongCombine(), llvm::LoongArchTargetLowering::ReplaceNodeResults(), llvm::X86TargetLowering::ReplaceNodeResults(), scalarizeVectorStore(), llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(), and llvm::X86TargetLowering::X86TargetLowering().
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Return true if this is a 16-bit vector type.
Definition at line 168 of file MachineValueType.h.
References getFixedSizeInBits(), and isFixedLengthVector().
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Return true if this is a 2048-bit vector type.
Definition at line 203 of file MachineValueType.h.
References getFixedSizeInBits(), and isFixedLengthVector().
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Return true if this is a 256-bit vector type.
Definition at line 188 of file MachineValueType.h.
References getFixedSizeInBits(), and isFixedLengthVector().
Referenced by CC_LoongArch(), CC_X86_VectorCallGetSSEs(), combineAndNotIntoANDNP(), combineAndNotIntoVANDN(), combineBlendOfPermutes(), combineConcatVectorOps(), combineINSERT_SUBVECTOR(), combineSetCCMOVMSK(), combineTargetShuffle(), combineX86ShuffleChain(), getZeroVector(), INITIALIZE_PASS(), isHorizontalBinOp(), LowerABD(), LowerABS(), LowerADDSAT_SUBSAT(), LowerAVG(), LowerAVXCONCAT_VECTORS(), LowerBITREVERSE(), LowerBITREVERSE_XOP(), lowerBUILD_VECTORAsBroadCastLoad(), lowerBuildVectorAsBroadcast(), LowerCONCAT_VECTORS(), LowerEXTEND_VECTOR_INREG(), LowerFunnelShift(), LowerMINMAX(), LowerMUL(), LowerMULH(), LowerRotate(), LowerShift(), lowerShuffleAsBroadcast(), lowerShuffleAsByteRotateAndPermute(), lowerShuffleAsLanePermuteAndShuffle(), lowerShuffleAsRepeatedMaskAndLanePermute(), lowerShuffleAsVALIGN(), lowerShuffleAsVTRUNC(), lowerShuffleOfExtractsAsVperm(), lowerShuffleWithPSHUFB(), lowerShuffleWithUndefHalf(), LowerStore(), LowerTruncateVecI1(), lowerVECTOR_SHUFFLE(), lowerVECTOR_SHUFFLEAsLanePermuteAndShuffle(), LowerVectorCTLZ(), LowerVectorCTLZ_AVX512CDI(), LowerVectorCTPOP(), LowerVSETCC(), matchBinaryPermuteShuffle(), matchBinaryShuffle(), matchShuffleAsBlend(), matchUnaryPermuteShuffle(), matchUnaryShuffle(), narrowExtractedVectorSelect(), and llvm::X86TargetLowering::SimplifyDemandedBitsForTargetNode().
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Return true if this is a 32-bit vector type.
Definition at line 173 of file MachineValueType.h.
References getFixedSizeInBits(), and isFixedLengthVector().
Referenced by CC_AArch64_Custom_Block(), and LowerStore().
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Return true if this is a 512-bit vector type.
Definition at line 193 of file MachineValueType.h.
References getFixedSizeInBits(), and isFixedLengthVector().
Referenced by CC_X86_VectorCallGetSSEs(), combineAndNotIntoANDNP(), combineAndnp(), combineConcatVectorOps(), combineINSERT_SUBVECTOR(), combineShuffleToAddSubOrFMAddSub(), combineTargetShuffle(), combineX86ShuffleChain(), getAVX512Node(), getAVX512TruncNode(), llvm::X86TargetLowering::getSetCCResultType(), getZeroVector(), LowerAVXCONCAT_VECTORS(), LowerBITREVERSE(), lowerBuildVectorAsBroadcast(), LowerCONCAT_VECTORS(), LowerEXTEND_VECTOR_INREG(), LowerFunnelShift(), LowerMGATHER(), LowerMLOAD(), LowerMSCATTER(), LowerMSTORE(), LowerPARTIAL_REDUCE_FMLA(), LowerPARTIAL_REDUCE_MLA(), LowerRotate(), LowerShift(), LowerShiftByScalarImmediate(), lowerShuffleAsBroadcast(), lowerShuffleAsByteRotate(), lowerShuffleAsByteRotateAndPermute(), lowerShuffleWithPERMV(), lowerShuffleWithPSHUFB(), lowerShuffleWithUndefHalf(), LowerSIGN_EXTEND_Mask(), LowerStore(), lowerV4X128Shuffle(), lowerVECTOR_SHUFFLE(), LowerVectorCTLZ(), LowerVectorCTLZ_AVX512CDI(), LowerVectorCTLZInRegLUT(), LowerVectorCTPOP(), LowerVSETCC(), LowerZERO_EXTEND_Mask(), matchBinaryPermuteShuffle(), matchBinaryShuffle(), matchShuffleAsVTRUNC(), matchUnaryPermuteShuffle(), matchUnaryShuffle(), narrowExtractedVectorSelect(), and useVPTERNLOG().
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Return true if this is a 64-bit vector type.
Definition at line 178 of file MachineValueType.h.
References getFixedSizeInBits(), and isFixedLengthVector().
Referenced by CC_AArch64_Custom_Block(), isIncompatibleReg(), LowerStore(), and tryExtendDUPToExtractHigh().
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Returns true if the number of bits for the type is a multiple of an 8-bit byte.
Definition at line 441 of file MachineValueType.h.
References getSizeInBits(), and llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::isKnownMultipleOf().
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Return true if this is a CHERI capability type.
Definition at line 208 of file MachineValueType.h.
References SimpleTy.
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Definition at line 157 of file MachineValueType.h.
References SimpleTy.
Referenced by CC_RISCV_FastCC(), CC_RISCV_Impl(), combineToVCPOP(), convertLocVTToValVT(), convertValVTToLocVT(), costShuffleViaSplitting(), costShuffleViaVRegSplitting(), getContainerForFixedLengthVector(), getDefaultVLOps(), llvm::AArch64TTIImpl::getIntrinsicInstrCost(), llvm::RISCVTargetLowering::getRegForInlineAsmConstraint(), llvm::AArch64TargetLowering::getVectorTypeBreakdownForCallingConv(), getWideningInterleave(), is1024BitVector(), is128BitVector(), is16BitVector(), is2048BitVector(), is256BitVector(), is32BitVector(), is512BitVector(), is64BitVector(), isFixedLengthVectorOf(), isLegalVTForZvzipDeinterleavedOperand(), isLegalVTForZvzipInterleavedOperand(), lowerBUILD_VECTOR(), lowerBuildVectorOfConstants(), lowerBuildVectorViaDominantValues(), lowerBuildVectorViaPacking(), lowerBuildVectorViaVID(), lowerCONVERT_FROM_ARBITRARY_FP(), lowerCttzElts(), lowerFMAXIMUM_FMINIMUM(), lowerFP_TO_INT_SAT(), llvm::RISCVTargetLowering::LowerOperation(), lowerScalarInsert(), lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND(), lowerVectorStrictFTRUNC_FCEIL_FFLOOR_FROUND(), lowerVectorXRINT_XROUND(), lowerZvzipVPAIR(), lowerZvzipVUNZIP(), lowerZvzipVZIP(), matchSplatAsGather(), llvm::RISCVTargetLowering::PerformDAGCombine(), performFP_TO_INTCombine(), llvm::RISCVTargetLowering::ReplaceNodeResults(), llvm::RISCVDAGToDAGISel::Select(), and useRVVForFixedLengthVectorVT().
Return true if this is a fixed length vector with matching element type.
Definition at line 163 of file MachineValueType.h.
References getVectorElementType(), isFixedLengthVector(), and MVT().
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Return true if this is a FP or a vector FP type.
Definition at line 92 of file MachineValueType.h.
References SimpleTy.
Referenced by llvm::AMDGPUTargetLowering::analyzeFormalArgumentsCompute(), CC_LoongArch(), CC_MipsO32(), CC_RISCV_Impl(), CC_X86_32_VectorCall(), CC_X86_64_VectorCall(), combineConcatVectorOps(), combineTargetShuffle(), combineX86ShuffleChain(), combineX86ShufflesConstants(), getConstantVector(), getConstantVector(), getCopyFromParts(), getCopyToParts(), getCopyToPartsVector(), llvm::SPIRVTargetLowering::getRegForInlineAsmConstraint(), getTargetShuffleAndZeroables(), llvm::TargetLoweringBase::getTypeToPromoteTo(), getVCmpInst(), getZeroVector(), isAddSubOrSubAdd(), isHorizontalBinOp(), llvm::LLT::LLT(), lowerBUILD_VECTOR(), lowerBuildVectorOfConstants(), lowerBuildVectorViaDominantValues(), lowerBuildVectorViaVID(), LowerFABSorFNEG(), LowerFCOPYSIGN(), llvm::RISCVTargetLowering::LowerOperation(), lowerScalarInsert(), lowerScalarSplat(), lowerShuffleAsElementInsertion(), lowerShuffleAsLanePermuteAndShuffle(), lowerShuffleAsPermuteAndUnpack(), lowerShuffleAsVALIGN(), lowerVECTOR_SHUFFLE(), lowerVECTOR_SHUFFLE_VEXTRINS(), lowerVECTOR_SHUFFLE_XVEXTRINS(), lowerVECTOR_SHUFFLEAsVSlide1(), LowerVSETCC(), performScatterStoreCombine(), tryWidenMaskForShuffle(), and widenShuffleMask().
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Return true if this is an integer or a vector integer type.
Definition at line 102 of file MachineValueType.h.
References SimpleTy.
Referenced by llvm::AMDGPUTargetLowering::analyzeFormalArgumentsCompute(), combineINSERT_SUBVECTOR(), convertLocVTToValVT(), llvm::TargetLowering::findOptimalMemOpLowering(), getCopyFromParts(), llvm::RegsForValue::getCopyFromRegs(), getCopyToParts(), getCopyToPartsVector(), llvm::SPIRVTargetLowering::getRegForInlineAsmConstraint(), getRegistersForValue(), llvm::X86TTIImpl::getScalarizationOverhead(), getShuffleScalarElt(), llvm::TargetLoweringBase::getTypeToPromoteTo(), llvm::X86TTIImpl::getVectorInstrCost(), isValueTypeInRegForCC(), llvm::TargetLowering::LegalizeSetCCCondCode(), lower256BitShuffle(), LowerABS(), lowerBuildVectorOfConstants(), lowerBuildVectorViaPacking(), LowerLoad(), llvm::RISCVTargetLowering::LowerOperation(), LowerSCALAR_TO_VECTOR(), lowerShuffleAsBitBlend(), lowerShuffleAsBroadcast(), lowerShuffleAsTruncBroadcast(), LowerStore(), matchUnaryShuffle(), llvm::RISCVDAGToDAGISel::PreprocessISelDAG(), llvm::X86TargetLowering::ReplaceNodeResults(), and widenIntegerElementType().
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Return true if this is an overloaded type for TableGen.
Definition at line 214 of file MachineValueType.h.
References SimpleTy.
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Returns true if the given vector is a power of 2.
Definition at line 303 of file MachineValueType.h.
References getVectorMinNumElements().
Referenced by getPow2VectorType(), llvm::SITargetLowering::getPreferredVectorAction(), llvm::TargetLoweringBase::getPreferredVectorAction(), and useRVVForFixedLengthVectorVT().
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Return true if this is a RISCV vector tuple type where the runtime length is machine dependent.
Definition at line 142 of file MachineValueType.h.
References SimpleTy.
Referenced by CC_RISCV_Impl(), llvm::RISCVTargetLowering::decomposeSubvectorInsertExtractToSubRegs(), llvm::RISCVTargetLowering::getLMUL(), llvm::RISCVTargetLowering::getRegClassIDForVecVT(), getRISCVVectorTupleNumFields(), isScalableTargetExtVT(), and llvm::RISCVTargetLowering::splitValueIntoRegisterParts().
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Return true if this is a custom target type that has a scalable size.
Definition at line 148 of file MachineValueType.h.
References isRISCVVectorTuple(), and SimpleTy.
Referenced by isScalableVT(), and llvm::LLT::LLT().
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Return true if this is a vector value type where the runtime length is machine dependent.
Definition at line 130 of file MachineValueType.h.
References SimpleTy.
Referenced by bitsGE(), bitsGT(), bitsLE(), bitsLT(), CC_AArch64_Custom_Block(), CC_RISCV_FastCC(), CC_RISCV_Impl(), llvm::TargetLoweringBase::computeRegisterProperties(), llvm::RISCVTargetLowering::computeVLMax(), llvm::RISCVTargetLowering::computeVLMAXBounds(), convertLocVTToValVT(), llvm::RISCVTargetLowering::decomposeSubvectorInsertExtractToSubRegs(), finishStackBlock(), getDefaultScalableVLOps(), getDefaultVLOps(), getDefaultVLOps(), llvm::AArch64TTIImpl::getIntrinsicInstrCost(), llvm::RISCVTargetLowering::getLMUL(), llvm::RISCVTargetLowering::getLMULCost(), getLMULOctuple(), llvm::HexagonTargetLowering::getPreferredVectorAction(), llvm::LoongArchTargetLowering::getPreferredVectorAction(), llvm::NVPTXTargetLowering::getPreferredVectorAction(), llvm::PPCTargetLowering::getPreferredVectorAction(), llvm::SITargetLowering::getPreferredVectorAction(), llvm::X86TargetLowering::getPreferredVectorAction(), getSmallestVTForIndex(), getVectorElementCount(), getVectorNumElements(), isScalableVectorOf(), isScalableVT(), llvm::RISCVTargetLowering::joinRegisterPartsIntoValue(), llvm::LLT::LLT(), llvm::RISCVTargetLowering::LowerFormalArguments(), llvm::RISCVCallLowering::lowerFormalArguments(), llvm::RISCVTargetLowering::LowerReturn(), llvm::RISCVCallLowering::lowerReturn(), lowerScalarInsert(), llvm::RISCVDAGToDAGISel::PreprocessISelDAG(), llvm::RISCVDAGToDAGISel::Select(), and llvm::RISCVTargetLowering::splitValueIntoRegisterParts().
Return true if this is a scalable vector with matching element type.
Definition at line 136 of file MachineValueType.h.
References getVectorElementType(), isScalableVector(), and MVT().
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Return true if the type is a scalable type.
Definition at line 153 of file MachineValueType.h.
References isScalableTargetExtVT(), and isScalableVector().
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Return true if this is an integer, not including vectors.
Definition at line 112 of file MachineValueType.h.
References SimpleTy.
Referenced by CC_LoongArch(), CC_RISCV_Impl(), llvm::X86TTIImpl::getIntrinsicInstrCost(), getMaskNode(), llvm::RTLIB::getOUTLINE_ATOMIC(), LowerABD(), LowerBITCAST(), LowerCTPOP(), llvm::RISCVTargetLowering::LowerOperation(), lowerSelectToBinOp(), lowerVectorIntrinsicScalars(), promoteVCIXScalar(), llvm::X86TargetLowering::SimplifyDemandedBitsForTargetNode(), and truncateScalarIntegerArg().
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Return true if this is a valid simple valuetype.
Definition at line 86 of file MachineValueType.h.
References SimpleTy.
Referenced by llvm::RISCVTTIImpl::getIntrinsicInstrCost(), getRegistersForValue(), llvm::RISCVTTIImpl::getShuffleCost(), getSmallestVTForIndex(), llvm::TargetLoweringBase::initActions(), llvm::HexagonSubtarget::isTypeForHVX(), llvm::LLT::LLT(), llvm::MipsTargetLowering::MipsTargetLowering(), llvm::RISCVTargetLowering::RISCVTargetLowering(), llvm::TargetLoweringBase::setAtomicLoadExtAction(), llvm::TargetLoweringBase::setCondCodeAction(), llvm::TargetLoweringBase::setLoadExtAction(), llvm::TargetLoweringBase::setPartialReduceMLAAction(), and llvm::TargetLoweringBase::setTruncStoreAction().
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Return true if this is a vector value type.
Definition at line 118 of file MachineValueType.h.
References SimpleTy.
Referenced by llvm::PPCTargetLowering::allowsMisalignedMemoryAccesses(), llvm::AMDGPUTargetLowering::analyzeFormalArgumentsCompute(), canonicalizeBitSelect(), CC_RISCV_FastCC(), CC_RISCV_Impl(), CC_X86_32_VectorCall(), CC_X86_64_VectorCall(), changeElementType(), changeTypeToInteger(), changeVectorElementCount(), combineAndnp(), combineX86FPLogicOp(), combineX86ShuffleChain(), combineX86ShufflesRecursively(), constructRetValue(), convertLocVTToValVT(), convertValVTToLocVT(), llvm::AArch64TTIImpl::getArithmeticReductionCost(), llvm::X86TTIImpl::getArithmeticReductionCost(), getAVX512Node(), llvm::X86TTIImpl::getCmpSelInstrCost(), getCopyFromParts(), getCopyToPartsVector(), llvm::X86TTIImpl::getInterleavedMemoryOpCost(), llvm::AArch64TTIImpl::getIntrinsicInstrCost(), llvm::X86TTIImpl::getIntrinsicInstrCost(), llvm::RISCVTargetLowering::getLMULCost(), getMaskTypeFor(), getMemCmpLoad(), llvm::X86TTIImpl::getMinMaxReductionCost(), llvm::PPCTargetLowering::getRegForInlineAsmConstraint(), llvm::RISCVTargetLowering::getRegForInlineAsmConstraint(), llvm::SITargetLowering::getRegForInlineAsmConstraint(), llvm::SPIRVTargetLowering::getRegForInlineAsmConstraint(), llvm::X86TargetLowering::getRegForInlineAsmConstraint(), llvm::X86TTIImpl::getReplicationShuffleCost(), getScalarType(), getScalarValueForVectorElement(), llvm::X86TargetLowering::getSetCCResultType(), llvm::X86TTIImpl::getShuffleCost(), llvm::CallLowering::ValueHandler::getStackValueStoreType(), getTargetVShiftNode(), llvm::TargetLoweringBase::getTypeConversion(), getVectorLoweringShape(), llvm::X86TargetLowering::isGuaranteedNotToBeUndefOrPoisonForTargetNode(), isPromotedOpNeedingSplit(), isValueTypeInRegForCC(), isVectorOf(), llvm::LLT::LLT(), LowerADDSAT_SUBSAT(), LowerAVXExtend(), LowerBITCAST(), LowerBITREVERSE(), LowerBITREVERSE_XOP(), llvm::RISCVTargetLowering::LowerCall(), LowerCLMUL(), LowerCTLZ(), LowerCTPOP(), LowerCTTZ(), LowerFABSorFNEG(), LowerFCOPYSIGN(), lowerFMAXIMUM_FMINIMUM(), llvm::RISCVTargetLowering::LowerFormalArguments(), lowerFP_TO_INT_SAT(), lowerFPToIntToFP(), lowerFTRUNC_FCEIL_FFLOOR_FROUND(), LowerFunnelShift(), LowerLoad(), LowerMINMAX(), LowerMULH(), LowerMULO(), llvm::RISCVTargetLowering::LowerOperation(), LowerPDEPPEXT(), llvm::AArch64CallLowering::lowerReturn(), LowerRotate(), llvm::HexagonTargetLowering::LowerSETCC(), LowerShift(), lowerShuffleAsTruncBroadcast(), LowerSIGN_EXTEND(), llvm::AMDGPUTargetLowering::LowerSIGN_EXTEND_INREG(), lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND(), lowerVectorXRINT_XROUND(), performConcatVectorsCombine(), llvm::RISCVDAGToDAGISel::PreprocessISelDAG(), processPSInputArgs(), llvm::X86TargetLowering::ReplaceNodeResults(), llvm::X86TargetLowering::SimplifyDemandedBitsForTargetNode(), llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(), and llvm::splitVectorType().
Return true if this is a vector with matching element type.
Definition at line 124 of file MachineValueType.h.
References getVectorElementType(), isVector(), and MVT().
Referenced by combineToVCPOP(), LowerBITREVERSE(), and LowerCLMUL().
Return true if we know at compile time this has more than or the same bits as VT.
Definition at line 450 of file MachineValueType.h.
References getSizeInBits(), llvm::details::FixedOrScalableQuantity< TypeSize, uint64_t >::isKnownGE(), and MVT().
Referenced by bitsGE().
Return true if we know at compile time this has more bits than VT.
Definition at line 444 of file MachineValueType.h.
References getSizeInBits(), llvm::details::FixedOrScalableQuantity< TypeSize, uint64_t >::isKnownGT(), and MVT().
Referenced by bitsGT().
Return true if we know at compile time this has fewer than or the same bits as VT.
Definition at line 461 of file MachineValueType.h.
References getSizeInBits(), llvm::details::FixedOrScalableQuantity< TypeSize, uint64_t >::isKnownLE(), and MVT().
Referenced by bitsLE().
Return true if we know at compile time this has fewer bits than VT.
Definition at line 455 of file MachineValueType.h.
References getSizeInBits(), llvm::details::FixedOrScalableQuantity< TypeSize, uint64_t >::isKnownLT(), and MVT().
Referenced by bitsLT().
Definition at line 63 of file MachineValueType.h.
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Definition at line 69 of file MachineValueType.h.
References SimpleTy.
Definition at line 61 of file MachineValueType.h.
Definition at line 65 of file MachineValueType.h.
Definition at line 62 of file MachineValueType.h.
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Definition at line 68 of file MachineValueType.h.
References SimpleTy.
Definition at line 60 of file MachineValueType.h.
Definition at line 64 of file MachineValueType.h.
| void MVT::print | ( | raw_ostream & | OS | ) | const |
Implement operator<<.
Definition at line 391 of file ValueTypes.cpp.
References INVALID_SIMPLE_VALUE_TYPE, and SimpleTy.
Referenced by dump(), getString(), and llvm::operator<<().
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Definition at line 613 of file MachineValueType.h.
References llvm::enum_seq_inclusive(), and llvm::force_iteration_on_noniterable_enum.
Referenced by llvm::AArch64TargetLowering::AArch64TargetLowering().
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Definition at line 601 of file MachineValueType.h.
References llvm::enum_seq_inclusive(), and llvm::force_iteration_on_noniterable_enum.
Referenced by findMemType().
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Definition at line 288 of file MachineValueType.h.
References assert(), changeElementType(), getIntegerVT(), getScalarSizeInBits(), getScalarType(), INVALID_SIMPLE_VALUE_TYPE, isInteger(), and MVT().
Referenced by combineX86ShuffleChain().
| SimpleValueType llvm::MVT::SimpleTy = INVALID_SIMPLE_VALUE_TYPE |
Definition at line 55 of file MachineValueType.h.
Referenced by AddCombineBUILD_VECTORToVPADDL(), llvm::TargetLoweringBase::AddPromotedToType(), llvm::TargetLoweringBase::addRegisterClass(), llvm::ARMTargetLowering::allowsMisalignedMemoryAccesses(), llvm::MipsSETargetLowering::allowsMisalignedMemoryAccesses(), AVRDAGToDAGISel::select< ISD::LOAD >(), CC_AArch64_Custom_Block(), CC_AIX(), CC_ARM_AAPCS_Custom_Aggregate(), changeVectorElementType(), changeVectorElementTypeToInteger(), llvm::SITargetLowering::checkAsmConstraintValA(), combineBitcastvxi1(), llvm::VETargetLowering::combineSelectCC(), convertFPToInt(), createVariablePermute(), llvm::SITargetLowering::denormalsEnabledForType(), llvm::TargetLowering::expandBSWAP(), llvm::TargetLowering::findOptimalMemOpLowering(), llvm::ARMTargetLowering::findRepresentativeClass(), llvm::TargetLoweringBase::findRepresentativeClass(), llvm::X86TargetLowering::findRepresentativeClass(), foldVectorXorShiftIntoCmp(), llvm::R600RegisterInfo::getCFGStructurizerRegClass(), llvm::TargetLoweringBase::getCondCodeAction(), getContainerForFixedLengthVector(), getContainerForFixedLengthVector(), getExtensionTo64Bits(), getFAddWithNegOpcode(), getFltSemantics(), llvm::PPCTargetLowering::getFPImmAction(), getFpSemanticsForMVT(), getImplicitScaleFactor(), llvm::RISCVTargetLowering::getLMUL(), llvm::TargetLoweringBase::getLoadAction(), llvm::TargetLoweringBase::getOperationAction(), getPackedSVEVectorVT(), llvm::TargetLoweringBase::getPartialReduceMLAAction(), llvm::AArch64TTIImpl::getPartialReductionCost(), getPredicateForFixedLengthVector(), llvm::MipsSETargetLowering::getPreferredVectorAction(), llvm::TargetLoweringBase::getRegClassFor(), llvm::HexagonTargetLowering::getRegForInlineAsmConstraint(), llvm::M68kTargetLowering::getRegForInlineAsmConstraint(), llvm::RISCVTargetLowering::getRegForInlineAsmConstraint(), llvm::SITargetLowering::getRegForInlineAsmConstraint(), llvm::X86TargetLowering::getRegForInlineAsmConstraint(), llvm::TargetLoweringBase::getRepRegClassCostFor(), llvm::TargetLoweringBase::getRepRegClassFor(), getRISCVVectorTupleNumFields(), llvm::TargetLoweringBase::getSetCCResultType(), getSizeInBits(), getSVEContainerType(), llvm::TargetLoweringBase::getTruncStoreAction(), llvm::TargetLoweringBase::ValueTypeActionImpl::getTypeAction(), llvm::TargetLoweringBase::getTypeConversion(), llvm::TargetLoweringBase::getTypeToPromoteTo(), llvm::SelectionDAG::getValueType(), getVectorElementType(), llvm::TargetLoweringBase::getVectorInterleaveAction(), getVectorLoweringShape(), getVectorMinNumElements(), getVectorTyFromPredicateVector(), llvm::AArch64TargetLowering::getVectorTypeBreakdownForCallingConv(), getVectorVT(), getVPTESTMOpc(), getWasmArgumentOpcode(), is32Bit(), isCheriCapability(), isConstantSplatVectorMaskForType(), isConstantSplatVectorMaskForType(), isFixedLengthVector(), isFloatingPoint(), llvm::AArch64TargetLowering::isFMAFasterThanFMulAndFAdd(), llvm::LoongArchTargetLowering::isFMAFasterThanFMulAndFAdd(), llvm::RISCVTargetLowering::isFMAFasterThanFMulAndFAdd(), llvm::SITargetLowering::isFMAFasterThanFMulAndFAdd(), llvm::SystemZTargetLowering::isFMAFasterThanFMulAndFAdd(), llvm::X86TargetLowering::isFMAFasterThanFMulAndFAdd(), llvm::ARMTargetLowering::isFNegFree(), isInteger(), isLegalAddressImmediate(), llvm::ARMTargetLowering::isLegalAddressingMode(), llvm::RISCVTargetLowering::isLegalElementTypeForRVV(), isLegalT1AddressImmediate(), isLegalT2AddressImmediate(), llvm::ARMTargetLowering::isLegalT2ScaledAddressingMode(), isOverloaded(), IsPredicateKnownToFail(), IsPTXVectorType(), isRISCVVectorTuple(), isScalableTargetExtVT(), isScalableVector(), isScalarInteger(), isSupportedFPArith(), isSupportedReciprocalEstimateType(), llvm::TargetLoweringBase::isTypeLegal(), isValid(), llvm::HexagonInstrInfo::isValidAutoIncImm(), isValidIndexedLoad(), isVector(), llvm::ARMTargetLowering::isZExtFree(), llvm::X86TargetLowering::isZExtFree(), llvm::XCoreTargetLowering::isZExtFree(), lower128BitShuffle(), lower128BitShuffle(), lower1BitShuffle(), lower256BitShuffle(), lower256BitShuffle(), lower512BitShuffle(), LowerADDSUBSAT(), lowerBSWAP(), LowerFLDEXP(), llvm::SystemZTargetLowering::LowerFormalArguments(), lowerLaneOp(), lowerMSTORE(), lowerRegToMasks(), lowerShuffleAsBlend(), lowerUINT_TO_FP_vec(), MVT(), llvm::EVT::operator!=(), operator!=(), operator!=(), operator<(), operator<=(), operator==(), operator==(), operator>(), operator>=(), performBITCASTCombine(), performUADDVZextCombine(), performUzpCombine(), print(), ReplaceINTRINSIC_W_CHAIN(), llvm::RISCVDAGToDAGISel::Select(), llvm::SelectionDAGISel::SelectCodeCommon(), llvm::HexagonDAGToDAGISel::SelectIndexedLoad(), llvm::HexagonDAGToDAGISel::SelectIndexedStore(), llvm::TargetLoweringBase::setAtomicLoadExtAction(), llvm::TargetLoweringBase::setCondCodeAction(), llvm::TargetLoweringBase::setLoadExtAction(), llvm::TargetLoweringBase::setOperationAction(), llvm::TargetLoweringBase::setPartialReduceMLAAction(), llvm::TargetLoweringBase::setTruncStoreAction(), llvm::TargetLoweringBase::ValueTypeActionImpl::setTypeAction(), llvm::TargetLoweringBase::setVectorInterleaveAction(), llvm::ARMTargetLowering::shouldConvertFpToSat(), llvm::RISCVTargetLowering::shouldConvertFpToSat(), llvm::X86InstrInfo::shouldScheduleLoadsNear(), unpackFromRegLoc(), usePartialVectorLoads(), useRVVForFixedLengthVectorVT(), llvm::AArch64TargetLowering::useSVEForFixedLengthVectorVT(), X86ChooseCmpImmediateOpcode(), and X86ChooseCmpOpcode().
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Definition at line 558 of file MachineValueType.h.
Referenced by getVectorVT().