LLVM 18.0.0git
AArch64ELFObjectWriter.cpp
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1//===-- AArch64ELFObjectWriter.cpp - AArch64 ELF Writer -------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file handles ELF-specific object emission, converting LLVM's internal
10// fixups into the appropriate relocations.
11//
12//===----------------------------------------------------------------------===//
13
14#include "MCTargetDesc/AArch64FixupKinds.h"
15#include "MCTargetDesc/AArch64MCExpr.h"
16#include "MCTargetDesc/AArch64MCTargetDesc.h"
17#include "llvm/BinaryFormat/ELF.h"
18#include "llvm/MC/MCContext.h"
19#include "llvm/MC/MCELFObjectWriter.h"
20#include "llvm/MC/MCFixup.h"
21#include "llvm/MC/MCObjectWriter.h"
22#include "llvm/MC/MCValue.h"
23#include "llvm/Support/ErrorHandling.h"
24#include <cassert>
25#include <cstdint>
26
27using namespace llvm;
28
29namespace {
30
31class AArch64ELFObjectWriter : public MCELFObjectTargetWriter {
32public:
33 AArch64ELFObjectWriter(uint8_t OSABI, bool IsILP32);
34
35 ~AArch64ELFObjectWriter() override = default;
36
37 MCSectionELF *getMemtagRelocsSection(MCContext &Ctx) const override;
38
39protected:
40 unsigned getRelocType(MCContext &Ctx, const MCValue &Target,
41 const MCFixup &Fixup, bool IsPCRel) const override;
42 bool needsRelocateWithSymbol(const MCValue &Val, const MCSymbol &Sym,
43 unsigned Type) const override;
44 bool IsILP32;
45};
46
47} // end anonymous namespace
48
49AArch64ELFObjectWriter::AArch64ELFObjectWriter(uint8_t OSABI, bool IsILP32)
50 : MCELFObjectTargetWriter(/*Is64Bit*/ !IsILP32, OSABI, ELF::EM_AARCH64,
51 /*HasRelocationAddend*/ true),
52 IsILP32(IsILP32) {}
53
54#define R_CLS(rtype) \
55 IsILP32 ? ELF::R_AARCH64_P32_##rtype : ELF::R_AARCH64_##rtype
56#define BAD_ILP32_MOV(lp64rtype) \
57 "ILP32 absolute MOV relocation not " \
58 "supported (LP64 eqv: " #lp64rtype ")"
59
60// assumes IsILP32 is true
61static bool isNonILP32reloc(const MCFixup &Fixup,
62 AArch64MCExpr::VariantKind RefKind,
63 MCContext &Ctx) {
64 if (Fixup.getTargetKind() != AArch64::fixup_aarch64_movw)
65 return false;
66 switch (RefKind) {
67 case AArch64MCExpr::VK_ABS_G3:
68 Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(MOVW_UABS_G3));
69 return true;
70 case AArch64MCExpr::VK_ABS_G2:
71 Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(MOVW_UABS_G2));
72 return true;
73 case AArch64MCExpr::VK_ABS_G2_S:
74 Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(MOVW_SABS_G2));
75 return true;
76 case AArch64MCExpr::VK_ABS_G2_NC:
77 Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(MOVW_UABS_G2_NC));
78 return true;
79 case AArch64MCExpr::VK_ABS_G1_S:
80 Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(MOVW_SABS_G1));
81 return true;
82 case AArch64MCExpr::VK_ABS_G1_NC:
83 Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(MOVW_UABS_G1_NC));
84 return true;
85 case AArch64MCExpr::VK_DTPREL_G2:
86 Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(TLSLD_MOVW_DTPREL_G2));
87 return true;
88 case AArch64MCExpr::VK_DTPREL_G1_NC:
89 Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(TLSLD_MOVW_DTPREL_G1_NC));
90 return true;
91 case AArch64MCExpr::VK_TPREL_G2:
92 Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(TLSLE_MOVW_TPREL_G2));
93 return true;
94 case AArch64MCExpr::VK_TPREL_G1_NC:
95 Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(TLSLE_MOVW_TPREL_G1_NC));
96 return true;
97 case AArch64MCExpr::VK_GOTTPREL_G1:
98 Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(TLSIE_MOVW_GOTTPREL_G1));
99 return true;
100 case AArch64MCExpr::VK_GOTTPREL_G0_NC:
101 Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(TLSIE_MOVW_GOTTPREL_G0_NC));
102 return true;
103 default:
104 return false;
105 }
106 return false;
107}
108
109unsigned AArch64ELFObjectWriter::getRelocType(MCContext &Ctx,
110 const MCValue &Target,
111 const MCFixup &Fixup,
112 bool IsPCRel) const {
113 unsigned Kind = Fixup.getTargetKind();
114 if (Kind >= FirstLiteralRelocationKind)
115 return Kind - FirstLiteralRelocationKind;
116 AArch64MCExpr::VariantKind RefKind =
117 static_cast<AArch64MCExpr::VariantKind>(Target.getRefKind());
118 AArch64MCExpr::VariantKind SymLoc = AArch64MCExpr::getSymbolLoc(RefKind);
119 bool IsNC = AArch64MCExpr::isNotChecked(RefKind);
120
121 assert((!Target.getSymA() ||
122 Target.getSymA()->getKind() == MCSymbolRefExpr::VK_None ||
123 Target.getSymA()->getKind() == MCSymbolRefExpr::VK_PLT) &&
124 "Should only be expression-level modifiers here");
125
126 assert((!Target.getSymB() ||
127 Target.getSymB()->getKind() == MCSymbolRefExpr::VK_None) &&
128 "Should only be expression-level modifiers here");
129
130 if (IsPCRel) {
131 switch (Kind) {
132 case FK_Data_1:
133 Ctx.reportError(Fixup.getLoc(), "1-byte data relocations not supported");
134 return ELF::R_AARCH64_NONE;
135 case FK_Data_2:
136 return R_CLS(PREL16);
137 case FK_Data_4: {
138 return Target.getAccessVariant() == MCSymbolRefExpr::VK_PLT
139 ? R_CLS(PLT32)
140 : R_CLS(PREL32);
141 }
142 case FK_Data_8:
143 if (IsILP32) {
144 Ctx.reportError(Fixup.getLoc(),
145 "ILP32 8 byte PC relative data "
146 "relocation not supported (LP64 eqv: PREL64)");
147 return ELF::R_AARCH64_NONE;
148 } else
149 return ELF::R_AARCH64_PREL64;
150 case AArch64::fixup_aarch64_pcrel_adr_imm21:
151 if (SymLoc != AArch64MCExpr::VK_ABS)
152 Ctx.reportError(Fixup.getLoc(),
153 "invalid symbol kind for ADR relocation");
154 return R_CLS(ADR_PREL_LO21);
155 case AArch64::fixup_aarch64_pcrel_adrp_imm21:
156 if (SymLoc == AArch64MCExpr::VK_ABS && !IsNC)
157 return R_CLS(ADR_PREL_PG_HI21);
158 if (SymLoc == AArch64MCExpr::VK_ABS && IsNC) {
159 if (IsILP32) {
160 Ctx.reportError(Fixup.getLoc(),
161 "invalid fixup for 32-bit pcrel ADRP instruction "
162 "VK_ABS VK_NC");
163 return ELF::R_AARCH64_NONE;
164 } else {
165 return ELF::R_AARCH64_ADR_PREL_PG_HI21_NC;
166 }
167 }
168 if (SymLoc == AArch64MCExpr::VK_GOT && !IsNC)
169 return R_CLS(ADR_GOT_PAGE);
170 if (SymLoc == AArch64MCExpr::VK_GOTTPREL && !IsNC)
171 return R_CLS(TLSIE_ADR_GOTTPREL_PAGE21);
172 if (SymLoc == AArch64MCExpr::VK_TLSDESC && !IsNC)
173 return R_CLS(TLSDESC_ADR_PAGE21);
174 Ctx.reportError(Fixup.getLoc(),
175 "invalid symbol kind for ADRP relocation");
176 return ELF::R_AARCH64_NONE;
177 case AArch64::fixup_aarch64_pcrel_branch26:
178 return R_CLS(JUMP26);
179 case AArch64::fixup_aarch64_pcrel_call26:
180 return R_CLS(CALL26);
181 case AArch64::fixup_aarch64_ldr_pcrel_imm19:
182 if (SymLoc == AArch64MCExpr::VK_GOTTPREL)
183 return R_CLS(TLSIE_LD_GOTTPREL_PREL19);
184 if (SymLoc == AArch64MCExpr::VK_GOT)
185 return R_CLS(GOT_LD_PREL19);
186 return R_CLS(LD_PREL_LO19);
187 case AArch64::fixup_aarch64_pcrel_branch14:
188 return R_CLS(TSTBR14);
189 case AArch64::fixup_aarch64_pcrel_branch19:
190 return R_CLS(CONDBR19);
191 default:
192 Ctx.reportError(Fixup.getLoc(), "Unsupported pc-relative fixup kind");
193 return ELF::R_AARCH64_NONE;
194 }
195 } else {
196 if (IsILP32 && isNonILP32reloc(Fixup, RefKind, Ctx))
197 return ELF::R_AARCH64_NONE;
198 switch (Fixup.getTargetKind()) {
199 case FK_Data_1:
200 Ctx.reportError(Fixup.getLoc(), "1-byte data relocations not supported");
201 return ELF::R_AARCH64_NONE;
202 case FK_Data_2:
203 return R_CLS(ABS16);
204 case FK_Data_4:
205 return R_CLS(ABS32);
206 case FK_Data_8:
207 if (IsILP32) {
208 Ctx.reportError(Fixup.getLoc(),
209 "ILP32 8 byte absolute data "
210 "relocation not supported (LP64 eqv: ABS64)");
211 return ELF::R_AARCH64_NONE;
212 } else {
213 if (RefKind == AArch64MCExpr::VK_AUTH ||
214 RefKind == AArch64MCExpr::VK_AUTHADDR)
215 return ELF::R_AARCH64_AUTH_ABS64;
216 return ELF::R_AARCH64_ABS64;
217 }
218 case AArch64::fixup_aarch64_add_imm12:
219 if (RefKind == AArch64MCExpr::VK_DTPREL_HI12)
220 return R_CLS(TLSLD_ADD_DTPREL_HI12);
221 if (RefKind == AArch64MCExpr::VK_TPREL_HI12)
222 return R_CLS(TLSLE_ADD_TPREL_HI12);
223 if (RefKind == AArch64MCExpr::VK_DTPREL_LO12_NC)
224 return R_CLS(TLSLD_ADD_DTPREL_LO12_NC);
225 if (RefKind == AArch64MCExpr::VK_DTPREL_LO12)
226 return R_CLS(TLSLD_ADD_DTPREL_LO12);
227 if (RefKind == AArch64MCExpr::VK_TPREL_LO12_NC)
228 return R_CLS(TLSLE_ADD_TPREL_LO12_NC);
229 if (RefKind == AArch64MCExpr::VK_TPREL_LO12)
230 return R_CLS(TLSLE_ADD_TPREL_LO12);
231 if (RefKind == AArch64MCExpr::VK_TLSDESC_LO12)
232 return R_CLS(TLSDESC_ADD_LO12);
233 if (SymLoc == AArch64MCExpr::VK_ABS && IsNC)
234 return R_CLS(ADD_ABS_LO12_NC);
235
236 Ctx.reportError(Fixup.getLoc(),
237 "invalid fixup for add (uimm12) instruction");
238 return ELF::R_AARCH64_NONE;
239 case AArch64::fixup_aarch64_ldst_imm12_scale1:
240 if (SymLoc == AArch64MCExpr::VK_ABS && IsNC)
241 return R_CLS(LDST8_ABS_LO12_NC);
242 if (SymLoc == AArch64MCExpr::VK_DTPREL && !IsNC)
243 return R_CLS(TLSLD_LDST8_DTPREL_LO12);
244 if (SymLoc == AArch64MCExpr::VK_DTPREL && IsNC)
245 return R_CLS(TLSLD_LDST8_DTPREL_LO12_NC);
246 if (SymLoc == AArch64MCExpr::VK_TPREL && !IsNC)
247 return R_CLS(TLSLE_LDST8_TPREL_LO12);
248 if (SymLoc == AArch64MCExpr::VK_TPREL && IsNC)
249 return R_CLS(TLSLE_LDST8_TPREL_LO12_NC);
250
251 Ctx.reportError(Fixup.getLoc(),
252 "invalid fixup for 8-bit load/store instruction");
253 return ELF::R_AARCH64_NONE;
254 case AArch64::fixup_aarch64_ldst_imm12_scale2:
255 if (SymLoc == AArch64MCExpr::VK_ABS && IsNC)
256 return R_CLS(LDST16_ABS_LO12_NC);
257 if (SymLoc == AArch64MCExpr::VK_DTPREL && !IsNC)
258 return R_CLS(TLSLD_LDST16_DTPREL_LO12);
259 if (SymLoc == AArch64MCExpr::VK_DTPREL && IsNC)
260 return R_CLS(TLSLD_LDST16_DTPREL_LO12_NC);
261 if (SymLoc == AArch64MCExpr::VK_TPREL && !IsNC)
262 return R_CLS(TLSLE_LDST16_TPREL_LO12);
263 if (SymLoc == AArch64MCExpr::VK_TPREL && IsNC)
264 return R_CLS(TLSLE_LDST16_TPREL_LO12_NC);
265
266 Ctx.reportError(Fixup.getLoc(),
267 "invalid fixup for 16-bit load/store instruction");
268 return ELF::R_AARCH64_NONE;
269 case AArch64::fixup_aarch64_ldst_imm12_scale4:
270 if (SymLoc == AArch64MCExpr::VK_ABS && IsNC)
271 return R_CLS(LDST32_ABS_LO12_NC);
272 if (SymLoc == AArch64MCExpr::VK_DTPREL && !IsNC)
273 return R_CLS(TLSLD_LDST32_DTPREL_LO12);
274 if (SymLoc == AArch64MCExpr::VK_DTPREL && IsNC)
275 return R_CLS(TLSLD_LDST32_DTPREL_LO12_NC);
276 if (SymLoc == AArch64MCExpr::VK_TPREL && !IsNC)
277 return R_CLS(TLSLE_LDST32_TPREL_LO12);
278 if (SymLoc == AArch64MCExpr::VK_TPREL && IsNC)
279 return R_CLS(TLSLE_LDST32_TPREL_LO12_NC);
280 if (SymLoc == AArch64MCExpr::VK_GOT && IsNC) {
281 if (IsILP32) {
282 return ELF::R_AARCH64_P32_LD32_GOT_LO12_NC;
283 } else {
284 Ctx.reportError(Fixup.getLoc(),
285 "LP64 4 byte unchecked GOT load/store relocation "
286 "not supported (ILP32 eqv: LD32_GOT_LO12_NC");
287 return ELF::R_AARCH64_NONE;
288 }
289 }
290 if (SymLoc == AArch64MCExpr::VK_GOT && !IsNC) {
291 if (IsILP32) {
292 Ctx.reportError(Fixup.getLoc(),
293 "ILP32 4 byte checked GOT load/store relocation "
294 "not supported (unchecked eqv: LD32_GOT_LO12_NC)");
295 } else {
296 Ctx.reportError(Fixup.getLoc(),
297 "LP64 4 byte checked GOT load/store relocation "
298 "not supported (unchecked/ILP32 eqv: "
299 "LD32_GOT_LO12_NC)");
300 }
301 return ELF::R_AARCH64_NONE;
302 }
303 if (SymLoc == AArch64MCExpr::VK_GOTTPREL && IsNC) {
304 if (IsILP32) {
305 return ELF::R_AARCH64_P32_TLSIE_LD32_GOTTPREL_LO12_NC;
306 } else {
307 Ctx.reportError(Fixup.getLoc(),
308 "LP64 32-bit load/store "
309 "relocation not supported (ILP32 eqv: "
310 "TLSIE_LD32_GOTTPREL_LO12_NC)");
311 return ELF::R_AARCH64_NONE;
312 }
313 }
314 if (SymLoc == AArch64MCExpr::VK_TLSDESC && !IsNC) {
315 if (IsILP32) {
316 return ELF::R_AARCH64_P32_TLSDESC_LD32_LO12;
317 } else {
318 Ctx.reportError(Fixup.getLoc(),
319 "LP64 4 byte TLSDESC load/store relocation "
320 "not supported (ILP32 eqv: TLSDESC_LD64_LO12)");
321 return ELF::R_AARCH64_NONE;
322 }
323 }
324
325 Ctx.reportError(Fixup.getLoc(),
326 "invalid fixup for 32-bit load/store instruction "
327 "fixup_aarch64_ldst_imm12_scale4");
328 return ELF::R_AARCH64_NONE;
329 case AArch64::fixup_aarch64_ldst_imm12_scale8:
330 if (SymLoc == AArch64MCExpr::VK_ABS && IsNC)
331 return R_CLS(LDST64_ABS_LO12_NC);
332 if (SymLoc == AArch64MCExpr::VK_GOT && IsNC) {
333 AArch64MCExpr::VariantKind AddressLoc =
334 AArch64MCExpr::getAddressFrag(RefKind);
335 if (!IsILP32) {
336 if (AddressLoc == AArch64MCExpr::VK_LO15)
337 return ELF::R_AARCH64_LD64_GOTPAGE_LO15;
338 return ELF::R_AARCH64_LD64_GOT_LO12_NC;
339 } else {
340 Ctx.reportError(Fixup.getLoc(), "ILP32 64-bit load/store "
341 "relocation not supported (LP64 eqv: "
342 "LD64_GOT_LO12_NC)");
343 return ELF::R_AARCH64_NONE;
344 }
345 }
346 if (SymLoc == AArch64MCExpr::VK_DTPREL && !IsNC)
347 return R_CLS(TLSLD_LDST64_DTPREL_LO12);
348 if (SymLoc == AArch64MCExpr::VK_DTPREL && IsNC)
349 return R_CLS(TLSLD_LDST64_DTPREL_LO12_NC);
350 if (SymLoc == AArch64MCExpr::VK_TPREL && !IsNC)
351 return R_CLS(TLSLE_LDST64_TPREL_LO12);
352 if (SymLoc == AArch64MCExpr::VK_TPREL && IsNC)
353 return R_CLS(TLSLE_LDST64_TPREL_LO12_NC);
354 if (SymLoc == AArch64MCExpr::VK_GOTTPREL && IsNC) {
355 if (!IsILP32) {
356 return ELF::R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC;
357 } else {
358 Ctx.reportError(Fixup.getLoc(), "ILP32 64-bit load/store "
359 "relocation not supported (LP64 eqv: "
360 "TLSIE_LD64_GOTTPREL_LO12_NC)");
361 return ELF::R_AARCH64_NONE;
362 }
363 }
364 if (SymLoc == AArch64MCExpr::VK_TLSDESC) {
365 if (!IsILP32) {
366 return ELF::R_AARCH64_TLSDESC_LD64_LO12;
367 } else {
368 Ctx.reportError(Fixup.getLoc(), "ILP32 64-bit load/store "
369 "relocation not supported (LP64 eqv: "
370 "TLSDESC_LD64_LO12)");
371 return ELF::R_AARCH64_NONE;
372 }
373 }
374 Ctx.reportError(Fixup.getLoc(),
375 "invalid fixup for 64-bit load/store instruction");
376 return ELF::R_AARCH64_NONE;
377 case AArch64::fixup_aarch64_ldst_imm12_scale16:
378 if (SymLoc == AArch64MCExpr::VK_ABS && IsNC)
379 return R_CLS(LDST128_ABS_LO12_NC);
380 if (SymLoc == AArch64MCExpr::VK_DTPREL && !IsNC)
381 return R_CLS(TLSLD_LDST128_DTPREL_LO12);
382 if (SymLoc == AArch64MCExpr::VK_DTPREL && IsNC)
383 return R_CLS(TLSLD_LDST128_DTPREL_LO12_NC);
384 if (SymLoc == AArch64MCExpr::VK_TPREL && !IsNC)
385 return R_CLS(TLSLE_LDST128_TPREL_LO12);
386 if (SymLoc == AArch64MCExpr::VK_TPREL && IsNC)
387 return R_CLS(TLSLE_LDST128_TPREL_LO12_NC);
388
389 Ctx.reportError(Fixup.getLoc(),
390 "invalid fixup for 128-bit load/store instruction");
391 return ELF::R_AARCH64_NONE;
392 // ILP32 case not reached here, tested with isNonILP32reloc
393 case AArch64::fixup_aarch64_movw:
394 if (RefKind == AArch64MCExpr::VK_ABS_G3)
395 return ELF::R_AARCH64_MOVW_UABS_G3;
396 if (RefKind == AArch64MCExpr::VK_ABS_G2)
397 return ELF::R_AARCH64_MOVW_UABS_G2;
398 if (RefKind == AArch64MCExpr::VK_ABS_G2_S)
399 return ELF::R_AARCH64_MOVW_SABS_G2;
400 if (RefKind == AArch64MCExpr::VK_ABS_G2_NC)
401 return ELF::R_AARCH64_MOVW_UABS_G2_NC;
402 if (RefKind == AArch64MCExpr::VK_ABS_G1)
403 return R_CLS(MOVW_UABS_G1);
404 if (RefKind == AArch64MCExpr::VK_ABS_G1_S)
405 return ELF::R_AARCH64_MOVW_SABS_G1;
406 if (RefKind == AArch64MCExpr::VK_ABS_G1_NC)
407 return ELF::R_AARCH64_MOVW_UABS_G1_NC;
408 if (RefKind == AArch64MCExpr::VK_ABS_G0)
409 return R_CLS(MOVW_UABS_G0);
410 if (RefKind == AArch64MCExpr::VK_ABS_G0_S)
411 return R_CLS(MOVW_SABS_G0);
412 if (RefKind == AArch64MCExpr::VK_ABS_G0_NC)
413 return R_CLS(MOVW_UABS_G0_NC);
414 if (RefKind == AArch64MCExpr::VK_PREL_G3)
415 return ELF::R_AARCH64_MOVW_PREL_G3;
416 if (RefKind == AArch64MCExpr::VK_PREL_G2)
417 return ELF::R_AARCH64_MOVW_PREL_G2;
418 if (RefKind == AArch64MCExpr::VK_PREL_G2_NC)
419 return ELF::R_AARCH64_MOVW_PREL_G2_NC;
420 if (RefKind == AArch64MCExpr::VK_PREL_G1)
421 return R_CLS(MOVW_PREL_G1);
422 if (RefKind == AArch64MCExpr::VK_PREL_G1_NC)
423 return ELF::R_AARCH64_MOVW_PREL_G1_NC;
424 if (RefKind == AArch64MCExpr::VK_PREL_G0)
425 return R_CLS(MOVW_PREL_G0);
426 if (RefKind == AArch64MCExpr::VK_PREL_G0_NC)
427 return R_CLS(MOVW_PREL_G0_NC);
428 if (RefKind == AArch64MCExpr::VK_DTPREL_G2)
429 return ELF::R_AARCH64_TLSLD_MOVW_DTPREL_G2;
430 if (RefKind == AArch64MCExpr::VK_DTPREL_G1)
431 return R_CLS(TLSLD_MOVW_DTPREL_G1);
432 if (RefKind == AArch64MCExpr::VK_DTPREL_G1_NC)
433 return ELF::R_AARCH64_TLSLD_MOVW_DTPREL_G1_NC;
434 if (RefKind == AArch64MCExpr::VK_DTPREL_G0)
435 return R_CLS(TLSLD_MOVW_DTPREL_G0);
436 if (RefKind == AArch64MCExpr::VK_DTPREL_G0_NC)
437 return R_CLS(TLSLD_MOVW_DTPREL_G0_NC);
438 if (RefKind == AArch64MCExpr::VK_TPREL_G2)
439 return ELF::R_AARCH64_TLSLE_MOVW_TPREL_G2;
440 if (RefKind == AArch64MCExpr::VK_TPREL_G1)
441 return R_CLS(TLSLE_MOVW_TPREL_G1);
442 if (RefKind == AArch64MCExpr::VK_TPREL_G1_NC)
443 return ELF::R_AARCH64_TLSLE_MOVW_TPREL_G1_NC;
444 if (RefKind == AArch64MCExpr::VK_TPREL_G0)
445 return R_CLS(TLSLE_MOVW_TPREL_G0);
446 if (RefKind == AArch64MCExpr::VK_TPREL_G0_NC)
447 return R_CLS(TLSLE_MOVW_TPREL_G0_NC);
448 if (RefKind == AArch64MCExpr::VK_GOTTPREL_G1)
449 return ELF::R_AARCH64_TLSIE_MOVW_GOTTPREL_G1;
450 if (RefKind == AArch64MCExpr::VK_GOTTPREL_G0_NC)
451 return ELF::R_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC;
452 Ctx.reportError(Fixup.getLoc(),
453 "invalid fixup for movz/movk instruction");
454 return ELF::R_AARCH64_NONE;
455 default:
456 Ctx.reportError(Fixup.getLoc(), "Unknown ELF relocation type");
457 return ELF::R_AARCH64_NONE;
458 }
459 }
460
461 llvm_unreachable("Unimplemented fixup -> relocation");
462}
463
464bool AArch64ELFObjectWriter::needsRelocateWithSymbol(const MCValue &Val,
465 const MCSymbol &,
466 unsigned) const {
467 return (Val.getRefKind() & AArch64MCExpr::VK_GOT) == AArch64MCExpr::VK_GOT;
468}
469
470MCSectionELF *
471AArch64ELFObjectWriter::getMemtagRelocsSection(MCContext &Ctx) const {
472 return Ctx.getELFSection(".memtag.globals.static",
473 ELF::SHT_AARCH64_MEMTAG_GLOBALS_STATIC, 0);
474}
475
476std::unique_ptr<MCObjectTargetWriter>
477llvm::createAArch64ELFObjectWriter(uint8_t OSABI, bool IsILP32) {
478 return std::make_unique<AArch64ELFObjectWriter>(OSABI, IsILP32);
479}
BAD_ILP32_MOV
#define BAD_ILP32_MOV(lp64rtype)
Definition: AArch64ELFObjectWriter.cpp:56
R_CLS
#define R_CLS(rtype)
Definition: AArch64ELFObjectWriter.cpp:54
isNonILP32reloc
static bool isNonILP32reloc(const MCFixup &Fixup, AArch64MCExpr::VariantKind RefKind, MCContext &Ctx)
Definition: AArch64ELFObjectWriter.cpp:61
true
basic Basic Alias true
Definition: BasicAliasAnalysis.cpp:1830
Sym
Symbol * Sym
Definition: ELF_riscv.cpp:468
Fixup
PowerPC TLS Dynamic Call Fixup
Definition: PPCTLSDynamicCall.cpp:230
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::AArch64MCExpr::getSymbolLoc
static VariantKind getSymbolLoc(VariantKind Kind)
Definition: AArch64MCExpr.h:148
llvm::AArch64MCExpr::isNotChecked
static bool isNotChecked(VariantKind Kind)
Definition: AArch64MCExpr.h:156
llvm::AArch64MCExpr::getAddressFrag
static VariantKind getAddressFrag(VariantKind Kind)
Definition: AArch64MCExpr.h:152
llvm::MCContext
Context object for machine code objects.
Definition: MCContext.h:76
llvm::MCContext::getELFSection
MCSectionELF * getELFSection(const Twine &Section, unsigned Type, unsigned Flags)
Definition: MCContext.h:565
llvm::MCContext::reportError
void reportError(SMLoc L, const Twine &Msg)
Definition: MCContext.cpp:1059
llvm::MCELFObjectTargetWriter::needsRelocateWithSymbol
virtual bool needsRelocateWithSymbol(const MCValue &Val, const MCSymbol &Sym, unsigned Type) const
Definition: MCELFObjectTargetWriter.cpp:20
llvm::MCELFObjectTargetWriter::getMemtagRelocsSection
virtual MCSectionELF * getMemtagRelocsSection(MCContext &Ctx) const
Definition: MCELFObjectWriter.h:145
llvm::MCELFObjectTargetWriter::getRelocType
virtual unsigned getRelocType(MCContext &Ctx, const MCValue &Target, const MCFixup &Fixup, bool IsPCRel) const =0
llvm::MCFixup
Encode information on a single operation to perform on a byte sequence (e.g., an encoded instruction)...
Definition: MCFixup.h:70
llvm::MCSectionELF
This represents a section on linux, lots of unix variants and some bare metal systems.
Definition: MCSectionELF.h:26
llvm::MCSymbol
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:41
llvm::MCValue
This represents an "assembler immediate".
Definition: MCValue.h:36
llvm::MCValue::getRefKind
uint32_t getRefKind() const
Definition: MCValue.h:46
llvm::Target
Target - Wrapper for Target specific information.
Definition: TargetRegistry.h:149
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
llvm::AArch64::fixup_aarch64_ldst_imm12_scale16
@ fixup_aarch64_ldst_imm12_scale16
Definition: AArch64FixupKinds.h:33
llvm::ELF::EM_AARCH64
@ EM_AARCH64
Definition: ELF.h:280
llvm::ELF::SHT_AARCH64_MEMTAG_GLOBALS_STATIC
@ SHT_AARCH64_MEMTAG_GLOBALS_STATIC
Definition: ELF.h:1061
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::FirstLiteralRelocationKind
@ FirstLiteralRelocationKind
The range [FirstLiteralRelocationKind, MaxTargetFixupKind) is used for relocations coming from ....
Definition: MCFixup.h:49
llvm::FK_Data_8
@ FK_Data_8
A eight-byte fixup.
Definition: MCFixup.h:26
llvm::FK_Data_1
@ FK_Data_1
A one-byte fixup.
Definition: MCFixup.h:23
llvm::FK_Data_4
@ FK_Data_4
A four-byte fixup.
Definition: MCFixup.h:25
llvm::FK_Data_2
@ FK_Data_2
A two-byte fixup.
Definition: MCFixup.h:24
llvm::createAArch64ELFObjectWriter
std::unique_ptr< MCObjectTargetWriter > createAArch64ELFObjectWriter(uint8_t OSABI, bool IsILP32)
Definition: AArch64ELFObjectWriter.cpp:477
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