LLVM 17.0.0git
AArch64ELFObjectWriter.cpp
Go to the documentation of this file.
1//===-- AArch64ELFObjectWriter.cpp - AArch64 ELF Writer -------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file handles ELF-specific object emission, converting LLVM's internal
10// fixups into the appropriate relocations.
11//
12//===----------------------------------------------------------------------===//
13
14#include "MCTargetDesc/AArch64FixupKinds.h"
15#include "MCTargetDesc/AArch64MCExpr.h"
16#include "MCTargetDesc/AArch64MCTargetDesc.h"
17#include "llvm/BinaryFormat/ELF.h"
18#include "llvm/MC/MCContext.h"
19#include "llvm/MC/MCELFObjectWriter.h"
20#include "llvm/MC/MCFixup.h"
21#include "llvm/MC/MCObjectWriter.h"
22#include "llvm/MC/MCValue.h"
23#include "llvm/Support/ErrorHandling.h"
24#include <cassert>
25#include <cstdint>
26
27using namespace llvm;
28
29namespace {
30
31class AArch64ELFObjectWriter : public MCELFObjectTargetWriter {
32public:
33 AArch64ELFObjectWriter(uint8_t OSABI, bool IsILP32);
34
35 ~AArch64ELFObjectWriter() override = default;
36
37 MCSectionELF *getMemtagRelocsSection(MCContext &Ctx) const override;
38
39protected:
40 unsigned getRelocType(MCContext &Ctx, const MCValue &Target,
41 const MCFixup &Fixup, bool IsPCRel) const override;
42 bool IsILP32;
43};
44
45} // end anonymous namespace
46
47AArch64ELFObjectWriter::AArch64ELFObjectWriter(uint8_t OSABI, bool IsILP32)
48 : MCELFObjectTargetWriter(/*Is64Bit*/ !IsILP32, OSABI, ELF::EM_AARCH64,
49 /*HasRelocationAddend*/ true),
50 IsILP32(IsILP32) {}
51
52#define R_CLS(rtype) \
53 IsILP32 ? ELF::R_AARCH64_P32_##rtype : ELF::R_AARCH64_##rtype
54#define BAD_ILP32_MOV(lp64rtype) \
55 "ILP32 absolute MOV relocation not " \
56 "supported (LP64 eqv: " #lp64rtype ")"
57
58// assumes IsILP32 is true
59static bool isNonILP32reloc(const MCFixup &Fixup,
60 AArch64MCExpr::VariantKind RefKind,
61 MCContext &Ctx) {
62 if (Fixup.getTargetKind() != AArch64::fixup_aarch64_movw)
63 return false;
64 switch (RefKind) {
65 case AArch64MCExpr::VK_ABS_G3:
66 Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(MOVW_UABS_G3));
67 return true;
68 case AArch64MCExpr::VK_ABS_G2:
69 Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(MOVW_UABS_G2));
70 return true;
71 case AArch64MCExpr::VK_ABS_G2_S:
72 Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(MOVW_SABS_G2));
73 return true;
74 case AArch64MCExpr::VK_ABS_G2_NC:
75 Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(MOVW_UABS_G2_NC));
76 return true;
77 case AArch64MCExpr::VK_ABS_G1_S:
78 Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(MOVW_SABS_G1));
79 return true;
80 case AArch64MCExpr::VK_ABS_G1_NC:
81 Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(MOVW_UABS_G1_NC));
82 return true;
83 case AArch64MCExpr::VK_DTPREL_G2:
84 Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(TLSLD_MOVW_DTPREL_G2));
85 return true;
86 case AArch64MCExpr::VK_DTPREL_G1_NC:
87 Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(TLSLD_MOVW_DTPREL_G1_NC));
88 return true;
89 case AArch64MCExpr::VK_TPREL_G2:
90 Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(TLSLE_MOVW_TPREL_G2));
91 return true;
92 case AArch64MCExpr::VK_TPREL_G1_NC:
93 Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(TLSLE_MOVW_TPREL_G1_NC));
94 return true;
95 case AArch64MCExpr::VK_GOTTPREL_G1:
96 Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(TLSIE_MOVW_GOTTPREL_G1));
97 return true;
98 case AArch64MCExpr::VK_GOTTPREL_G0_NC:
99 Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(TLSIE_MOVW_GOTTPREL_G0_NC));
100 return true;
101 default:
102 return false;
103 }
104 return false;
105}
106
107unsigned AArch64ELFObjectWriter::getRelocType(MCContext &Ctx,
108 const MCValue &Target,
109 const MCFixup &Fixup,
110 bool IsPCRel) const {
111 unsigned Kind = Fixup.getTargetKind();
112 if (Kind >= FirstLiteralRelocationKind)
113 return Kind - FirstLiteralRelocationKind;
114 AArch64MCExpr::VariantKind RefKind =
115 static_cast<AArch64MCExpr::VariantKind>(Target.getRefKind());
116 AArch64MCExpr::VariantKind SymLoc = AArch64MCExpr::getSymbolLoc(RefKind);
117 bool IsNC = AArch64MCExpr::isNotChecked(RefKind);
118
119 assert((!Target.getSymA() ||
120 Target.getSymA()->getKind() == MCSymbolRefExpr::VK_None ||
121 Target.getSymA()->getKind() == MCSymbolRefExpr::VK_PLT) &&
122 "Should only be expression-level modifiers here");
123
124 assert((!Target.getSymB() ||
125 Target.getSymB()->getKind() == MCSymbolRefExpr::VK_None) &&
126 "Should only be expression-level modifiers here");
127
128 if (IsPCRel) {
129 switch (Kind) {
130 case FK_Data_1:
131 Ctx.reportError(Fixup.getLoc(), "1-byte data relocations not supported");
132 return ELF::R_AARCH64_NONE;
133 case FK_Data_2:
134 return R_CLS(PREL16);
135 case FK_Data_4: {
136 return Target.getAccessVariant() == MCSymbolRefExpr::VK_PLT
137 ? R_CLS(PLT32)
138 : R_CLS(PREL32);
139 }
140 case FK_Data_8:
141 if (IsILP32) {
142 Ctx.reportError(Fixup.getLoc(),
143 "ILP32 8 byte PC relative data "
144 "relocation not supported (LP64 eqv: PREL64)");
145 return ELF::R_AARCH64_NONE;
146 } else
147 return ELF::R_AARCH64_PREL64;
148 case AArch64::fixup_aarch64_pcrel_adr_imm21:
149 if (SymLoc != AArch64MCExpr::VK_ABS)
150 Ctx.reportError(Fixup.getLoc(),
151 "invalid symbol kind for ADR relocation");
152 return R_CLS(ADR_PREL_LO21);
153 case AArch64::fixup_aarch64_pcrel_adrp_imm21:
154 if (SymLoc == AArch64MCExpr::VK_ABS && !IsNC)
155 return R_CLS(ADR_PREL_PG_HI21);
156 if (SymLoc == AArch64MCExpr::VK_ABS && IsNC) {
157 if (IsILP32) {
158 Ctx.reportError(Fixup.getLoc(),
159 "invalid fixup for 32-bit pcrel ADRP instruction "
160 "VK_ABS VK_NC");
161 return ELF::R_AARCH64_NONE;
162 } else {
163 return ELF::R_AARCH64_ADR_PREL_PG_HI21_NC;
164 }
165 }
166 if (SymLoc == AArch64MCExpr::VK_GOT && !IsNC)
167 return R_CLS(ADR_GOT_PAGE);
168 if (SymLoc == AArch64MCExpr::VK_GOTTPREL && !IsNC)
169 return R_CLS(TLSIE_ADR_GOTTPREL_PAGE21);
170 if (SymLoc == AArch64MCExpr::VK_TLSDESC && !IsNC)
171 return R_CLS(TLSDESC_ADR_PAGE21);
172 Ctx.reportError(Fixup.getLoc(),
173 "invalid symbol kind for ADRP relocation");
174 return ELF::R_AARCH64_NONE;
175 case AArch64::fixup_aarch64_pcrel_branch26:
176 return R_CLS(JUMP26);
177 case AArch64::fixup_aarch64_pcrel_call26:
178 return R_CLS(CALL26);
179 case AArch64::fixup_aarch64_ldr_pcrel_imm19:
180 if (SymLoc == AArch64MCExpr::VK_GOTTPREL)
181 return R_CLS(TLSIE_LD_GOTTPREL_PREL19);
182 if (SymLoc == AArch64MCExpr::VK_GOT)
183 return R_CLS(GOT_LD_PREL19);
184 return R_CLS(LD_PREL_LO19);
185 case AArch64::fixup_aarch64_pcrel_branch14:
186 return R_CLS(TSTBR14);
187 case AArch64::fixup_aarch64_pcrel_branch19:
188 return R_CLS(CONDBR19);
189 default:
190 Ctx.reportError(Fixup.getLoc(), "Unsupported pc-relative fixup kind");
191 return ELF::R_AARCH64_NONE;
192 }
193 } else {
194 if (IsILP32 && isNonILP32reloc(Fixup, RefKind, Ctx))
195 return ELF::R_AARCH64_NONE;
196 switch (Fixup.getTargetKind()) {
197 case FK_Data_1:
198 Ctx.reportError(Fixup.getLoc(), "1-byte data relocations not supported");
199 return ELF::R_AARCH64_NONE;
200 case FK_Data_2:
201 return R_CLS(ABS16);
202 case FK_Data_4:
203 return R_CLS(ABS32);
204 case FK_Data_8:
205 if (IsILP32) {
206 Ctx.reportError(Fixup.getLoc(),
207 "ILP32 8 byte absolute data "
208 "relocation not supported (LP64 eqv: ABS64)");
209 return ELF::R_AARCH64_NONE;
210 } else
211 return ELF::R_AARCH64_ABS64;
212 case AArch64::fixup_aarch64_add_imm12:
213 if (RefKind == AArch64MCExpr::VK_DTPREL_HI12)
214 return R_CLS(TLSLD_ADD_DTPREL_HI12);
215 if (RefKind == AArch64MCExpr::VK_TPREL_HI12)
216 return R_CLS(TLSLE_ADD_TPREL_HI12);
217 if (RefKind == AArch64MCExpr::VK_DTPREL_LO12_NC)
218 return R_CLS(TLSLD_ADD_DTPREL_LO12_NC);
219 if (RefKind == AArch64MCExpr::VK_DTPREL_LO12)
220 return R_CLS(TLSLD_ADD_DTPREL_LO12);
221 if (RefKind == AArch64MCExpr::VK_TPREL_LO12_NC)
222 return R_CLS(TLSLE_ADD_TPREL_LO12_NC);
223 if (RefKind == AArch64MCExpr::VK_TPREL_LO12)
224 return R_CLS(TLSLE_ADD_TPREL_LO12);
225 if (RefKind == AArch64MCExpr::VK_TLSDESC_LO12)
226 return R_CLS(TLSDESC_ADD_LO12);
227 if (SymLoc == AArch64MCExpr::VK_ABS && IsNC)
228 return R_CLS(ADD_ABS_LO12_NC);
229
230 Ctx.reportError(Fixup.getLoc(),
231 "invalid fixup for add (uimm12) instruction");
232 return ELF::R_AARCH64_NONE;
233 case AArch64::fixup_aarch64_ldst_imm12_scale1:
234 if (SymLoc == AArch64MCExpr::VK_ABS && IsNC)
235 return R_CLS(LDST8_ABS_LO12_NC);
236 if (SymLoc == AArch64MCExpr::VK_DTPREL && !IsNC)
237 return R_CLS(TLSLD_LDST8_DTPREL_LO12);
238 if (SymLoc == AArch64MCExpr::VK_DTPREL && IsNC)
239 return R_CLS(TLSLD_LDST8_DTPREL_LO12_NC);
240 if (SymLoc == AArch64MCExpr::VK_TPREL && !IsNC)
241 return R_CLS(TLSLE_LDST8_TPREL_LO12);
242 if (SymLoc == AArch64MCExpr::VK_TPREL && IsNC)
243 return R_CLS(TLSLE_LDST8_TPREL_LO12_NC);
244
245 Ctx.reportError(Fixup.getLoc(),
246 "invalid fixup for 8-bit load/store instruction");
247 return ELF::R_AARCH64_NONE;
248 case AArch64::fixup_aarch64_ldst_imm12_scale2:
249 if (SymLoc == AArch64MCExpr::VK_ABS && IsNC)
250 return R_CLS(LDST16_ABS_LO12_NC);
251 if (SymLoc == AArch64MCExpr::VK_DTPREL && !IsNC)
252 return R_CLS(TLSLD_LDST16_DTPREL_LO12);
253 if (SymLoc == AArch64MCExpr::VK_DTPREL && IsNC)
254 return R_CLS(TLSLD_LDST16_DTPREL_LO12_NC);
255 if (SymLoc == AArch64MCExpr::VK_TPREL && !IsNC)
256 return R_CLS(TLSLE_LDST16_TPREL_LO12);
257 if (SymLoc == AArch64MCExpr::VK_TPREL && IsNC)
258 return R_CLS(TLSLE_LDST16_TPREL_LO12_NC);
259
260 Ctx.reportError(Fixup.getLoc(),
261 "invalid fixup for 16-bit load/store instruction");
262 return ELF::R_AARCH64_NONE;
263 case AArch64::fixup_aarch64_ldst_imm12_scale4:
264 if (SymLoc == AArch64MCExpr::VK_ABS && IsNC)
265 return R_CLS(LDST32_ABS_LO12_NC);
266 if (SymLoc == AArch64MCExpr::VK_DTPREL && !IsNC)
267 return R_CLS(TLSLD_LDST32_DTPREL_LO12);
268 if (SymLoc == AArch64MCExpr::VK_DTPREL && IsNC)
269 return R_CLS(TLSLD_LDST32_DTPREL_LO12_NC);
270 if (SymLoc == AArch64MCExpr::VK_TPREL && !IsNC)
271 return R_CLS(TLSLE_LDST32_TPREL_LO12);
272 if (SymLoc == AArch64MCExpr::VK_TPREL && IsNC)
273 return R_CLS(TLSLE_LDST32_TPREL_LO12_NC);
274 if (SymLoc == AArch64MCExpr::VK_GOT && IsNC) {
275 if (IsILP32) {
276 return ELF::R_AARCH64_P32_LD32_GOT_LO12_NC;
277 } else {
278 Ctx.reportError(Fixup.getLoc(),
279 "LP64 4 byte unchecked GOT load/store relocation "
280 "not supported (ILP32 eqv: LD32_GOT_LO12_NC");
281 return ELF::R_AARCH64_NONE;
282 }
283 }
284 if (SymLoc == AArch64MCExpr::VK_GOT && !IsNC) {
285 if (IsILP32) {
286 Ctx.reportError(Fixup.getLoc(),
287 "ILP32 4 byte checked GOT load/store relocation "
288 "not supported (unchecked eqv: LD32_GOT_LO12_NC)");
289 } else {
290 Ctx.reportError(Fixup.getLoc(),
291 "LP64 4 byte checked GOT load/store relocation "
292 "not supported (unchecked/ILP32 eqv: "
293 "LD32_GOT_LO12_NC)");
294 }
295 return ELF::R_AARCH64_NONE;
296 }
297 if (SymLoc == AArch64MCExpr::VK_GOTTPREL && IsNC) {
298 if (IsILP32) {
299 return ELF::R_AARCH64_P32_TLSIE_LD32_GOTTPREL_LO12_NC;
300 } else {
301 Ctx.reportError(Fixup.getLoc(),
302 "LP64 32-bit load/store "
303 "relocation not supported (ILP32 eqv: "
304 "TLSIE_LD32_GOTTPREL_LO12_NC)");
305 return ELF::R_AARCH64_NONE;
306 }
307 }
308 if (SymLoc == AArch64MCExpr::VK_TLSDESC && !IsNC) {
309 if (IsILP32) {
310 return ELF::R_AARCH64_P32_TLSDESC_LD32_LO12;
311 } else {
312 Ctx.reportError(Fixup.getLoc(),
313 "LP64 4 byte TLSDESC load/store relocation "
314 "not supported (ILP32 eqv: TLSDESC_LD64_LO12)");
315 return ELF::R_AARCH64_NONE;
316 }
317 }
318
319 Ctx.reportError(Fixup.getLoc(),
320 "invalid fixup for 32-bit load/store instruction "
321 "fixup_aarch64_ldst_imm12_scale4");
322 return ELF::R_AARCH64_NONE;
323 case AArch64::fixup_aarch64_ldst_imm12_scale8:
324 if (SymLoc == AArch64MCExpr::VK_ABS && IsNC)
325 return R_CLS(LDST64_ABS_LO12_NC);
326 if (SymLoc == AArch64MCExpr::VK_GOT && IsNC) {
327 AArch64MCExpr::VariantKind AddressLoc =
328 AArch64MCExpr::getAddressFrag(RefKind);
329 if (!IsILP32) {
330 if (AddressLoc == AArch64MCExpr::VK_LO15)
331 return ELF::R_AARCH64_LD64_GOTPAGE_LO15;
332 return ELF::R_AARCH64_LD64_GOT_LO12_NC;
333 } else {
334 Ctx.reportError(Fixup.getLoc(), "ILP32 64-bit load/store "
335 "relocation not supported (LP64 eqv: "
336 "LD64_GOT_LO12_NC)");
337 return ELF::R_AARCH64_NONE;
338 }
339 }
340 if (SymLoc == AArch64MCExpr::VK_DTPREL && !IsNC)
341 return R_CLS(TLSLD_LDST64_DTPREL_LO12);
342 if (SymLoc == AArch64MCExpr::VK_DTPREL && IsNC)
343 return R_CLS(TLSLD_LDST64_DTPREL_LO12_NC);
344 if (SymLoc == AArch64MCExpr::VK_TPREL && !IsNC)
345 return R_CLS(TLSLE_LDST64_TPREL_LO12);
346 if (SymLoc == AArch64MCExpr::VK_TPREL && IsNC)
347 return R_CLS(TLSLE_LDST64_TPREL_LO12_NC);
348 if (SymLoc == AArch64MCExpr::VK_GOTTPREL && IsNC) {
349 if (!IsILP32) {
350 return ELF::R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC;
351 } else {
352 Ctx.reportError(Fixup.getLoc(), "ILP32 64-bit load/store "
353 "relocation not supported (LP64 eqv: "
354 "TLSIE_LD64_GOTTPREL_LO12_NC)");
355 return ELF::R_AARCH64_NONE;
356 }
357 }
358 if (SymLoc == AArch64MCExpr::VK_TLSDESC) {
359 if (!IsILP32) {
360 return ELF::R_AARCH64_TLSDESC_LD64_LO12;
361 } else {
362 Ctx.reportError(Fixup.getLoc(), "ILP32 64-bit load/store "
363 "relocation not supported (LP64 eqv: "
364 "TLSDESC_LD64_LO12)");
365 return ELF::R_AARCH64_NONE;
366 }
367 }
368 Ctx.reportError(Fixup.getLoc(),
369 "invalid fixup for 64-bit load/store instruction");
370 return ELF::R_AARCH64_NONE;
371 case AArch64::fixup_aarch64_ldst_imm12_scale16:
372 if (SymLoc == AArch64MCExpr::VK_ABS && IsNC)
373 return R_CLS(LDST128_ABS_LO12_NC);
374 if (SymLoc == AArch64MCExpr::VK_DTPREL && !IsNC)
375 return R_CLS(TLSLD_LDST128_DTPREL_LO12);
376 if (SymLoc == AArch64MCExpr::VK_DTPREL && IsNC)
377 return R_CLS(TLSLD_LDST128_DTPREL_LO12_NC);
378 if (SymLoc == AArch64MCExpr::VK_TPREL && !IsNC)
379 return R_CLS(TLSLE_LDST128_TPREL_LO12);
380 if (SymLoc == AArch64MCExpr::VK_TPREL && IsNC)
381 return R_CLS(TLSLE_LDST128_TPREL_LO12_NC);
382
383 Ctx.reportError(Fixup.getLoc(),
384 "invalid fixup for 128-bit load/store instruction");
385 return ELF::R_AARCH64_NONE;
386 // ILP32 case not reached here, tested with isNonILP32reloc
387 case AArch64::fixup_aarch64_movw:
388 if (RefKind == AArch64MCExpr::VK_ABS_G3)
389 return ELF::R_AARCH64_MOVW_UABS_G3;
390 if (RefKind == AArch64MCExpr::VK_ABS_G2)
391 return ELF::R_AARCH64_MOVW_UABS_G2;
392 if (RefKind == AArch64MCExpr::VK_ABS_G2_S)
393 return ELF::R_AARCH64_MOVW_SABS_G2;
394 if (RefKind == AArch64MCExpr::VK_ABS_G2_NC)
395 return ELF::R_AARCH64_MOVW_UABS_G2_NC;
396 if (RefKind == AArch64MCExpr::VK_ABS_G1)
397 return R_CLS(MOVW_UABS_G1);
398 if (RefKind == AArch64MCExpr::VK_ABS_G1_S)
399 return ELF::R_AARCH64_MOVW_SABS_G1;
400 if (RefKind == AArch64MCExpr::VK_ABS_G1_NC)
401 return ELF::R_AARCH64_MOVW_UABS_G1_NC;
402 if (RefKind == AArch64MCExpr::VK_ABS_G0)
403 return R_CLS(MOVW_UABS_G0);
404 if (RefKind == AArch64MCExpr::VK_ABS_G0_S)
405 return R_CLS(MOVW_SABS_G0);
406 if (RefKind == AArch64MCExpr::VK_ABS_G0_NC)
407 return R_CLS(MOVW_UABS_G0_NC);
408 if (RefKind == AArch64MCExpr::VK_PREL_G3)
409 return ELF::R_AARCH64_MOVW_PREL_G3;
410 if (RefKind == AArch64MCExpr::VK_PREL_G2)
411 return ELF::R_AARCH64_MOVW_PREL_G2;
412 if (RefKind == AArch64MCExpr::VK_PREL_G2_NC)
413 return ELF::R_AARCH64_MOVW_PREL_G2_NC;
414 if (RefKind == AArch64MCExpr::VK_PREL_G1)
415 return R_CLS(MOVW_PREL_G1);
416 if (RefKind == AArch64MCExpr::VK_PREL_G1_NC)
417 return ELF::R_AARCH64_MOVW_PREL_G1_NC;
418 if (RefKind == AArch64MCExpr::VK_PREL_G0)
419 return R_CLS(MOVW_PREL_G0);
420 if (RefKind == AArch64MCExpr::VK_PREL_G0_NC)
421 return R_CLS(MOVW_PREL_G0_NC);
422 if (RefKind == AArch64MCExpr::VK_DTPREL_G2)
423 return ELF::R_AARCH64_TLSLD_MOVW_DTPREL_G2;
424 if (RefKind == AArch64MCExpr::VK_DTPREL_G1)
425 return R_CLS(TLSLD_MOVW_DTPREL_G1);
426 if (RefKind == AArch64MCExpr::VK_DTPREL_G1_NC)
427 return ELF::R_AARCH64_TLSLD_MOVW_DTPREL_G1_NC;
428 if (RefKind == AArch64MCExpr::VK_DTPREL_G0)
429 return R_CLS(TLSLD_MOVW_DTPREL_G0);
430 if (RefKind == AArch64MCExpr::VK_DTPREL_G0_NC)
431 return R_CLS(TLSLD_MOVW_DTPREL_G0_NC);
432 if (RefKind == AArch64MCExpr::VK_TPREL_G2)
433 return ELF::R_AARCH64_TLSLE_MOVW_TPREL_G2;
434 if (RefKind == AArch64MCExpr::VK_TPREL_G1)
435 return R_CLS(TLSLE_MOVW_TPREL_G1);
436 if (RefKind == AArch64MCExpr::VK_TPREL_G1_NC)
437 return ELF::R_AARCH64_TLSLE_MOVW_TPREL_G1_NC;
438 if (RefKind == AArch64MCExpr::VK_TPREL_G0)
439 return R_CLS(TLSLE_MOVW_TPREL_G0);
440 if (RefKind == AArch64MCExpr::VK_TPREL_G0_NC)
441 return R_CLS(TLSLE_MOVW_TPREL_G0_NC);
442 if (RefKind == AArch64MCExpr::VK_GOTTPREL_G1)
443 return ELF::R_AARCH64_TLSIE_MOVW_GOTTPREL_G1;
444 if (RefKind == AArch64MCExpr::VK_GOTTPREL_G0_NC)
445 return ELF::R_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC;
446 Ctx.reportError(Fixup.getLoc(),
447 "invalid fixup for movz/movk instruction");
448 return ELF::R_AARCH64_NONE;
449 default:
450 Ctx.reportError(Fixup.getLoc(), "Unknown ELF relocation type");
451 return ELF::R_AARCH64_NONE;
452 }
453 }
454
455 llvm_unreachable("Unimplemented fixup -> relocation");
456}
457
458MCSectionELF *
459AArch64ELFObjectWriter::getMemtagRelocsSection(MCContext &Ctx) const {
460 return Ctx.getELFSection(".memtag.globals.static",
461 ELF::SHT_AARCH64_MEMTAG_GLOBALS_STATIC, 0);
462}
463
464std::unique_ptr<MCObjectTargetWriter>
465llvm::createAArch64ELFObjectWriter(uint8_t OSABI, bool IsILP32) {
466 return std::make_unique<AArch64ELFObjectWriter>(OSABI, IsILP32);
467}
BAD_ILP32_MOV
#define BAD_ILP32_MOV(lp64rtype)
Definition: AArch64ELFObjectWriter.cpp:54
R_CLS
#define R_CLS(rtype)
Definition: AArch64ELFObjectWriter.cpp:52
isNonILP32reloc
static bool isNonILP32reloc(const MCFixup &Fixup, AArch64MCExpr::VariantKind RefKind, MCContext &Ctx)
Definition: AArch64ELFObjectWriter.cpp:59
true
basic Basic Alias true
Definition: BasicAliasAnalysis.cpp:1806
Fixup
PowerPC TLS Dynamic Call Fixup
Definition: PPCTLSDynamicCall.cpp:215
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::AArch64MCExpr::getSymbolLoc
static VariantKind getSymbolLoc(VariantKind Kind)
Definition: AArch64MCExpr.h:143
llvm::AArch64MCExpr::isNotChecked
static bool isNotChecked(VariantKind Kind)
Definition: AArch64MCExpr.h:151
llvm::AArch64MCExpr::getAddressFrag
static VariantKind getAddressFrag(VariantKind Kind)
Definition: AArch64MCExpr.h:147
llvm::MCContext
Context object for machine code objects.
Definition: MCContext.h:76
llvm::MCContext::getELFSection
MCSectionELF * getELFSection(const Twine &Section, unsigned Type, unsigned Flags)
Definition: MCContext.h:563
llvm::MCContext::reportError
void reportError(SMLoc L, const Twine &Msg)
Definition: MCContext.cpp:1052
llvm::MCELFObjectTargetWriter::getMemtagRelocsSection
virtual MCSectionELF * getMemtagRelocsSection(MCContext &Ctx) const
Definition: MCELFObjectWriter.h:147
llvm::MCELFObjectTargetWriter::getRelocType
virtual unsigned getRelocType(MCContext &Ctx, const MCValue &Target, const MCFixup &Fixup, bool IsPCRel) const =0
llvm::MCFixup
Encode information on a single operation to perform on a byte sequence (e.g., an encoded instruction)...
Definition: MCFixup.h:71
llvm::MCSectionELF
This represents a section on linux, lots of unix variants and some bare metal systems.
Definition: MCSectionELF.h:26
llvm::MCValue
This represents an "assembler immediate".
Definition: MCValue.h:36
llvm::Target
Target - Wrapper for Target specific information.
Definition: TargetRegistry.h:149
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
llvm::AArch64::fixup_aarch64_ldst_imm12_scale16
@ fixup_aarch64_ldst_imm12_scale16
Definition: AArch64FixupKinds.h:33
llvm::ELF::EM_AARCH64
@ EM_AARCH64
Definition: ELF.h:280
llvm::ELF::SHT_AARCH64_MEMTAG_GLOBALS_STATIC
@ SHT_AARCH64_MEMTAG_GLOBALS_STATIC
Definition: ELF.h:1055
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::FirstLiteralRelocationKind
@ FirstLiteralRelocationKind
The range [FirstLiteralRelocationKind, MaxTargetFixupKind) is used for relocations coming from ....
Definition: MCFixup.h:50
llvm::FK_Data_8
@ FK_Data_8
A eight-byte fixup.
Definition: MCFixup.h:26
llvm::FK_Data_1
@ FK_Data_1
A one-byte fixup.
Definition: MCFixup.h:23
llvm::FK_Data_4
@ FK_Data_4
A four-byte fixup.
Definition: MCFixup.h:25
llvm::FK_Data_2
@ FK_Data_2
A two-byte fixup.
Definition: MCFixup.h:24
llvm::createAArch64ELFObjectWriter
std::unique_ptr< MCObjectTargetWriter > createAArch64ELFObjectWriter(uint8_t OSABI, bool IsILP32)
Definition: AArch64ELFObjectWriter.cpp:465
Generated on Sun Mar 26 2023 02:05:03 for LLVM by doxygen 1.9.6