33 AArch64ELFObjectWriter(uint8_t OSABI,
bool IsILP32);
35 ~AArch64ELFObjectWriter()
override =
default;
43 unsigned Type)
const override;
49AArch64ELFObjectWriter::AArch64ELFObjectWriter(uint8_t OSABI,
bool IsILP32)
55 IsILP32 ? ELF::R_AARCH64_P32_##rtype : ELF::R_AARCH64_##rtype
56#define BAD_ILP32_MOV(lp64rtype) \
57 "ILP32 absolute MOV relocation not " \
58 "supported (LP64 eqv: " #lp64rtype ")"
109unsigned AArch64ELFObjectWriter::getRelocType(
MCContext &Ctx,
112 bool IsPCRel)
const {
124 "Should only be expression-level modifiers here");
128 "Should only be expression-level modifiers here");
134 return ELF::R_AARCH64_NONE;
136 return R_CLS(PREL16);
145 "ILP32 8 byte PC relative data "
146 "relocation not supported (LP64 eqv: PREL64)");
147 return ELF::R_AARCH64_NONE;
149 return ELF::R_AARCH64_PREL64;
153 "invalid symbol kind for ADR relocation");
154 return R_CLS(ADR_PREL_LO21);
157 return R_CLS(ADR_PREL_PG_HI21);
161 "invalid fixup for 32-bit pcrel ADRP instruction "
163 return ELF::R_AARCH64_NONE;
165 return ELF::R_AARCH64_ADR_PREL_PG_HI21_NC;
169 return R_CLS(ADR_GOT_PAGE);
171 return R_CLS(TLSIE_ADR_GOTTPREL_PAGE21);
173 return R_CLS(TLSDESC_ADR_PAGE21);
175 "invalid symbol kind for ADRP relocation");
176 return ELF::R_AARCH64_NONE;
178 return R_CLS(JUMP26);
180 return R_CLS(CALL26);
183 return R_CLS(TLSIE_LD_GOTTPREL_PREL19);
185 return R_CLS(GOT_LD_PREL19);
186 return R_CLS(LD_PREL_LO19);
188 return R_CLS(TSTBR14);
190 return R_CLS(CONDBR19);
193 return ELF::R_AARCH64_NONE;
197 return ELF::R_AARCH64_NONE;
198 switch (
Fixup.getTargetKind()) {
201 return ELF::R_AARCH64_NONE;
209 "ILP32 8 byte absolute data "
210 "relocation not supported (LP64 eqv: ABS64)");
211 return ELF::R_AARCH64_NONE;
215 return ELF::R_AARCH64_AUTH_ABS64;
216 return ELF::R_AARCH64_ABS64;
220 return R_CLS(TLSLD_ADD_DTPREL_HI12);
222 return R_CLS(TLSLE_ADD_TPREL_HI12);
224 return R_CLS(TLSLD_ADD_DTPREL_LO12_NC);
226 return R_CLS(TLSLD_ADD_DTPREL_LO12);
228 return R_CLS(TLSLE_ADD_TPREL_LO12_NC);
230 return R_CLS(TLSLE_ADD_TPREL_LO12);
232 return R_CLS(TLSDESC_ADD_LO12);
234 return R_CLS(ADD_ABS_LO12_NC);
237 "invalid fixup for add (uimm12) instruction");
238 return ELF::R_AARCH64_NONE;
241 return R_CLS(LDST8_ABS_LO12_NC);
243 return R_CLS(TLSLD_LDST8_DTPREL_LO12);
245 return R_CLS(TLSLD_LDST8_DTPREL_LO12_NC);
247 return R_CLS(TLSLE_LDST8_TPREL_LO12);
249 return R_CLS(TLSLE_LDST8_TPREL_LO12_NC);
252 "invalid fixup for 8-bit load/store instruction");
253 return ELF::R_AARCH64_NONE;
256 return R_CLS(LDST16_ABS_LO12_NC);
258 return R_CLS(TLSLD_LDST16_DTPREL_LO12);
260 return R_CLS(TLSLD_LDST16_DTPREL_LO12_NC);
262 return R_CLS(TLSLE_LDST16_TPREL_LO12);
264 return R_CLS(TLSLE_LDST16_TPREL_LO12_NC);
267 "invalid fixup for 16-bit load/store instruction");
268 return ELF::R_AARCH64_NONE;
271 return R_CLS(LDST32_ABS_LO12_NC);
273 return R_CLS(TLSLD_LDST32_DTPREL_LO12);
275 return R_CLS(TLSLD_LDST32_DTPREL_LO12_NC);
277 return R_CLS(TLSLE_LDST32_TPREL_LO12);
279 return R_CLS(TLSLE_LDST32_TPREL_LO12_NC);
282 return ELF::R_AARCH64_P32_LD32_GOT_LO12_NC;
285 "LP64 4 byte unchecked GOT load/store relocation "
286 "not supported (ILP32 eqv: LD32_GOT_LO12_NC");
287 return ELF::R_AARCH64_NONE;
293 "ILP32 4 byte checked GOT load/store relocation "
294 "not supported (unchecked eqv: LD32_GOT_LO12_NC)");
297 "LP64 4 byte checked GOT load/store relocation "
298 "not supported (unchecked/ILP32 eqv: "
299 "LD32_GOT_LO12_NC)");
301 return ELF::R_AARCH64_NONE;
305 return ELF::R_AARCH64_P32_TLSIE_LD32_GOTTPREL_LO12_NC;
308 "LP64 32-bit load/store "
309 "relocation not supported (ILP32 eqv: "
310 "TLSIE_LD32_GOTTPREL_LO12_NC)");
311 return ELF::R_AARCH64_NONE;
316 return ELF::R_AARCH64_P32_TLSDESC_LD32_LO12;
319 "LP64 4 byte TLSDESC load/store relocation "
320 "not supported (ILP32 eqv: TLSDESC_LD64_LO12)");
321 return ELF::R_AARCH64_NONE;
326 "invalid fixup for 32-bit load/store instruction "
327 "fixup_aarch64_ldst_imm12_scale4");
328 return ELF::R_AARCH64_NONE;
331 return R_CLS(LDST64_ABS_LO12_NC);
337 return ELF::R_AARCH64_LD64_GOTPAGE_LO15;
338 return ELF::R_AARCH64_LD64_GOT_LO12_NC;
341 "relocation not supported (LP64 eqv: "
342 "LD64_GOT_LO12_NC)");
343 return ELF::R_AARCH64_NONE;
347 return R_CLS(TLSLD_LDST64_DTPREL_LO12);
349 return R_CLS(TLSLD_LDST64_DTPREL_LO12_NC);
351 return R_CLS(TLSLE_LDST64_TPREL_LO12);
353 return R_CLS(TLSLE_LDST64_TPREL_LO12_NC);
356 return ELF::R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC;
359 "relocation not supported (LP64 eqv: "
360 "TLSIE_LD64_GOTTPREL_LO12_NC)");
361 return ELF::R_AARCH64_NONE;
366 return ELF::R_AARCH64_TLSDESC_LD64_LO12;
369 "relocation not supported (LP64 eqv: "
370 "TLSDESC_LD64_LO12)");
371 return ELF::R_AARCH64_NONE;
375 "invalid fixup for 64-bit load/store instruction");
376 return ELF::R_AARCH64_NONE;
379 return R_CLS(LDST128_ABS_LO12_NC);
381 return R_CLS(TLSLD_LDST128_DTPREL_LO12);
383 return R_CLS(TLSLD_LDST128_DTPREL_LO12_NC);
385 return R_CLS(TLSLE_LDST128_TPREL_LO12);
387 return R_CLS(TLSLE_LDST128_TPREL_LO12_NC);
390 "invalid fixup for 128-bit load/store instruction");
391 return ELF::R_AARCH64_NONE;
395 return ELF::R_AARCH64_MOVW_UABS_G3;
397 return ELF::R_AARCH64_MOVW_UABS_G2;
399 return ELF::R_AARCH64_MOVW_SABS_G2;
401 return ELF::R_AARCH64_MOVW_UABS_G2_NC;
403 return R_CLS(MOVW_UABS_G1);
405 return ELF::R_AARCH64_MOVW_SABS_G1;
407 return ELF::R_AARCH64_MOVW_UABS_G1_NC;
409 return R_CLS(MOVW_UABS_G0);
411 return R_CLS(MOVW_SABS_G0);
413 return R_CLS(MOVW_UABS_G0_NC);
415 return ELF::R_AARCH64_MOVW_PREL_G3;
417 return ELF::R_AARCH64_MOVW_PREL_G2;
419 return ELF::R_AARCH64_MOVW_PREL_G2_NC;
421 return R_CLS(MOVW_PREL_G1);
423 return ELF::R_AARCH64_MOVW_PREL_G1_NC;
425 return R_CLS(MOVW_PREL_G0);
427 return R_CLS(MOVW_PREL_G0_NC);
429 return ELF::R_AARCH64_TLSLD_MOVW_DTPREL_G2;
431 return R_CLS(TLSLD_MOVW_DTPREL_G1);
433 return ELF::R_AARCH64_TLSLD_MOVW_DTPREL_G1_NC;
435 return R_CLS(TLSLD_MOVW_DTPREL_G0);
437 return R_CLS(TLSLD_MOVW_DTPREL_G0_NC);
439 return ELF::R_AARCH64_TLSLE_MOVW_TPREL_G2;
441 return R_CLS(TLSLE_MOVW_TPREL_G1);
443 return ELF::R_AARCH64_TLSLE_MOVW_TPREL_G1_NC;
445 return R_CLS(TLSLE_MOVW_TPREL_G0);
447 return R_CLS(TLSLE_MOVW_TPREL_G0_NC);
449 return ELF::R_AARCH64_TLSIE_MOVW_GOTTPREL_G1;
451 return ELF::R_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC;
453 "invalid fixup for movz/movk instruction");
454 return ELF::R_AARCH64_NONE;
457 return ELF::R_AARCH64_NONE;
464bool AArch64ELFObjectWriter::needsRelocateWithSymbol(
const MCValue &Val,
471AArch64ELFObjectWriter::getMemtagRelocsSection(
MCContext &Ctx)
const {
476std::unique_ptr<MCObjectTargetWriter>
478 return std::make_unique<AArch64ELFObjectWriter>(OSABI, IsILP32);
#define BAD_ILP32_MOV(lp64rtype)
static bool isNonILP32reloc(const MCFixup &Fixup, AArch64MCExpr::VariantKind RefKind, MCContext &Ctx)
PowerPC TLS Dynamic Call Fixup
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static VariantKind getSymbolLoc(VariantKind Kind)
static bool isNotChecked(VariantKind Kind)
static VariantKind getAddressFrag(VariantKind Kind)
Context object for machine code objects.
MCSectionELF * getELFSection(const Twine &Section, unsigned Type, unsigned Flags)
void reportError(SMLoc L, const Twine &Msg)
virtual bool needsRelocateWithSymbol(const MCValue &Val, const MCSymbol &Sym, unsigned Type) const
virtual MCSectionELF * getMemtagRelocsSection(MCContext &Ctx) const
virtual unsigned getRelocType(MCContext &Ctx, const MCValue &Target, const MCFixup &Fixup, bool IsPCRel) const =0
Encode information on a single operation to perform on a byte sequence (e.g., an encoded instruction)...
This represents a section on linux, lots of unix variants and some bare metal systems.
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
This represents an "assembler immediate".
uint32_t getRefKind() const
Target - Wrapper for Target specific information.
The instances of the Type class are immutable: once they are created, they are never changed.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ fixup_aarch64_ldst_imm12_scale4
@ fixup_aarch64_pcrel_call26
@ fixup_aarch64_pcrel_branch26
@ fixup_aarch64_pcrel_branch19
@ fixup_aarch64_ldr_pcrel_imm19
@ fixup_aarch64_pcrel_adr_imm21
@ fixup_aarch64_pcrel_branch14
@ fixup_aarch64_ldst_imm12_scale2
@ fixup_aarch64_ldst_imm12_scale16
@ fixup_aarch64_pcrel_adrp_imm21
@ fixup_aarch64_add_imm12
@ fixup_aarch64_ldst_imm12_scale8
@ fixup_aarch64_ldst_imm12_scale1
@ SHT_AARCH64_MEMTAG_GLOBALS_STATIC
This is an optimization pass for GlobalISel generic memory operations.
@ FirstLiteralRelocationKind
The range [FirstLiteralRelocationKind, MaxTargetFixupKind) is used for relocations coming from ....
@ FK_Data_8
A eight-byte fixup.
@ FK_Data_1
A one-byte fixup.
@ FK_Data_4
A four-byte fixup.
@ FK_Data_2
A two-byte fixup.
std::unique_ptr< MCObjectTargetWriter > createAArch64ELFObjectWriter(uint8_t OSABI, bool IsILP32)