LLVM 17.0.0git
AArch64ExpandImm.cpp
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1//===- AArch64ExpandImm.h - AArch64 Immediate Expansion -------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements the AArch64ExpandImm stuff.
10//
11//===----------------------------------------------------------------------===//
12
13#include "AArch64.h"
14#include "AArch64ExpandImm.h"
16
17using namespace llvm;
18using namespace llvm::AArch64_IMM;
19
20/// Helper function which extracts the specified 16-bit chunk from a
21/// 64-bit value.
22static uint64_t getChunk(uint64_t Imm, unsigned ChunkIdx) {
23 assert(ChunkIdx < 4 && "Out of range chunk index specified!");
24
25 return (Imm >> (ChunkIdx * 16)) & 0xFFFF;
26}
27
28/// Check whether the given 16-bit chunk replicated to full 64-bit width
29/// can be materialized with an ORR instruction.
30static bool canUseOrr(uint64_t Chunk, uint64_t &Encoding) {
31 Chunk = (Chunk << 48) | (Chunk << 32) | (Chunk << 16) | Chunk;
32
33 return AArch64_AM::processLogicalImmediate(Chunk, 64, Encoding);
34}
35
36/// Check for identical 16-bit chunks within the constant and if so
37/// materialize them with a single ORR instruction. The remaining one or two
38/// 16-bit chunks will be materialized with MOVK instructions.
39///
40/// This allows us to materialize constants like |A|B|A|A| or |A|B|C|A| (order
41/// of the chunks doesn't matter), assuming |A|A|A|A| can be materialized with
42/// an ORR instruction.
45 using CountMap = DenseMap<uint64_t, unsigned>;
46
47 CountMap Counts;
48
49 // Scan the constant and count how often every chunk occurs.
50 for (unsigned Idx = 0; Idx < 4; ++Idx)
51 ++Counts[getChunk(UImm, Idx)];
52
53 // Traverse the chunks to find one which occurs more than once.
54 for (const auto &Chunk : Counts) {
55 const uint64_t ChunkVal = Chunk.first;
56 const unsigned Count = Chunk.second;
57
58 uint64_t Encoding = 0;
59
60 // We are looking for chunks which have two or three instances and can be
61 // materialized with an ORR instruction.
62 if ((Count != 2 && Count != 3) || !canUseOrr(ChunkVal, Encoding))
63 continue;
64
65 const bool CountThree = Count == 3;
66
67 Insn.push_back({ AArch64::ORRXri, 0, Encoding });
68
69 unsigned ShiftAmt = 0;
70 uint64_t Imm16 = 0;
71 // Find the first chunk not materialized with the ORR instruction.
72 for (; ShiftAmt < 64; ShiftAmt += 16) {
73 Imm16 = (UImm >> ShiftAmt) & 0xFFFF;
74
75 if (Imm16 != ChunkVal)
76 break;
77 }
78
79 // Create the first MOVK instruction.
80 Insn.push_back({ AArch64::MOVKXi, Imm16,
82
83 // In case we have three instances the whole constant is now materialized
84 // and we can exit.
85 if (CountThree)
86 return true;
87
88 // Find the remaining chunk which needs to be materialized.
89 for (ShiftAmt += 16; ShiftAmt < 64; ShiftAmt += 16) {
90 Imm16 = (UImm >> ShiftAmt) & 0xFFFF;
91
92 if (Imm16 != ChunkVal)
93 break;
94 }
95 Insn.push_back({ AArch64::MOVKXi, Imm16,
97 return true;
98 }
99
100 return false;
101}
102
103/// Check whether this chunk matches the pattern '1...0...'. This pattern
104/// starts a contiguous sequence of ones if we look at the bits from the LSB
105/// towards the MSB.
106static bool isStartChunk(uint64_t Chunk) {
107 if (Chunk == 0 || Chunk == std::numeric_limits<uint64_t>::max())
108 return false;
109
110 return isMask_64(~Chunk);
111}
112
113/// Check whether this chunk matches the pattern '0...1...' This pattern
114/// ends a contiguous sequence of ones if we look at the bits from the LSB
115/// towards the MSB.
116static bool isEndChunk(uint64_t Chunk) {
117 if (Chunk == 0 || Chunk == std::numeric_limits<uint64_t>::max())
118 return false;
119
120 return isMask_64(Chunk);
121}
122
123/// Clear or set all bits in the chunk at the given index.
124static uint64_t updateImm(uint64_t Imm, unsigned Idx, bool Clear) {
125 const uint64_t Mask = 0xFFFF;
126
127 if (Clear)
128 // Clear chunk in the immediate.
129 Imm &= ~(Mask << (Idx * 16));
130 else
131 // Set all bits in the immediate for the particular chunk.
132 Imm |= Mask << (Idx * 16);
133
134 return Imm;
135}
136
137/// Check whether the constant contains a sequence of contiguous ones,
138/// which might be interrupted by one or two chunks. If so, materialize the
139/// sequence of contiguous ones with an ORR instruction.
140/// Materialize the chunks which are either interrupting the sequence or outside
141/// of the sequence with a MOVK instruction.
142///
143/// Assuming S is a chunk which starts the sequence (1...0...), E is a chunk
144/// which ends the sequence (0...1...). Then we are looking for constants which
145/// contain at least one S and E chunk.
146/// E.g. |E|A|B|S|, |A|E|B|S| or |A|B|E|S|.
147///
148/// We are also looking for constants like |S|A|B|E| where the contiguous
149/// sequence of ones wraps around the MSB into the LSB.
152 const int NotSet = -1;
153 const uint64_t Mask = 0xFFFF;
154
155 int StartIdx = NotSet;
156 int EndIdx = NotSet;
157 // Try to find the chunks which start/end a contiguous sequence of ones.
158 for (int Idx = 0; Idx < 4; ++Idx) {
159 int64_t Chunk = getChunk(UImm, Idx);
160 // Sign extend the 16-bit chunk to 64-bit.
161 Chunk = (Chunk << 48) >> 48;
162
163 if (isStartChunk(Chunk))
164 StartIdx = Idx;
165 else if (isEndChunk(Chunk))
166 EndIdx = Idx;
167 }
168
169 // Early exit in case we can't find a start/end chunk.
170 if (StartIdx == NotSet || EndIdx == NotSet)
171 return false;
172
173 // Outside of the contiguous sequence of ones everything needs to be zero.
174 uint64_t Outside = 0;
175 // Chunks between the start and end chunk need to have all their bits set.
176 uint64_t Inside = Mask;
177
178 // If our contiguous sequence of ones wraps around from the MSB into the LSB,
179 // just swap indices and pretend we are materializing a contiguous sequence
180 // of zeros surrounded by a contiguous sequence of ones.
181 if (StartIdx > EndIdx) {
182 std::swap(StartIdx, EndIdx);
183 std::swap(Outside, Inside);
184 }
185
186 uint64_t OrrImm = UImm;
187 int FirstMovkIdx = NotSet;
188 int SecondMovkIdx = NotSet;
189
190 // Find out which chunks we need to patch up to obtain a contiguous sequence
191 // of ones.
192 for (int Idx = 0; Idx < 4; ++Idx) {
193 const uint64_t Chunk = getChunk(UImm, Idx);
194
195 // Check whether we are looking at a chunk which is not part of the
196 // contiguous sequence of ones.
197 if ((Idx < StartIdx || EndIdx < Idx) && Chunk != Outside) {
198 OrrImm = updateImm(OrrImm, Idx, Outside == 0);
199
200 // Remember the index we need to patch.
201 if (FirstMovkIdx == NotSet)
202 FirstMovkIdx = Idx;
203 else
204 SecondMovkIdx = Idx;
205
206 // Check whether we are looking a chunk which is part of the contiguous
207 // sequence of ones.
208 } else if (Idx > StartIdx && Idx < EndIdx && Chunk != Inside) {
209 OrrImm = updateImm(OrrImm, Idx, Inside != Mask);
210
211 // Remember the index we need to patch.
212 if (FirstMovkIdx == NotSet)
213 FirstMovkIdx = Idx;
214 else
215 SecondMovkIdx = Idx;
216 }
217 }
218 assert(FirstMovkIdx != NotSet && "Constant materializable with single ORR!");
219
220 // Create the ORR-immediate instruction.
221 uint64_t Encoding = 0;
222 AArch64_AM::processLogicalImmediate(OrrImm, 64, Encoding);
223 Insn.push_back({ AArch64::ORRXri, 0, Encoding });
224
225 const bool SingleMovk = SecondMovkIdx == NotSet;
226 Insn.push_back({ AArch64::MOVKXi, getChunk(UImm, FirstMovkIdx),
228 FirstMovkIdx * 16) });
229
230 // Early exit in case we only need to emit a single MOVK instruction.
231 if (SingleMovk)
232 return true;
233
234 // Create the second MOVK instruction.
235 Insn.push_back({ AArch64::MOVKXi, getChunk(UImm, SecondMovkIdx),
237 SecondMovkIdx * 16) });
238
239 return true;
240}
241
243 uint64_t NumOnes = llvm::countr_one(V >> StartPosition);
244
245 uint64_t UnshiftedOnes;
246 if (NumOnes == 64) {
247 UnshiftedOnes = ~0ULL;
248 } else {
249 UnshiftedOnes = (1ULL << NumOnes) - 1;
250 }
251 return UnshiftedOnes << StartPosition;
252}
253
255 uint64_t Result = Subset;
256
257 // 64, 32, 16, 8, 4, 2
258 for (uint64_t i = 0; i < 6; ++i) {
259 uint64_t Rotation = 1ULL << (6 - i);
260 uint64_t Closure = Result | llvm::rotl<uint64_t>(Result, Rotation);
261 if (Closure != (Closure & V)) {
262 break;
263 }
264 Result = Closure;
265 }
266
267 return Result;
268}
269
270// Find the logical immediate that covers the most bits in RemainingBits,
271// allowing for additional bits to be set that were set in OriginalBits.
273 uint64_t OriginalBits) {
274 // Find the first set bit.
275 uint32_t Position = llvm::countr_zero(RemainingBits);
276
277 // Get the first run of set bits.
278 uint64_t FirstRun = GetRunOfOnesStartingAt(OriginalBits, Position);
279
280 // Replicate the run as many times as possible, as long as the bits are set in
281 // RemainingBits.
282 uint64_t MaximalImm = MaximallyReplicateSubImmediate(OriginalBits, FirstRun);
283
284 return MaximalImm;
285}
286
287static std::optional<std::pair<uint64_t, uint64_t>>
289 if (UImm == 0 || ~UImm == 0)
290 return std::nullopt;
291
292 // Make sure we don't have a run of ones split around the rotation boundary.
293 uint32_t InitialTrailingOnes = llvm::countr_one(UImm);
294 uint64_t RotatedBits = llvm::rotr<uint64_t>(UImm, InitialTrailingOnes);
295
296 // Find the largest logical immediate that fits within the full immediate.
297 uint64_t MaximalImm1 = maximalLogicalImmWithin(RotatedBits, RotatedBits);
298
299 // Remove all bits that are set by this mask.
300 uint64_t RemainingBits = RotatedBits & ~MaximalImm1;
301
302 // Find the largest logical immediate covering the remaining bits, allowing
303 // for additional bits to be set that were also set in the original immediate.
304 uint64_t MaximalImm2 = maximalLogicalImmWithin(RemainingBits, RotatedBits);
305
306 // If any bits still haven't been covered, then give up.
307 if (RemainingBits & ~MaximalImm2)
308 return std::nullopt;
309
310 // Make sure to un-rotate the immediates.
311 return std::make_pair(rotl(MaximalImm1, InitialTrailingOnes),
312 rotl(MaximalImm2, InitialTrailingOnes));
313}
314
315// Attempt to expand an immediate as the ORR of a pair of logical immediates.
318 auto MaybeDecomposition = decomposeIntoOrrOfLogicalImmediates(UImm);
319 if (MaybeDecomposition == std::nullopt)
320 return false;
321 uint64_t Imm1 = MaybeDecomposition->first;
322 uint64_t Imm2 = MaybeDecomposition->second;
323
324 uint64_t Encoding1, Encoding2;
325 bool Imm1Success = AArch64_AM::processLogicalImmediate(Imm1, 64, Encoding1);
326 bool Imm2Success = AArch64_AM::processLogicalImmediate(Imm2, 64, Encoding2);
327
328 if (Imm1Success && Imm2Success) {
329 // Create the ORR-immediate instructions.
330 Insn.push_back({AArch64::ORRXri, 0, Encoding1});
331 Insn.push_back({AArch64::ORRXri, 1, Encoding2});
332 return true;
333 }
334
335 return false;
336}
337
338// Attempt to expand an immediate as the AND of a pair of logical immediates.
339// This is done by applying DeMorgan's law, under which logical immediates
340// are closed.
343 // Apply DeMorgan's law to turn this into an ORR problem.
344 auto MaybeDecomposition = decomposeIntoOrrOfLogicalImmediates(~UImm);
345 if (MaybeDecomposition == std::nullopt)
346 return false;
347 uint64_t Imm1 = MaybeDecomposition->first;
348 uint64_t Imm2 = MaybeDecomposition->second;
349
350 uint64_t Encoding1, Encoding2;
351 bool Imm1Success = AArch64_AM::processLogicalImmediate(~Imm1, 64, Encoding1);
352 bool Imm2Success = AArch64_AM::processLogicalImmediate(~Imm2, 64, Encoding2);
353
354 if (Imm1Success && Imm2Success) {
355 // Materialize Imm1, the LHS of the AND
356 Insn.push_back({AArch64::ORRXri, 0, Encoding1});
357 // AND Imm1 with Imm2
358 Insn.push_back({AArch64::ANDXri, 1, Encoding2});
359 return true;
360 }
361
362 return false;
363}
364
365/// \brief Expand a MOVi32imm or MOVi64imm pseudo instruction to a
366/// MOVZ or MOVN of width BitSize followed by up to 3 MOVK instructions.
367static inline void expandMOVImmSimple(uint64_t Imm, unsigned BitSize,
368 unsigned OneChunks, unsigned ZeroChunks,
370 const unsigned Mask = 0xFFFF;
371
372 // Use a MOVZ or MOVN instruction to set the high bits, followed by one or
373 // more MOVK instructions to insert additional 16-bit portions into the
374 // lower bits.
375 bool isNeg = false;
376
377 // Use MOVN to materialize the high bits if we have more all one chunks
378 // than all zero chunks.
379 if (OneChunks > ZeroChunks) {
380 isNeg = true;
381 Imm = ~Imm;
382 }
383
384 unsigned FirstOpc;
385 if (BitSize == 32) {
386 Imm &= (1LL << 32) - 1;
387 FirstOpc = (isNeg ? AArch64::MOVNWi : AArch64::MOVZWi);
388 } else {
389 FirstOpc = (isNeg ? AArch64::MOVNXi : AArch64::MOVZXi);
390 }
391 unsigned Shift = 0; // LSL amount for high bits with MOVZ/MOVN
392 unsigned LastShift = 0; // LSL amount for last MOVK
393 if (Imm != 0) {
394 unsigned LZ = llvm::countl_zero(Imm);
395 unsigned TZ = llvm::countr_zero(Imm);
396 Shift = (TZ / 16) * 16;
397 LastShift = ((63 - LZ) / 16) * 16;
398 }
399 unsigned Imm16 = (Imm >> Shift) & Mask;
400
401 Insn.push_back({ FirstOpc, Imm16,
403
404 if (Shift == LastShift)
405 return;
406
407 // If a MOVN was used for the high bits of a negative value, flip the rest
408 // of the bits back for use with MOVK.
409 if (isNeg)
410 Imm = ~Imm;
411
412 unsigned Opc = (BitSize == 32 ? AArch64::MOVKWi : AArch64::MOVKXi);
413 while (Shift < LastShift) {
414 Shift += 16;
415 Imm16 = (Imm >> Shift) & Mask;
416 if (Imm16 == (isNeg ? Mask : 0))
417 continue; // This 16-bit portion is already set correctly.
418
419 Insn.push_back({ Opc, Imm16,
421 }
422}
423
424/// Expand a MOVi32imm or MOVi64imm pseudo instruction to one or more
425/// real move-immediate instructions to synthesize the immediate.
426void AArch64_IMM::expandMOVImm(uint64_t Imm, unsigned BitSize,
428 const unsigned Mask = 0xFFFF;
429
430 // Scan the immediate and count the number of 16-bit chunks which are either
431 // all ones or all zeros.
432 unsigned OneChunks = 0;
433 unsigned ZeroChunks = 0;
434 for (unsigned Shift = 0; Shift < BitSize; Shift += 16) {
435 const unsigned Chunk = (Imm >> Shift) & Mask;
436 if (Chunk == Mask)
437 OneChunks++;
438 else if (Chunk == 0)
439 ZeroChunks++;
440 }
441
442 // Prefer MOVZ/MOVN over ORR because of the rules for the "mov" alias.
443 if ((BitSize / 16) - OneChunks <= 1 || (BitSize / 16) - ZeroChunks <= 1) {
444 expandMOVImmSimple(Imm, BitSize, OneChunks, ZeroChunks, Insn);
445 return;
446 }
447
448 // Try a single ORR.
449 uint64_t UImm = Imm << (64 - BitSize) >> (64 - BitSize);
450 uint64_t Encoding;
451 if (AArch64_AM::processLogicalImmediate(UImm, BitSize, Encoding)) {
452 unsigned Opc = (BitSize == 32 ? AArch64::ORRWri : AArch64::ORRXri);
453 Insn.push_back({ Opc, 0, Encoding });
454 return;
455 }
456
457 // One to up three instruction sequences.
458 //
459 // Prefer MOVZ/MOVN followed by MOVK; it's more readable, and possibly the
460 // fastest sequence with fast literal generation.
461 if (OneChunks >= (BitSize / 16) - 2 || ZeroChunks >= (BitSize / 16) - 2) {
462 expandMOVImmSimple(Imm, BitSize, OneChunks, ZeroChunks, Insn);
463 return;
464 }
465
466 assert(BitSize == 64 && "All 32-bit immediates can be expanded with a"
467 "MOVZ/MOVK pair");
468
469 // Try other two-instruction sequences.
470
471 // 64-bit ORR followed by MOVK.
472 // We try to construct the ORR immediate in three different ways: either we
473 // zero out the chunk which will be replaced, we fill the chunk which will
474 // be replaced with ones, or we take the bit pattern from the other half of
475 // the 64-bit immediate. This is comprehensive because of the way ORR
476 // immediates are constructed.
477 for (unsigned Shift = 0; Shift < BitSize; Shift += 16) {
478 uint64_t ShiftedMask = (0xFFFFULL << Shift);
479 uint64_t ZeroChunk = UImm & ~ShiftedMask;
480 uint64_t OneChunk = UImm | ShiftedMask;
481 uint64_t RotatedImm = (UImm << 32) | (UImm >> 32);
482 uint64_t ReplicateChunk = ZeroChunk | (RotatedImm & ShiftedMask);
483 if (AArch64_AM::processLogicalImmediate(ZeroChunk, BitSize, Encoding) ||
484 AArch64_AM::processLogicalImmediate(OneChunk, BitSize, Encoding) ||
485 AArch64_AM::processLogicalImmediate(ReplicateChunk, BitSize,
486 Encoding)) {
487 // Create the ORR-immediate instruction.
488 Insn.push_back({ AArch64::ORRXri, 0, Encoding });
489
490 // Create the MOVK instruction.
491 const unsigned Imm16 = getChunk(UImm, Shift / 16);
492 Insn.push_back({ AArch64::MOVKXi, Imm16,
494 return;
495 }
496 }
497
498 // Attempt to use a sequence of two ORR-immediate instructions.
500 return;
501
502 // Attempt to use a sequence of ORR-immediate followed by AND-immediate.
504 return;
505
506 // FIXME: Add more two-instruction sequences.
507
508 // Three instruction sequences.
509 //
510 // Prefer MOVZ/MOVN followed by two MOVK; it's more readable, and possibly
511 // the fastest sequence with fast literal generation. (If neither MOVK is
512 // part of a fast literal generation pair, it could be slower than the
513 // four-instruction sequence, but we won't worry about that for now.)
514 if (OneChunks || ZeroChunks) {
515 expandMOVImmSimple(Imm, BitSize, OneChunks, ZeroChunks, Insn);
516 return;
517 }
518
519 // Check for identical 16-bit chunks within the constant and if so materialize
520 // them with a single ORR instruction. The remaining one or two 16-bit chunks
521 // will be materialized with MOVK instructions.
522 if (BitSize == 64 && tryToreplicateChunks(UImm, Insn))
523 return;
524
525 // Check whether the constant contains a sequence of contiguous ones, which
526 // might be interrupted by one or two chunks. If so, materialize the sequence
527 // of contiguous ones with an ORR instruction. Materialize the chunks which
528 // are either interrupting the sequence or outside of the sequence with a
529 // MOVK instruction.
530 if (BitSize == 64 && trySequenceOfOnes(UImm, Insn))
531 return;
532
533 // We found no possible two or three instruction sequence; use the general
534 // four-instruction sequence.
535 expandMOVImmSimple(Imm, BitSize, OneChunks, ZeroChunks, Insn);
536}
static uint64_t GetRunOfOnesStartingAt(uint64_t V, uint64_t StartPosition)
static void expandMOVImmSimple(uint64_t Imm, unsigned BitSize, unsigned OneChunks, unsigned ZeroChunks, SmallVectorImpl< ImmInsnModel > &Insn)
Expand a MOVi32imm or MOVi64imm pseudo instruction to a MOVZ or MOVN of width BitSize followed by up ...
static uint64_t updateImm(uint64_t Imm, unsigned Idx, bool Clear)
Clear or set all bits in the chunk at the given index.
static bool canUseOrr(uint64_t Chunk, uint64_t &Encoding)
Check whether the given 16-bit chunk replicated to full 64-bit width can be materialized with an ORR ...
static bool tryToreplicateChunks(uint64_t UImm, SmallVectorImpl< ImmInsnModel > &Insn)
Check for identical 16-bit chunks within the constant and if so materialize them with a single ORR in...
static bool trySequenceOfOnes(uint64_t UImm, SmallVectorImpl< ImmInsnModel > &Insn)
Check whether the constant contains a sequence of contiguous ones, which might be interrupted by one ...
static uint64_t MaximallyReplicateSubImmediate(uint64_t V, uint64_t Subset)
static bool tryAndOfLogicalImmediates(uint64_t UImm, SmallVectorImpl< ImmInsnModel > &Insn)
static uint64_t getChunk(uint64_t Imm, unsigned ChunkIdx)
Helper function which extracts the specified 16-bit chunk from a 64-bit value.
static uint64_t maximalLogicalImmWithin(uint64_t RemainingBits, uint64_t OriginalBits)
static bool isStartChunk(uint64_t Chunk)
Check whether this chunk matches the pattern '1...0...'.
static bool isEndChunk(uint64_t Chunk)
Check whether this chunk matches the pattern '0...1...' This pattern ends a contiguous sequence of on...
static bool tryOrrOfLogicalImmediates(uint64_t UImm, SmallVectorImpl< ImmInsnModel > &Insn)
static std::optional< std::pair< uint64_t, uint64_t > > decomposeIntoOrrOfLogicalImmediates(uint64_t UImm)
SmallVector< AArch64_IMM::ImmInsnModel, 4 > Insn
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:577
static bool processLogicalImmediate(uint64_t Imm, unsigned RegSize, uint64_t &Encoding)
processLogicalImmediate - Determine if an immediate value can be encoded as the immediate operand of ...
static unsigned getShifterImm(AArch64_AM::ShiftExtendType ST, unsigned Imm)
getShifterImm - Encode the shift type and amount: imm: 6-bit shift amount shifter: 000 ==> lsl 001 ==...
void expandMOVImm(uint64_t Imm, unsigned BitSize, SmallVectorImpl< ImmInsnModel > &Insn)
Expand a MOVi32imm or MOVi64imm pseudo instruction to one or more real move-immediate instructions to...
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
int countr_one(T Value)
Count the number of ones from the least significant bit to the first zero bit.
Definition: bit.h:271
int countr_zero(T Val)
Count number of 0's from the least significant bit to the most stopping at the first 1.
Definition: bit.h:179
int countl_zero(T Val)
Count number of 0's from the most significant bit to the least stopping at the first 1.
Definition: bit.h:245
constexpr bool isMask_64(uint64_t Value)
Return true if the argument is a non-empty sequence of ones starting at the least significant bit wit...
Definition: MathExtras.h:274
constexpr T rotl(T V, int R)
Definition: bit.h:358
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Definition: BitVector.h:860