LLVM 17.0.0git
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AArch64_AM - AArch64 Addressing Mode Stuff. More...
Enumerations | |
enum | ShiftExtendType { InvalidShiftExtend = -1 , LSL = 0 , LSR , ASR , ROR , MSL , UXTB , UXTH , UXTW , UXTX , SXTB , SXTH , SXTW , SXTX } |
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static const char * | getShiftExtendName (AArch64_AM::ShiftExtendType ST) |
getShiftName - Get the string encoding for the shift type. | |
static AArch64_AM::ShiftExtendType | getShiftType (unsigned Imm) |
getShiftType - Extract the shift type. | |
static unsigned | getShiftValue (unsigned Imm) |
getShiftValue - Extract the shift value. | |
static unsigned | getShifterImm (AArch64_AM::ShiftExtendType ST, unsigned Imm) |
getShifterImm - Encode the shift type and amount: imm: 6-bit shift amount shifter: 000 ==> lsl 001 ==> lsr 010 ==> asr 011 ==> ror 100 ==> msl {8-6} = shifter {5-0} = imm | |
static unsigned | getArithShiftValue (unsigned Imm) |
getArithShiftValue - get the arithmetic shift value. | |
static AArch64_AM::ShiftExtendType | getExtendType (unsigned Imm) |
getExtendType - Extract the extend type for operands of arithmetic ops. | |
static AArch64_AM::ShiftExtendType | getArithExtendType (unsigned Imm) |
unsigned | getExtendEncoding (AArch64_AM::ShiftExtendType ET) |
Mapping from extend bits to required operation: shifter: 000 ==> uxtb 001 ==> uxth 010 ==> uxtw 011 ==> uxtx 100 ==> sxtb 101 ==> sxth 110 ==> sxtw 111 ==> sxtx. | |
static unsigned | getArithExtendImm (AArch64_AM::ShiftExtendType ET, unsigned Imm) |
getArithExtendImm - Encode the extend type and shift amount for an arithmetic instruction: imm: 3-bit extend amount {5-3} = shifter {2-0} = imm3 | |
static bool | getMemDoShift (unsigned Imm) |
getMemDoShift - Extract the "do shift" flag value for load/store instructions. | |
static AArch64_AM::ShiftExtendType | getMemExtendType (unsigned Imm) |
getExtendType - Extract the extend type for the offset operand of loads/stores. | |
static unsigned | getMemExtendImm (AArch64_AM::ShiftExtendType ET, bool DoShift) |
getExtendImm - Encode the extend type and amount for a load/store inst: doshift: should the offset be scaled by the access size shifter: 000 ==> uxtb 001 ==> uxth 010 ==> uxtw 011 ==> uxtx 100 ==> sxtb 101 ==> sxth 110 ==> sxtw 111 ==> sxtx {3-1} = shifter {0} = doshift | |
static uint64_t | ror (uint64_t elt, unsigned size) |
static bool | processLogicalImmediate (uint64_t Imm, unsigned RegSize, uint64_t &Encoding) |
processLogicalImmediate - Determine if an immediate value can be encoded as the immediate operand of a logical instruction for the given register size. | |
static bool | isLogicalImmediate (uint64_t imm, unsigned regSize) |
isLogicalImmediate - Return true if the immediate is valid for a logical immediate instruction of the given register size. | |
static uint64_t | encodeLogicalImmediate (uint64_t imm, unsigned regSize) |
encodeLogicalImmediate - Return the encoded immediate value for a logical immediate instruction of the given register size. | |
static uint64_t | decodeLogicalImmediate (uint64_t val, unsigned regSize) |
decodeLogicalImmediate - Decode a logical immediate value in the form "N:immr:imms" (where the immr and imms fields are each 6 bits) into the integer value it represents with regSize bits. | |
static bool | isValidDecodeLogicalImmediate (uint64_t val, unsigned regSize) |
isValidDecodeLogicalImmediate - Check to see if the logical immediate value in the form "N:immr:imms" (where the immr and imms fields are each 6 bits) is a valid encoding for an integer value with regSize bits. | |
static float | getFPImmFloat (unsigned Imm) |
static int | getFP16Imm (const APInt &Imm) |
getFP16Imm - Return an 8-bit floating-point version of the 16-bit floating-point value. | |
static int | getFP16Imm (const APFloat &FPImm) |
static int | getFP32Imm (const APInt &Imm) |
getFP32Imm - Return an 8-bit floating-point version of the 32-bit floating-point value. | |
static int | getFP32Imm (const APFloat &FPImm) |
static int | getFP64Imm (const APInt &Imm) |
getFP64Imm - Return an 8-bit floating-point version of the 64-bit floating-point value. | |
static int | getFP64Imm (const APFloat &FPImm) |
static bool | isAdvSIMDModImmType1 (uint64_t Imm) |
static uint8_t | encodeAdvSIMDModImmType1 (uint64_t Imm) |
static uint64_t | decodeAdvSIMDModImmType1 (uint8_t Imm) |
static bool | isAdvSIMDModImmType2 (uint64_t Imm) |
static uint8_t | encodeAdvSIMDModImmType2 (uint64_t Imm) |
static uint64_t | decodeAdvSIMDModImmType2 (uint8_t Imm) |
static bool | isAdvSIMDModImmType3 (uint64_t Imm) |
static uint8_t | encodeAdvSIMDModImmType3 (uint64_t Imm) |
static uint64_t | decodeAdvSIMDModImmType3 (uint8_t Imm) |
static bool | isAdvSIMDModImmType4 (uint64_t Imm) |
static uint8_t | encodeAdvSIMDModImmType4 (uint64_t Imm) |
static uint64_t | decodeAdvSIMDModImmType4 (uint8_t Imm) |
static bool | isAdvSIMDModImmType5 (uint64_t Imm) |
static uint8_t | encodeAdvSIMDModImmType5 (uint64_t Imm) |
static uint64_t | decodeAdvSIMDModImmType5 (uint8_t Imm) |
static bool | isAdvSIMDModImmType6 (uint64_t Imm) |
static uint8_t | encodeAdvSIMDModImmType6 (uint64_t Imm) |
static uint64_t | decodeAdvSIMDModImmType6 (uint8_t Imm) |
static bool | isAdvSIMDModImmType7 (uint64_t Imm) |
static uint8_t | encodeAdvSIMDModImmType7 (uint64_t Imm) |
static uint64_t | decodeAdvSIMDModImmType7 (uint8_t Imm) |
static bool | isAdvSIMDModImmType8 (uint64_t Imm) |
static uint64_t | decodeAdvSIMDModImmType8 (uint8_t Imm) |
static uint8_t | encodeAdvSIMDModImmType8 (uint64_t Imm) |
static bool | isAdvSIMDModImmType9 (uint64_t Imm) |
static uint8_t | encodeAdvSIMDModImmType9 (uint64_t Imm) |
static uint64_t | decodeAdvSIMDModImmType9 (uint8_t Imm) |
static bool | isAdvSIMDModImmType10 (uint64_t Imm) |
static uint8_t | encodeAdvSIMDModImmType10 (uint64_t Imm) |
static uint64_t | decodeAdvSIMDModImmType10 (uint8_t Imm) |
static bool | isAdvSIMDModImmType11 (uint64_t Imm) |
static uint8_t | encodeAdvSIMDModImmType11 (uint64_t Imm) |
static uint64_t | decodeAdvSIMDModImmType11 (uint8_t Imm) |
static bool | isAdvSIMDModImmType12 (uint64_t Imm) |
static uint8_t | encodeAdvSIMDModImmType12 (uint64_t Imm) |
static uint64_t | decodeAdvSIMDModImmType12 (uint8_t Imm) |
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static bool | isSVEMaskOfIdenticalElements (int64_t Imm) |
Returns true if Imm is the concatenation of a repeating pattern of type T. | |
template<typename T > | |
static bool | isSVECpyImm (int64_t Imm) |
Returns true if Imm is valid for CPY/DUP. | |
template<typename T > | |
static bool | isSVEAddSubImm (int64_t Imm) |
Returns true if Imm is valid for ADD/SUB. | |
static bool | isSVEMoveMaskPreferredLogicalImmediate (int64_t Imm) |
Return true if Imm is valid for DUPM and has no single CPY/DUP equivalent. | |
static bool | isAnyMOVZMovAlias (uint64_t Value, int RegWidth) |
static bool | isMOVZMovAlias (uint64_t Value, int Shift, int RegWidth) |
static bool | isMOVNMovAlias (uint64_t Value, int Shift, int RegWidth) |
static bool | isAnyMOVWMovAlias (uint64_t Value, int RegWidth) |
AArch64_AM - AArch64 Addressing Mode Stuff.
Enumerator | |
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InvalidShiftExtend | |
LSL | |
LSR | |
ASR | |
ROR | |
MSL | |
UXTB | |
UXTH | |
UXTW | |
UXTX | |
SXTB | |
SXTH | |
SXTW | |
SXTX |
Definition at line 33 of file AArch64AddressingModes.h.
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Definition at line 461 of file AArch64AddressingModes.h.
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Definition at line 642 of file AArch64AddressingModes.h.
Referenced by llvm::AArch64InstPrinter::printSIMDType10Operand().
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Definition at line 691 of file AArch64AddressingModes.h.
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Definition at line 740 of file AArch64AddressingModes.h.
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Definition at line 476 of file AArch64AddressingModes.h.
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Definition at line 491 of file AArch64AddressingModes.h.
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Definition at line 506 of file AArch64AddressingModes.h.
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Definition at line 522 of file AArch64AddressingModes.h.
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Definition at line 538 of file AArch64AddressingModes.h.
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Definition at line 553 of file AArch64AddressingModes.h.
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Definition at line 564 of file AArch64AddressingModes.h.
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Definition at line 584 of file AArch64AddressingModes.h.
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decodeLogicalImmediate - Decode a logical immediate value in the form "N:immr:imms" (where the immr and imms fields are each 6 bits) into the integer value it represents with regSize bits.
Definition at line 294 of file AArch64AddressingModes.h.
References assert(), llvm::countl_zero(), N, ror(), and llvm::size().
Referenced by llvm::AArch64InstrInfo::analyzeCompare(), getUsefulBitsFromAndWithImmediate(), llvm::AArch64InstrInfo::optimizeCondBranch(), llvm::AArch64InstPrinter::printInst(), llvm::AArch64InstPrinter::printLogicalImm(), and llvm::AArch64InstPrinter::printSVELogicalImm().
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Definition at line 457 of file AArch64AddressingModes.h.
Referenced by tryAdvSIMDModImm32().
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Definition at line 614 of file AArch64AddressingModes.h.
Referenced by tryAdvSIMDModImm64().
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Definition at line 663 of file AArch64AddressingModes.h.
Referenced by tryAdvSIMDModImmFP().
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Definition at line 712 of file AArch64AddressingModes.h.
Referenced by tryAdvSIMDModImmFP().
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Definition at line 472 of file AArch64AddressingModes.h.
Referenced by tryAdvSIMDModImm32().
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Definition at line 487 of file AArch64AddressingModes.h.
Referenced by tryAdvSIMDModImm32().
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Definition at line 502 of file AArch64AddressingModes.h.
Referenced by tryAdvSIMDModImm32().
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Definition at line 518 of file AArch64AddressingModes.h.
Referenced by tryAdvSIMDModImm16().
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Definition at line 534 of file AArch64AddressingModes.h.
Referenced by tryAdvSIMDModImm16().
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Definition at line 549 of file AArch64AddressingModes.h.
Referenced by tryAdvSIMDModImm321s().
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Definition at line 569 of file AArch64AddressingModes.h.
Referenced by tryAdvSIMDModImm321s().
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Definition at line 580 of file AArch64AddressingModes.h.
Referenced by tryAdvSIMDModImm8().
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encodeLogicalImmediate - Return the encoded immediate value for a logical immediate instruction of the given register size.
Definition at line 283 of file AArch64AddressingModes.h.
References assert(), and processLogicalImmediate().
Referenced by llvm::AArch64FrameLowering::emitPrologue(), llvm::AArch64InstrInfo::insertSelect(), and optimizeLogicalImm().
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getArithExtendImm - Encode the extend type and shift amount for an arithmetic instruction: imm: 3-bit extend amount {5-3} = shifter {2-0} = imm3
Definition at line 171 of file AArch64AddressingModes.h.
References assert(), and getExtendEncoding().
Referenced by llvm::AArch64FrameLowering::emitPrologue().
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Definition at line 139 of file AArch64AddressingModes.h.
References getExtendType().
Referenced by llvm::AArch64InstrInfo::isFalkorShiftExtFast(), and llvm::AArch64InstPrinter::printArithExtend().
getArithShiftValue - get the arithmetic shift value.
Definition at line 119 of file AArch64AddressingModes.h.
Referenced by llvm::AArch64InstrInfo::isFalkorShiftExtFast(), and llvm::AArch64InstPrinter::printArithExtend().
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Mapping from extend bits to required operation: shifter: 000 ==> uxtb 001 ==> uxth 010 ==> uxtw 011 ==> uxtx 100 ==> sxtb 101 ==> sxth 110 ==> sxtw 111 ==> sxtx.
Definition at line 152 of file AArch64AddressingModes.h.
References llvm_unreachable, SXTB, SXTH, SXTW, SXTX, UXTB, UXTH, UXTW, and UXTX.
Referenced by getArithExtendImm(), and getMemExtendImm().
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getExtendType - Extract the extend type for operands of arithmetic ops.
Definition at line 124 of file AArch64AddressingModes.h.
References assert(), llvm_unreachable, SXTB, SXTH, SXTW, SXTX, UXTB, UXTH, UXTW, and UXTX.
Referenced by getArithExtendType(), and getMemExtendType().
Definition at line 387 of file AArch64AddressingModes.h.
References llvm::APFloat::bitcastToAPInt(), and getFP16Imm().
getFP16Imm - Return an 8-bit floating-point version of the 16-bit floating-point value.
If the value cannot be represented as an 8-bit floating-point value, then return -1.
Definition at line 368 of file AArch64AddressingModes.h.
Referenced by getFP16Imm(), and llvm::AArch64TargetLowering::isFPImmLegal().
Definition at line 415 of file AArch64AddressingModes.h.
References llvm::APFloat::bitcastToAPInt(), and getFP32Imm().
getFP32Imm - Return an 8-bit floating-point version of the 32-bit floating-point value.
If the value cannot be represented as an 8-bit floating-point value, then return -1.
Definition at line 394 of file AArch64AddressingModes.h.
Referenced by getFP32Imm(), and llvm::AArch64TargetLowering::isFPImmLegal().
Definition at line 443 of file AArch64AddressingModes.h.
References llvm::APFloat::bitcastToAPInt(), and getFP64Imm().
getFP64Imm - Return an 8-bit floating-point version of the 64-bit floating-point value.
If the value cannot be represented as an 8-bit floating-point value, then return -1.
Definition at line 422 of file AArch64AddressingModes.h.
Referenced by getFP64Imm(), and llvm::AArch64TargetLowering::isFPImmLegal().
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Definition at line 344 of file AArch64AddressingModes.h.
References I.
Referenced by llvm::AArch64InstPrinter::printFPImmOperand().
getMemDoShift - Extract the "do shift" flag value for load/store instructions.
Definition at line 179 of file AArch64AddressingModes.h.
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getExtendImm - Encode the extend type and amount for a load/store inst: doshift: should the offset be scaled by the access size shifter: 000 ==> uxtb 001 ==> uxth 010 ==> uxtw 011 ==> uxtx 100 ==> sxtb 101 ==> sxth 110 ==> sxtw 111 ==> sxtx {3-1} = shifter {0} = doshift
Definition at line 201 of file AArch64AddressingModes.h.
References getExtendEncoding().
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getExtendType - Extract the extend type for the offset operand of loads/stores.
Definition at line 185 of file AArch64AddressingModes.h.
References getExtendType().
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getShifterImm - Encode the shift type and amount: imm: 6-bit shift amount shifter: 000 ==> lsl 001 ==> lsr 010 ==> asr 011 ==> ror 100 ==> msl {8-6} = shifter {5-0} = imm
Definition at line 99 of file AArch64AddressingModes.h.
References ASR, assert(), llvm_unreachable, LSL, LSR, MSL, and ROR.
Referenced by llvm::AArch64InstrInfo::copyPhysReg(), emitFrameOffsetAdj(), llvm::AArch64FrameLowering::emitPrologue(), llvm::AArch64_IMM::expandMOVImm(), expandMOVImmSimple(), isWorthFoldingIntoOrrWithShift(), llvm::AArch64RegisterInfo::materializeFrameBaseRegister(), tryOrrWithShift(), trySequenceOfOnes(), and tryToreplicateChunks().
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getShiftName - Get the string encoding for the shift type.
Definition at line 53 of file AArch64AddressingModes.h.
References ASR, llvm_unreachable, LSL, LSR, MSL, ROR, SXTB, SXTH, SXTW, SXTX, UXTB, UXTH, UXTW, and UXTX.
Referenced by llvm::AArch64InstPrinter::printArithExtend(), and llvm::AArch64InstPrinter::printShifter().
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getShiftType - Extract the shift type.
Definition at line 74 of file AArch64AddressingModes.h.
References ASR, InvalidShiftExtend, LSL, LSR, MSL, and ROR.
Referenced by getUsefulBitsFromOrWithShiftedReg(), llvm::AArch64InstrInfo::isFalkorShiftExtFast(), llvm::AArch64InstPrinter::printImm8OptLsl(), and llvm::AArch64InstPrinter::printShifter().
getShiftValue - Extract the shift value.
Definition at line 86 of file AArch64AddressingModes.h.
Referenced by getUsefulBitsFromOrWithShiftedReg(), llvm::AArch64InstrInfo::isFalkorShiftExtFast(), llvm::AArch64InstPrinter::printAddSubImm(), llvm::AArch64InstPrinter::printImm8OptLsl(), and llvm::AArch64InstPrinter::printShifter().
Definition at line 452 of file AArch64AddressingModes.h.
Referenced by tryAdvSIMDModImm32().
Definition at line 594 of file AArch64AddressingModes.h.
Referenced by tryAdvSIMDModImm64().
Definition at line 656 of file AArch64AddressingModes.h.
Referenced by tryAdvSIMDModImmFP().
Definition at line 706 of file AArch64AddressingModes.h.
Referenced by tryAdvSIMDModImmFP().
Definition at line 467 of file AArch64AddressingModes.h.
Referenced by tryAdvSIMDModImm32().
Definition at line 482 of file AArch64AddressingModes.h.
Referenced by tryAdvSIMDModImm32().
Definition at line 497 of file AArch64AddressingModes.h.
Referenced by tryAdvSIMDModImm32().
Definition at line 512 of file AArch64AddressingModes.h.
Referenced by tryAdvSIMDModImm16().
Definition at line 528 of file AArch64AddressingModes.h.
Referenced by tryAdvSIMDModImm16().
Definition at line 544 of file AArch64AddressingModes.h.
Referenced by tryAdvSIMDModImm321s().
Definition at line 559 of file AArch64AddressingModes.h.
Referenced by tryAdvSIMDModImm321s().
Definition at line 574 of file AArch64AddressingModes.h.
Referenced by tryAdvSIMDModImm8().
Definition at line 841 of file AArch64AddressingModes.h.
References isAnyMOVZMovAlias().
Referenced by llvm::AArch64InstPrinter::printInst().
Definition at line 810 of file AArch64AddressingModes.h.
Referenced by isAnyMOVWMovAlias(), and isMOVNMovAlias().
isLogicalImmediate - Return true if the immediate is valid for a logical immediate instruction of the given register size.
Return false otherwise.
Definition at line 276 of file AArch64AddressingModes.h.
References processLogicalImmediate().
Referenced by llvm::AArch64TTIImpl::getIntImmCost(), isSVEMoveMaskPreferredLogicalImmediate(), optimizeLogicalImm(), llvm::AArch64TargetLowering::shouldConvertConstantLoadToIntImm(), and tryBitfieldInsertOpFromOrAndImm().
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Definition at line 829 of file AArch64AddressingModes.h.
References isAnyMOVZMovAlias(), and isMOVZMovAlias().
Referenced by llvm::AArch64InstPrinter::printInst().
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Definition at line 818 of file AArch64AddressingModes.h.
Referenced by isMOVNMovAlias(), and llvm::AArch64InstPrinter::printInst().
Returns true if Imm is valid for ADD/SUB.
Definition at line 786 of file AArch64AddressingModes.h.
References value.
Returns true if Imm is valid for CPY/DUP.
Definition at line 763 of file AArch64AddressingModes.h.
References llvm::max(), and T.
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Returns true if Imm is the concatenation of a repeating pattern of type T.
Definition at line 756 of file AArch64AddressingModes.h.
References llvm::all_equal(), llvm::bit_cast(), and T.
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Return true if Imm is valid for DUPM and has no single CPY/DUP equivalent.
Definition at line 793 of file AArch64AddressingModes.h.
References B, H, and isLogicalImmediate().
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isValidDecodeLogicalImmediate - Check to see if the logical immediate value in the form "N:immr:imms" (where the immr and imms fields are each 6 bits) is a valid encoding for an integer value with regSize bits.
Definition at line 322 of file AArch64AddressingModes.h.
References llvm::countl_zero(), N, and llvm::size().
Referenced by DecodeLogicalImmInstruction(), and DecodeSVELogicalImmInstruction().
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processLogicalImmediate - Determine if an immediate value can be encoded as the immediate operand of a logical instruction for the given register size.
If so, return true with "encoding" set to the encoded value in the form N:immr:imms.
Definition at line 214 of file AArch64AddressingModes.h.
References assert(), llvm::countl_one(), llvm::countr_one(), llvm::countr_zero(), I, llvm::isShiftedMask_64(), N, RegSize, and Size.
Referenced by canBeExpandedToORR(), canUseOrr(), encodeLogicalImmediate(), llvm::AArch64_IMM::expandMOVImm(), isLogicalImmediate(), tryAndOfLogicalImmediates(), tryOrrOfLogicalImmediates(), and trySequenceOfOnes().
Definition at line 206 of file AArch64AddressingModes.h.
References llvm::size().
Referenced by decodeLogicalImmediate().