Shared types for co-execution modeling used by GCNHazardRecognizer and the schedulers. More...

#include "SIDefines.h"
#include "SIInstrInfo.h"
#include "llvm/ADT/BitmaskEnum.h"
#include "llvm/ADT/StringRef.h"
#include <cassert>
#include <cstdint>
#include <optional>

Classes
struct	llvm::AMDGPU::CoExecSlotInfo
	Per-slot info: which instruction classes may co-execute here. More...
struct	llvm::AMDGPU::CoExecInfo
	Co-execution characteristics for a multi-cycle instruction. More...

Namespaces
namespace	llvm
	This is an optimization pass for GlobalISel generic memory operations.
namespace	llvm::AMDGPU

Typedefs
using	llvm::AMDGPU::CoExecMaskT = CoExecMask

Enumerations
enum class	llvm::AMDGPU::CoExecMask : uint16_t { llvm::AMDGPU::None = 0 , llvm::AMDGPU::CTRL = 1 << 0 , llvm::AMDGPU::VALU = 1 << 1 , llvm::AMDGPU::TRANS = 1 << 2 , llvm::AMDGPU::SALU = 1 << 3 , llvm::AMDGPU::DS = 1 << 4 , llvm::AMDGPU::VMEM = 1 << 5 , llvm::AMDGPU::SMEM = 1 << 6 , llvm::AMDGPU::WMMA = 1 << 7 , llvm::AMDGPU::All = 0xFFFF , llvm::AMDGPU::MEM = DS \| VMEM \| SMEM , llvm::AMDGPU::StageE0 = CTRL , llvm::AMDGPU::StageE = CTRL \| SALU \| MEM , llvm::AMDGPU::StageI = CTRL \| SALU \| MEM \| VALU \| TRANS , llvm::AMDGPU::StageIS = StageI \| WMMA , llvm::AMDGPU::StageV = CTRL \| SALU \| MEM \| WMMA , llvm::AMDGPU::StageTR = All & ~TRANS }
	Bitmask for instruction types allowed to co-execute at a stage. More...
enum class	llvm::AMDGPU::InstructionFlavor : uint8_t { llvm::AMDGPU::WMMA , llvm::AMDGPU::SingleCycleVALU , llvm::AMDGPU::TRANS , llvm::AMDGPU::MultiCycleVALU , llvm::AMDGPU::VMEM , llvm::AMDGPU::SMEM , llvm::AMDGPU::DS , llvm::AMDGPU::SALU , llvm::AMDGPU::DMA , llvm::AMDGPU::Fence , llvm::AMDGPU::Other , llvm::AMDGPU::NUM_FLAVORS }
	Classification of instructions by execution characteristics. More...
enum class	llvm::AMDGPU::CoExecStageType : uint8_t { llvm::AMDGPU::NONE = 0 , llvm::AMDGPU::E0 , llvm::AMDGPU::E , llvm::AMDGPU::I , llvm::AMDGPU::IS , llvm::AMDGPU::V , llvm::AMDGPU::TR }
	Stage type for co-execution (for annotation/display). More...

Functions
constexpr StringRef	llvm::AMDGPU::getFlavorName (InstructionFlavor F)
InstructionFlavor	llvm::AMDGPU::classifyFlavor (const MachineInstr &MI, const SIInstrInfo &SII)
	Classify `MI` into the execution flavor that drives both the scheduler's slot preferences and the hazard recognizer's co-execution masks.
constexpr CoExecMaskT	llvm::AMDGPU::getCoExecMask (InstructionFlavor F)
	Map a flavor to the co-execution class it occupies in a window slot.
const char *	llvm::AMDGPU::getStageTypeName (CoExecStageType T)
const char *	llvm::AMDGPU::getCoExecMaskName (CoExecMaskT Mask)
	Return a human-readable name for a mask holding a single instruction class, as produced by getCoExecMask().
CoExecInfo	llvm::AMDGPU::getCoExecInfo (const MachineInstr &MI, const SIInstrInfo &TII)
	Get co-execution info for a WMMA instruction, selecting the per-cycle slot pattern from the opcode (and operand formats for the F8F6F4 variants).

Variables
constexpr unsigned	llvm::AMDGPU::MaxCoExecStages = 32
	Max stages: INT8 16x16x64 = 17 cycles, round up for safety.

Detailed Description

Shared types for co-execution modeling used by GCNHazardRecognizer and the schedulers.

Multi-cycle instructions (WMMA, TRANS, etc.) have execution windows where other instruction types can co-execute. For WMMA, slot patterns depend on the variant:

E0 (Issue): Control instructions only (s_delay_alu, s_set_vgpr_msb) E (External): Memory and SALU can co-execute, no VALU I (Internal): VALU, TRANS, memory, and SALU can all co-execute V (Vacant): Memory/SALU/next-WMMA ok, NO VALU/TRANS

Definition in file AMDGPUCoExecInfo.h.

Classes

Namespaces

Typedefs

Enumerations

Functions

Variables

Detailed Description