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25 #define DEBUG_TYPE "arc-branch-finalize"
47 return "ARC Branch Finalization Pass";
63 "ARC finalize branches",
false,
false)
96 return !(
MI->getOpcode() != ARC::BRcc_rr_p &&
97 MI->getOpcode() != ARC::BRcc_ru6_p);
102 if (
MI->getOpcode() == ARC::BRcc_rr_p)
104 return ARC::BRcc_ru6;
109 if (
MI->getOpcode() == ARC::BRcc_rr_p)
122 .
add(
MI->getOperand(2))
124 MI->eraseFromParent();
126 replaceWithCmpBcc(
MI);
130 void ARCBranchFinalize::replaceWithCmpBcc(
MachineInstr *
MI)
const {
136 .
add(
MI->getOperand(2));
139 .
addImm(
MI->getOperand(3).getImm());
140 MI->eraseFromParent();
146 std::vector<MachineInstr *> Branches;
147 bool Changed =
false;
148 unsigned MaxSize = 0;
150 std::map<MachineBasicBlock *, unsigned> BlockToPCMap;
151 std::vector<std::pair<MachineInstr *, unsigned>> BranchToPCList;
154 for (
auto &
MBB : MF) {
155 BlockToPCMap.insert(std::make_pair(&
MBB, PC));
156 for (
auto &
MI :
MBB) {
157 unsigned Size =
TII->getInstSizeInBytes(
MI);
158 if (Size > 8 || Size == 0) {
164 Branches.push_back(&
MI);
165 BranchToPCList.emplace_back(&
MI, PC);
170 for (
auto P : BranchToPCList) {
172 isInt<9>(MaxSize) ? replaceWithBRcc(
P.first) : replaceWithCmpBcc(
P.first);
175 LLVM_DEBUG(
dbgs() <<
"Estimated function size for " << MF.getName() <<
": "
182 return new ARCBranchFinalize();
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
This is an optimization pass for GlobalISel generic memory operations.
const MachineInstrBuilder & add(const MachineOperand &MO) const
This currently compiles esp xmm0 movsd esp eax eax esp ret We should use not the dag combiner This is because dagcombine2 needs to be able to see through the X86ISD::Wrapper which DAGCombine can t really do The code for turning x load into a single vector load is target independent and should be moved to the dag combiner The code for turning x load into a vector load can only handle a direct load from a global or a direct load from the stack It should be generalized to handle any load from P
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
INITIALIZE_PASS_BEGIN(ARCBranchFinalize, "arc-branch-finalize", "ARC finalize branches", false, false) INITIALIZE_PASS_END(ARCBranchFinalize
const HexagonInstrInfo * TII
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
static unsigned getCmpForPseudo(MachineInstr *MI)
Representation of each machine instruction.
arc branch ARC finalize static false unsigned getCCForBRcc(unsigned CC)
INITIALIZE_PASS_DEPENDENCY(DominatorTreeWrapperPass)
void initializeARCBranchFinalizePass(PassRegistry &Registry)
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
StringRef - Represent a constant reference to a string, i.e.
static unsigned getBRccForPseudo(MachineInstr *MI)
A global registry used in conjunction with static constructors to make pluggable components (like tar...
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
FunctionPass class - This class is used to implement most global optimizations.
FunctionPass * createARCBranchFinalizePass()
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
arc branch ARC finalize branches
static bool isBRccPseudo(MachineInstr *MI)