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34 #define DEBUG_TYPE "riscv-copyelim"
36 STATISTIC(NumCopiesRemoved,
"Number of copies removed.");
57 return "RISCV Redundant Copy Elimination";
69 "RISCV redundant copy elimination pass",
false,
false)
73 unsigned Opc =
MI.getOpcode();
74 if (Opc == RISCV::BEQ &&
MI.getOperand(1).getReg() == RISCV::X0 &&
75 &
MBB ==
MI.getOperand(2).getMBB())
77 if (Opc == RISCV::BNE &&
MI.getOperand(1).getReg() == RISCV::X0 &&
78 &
MBB !=
MI.getOperand(2).getMBB())
96 if (CondBr == PredMBB->
end())
101 if (!CondBr->isTerminator())
105 if (guaranteesZeroRegInBlock(*CondBr,
MBB))
108 if (CondBr == PredMBB->
begin())
113 Register TargetReg = CondBr->getOperand(0).getReg();
117 bool Changed =
false;
123 if (
MI->isCopy() &&
MI->getOperand(0).isReg() &&
124 MI->getOperand(1).isReg()) {
129 TargetReg == DefReg) {
133 MI->eraseFromParent();
141 if (
MI->modifiesRegister(TargetReg,
TRI))
150 CondBr->clearRegisterKills(TargetReg,
TRI);
158 MMI.clearRegisterKills(TargetReg,
TRI);
163 bool RISCVRedundantCopyElimination::runOnMachineFunction(
MachineFunction &MF) {
170 bool Changed =
false;
178 return new RISCVRedundantCopyElimination();
unsigned succ_size() const
pred_iterator pred_begin()
This is an optimization pass for GlobalISel generic memory operations.
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
bool isLiveIn(MCPhysReg Reg, LaneBitmask LaneMask=LaneBitmask::getAll()) const
Return true if the specified register is in the live in set.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Properties which a MachineFunction may have at a given point in time.
unsigned const TargetRegisterInfo * TRI
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
unsigned pred_size() const
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
bool isReserved(MCRegister PhysReg) const
isReserved - Returns true when PhysReg is a reserved register.
void initializeRISCVRedundantCopyEliminationPass(PassRegistry &)
MachineFunctionProperties & set(Property P)
STATISTIC(NumFunctions, "Total number of functions")
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
virtual void print(raw_ostream &OS, const Module *M) const
print - Print out the internal state of the pass.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
INITIALIZE_PASS(RISCVRedundantCopyElimination, "riscv-copyelim", "RISCV redundant copy elimination pass", false, false) static bool guaranteesZeroRegInBlock(const MachineInstr &MI
Representation of each machine instruction.
iterator getLastNonDebugInstr(bool SkipPseudoOp=true)
Returns an iterator to the last non-debug instruction in the basic block, or end().
const MachineBasicBlock & MBB
StringRef - Represent a constant reference to a string, i.e.
unsigned const MachineRegisterInfo * MRI
Wrapper class representing virtual and physical registers.
void addLiveIn(MCRegister PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
Function & getFunction()
Return the LLVM function that this machine code represents.
FunctionPass * createRISCVRedundantCopyEliminationPass()
static bool optimizeBlock(BasicBlock &BB, bool &ModifiedDT, const TargetTransformInfo &TTI, const DataLayout &DL, DomTreeUpdater *DTU)
FunctionPass class - This class is used to implement most global optimizations.