LLVM  13.0.0git
MachineInstrBuilder.h
Go to the documentation of this file.
1 //===- CodeGen/MachineInstrBuilder.h - Simplify creation of MIs --*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file exposes a function named BuildMI, which is useful for dramatically
10 // simplifying how MachineInstr's are created. It allows use of code like this:
11 //
12 // M = BuildMI(MBB, MI, DL, TII.get(X86::ADD8rr), Dst)
13 // .addReg(argVal1)
14 // .addReg(argVal2);
15 //
16 //===----------------------------------------------------------------------===//
17 
18 #ifndef LLVM_CODEGEN_MACHINEINSTRBUILDER_H
19 #define LLVM_CODEGEN_MACHINEINSTRBUILDER_H
20 
21 #include "llvm/ADT/ArrayRef.h"
29 #include "llvm/IR/InstrTypes.h"
30 #include "llvm/IR/Intrinsics.h"
32 #include <cassert>
33 #include <cstdint>
34 #include <utility>
35 
36 namespace llvm {
37 
38 class MCInstrDesc;
39 class MDNode;
40 
41 namespace RegState {
42 
43 enum {
44  /// Register definition.
45  Define = 0x2,
46  /// Not emitted register (e.g. carry, or temporary result).
47  Implicit = 0x4,
48  /// The last use of a register.
49  Kill = 0x8,
50  /// Unused definition.
51  Dead = 0x10,
52  /// Value of the register doesn't matter.
53  Undef = 0x20,
54  /// Register definition happens before uses.
55  EarlyClobber = 0x40,
56  /// Register 'use' is for debugging purpose.
57  Debug = 0x80,
58  /// Register reads a value that is defined inside the same instruction or
59  /// bundle.
60  InternalRead = 0x100,
61  /// Register that may be renamed.
62  Renamable = 0x200,
66 };
67 
68 } // end namespace RegState
69 
71  MachineFunction *MF = nullptr;
72  MachineInstr *MI = nullptr;
73 
74 public:
75  MachineInstrBuilder() = default;
76 
77  /// Create a MachineInstrBuilder for manipulating an existing instruction.
78  /// F must be the machine function that was used to allocate I.
81  : MF(&F), MI(&*I) {}
82 
83  /// Allow automatic conversion to the machine instruction we are working on.
84  operator MachineInstr*() const { return MI; }
85  MachineInstr *operator->() const { return MI; }
86  operator MachineBasicBlock::iterator() const { return MI; }
87 
88  /// If conversion operators fail, use this method to get the MachineInstr
89  /// explicitly.
90  MachineInstr *getInstr() const { return MI; }
91 
92  /// Get the register for the operand index.
93  /// The operand at the index should be a register (asserted by
94  /// MachineOperand).
95  Register getReg(unsigned Idx) const { return MI->getOperand(Idx).getReg(); }
96 
97  /// Add a new virtual register operand.
98  const MachineInstrBuilder &addReg(Register RegNo, unsigned flags = 0,
99  unsigned SubReg = 0) const {
100  assert((flags & 0x1) == 0 &&
101  "Passing in 'true' to addReg is forbidden! Use enums instead.");
102  MI->addOperand(*MF, MachineOperand::CreateReg(RegNo,
103  flags & RegState::Define,
104  flags & RegState::Implicit,
105  flags & RegState::Kill,
106  flags & RegState::Dead,
107  flags & RegState::Undef,
108  flags & RegState::EarlyClobber,
109  SubReg,
110  flags & RegState::Debug,
111  flags & RegState::InternalRead,
112  flags & RegState::Renamable));
113  return *this;
114  }
115 
116  /// Add a virtual register definition operand.
117  const MachineInstrBuilder &addDef(Register RegNo, unsigned Flags = 0,
118  unsigned SubReg = 0) const {
119  return addReg(RegNo, Flags | RegState::Define, SubReg);
120  }
121 
122  /// Add a virtual register use operand. It is an error for Flags to contain
123  /// `RegState::Define` when calling this function.
124  const MachineInstrBuilder &addUse(Register RegNo, unsigned Flags = 0,
125  unsigned SubReg = 0) const {
126  assert(!(Flags & RegState::Define) &&
127  "Misleading addUse defines register, use addReg instead.");
128  return addReg(RegNo, Flags, SubReg);
129  }
130 
131  /// Add a new immediate operand.
132  const MachineInstrBuilder &addImm(int64_t Val) const {
133  MI->addOperand(*MF, MachineOperand::CreateImm(Val));
134  return *this;
135  }
136 
137  const MachineInstrBuilder &addCImm(const ConstantInt *Val) const {
138  MI->addOperand(*MF, MachineOperand::CreateCImm(Val));
139  return *this;
140  }
141 
142  const MachineInstrBuilder &addFPImm(const ConstantFP *Val) const {
143  MI->addOperand(*MF, MachineOperand::CreateFPImm(Val));
144  return *this;
145  }
146 
148  unsigned TargetFlags = 0) const {
149  MI->addOperand(*MF, MachineOperand::CreateMBB(MBB, TargetFlags));
150  return *this;
151  }
152 
153  const MachineInstrBuilder &addFrameIndex(int Idx) const {
154  MI->addOperand(*MF, MachineOperand::CreateFI(Idx));
155  return *this;
156  }
157 
158  const MachineInstrBuilder &
159  addConstantPoolIndex(unsigned Idx, int Offset = 0,
160  unsigned TargetFlags = 0) const {
161  MI->addOperand(*MF, MachineOperand::CreateCPI(Idx, Offset, TargetFlags));
162  return *this;
163  }
164 
165  const MachineInstrBuilder &addTargetIndex(unsigned Idx, int64_t Offset = 0,
166  unsigned TargetFlags = 0) const {
167  MI->addOperand(*MF, MachineOperand::CreateTargetIndex(Idx, Offset,
168  TargetFlags));
169  return *this;
170  }
171 
173  unsigned TargetFlags = 0) const {
174  MI->addOperand(*MF, MachineOperand::CreateJTI(Idx, TargetFlags));
175  return *this;
176  }
177 
179  int64_t Offset = 0,
180  unsigned TargetFlags = 0) const {
181  MI->addOperand(*MF, MachineOperand::CreateGA(GV, Offset, TargetFlags));
182  return *this;
183  }
184 
185  const MachineInstrBuilder &addExternalSymbol(const char *FnName,
186  unsigned TargetFlags = 0) const {
187  MI->addOperand(*MF, MachineOperand::CreateES(FnName, TargetFlags));
188  return *this;
189  }
190 
192  int64_t Offset = 0,
193  unsigned TargetFlags = 0) const {
194  MI->addOperand(*MF, MachineOperand::CreateBA(BA, Offset, TargetFlags));
195  return *this;
196  }
197 
199  MI->addOperand(*MF, MachineOperand::CreateRegMask(Mask));
200  return *this;
201  }
202 
204  MI->addMemOperand(*MF, MMO);
205  return *this;
206  }
207 
208  const MachineInstrBuilder &
210  MI->setMemRefs(*MF, MMOs);
211  return *this;
212  }
213 
214  const MachineInstrBuilder &cloneMemRefs(const MachineInstr &OtherMI) const {
215  MI->cloneMemRefs(*MF, OtherMI);
216  return *this;
217  }
218 
219  const MachineInstrBuilder &
221  MI->cloneMergedMemRefs(*MF, OtherMIs);
222  return *this;
223  }
224 
225  const MachineInstrBuilder &add(const MachineOperand &MO) const {
226  MI->addOperand(*MF, MO);
227  return *this;
228  }
229 
231  for (const MachineOperand &MO : MOs) {
232  MI->addOperand(*MF, MO);
233  }
234  return *this;
235  }
236 
237  const MachineInstrBuilder &addMetadata(const MDNode *MD) const {
238  MI->addOperand(*MF, MachineOperand::CreateMetadata(MD));
239  assert((MI->isDebugValue() ? static_cast<bool>(MI->getDebugVariable())
240  : true) &&
241  "first MDNode argument of a DBG_VALUE not a variable");
242  assert((MI->isDebugLabel() ? static_cast<bool>(MI->getDebugLabel())
243  : true) &&
244  "first MDNode argument of a DBG_LABEL not a label");
245  return *this;
246  }
247 
248  const MachineInstrBuilder &addCFIIndex(unsigned CFIIndex) const {
249  MI->addOperand(*MF, MachineOperand::CreateCFIIndex(CFIIndex));
250  return *this;
251  }
252 
254  MI->addOperand(*MF, MachineOperand::CreateIntrinsicID(ID));
255  return *this;
256  }
257 
259  MI->addOperand(*MF, MachineOperand::CreatePredicate(Pred));
260  return *this;
261  }
262 
264  MI->addOperand(*MF, MachineOperand::CreateShuffleMask(Val));
265  return *this;
266  }
267 
269  unsigned char TargetFlags = 0) const {
270  MI->addOperand(*MF, MachineOperand::CreateMCSymbol(Sym, TargetFlags));
271  return *this;
272  }
273 
274  const MachineInstrBuilder &setMIFlags(unsigned Flags) const {
275  MI->setFlags(Flags);
276  return *this;
277  }
278 
280  MI->setFlag(Flag);
281  return *this;
282  }
283 
284  // Add a displacement from an existing MachineOperand with an added offset.
285  const MachineInstrBuilder &addDisp(const MachineOperand &Disp, int64_t off,
286  unsigned char TargetFlags = 0) const {
287  // If caller specifies new TargetFlags then use it, otherwise the
288  // default behavior is to copy the target flags from the existing
289  // MachineOperand. This means if the caller wants to clear the
290  // target flags it needs to do so explicitly.
291  if (0 == TargetFlags)
292  TargetFlags = Disp.getTargetFlags();
293 
294  switch (Disp.getType()) {
295  default:
296  llvm_unreachable("Unhandled operand type in addDisp()");
298  return addImm(Disp.getImm() + off);
300  return addConstantPoolIndex(Disp.getIndex(), Disp.getOffset() + off,
301  TargetFlags);
303  return addGlobalAddress(Disp.getGlobal(), Disp.getOffset() + off,
304  TargetFlags);
306  return addBlockAddress(Disp.getBlockAddress(), Disp.getOffset() + off,
307  TargetFlags);
309  assert(off == 0 && "cannot create offset into jump tables");
310  return addJumpTableIndex(Disp.getIndex(), TargetFlags);
311  }
312  }
313 
314  /// Copy all the implicit operands from OtherMI onto this one.
315  const MachineInstrBuilder &
316  copyImplicitOps(const MachineInstr &OtherMI) const {
317  MI->copyImplicitOps(*MF, OtherMI);
318  return *this;
319  }
320 
322  const TargetRegisterInfo &TRI,
323  const RegisterBankInfo &RBI) const {
324  return constrainSelectedInstRegOperands(*MI, TII, TRI, RBI);
325  }
326 };
327 
328 /// Builder interface. Specify how to create the initial instruction itself.
330  const MCInstrDesc &MCID) {
331  return MachineInstrBuilder(MF, MF.CreateMachineInstr(MCID, DL));
332 }
333 
334 /// This version of the builder sets up the first operand as a
335 /// destination virtual register.
337  const MCInstrDesc &MCID, Register DestReg) {
338  return MachineInstrBuilder(MF, MF.CreateMachineInstr(MCID, DL))
339  .addReg(DestReg, RegState::Define);
340 }
341 
342 /// This version of the builder inserts the newly-built instruction before
343 /// the given position in the given MachineBasicBlock, and sets up the first
344 /// operand as a destination virtual register.
347  const DebugLoc &DL, const MCInstrDesc &MCID,
348  Register DestReg) {
349  MachineFunction &MF = *BB.getParent();
350  MachineInstr *MI = MF.CreateMachineInstr(MCID, DL);
351  BB.insert(I, MI);
352  return MachineInstrBuilder(MF, MI).addReg(DestReg, RegState::Define);
353 }
354 
355 /// This version of the builder inserts the newly-built instruction before
356 /// the given position in the given MachineBasicBlock, and sets up the first
357 /// operand as a destination virtual register.
358 ///
359 /// If \c I is inside a bundle, then the newly inserted \a MachineInstr is
360 /// added to the same bundle.
363  const DebugLoc &DL, const MCInstrDesc &MCID,
364  Register DestReg) {
365  MachineFunction &MF = *BB.getParent();
366  MachineInstr *MI = MF.CreateMachineInstr(MCID, DL);
367  BB.insert(I, MI);
368  return MachineInstrBuilder(MF, MI).addReg(DestReg, RegState::Define);
369 }
370 
372  const DebugLoc &DL, const MCInstrDesc &MCID,
373  Register DestReg) {
374  // Calling the overload for instr_iterator is always correct. However, the
375  // definition is not available in headers, so inline the check.
376  if (I.isInsideBundle())
377  return BuildMI(BB, MachineBasicBlock::instr_iterator(I), DL, MCID, DestReg);
378  return BuildMI(BB, MachineBasicBlock::iterator(I), DL, MCID, DestReg);
379 }
380 
382  const DebugLoc &DL, const MCInstrDesc &MCID,
383  Register DestReg) {
384  return BuildMI(BB, *I, DL, MCID, DestReg);
385 }
386 
387 /// This version of the builder inserts the newly-built instruction before the
388 /// given position in the given MachineBasicBlock, and does NOT take a
389 /// destination register.
392  const DebugLoc &DL,
393  const MCInstrDesc &MCID) {
394  MachineFunction &MF = *BB.getParent();
395  MachineInstr *MI = MF.CreateMachineInstr(MCID, DL);
396  BB.insert(I, MI);
397  return MachineInstrBuilder(MF, MI);
398 }
399 
402  const DebugLoc &DL,
403  const MCInstrDesc &MCID) {
404  MachineFunction &MF = *BB.getParent();
405  MachineInstr *MI = MF.CreateMachineInstr(MCID, DL);
406  BB.insert(I, MI);
407  return MachineInstrBuilder(MF, MI);
408 }
409 
411  const DebugLoc &DL,
412  const MCInstrDesc &MCID) {
413  // Calling the overload for instr_iterator is always correct. However, the
414  // definition is not available in headers, so inline the check.
415  if (I.isInsideBundle())
417  return BuildMI(BB, MachineBasicBlock::iterator(I), DL, MCID);
418 }
419 
421  const DebugLoc &DL,
422  const MCInstrDesc &MCID) {
423  return BuildMI(BB, *I, DL, MCID);
424 }
425 
426 /// This version of the builder inserts the newly-built instruction at the end
427 /// of the given MachineBasicBlock, and does NOT take a destination register.
429  const MCInstrDesc &MCID) {
430  return BuildMI(*BB, BB->end(), DL, MCID);
431 }
432 
433 /// This version of the builder inserts the newly-built instruction at the
434 /// end of the given MachineBasicBlock, and sets up the first operand as a
435 /// destination virtual register.
437  const MCInstrDesc &MCID, Register DestReg) {
438  return BuildMI(*BB, BB->end(), DL, MCID, DestReg);
439 }
440 
441 /// This version of the builder builds a DBG_VALUE intrinsic
442 /// for either a value in a register or a register-indirect
443 /// address. The convention is that a DBG_VALUE is indirect iff the
444 /// second operand is an immediate.
445 MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL,
446  const MCInstrDesc &MCID, bool IsIndirect,
447  Register Reg, const MDNode *Variable,
448  const MDNode *Expr);
449 
450 /// This version of the builder builds a DBG_VALUE intrinsic
451 /// for a MachineOperand.
452 MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL,
453  const MCInstrDesc &MCID, bool IsIndirect,
454  const MachineOperand &MO, const MDNode *Variable,
455  const MDNode *Expr);
456 
457 /// This version of the builder builds a DBG_VALUE or DBG_VALUE_LIST intrinsic
458 /// for a MachineOperand.
459 MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL,
460  const MCInstrDesc &MCID, bool IsIndirect,
461  ArrayRef<MachineOperand> MOs,
462  const MDNode *Variable, const MDNode *Expr);
463 
464 /// This version of the builder builds a DBG_VALUE intrinsic
465 /// for either a value in a register or a register-indirect
466 /// address and inserts it at position I.
467 MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
468  MachineBasicBlock::iterator I, const DebugLoc &DL,
469  const MCInstrDesc &MCID, bool IsIndirect,
470  Register Reg, const MDNode *Variable,
471  const MDNode *Expr);
472 
473 /// This version of the builder builds a DBG_VALUE intrinsic
474 /// for a machine operand and inserts it at position I.
475 MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
476  MachineBasicBlock::iterator I, const DebugLoc &DL,
477  const MCInstrDesc &MCID, bool IsIndirect,
478  MachineOperand &MO, const MDNode *Variable,
479  const MDNode *Expr);
480 
481 /// This version of the builder builds a DBG_VALUE or DBG_VALUE_LIST intrinsic
482 /// for a machine operand and inserts it at position I.
483 MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
484  MachineBasicBlock::iterator I, const DebugLoc &DL,
485  const MCInstrDesc &MCID, bool IsIndirect,
486  ArrayRef<MachineOperand> MOs,
487  const MDNode *Variable, const MDNode *Expr);
488 
489 /// Clone a DBG_VALUE whose value has been spilled to FrameIndex.
490 MachineInstr *buildDbgValueForSpill(MachineBasicBlock &BB,
492  const MachineInstr &Orig, int FrameIndex,
493  Register SpillReg);
494 MachineInstr *
496  const MachineInstr &Orig, int FrameIndex,
497  SmallVectorImpl<const MachineOperand *> &SpilledOperands);
498 
499 /// Update a DBG_VALUE whose value has been spilled to FrameIndex. Useful when
500 /// modifying an instruction in place while iterating over a basic block.
501 void updateDbgValueForSpill(MachineInstr &Orig, int FrameIndex, Register Reg);
502 
503 inline unsigned getDefRegState(bool B) {
504  return B ? RegState::Define : 0;
505 }
506 inline unsigned getImplRegState(bool B) {
507  return B ? RegState::Implicit : 0;
508 }
509 inline unsigned getKillRegState(bool B) {
510  return B ? RegState::Kill : 0;
511 }
512 inline unsigned getDeadRegState(bool B) {
513  return B ? RegState::Dead : 0;
514 }
515 inline unsigned getUndefRegState(bool B) {
516  return B ? RegState::Undef : 0;
517 }
518 inline unsigned getInternalReadRegState(bool B) {
519  return B ? RegState::InternalRead : 0;
520 }
521 inline unsigned getDebugRegState(bool B) {
522  return B ? RegState::Debug : 0;
523 }
524 inline unsigned getRenamableRegState(bool B) {
525  return B ? RegState::Renamable : 0;
526 }
527 
528 /// Get all register state flags from machine operand \p RegOp.
529 inline unsigned getRegState(const MachineOperand &RegOp) {
530  assert(RegOp.isReg() && "Not a register operand");
531  return getDefRegState(RegOp.isDef()) | getImplRegState(RegOp.isImplicit()) |
532  getKillRegState(RegOp.isKill()) | getDeadRegState(RegOp.isDead()) |
533  getUndefRegState(RegOp.isUndef()) |
535  getDebugRegState(RegOp.isDebug()) |
537  RegOp.isRenamable());
538 }
539 
540 /// Helper class for constructing bundles of MachineInstrs.
541 ///
542 /// MIBundleBuilder can create a bundle from scratch by inserting new
543 /// MachineInstrs one at a time, or it can create a bundle from a sequence of
544 /// existing MachineInstrs in a basic block.
546  MachineBasicBlock &MBB;
549 
550 public:
551  /// Create an MIBundleBuilder that inserts instructions into a new bundle in
552  /// BB above the bundle or instruction at Pos.
554  : MBB(BB), Begin(Pos.getInstrIterator()), End(Begin) {}
555 
556  /// Create a bundle from the sequence of instructions between B and E.
559  : MBB(BB), Begin(B.getInstrIterator()), End(E.getInstrIterator()) {
560  assert(B != E && "No instructions to bundle");
561  ++B;
562  while (B != E) {
563  MachineInstr &MI = *B;
564  ++B;
565  MI.bundleWithPred();
566  }
567  }
568 
569  /// Create an MIBundleBuilder representing an existing instruction or bundle
570  /// that has MI as its head.
572  : MBB(*MI->getParent()), Begin(MI),
573  End(getBundleEnd(MI->getIterator())) {}
574 
575  /// Return a reference to the basic block containing this bundle.
576  MachineBasicBlock &getMBB() const { return MBB; }
577 
578  /// Return true if no instructions have been inserted in this bundle yet.
579  /// Empty bundles aren't representable in a MachineBasicBlock.
580  bool empty() const { return Begin == End; }
581 
582  /// Return an iterator to the first bundled instruction.
583  MachineBasicBlock::instr_iterator begin() const { return Begin; }
584 
585  /// Return an iterator beyond the last bundled instruction.
586  MachineBasicBlock::instr_iterator end() const { return End; }
587 
588  /// Insert MI into this bundle before I which must point to an instruction in
589  /// the bundle, or end().
591  MachineInstr *MI) {
592  MBB.insert(I, MI);
593  if (I == Begin) {
594  if (!empty())
595  MI->bundleWithSucc();
596  Begin = MI->getIterator();
597  return *this;
598  }
599  if (I == End) {
600  MI->bundleWithPred();
601  return *this;
602  }
603  // MI was inserted in the middle of the bundle, so its neighbors' flags are
604  // already fine. Update MI's bundle flags manually.
605  MI->setFlag(MachineInstr::BundledPred);
606  MI->setFlag(MachineInstr::BundledSucc);
607  return *this;
608  }
609 
610  /// Insert MI into MBB by prepending it to the instructions in the bundle.
611  /// MI will become the first instruction in the bundle.
613  return insert(begin(), MI);
614  }
615 
616  /// Insert MI into MBB by appending it to the instructions in the bundle.
617  /// MI will become the last instruction in the bundle.
619  return insert(end(), MI);
620  }
621 };
622 
623 } // end namespace llvm
624 
625 #endif // LLVM_CODEGEN_MACHINEINSTRBUILDER_H
llvm::MachineInstrBuilder::operator->
MachineInstr * operator->() const
Definition: MachineInstrBuilder.h:85
llvm::MachineOperand::CreateCPI
static MachineOperand CreateCPI(unsigned Idx, int Offset, unsigned TargetFlags=0)
Definition: MachineOperand.h:825
llvm::MachineOperand::CreateJTI
static MachineOperand CreateJTI(unsigned Idx, unsigned TargetFlags=0)
Definition: MachineOperand.h:841
llvm::MachineInstrBuilder::addCImm
const MachineInstrBuilder & addCImm(const ConstantInt *Val) const
Definition: MachineInstrBuilder.h:137
llvm::MachineOperand::MO_BlockAddress
@ MO_BlockAddress
Address of a basic block.
Definition: MachineOperand.h:63
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:100
MachineInstr.h
llvm::MachineOperand::MO_Immediate
@ MO_Immediate
Immediate operand.
Definition: MachineOperand.h:53
llvm::MachineInstrBuilder::addImm
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Definition: MachineInstrBuilder.h:132
llvm
Definition: AllocatorList.h:23
llvm::MachineInstrBuilder::copyImplicitOps
const MachineInstrBuilder & copyImplicitOps(const MachineInstr &OtherMI) const
Copy all the implicit operands from OtherMI onto this one.
Definition: MachineInstrBuilder.h:316
Reg
unsigned Reg
Definition: MachineSink.cpp:1566
llvm::MCSymbol
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:41
llvm::MachineInstrBuilder::addFPImm
const MachineInstrBuilder & addFPImm(const ConstantFP *Val) const
Definition: MachineInstrBuilder.h:142
llvm::MachineOperand::CreateReg
static MachineOperand CreateReg(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)
Definition: MachineOperand.h:788
llvm::MIBundleBuilder::begin
MachineBasicBlock::instr_iterator begin() const
Return an iterator to the first bundled instruction.
Definition: MachineInstrBuilder.h:583
llvm::CmpInst::Predicate
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:722
llvm::MachineOperand::getGlobal
const GlobalValue * getGlobal() const
Definition: MachineOperand.h:560
llvm::MachineInstrBuilder::add
const MachineInstrBuilder & add(const MachineOperand &MO) const
Definition: MachineInstrBuilder.h:225
llvm::MIBundleBuilder::end
MachineBasicBlock::instr_iterator end() const
Return an iterator beyond the last bundled instruction.
Definition: MachineInstrBuilder.h:586
llvm::RegState::Dead
@ Dead
Unused definition.
Definition: MachineInstrBuilder.h:51
llvm::MachineInstrBuilder::addCFIIndex
const MachineInstrBuilder & addCFIIndex(unsigned CFIIndex) const
Definition: MachineInstrBuilder.h:248
llvm::MachineOperand::getBlockAddress
const BlockAddress * getBlockAddress() const
Definition: MachineOperand.h:565
llvm::MIBundleBuilder::MIBundleBuilder
MIBundleBuilder(MachineBasicBlock &BB, MachineBasicBlock::iterator B, MachineBasicBlock::iterator E)
Create a bundle from the sequence of instructions between B and E.
Definition: MachineInstrBuilder.h:557
ErrorHandling.h
MachineBasicBlock.h
llvm::MIBundleBuilder::MIBundleBuilder
MIBundleBuilder(MachineBasicBlock &BB, MachineBasicBlock::iterator Pos)
Create an MIBundleBuilder that inserts instructions into a new bundle in BB above the bundle or instr...
Definition: MachineInstrBuilder.h:553
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:231
llvm::MachineOperand::CreateMetadata
static MachineOperand CreateMetadata(const MDNode *Meta)
Definition: MachineOperand.h:895
llvm::MachineOperand::CreateCFIIndex
static MachineOperand CreateCFIIndex(unsigned CFIIndex)
Definition: MachineOperand.h:910
llvm::MachineMemOperand
A description of a memory reference used in the backend.
Definition: MachineMemOperand.h:127
llvm::RegState::InternalRead
@ InternalRead
Register reads a value that is defined inside the same instruction or bundle.
Definition: MachineInstrBuilder.h:60
llvm::getDeadRegState
unsigned getDeadRegState(bool B)
Definition: MachineInstrBuilder.h:512
Offset
uint64_t Offset
Definition: ELFObjHandler.cpp:81
llvm::RegState::Renamable
@ Renamable
Register that may be renamed.
Definition: MachineInstrBuilder.h:62
llvm::MachineOperand::getOffset
int64_t getOffset() const
Return the offset from the symbol in this operand.
Definition: MachineOperand.h:597
llvm::BitmaskEnumDetail::Mask
std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1567
llvm::constrainSelectedInstRegOperands
bool constrainSelectedInstRegOperands(MachineInstr &I, const TargetInstrInfo &TII, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI)
Mutate the newly-selected instruction I to constrain its (possibly generic) virtual register operands...
Definition: Utils.cpp:134
F
#define F(x, y, z)
Definition: MD5.cpp:56
llvm::getUndefRegState
unsigned getUndefRegState(bool B)
Definition: MachineInstrBuilder.h:515
llvm::MachineOperand::CreateES
static MachineOperand CreateES(const char *SymName, unsigned TargetFlags=0)
Definition: MachineOperand.h:855
llvm::getBundleEnd
MachineBasicBlock::instr_iterator getBundleEnd(MachineBasicBlock::instr_iterator I)
Returns an iterator pointing beyond the bundle containing I.
Definition: MachineInstrBundle.h:60
llvm::MachineOperand::isKill
bool isKill() const
Definition: MachineOperand.h:387
llvm::MachineInstrBuilder::addDef
const MachineInstrBuilder & addDef(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register definition operand.
Definition: MachineInstrBuilder.h:117
llvm::MachineOperand::isRenamable
bool isRenamable() const
isRenamable - Returns true if this register may be renamed, i.e.
Definition: MachineOperand.cpp:118
llvm::ConstantInt
This is the shared class of boolean and integer constants.
Definition: Constants.h:77
llvm::getDefRegState
unsigned getDefRegState(bool B)
Definition: MachineInstrBuilder.h:503
llvm::MIBundleBuilder::insert
MIBundleBuilder & insert(MachineBasicBlock::instr_iterator I, MachineInstr *MI)
Insert MI into this bundle before I which must point to an instruction in the bundle,...
Definition: MachineInstrBuilder.h:590
llvm::MachineOperand::isImplicit
bool isImplicit() const
Definition: MachineOperand.h:377
llvm::TargetInstrInfo
TargetInstrInfo - Interface to description of machine instruction set.
Definition: TargetInstrInfo.h:97
llvm::getRenamableRegState
unsigned getRenamableRegState(bool B)
Definition: MachineInstrBuilder.h:524
llvm::MachineInstrBuilder::addMBB
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
Definition: MachineInstrBuilder.h:147
llvm::MIBundleBuilder::getMBB
MachineBasicBlock & getMBB() const
Return a reference to the basic block containing this bundle.
Definition: MachineInstrBuilder.h:576
llvm::MachineOperand::CreateImm
static MachineOperand CreateImm(int64_t Val)
Definition: MachineOperand.h:770
llvm::MachineOperand::MO_GlobalAddress
@ MO_GlobalAddress
Address of a global value.
Definition: MachineOperand.h:62
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
llvm::MachineOperand::getImm
int64_t getImm() const
Definition: MachineOperand.h:534
Intrinsics.h
llvm::buildDbgValueForSpill
MachineInstr * buildDbgValueForSpill(MachineBasicBlock &BB, MachineBasicBlock::iterator I, const MachineInstr &Orig, int FrameIndex, Register SpillReg)
Clone a DBG_VALUE whose value has been spilled to FrameIndex.
Definition: MachineInstr.cpp:2228
InstrTypes.h
llvm::Register::isPhysicalRegister
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:65
Utils.h
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:129
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:196
B
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:49
llvm::MCID::Flag
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:147
MachineInstrBundle.h
llvm::ConstantFP
ConstantFP - Floating Point Values [float, double].
Definition: Constants.h:255
llvm::MachineOperand::CreateFI
static MachineOperand CreateFI(int Idx)
Definition: MachineOperand.h:820
llvm::RegState::Define
@ Define
Register definition.
Definition: MachineInstrBuilder.h:45
llvm::RegState::Implicit
@ Implicit
Not emitted register (e.g. carry, or temporary result).
Definition: MachineInstrBuilder.h:47
llvm::MachineInstrBuilder::addExternalSymbol
const MachineInstrBuilder & addExternalSymbol(const char *FnName, unsigned TargetFlags=0) const
Definition: MachineInstrBuilder.h:185
llvm::RegState::Kill
@ Kill
The last use of a register.
Definition: MachineInstrBuilder.h:49
llvm::MachineInstrBuilder::getReg
Register getReg(unsigned Idx) const
Get the register for the operand index.
Definition: MachineInstrBuilder.h:95
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
llvm::MachineInstrBuilder::cloneMemRefs
const MachineInstrBuilder & cloneMemRefs(const MachineInstr &OtherMI) const
Definition: MachineInstrBuilder.h:214
llvm::MachineInstrBuilder::addFrameIndex
const MachineInstrBuilder & addFrameIndex(int Idx) const
Definition: MachineInstrBuilder.h:153
llvm::RegState::EarlyClobber
@ EarlyClobber
Register definition happens before uses.
Definition: MachineInstrBuilder.h:55
llvm::MachineInstrBuilder::setMIFlag
const MachineInstrBuilder & setMIFlag(MachineInstr::MIFlag Flag) const
Definition: MachineInstrBuilder.h:279
llvm::MachineOperand::CreateShuffleMask
static MachineOperand CreateShuffleMask(ArrayRef< int > Mask)
Definition: MachineOperand.h:928
llvm::getRegState
unsigned getRegState(const MachineOperand &RegOp)
Get all register state flags from machine operand RegOp.
Definition: MachineInstrBuilder.h:529
llvm::RegisterBankInfo
Holds all the information related to register banks.
Definition: RegisterBankInfo.h:39
llvm::GlobalValue
Definition: GlobalValue.h:44
llvm::MachineOperand::isUndef
bool isUndef() const
Definition: MachineOperand.h:392
llvm::MachineOperand::getTargetFlags
unsigned getTargetFlags() const
Definition: MachineOperand.h:218
llvm::MachineOperand::isReg
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Definition: MachineOperand.h:318
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
llvm::MachineInstrBuilder
Definition: MachineInstrBuilder.h:70
llvm::MachineOperand::CreateMBB
static MachineOperand CreateMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0)
Definition: MachineOperand.h:813
llvm::MachineInstrBuilder::addShuffleMask
const MachineInstrBuilder & addShuffleMask(ArrayRef< int > Val) const
Definition: MachineInstrBuilder.h:263
llvm::updateDbgValueForSpill
void updateDbgValueForSpill(MachineInstr &Orig, int FrameIndex, Register Reg)
Update a DBG_VALUE whose value has been spilled to FrameIndex.
Definition: MachineInstr.cpp:2271
llvm::MIBundleBuilder::empty
bool empty() const
Return true if no instructions have been inserted in this bundle yet.
Definition: MachineInstrBuilder.h:580
llvm::MachineOperand::isDead
bool isDead() const
Definition: MachineOperand.h:382
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::MachineInstrBuilder::addDisp
const MachineInstrBuilder & addDisp(const MachineOperand &Disp, int64_t off, unsigned char TargetFlags=0) const
Definition: MachineInstrBuilder.h:285
ArrayRef.h
llvm::MachineOperand::getType
MachineOperandType getType() const
getType - Returns the MachineOperandType for this operand.
Definition: MachineOperand.h:216
llvm::MachineInstrBuilder::addIntrinsicID
const MachineInstrBuilder & addIntrinsicID(Intrinsic::ID ID) const
Definition: MachineInstrBuilder.h:253
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::MachineInstrBuilder::addMemOperand
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
Definition: MachineInstrBuilder.h:203
llvm::MachineOperand::CreateBA
static MachineOperand CreateBA(const BlockAddress *BA, int64_t Offset, unsigned TargetFlags=0)
Definition: MachineOperand.h:863
llvm::MachineInstrBuilder::MachineInstrBuilder
MachineInstrBuilder(MachineFunction &F, MachineBasicBlock::iterator I)
Definition: MachineInstrBuilder.h:80
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Definition: MachineInstrBuilder.h:98
llvm::MachineInstrBuilder::addUse
const MachineInstrBuilder & addUse(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register use operand.
Definition: MachineInstrBuilder.h:124
llvm::MachineOperand::getReg
Register getReg() const
getReg - Returns the register number.
Definition: MachineOperand.h:357
llvm::MDNode
Metadata node.
Definition: Metadata.h:897
llvm::MachineOperand::CreateMCSymbol
static MachineOperand CreateMCSymbol(MCSymbol *Sym, unsigned TargetFlags=0)
Definition: MachineOperand.h:901
llvm::MachineInstrBuilder::constrainAllUses
bool constrainAllUses(const TargetInstrInfo &TII, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI) const
Definition: MachineInstrBuilder.h:321
llvm::MachineInstr::MIFlag
MIFlag
Definition: MachineInstr.h:80
llvm::MachineFunction
Definition: MachineFunction.h:227
llvm::MachineOperand::MO_JumpTableIndex
@ MO_JumpTableIndex
Address of indexed Jump Table for switch.
Definition: MachineOperand.h:60
llvm::BlockAddress
The address of a basic block.
Definition: Constants.h:847
llvm::MachineInstrBuilder::addRegMask
const MachineInstrBuilder & addRegMask(const uint32_t *Mask) const
Definition: MachineInstrBuilder.h:198
llvm::RegState::ImplicitKill
@ ImplicitKill
Definition: MachineInstrBuilder.h:65
llvm::MachineBasicBlock::iterator
MachineInstrBundleIterator< MachineInstr > iterator
Definition: MachineBasicBlock.h:233
llvm::MachineOperand::CreateIntrinsicID
static MachineOperand CreateIntrinsicID(Intrinsic::ID ID)
Definition: MachineOperand.h:916
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::MachineInstrBuilder::add
const MachineInstrBuilder & add(ArrayRef< MachineOperand > MOs) const
Definition: MachineInstrBuilder.h:230
llvm::MachineOperand::CreateGA
static MachineOperand CreateGA(const GlobalValue *GV, int64_t Offset, unsigned TargetFlags=0)
Definition: MachineOperand.h:847
llvm::RegState::Debug
@ Debug
Register 'use' is for debugging purpose.
Definition: MachineInstrBuilder.h:57
llvm::MachineInstrBuilder::addJumpTableIndex
const MachineInstrBuilder & addJumpTableIndex(unsigned Idx, unsigned TargetFlags=0) const
Definition: MachineInstrBuilder.h:172
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:136
getParent
static const Function * getParent(const Value *V)
Definition: BasicAliasAnalysis.cpp:759
uint32_t
llvm::MIBundleBuilder
Helper class for constructing bundles of MachineInstrs.
Definition: MachineInstrBuilder.h:545
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::MachineOperand::isDef
bool isDef() const
Definition: MachineOperand.h:372
llvm::MachineInstrBuilder::addPredicate
const MachineInstrBuilder & addPredicate(CmpInst::Predicate Pred) const
Definition: MachineInstrBuilder.h:258
llvm::MachineInstrBuilder::addBlockAddress
const MachineInstrBuilder & addBlockAddress(const BlockAddress *BA, int64_t Offset=0, unsigned TargetFlags=0) const
Definition: MachineInstrBuilder.h:191
llvm::MachineOperand::CreateCImm
static MachineOperand CreateCImm(const ConstantInt *CI)
Definition: MachineOperand.h:776
llvm::MachineInstrBuilder::cloneMergedMemRefs
const MachineInstrBuilder & cloneMergedMemRefs(ArrayRef< const MachineInstr * > OtherMIs) const
Definition: MachineInstrBuilder.h:220
llvm::MachineInstrBuilder::getInstr
MachineInstr * getInstr() const
If conversion operators fail, use this method to get the MachineInstr explicitly.
Definition: MachineInstrBuilder.h:90
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::ISD::FrameIndex
@ FrameIndex
Definition: ISDOpcodes.h:73
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::MIBundleBuilder::prepend
MIBundleBuilder & prepend(MachineInstr *MI)
Insert MI into MBB by prepending it to the instructions in the bundle.
Definition: MachineInstrBuilder.h:612
llvm::RegState::DefineNoRead
@ DefineNoRead
Definition: MachineInstrBuilder.h:63
llvm::getDebugRegState
unsigned getDebugRegState(bool B)
Definition: MachineInstrBuilder.h:521
llvm::RegState::Undef
@ Undef
Value of the register doesn't matter.
Definition: MachineInstrBuilder.h:53
llvm::MachineOperand::getIndex
int getIndex() const
Definition: MachineOperand.h:554
llvm::MachineInstrBuilder::addConstantPoolIndex
const MachineInstrBuilder & addConstantPoolIndex(unsigned Idx, int Offset=0, unsigned TargetFlags=0) const
Definition: MachineInstrBuilder.h:159
llvm::MachineBasicBlock::instr_iterator
Instructions::iterator instr_iterator
Definition: MachineBasicBlock.h:228
llvm::MIBundleBuilder::MIBundleBuilder
MIBundleBuilder(MachineInstr *MI)
Create an MIBundleBuilder representing an existing instruction or bundle that has MI as its head.
Definition: MachineInstrBuilder.h:571
llvm::MachineInstrBuilder::setMemRefs
const MachineInstrBuilder & setMemRefs(ArrayRef< MachineMemOperand * > MMOs) const
Definition: MachineInstrBuilder.h:209
llvm::MachineInstrBuilder::addTargetIndex
const MachineInstrBuilder & addTargetIndex(unsigned Idx, int64_t Offset=0, unsigned TargetFlags=0) const
Definition: MachineInstrBuilder.h:165
llvm::MIBundleBuilder::append
MIBundleBuilder & append(MachineInstr *MI)
Insert MI into MBB by appending it to the instructions in the bundle.
Definition: MachineInstrBuilder.h:618
llvm::MachineOperand::isDebug
bool isDebug() const
Definition: MachineOperand.h:443
llvm::MachineInstrBuilder::addGlobalAddress
const MachineInstrBuilder & addGlobalAddress(const GlobalValue *GV, int64_t Offset=0, unsigned TargetFlags=0) const
Definition: MachineInstrBuilder.h:178
llvm::getKillRegState
unsigned getKillRegState(bool B)
Definition: MachineInstrBuilder.h:509
llvm::MachineInstrBuilder::addSym
const MachineInstrBuilder & addSym(MCSymbol *Sym, unsigned char TargetFlags=0) const
Definition: MachineInstrBuilder.h:268
llvm::MachineOperand::CreateRegMask
static MachineOperand CreateRegMask(const uint32_t *Mask)
CreateRegMask - Creates a register mask operand referencing Mask.
Definition: MachineOperand.h:883
llvm::MachineInstrBuilder::setMIFlags
const MachineInstrBuilder & setMIFlags(unsigned Flags) const
Definition: MachineInstrBuilder.h:274
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition: MachineInstrBuilder.h:329
llvm::MachineInstr::BundledSucc
@ BundledSucc
Definition: MachineInstr.h:87
llvm::MachineInstrBuilder::MachineInstrBuilder
MachineInstrBuilder()=default
llvm::MachineOperand::isInternalRead
bool isInternalRead() const
Definition: MachineOperand.h:428
llvm::MachineInstrBuilder::addMetadata
const MachineInstrBuilder & addMetadata(const MDNode *MD) const
Definition: MachineInstrBuilder.h:237
MachineOperand.h
BB
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
Definition: README.txt:39
llvm::MachineFunction::CreateMachineInstr
MachineInstr * CreateMachineInstr(const MCInstrDesc &MCID, const DebugLoc &DL, bool NoImplicit=false)
CreateMachineInstr - Allocate a new MachineInstr.
Definition: MachineFunction.cpp:348
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
llvm::getInternalReadRegState
unsigned getInternalReadRegState(bool B)
Definition: MachineInstrBuilder.h:518
MachineFunction.h
llvm::MachineInstr::BundledPred
@ BundledPred
Definition: MachineInstr.h:86
llvm::MachineInstrBuilder::MachineInstrBuilder
MachineInstrBuilder(MachineFunction &F, MachineInstr *I)
Create a MachineInstrBuilder for manipulating an existing instruction.
Definition: MachineInstrBuilder.h:79
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::RegState::ImplicitDefine
@ ImplicitDefine
Definition: MachineInstrBuilder.h:64
llvm::getImplRegState
unsigned getImplRegState(bool B)
Definition: MachineInstrBuilder.h:506
llvm::MachineOperand::CreatePredicate
static MachineOperand CreatePredicate(unsigned Pred)
Definition: MachineOperand.h:922
TargetRegisterInfo.h
SubReg
unsigned SubReg
Definition: AArch64AdvSIMDScalarPass.cpp:104
llvm::MachineOperand::CreateFPImm
static MachineOperand CreateFPImm(const ConstantFP *CFP)
Definition: MachineOperand.h:782
llvm::MachineOperand::CreateTargetIndex
static MachineOperand CreateTargetIndex(unsigned Idx, int64_t Offset, unsigned TargetFlags=0)
Definition: MachineOperand.h:833
llvm::Intrinsic::ID
unsigned ID
Definition: TargetTransformInfo.h:38
llvm::MachineOperand::MO_ConstantPoolIndex
@ MO_ConstantPoolIndex
Address of indexed Constant in Constant Pool.
Definition: MachineOperand.h:58