LLVM 17.0.0git
MachineInstrBuilder.h
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1//===- CodeGen/MachineInstrBuilder.h - Simplify creation of MIs --*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file exposes a function named BuildMI, which is useful for dramatically
10// simplifying how MachineInstr's are created. It allows use of code like this:
11//
12// M = BuildMI(MBB, MI, DL, TII.get(X86::ADD8rr), Dst)
13// .addReg(argVal1)
14// .addReg(argVal2);
15//
16//===----------------------------------------------------------------------===//
17
18#ifndef LLVM_CODEGEN_MACHINEINSTRBUILDER_H
19#define LLVM_CODEGEN_MACHINEINSTRBUILDER_H
20
21#include "llvm/ADT/ArrayRef.h"
29#include "llvm/IR/InstrTypes.h"
30#include "llvm/IR/Intrinsics.h"
32#include <cassert>
33#include <cstdint>
34
35namespace llvm {
36
37class MCInstrDesc;
38class MDNode;
39
40namespace RegState {
41
42enum {
43 /// Register definition.
44 Define = 0x2,
45 /// Not emitted register (e.g. carry, or temporary result).
46 Implicit = 0x4,
47 /// The last use of a register.
48 Kill = 0x8,
49 /// Unused definition.
50 Dead = 0x10,
51 /// Value of the register doesn't matter.
52 Undef = 0x20,
53 /// Register definition happens before uses.
55 /// Register 'use' is for debugging purpose.
56 Debug = 0x80,
57 /// Register reads a value that is defined inside the same instruction or
58 /// bundle.
59 InternalRead = 0x100,
60 /// Register that may be renamed.
61 Renamable = 0x200,
65};
66
67} // end namespace RegState
68
70 MachineFunction *MF = nullptr;
71 MachineInstr *MI = nullptr;
72
73public:
75
76 /// Create a MachineInstrBuilder for manipulating an existing instruction.
77 /// F must be the machine function that was used to allocate I.
80 : MF(&F), MI(&*I) {}
81
82 /// Allow automatic conversion to the machine instruction we are working on.
83 operator MachineInstr*() const { return MI; }
84 MachineInstr *operator->() const { return MI; }
85 operator MachineBasicBlock::iterator() const { return MI; }
86
87 /// If conversion operators fail, use this method to get the MachineInstr
88 /// explicitly.
89 MachineInstr *getInstr() const { return MI; }
90
91 /// Get the register for the operand index.
92 /// The operand at the index should be a register (asserted by
93 /// MachineOperand).
94 Register getReg(unsigned Idx) const { return MI->getOperand(Idx).getReg(); }
95
96 /// Add a new virtual register operand.
97 const MachineInstrBuilder &addReg(Register RegNo, unsigned flags = 0,
98 unsigned SubReg = 0) const {
99 assert((flags & 0x1) == 0 &&
100 "Passing in 'true' to addReg is forbidden! Use enums instead.");
101 MI->addOperand(*MF, MachineOperand::CreateReg(RegNo,
102 flags & RegState::Define,
103 flags & RegState::Implicit,
104 flags & RegState::Kill,
105 flags & RegState::Dead,
106 flags & RegState::Undef,
108 SubReg,
109 flags & RegState::Debug,
111 flags & RegState::Renamable));
112 return *this;
113 }
114
115 /// Add a virtual register definition operand.
116 const MachineInstrBuilder &addDef(Register RegNo, unsigned Flags = 0,
117 unsigned SubReg = 0) const {
118 return addReg(RegNo, Flags | RegState::Define, SubReg);
119 }
120
121 /// Add a virtual register use operand. It is an error for Flags to contain
122 /// `RegState::Define` when calling this function.
123 const MachineInstrBuilder &addUse(Register RegNo, unsigned Flags = 0,
124 unsigned SubReg = 0) const {
125 assert(!(Flags & RegState::Define) &&
126 "Misleading addUse defines register, use addReg instead.");
127 return addReg(RegNo, Flags, SubReg);
128 }
129
130 /// Add a new immediate operand.
131 const MachineInstrBuilder &addImm(int64_t Val) const {
132 MI->addOperand(*MF, MachineOperand::CreateImm(Val));
133 return *this;
134 }
135
136 const MachineInstrBuilder &addCImm(const ConstantInt *Val) const {
137 MI->addOperand(*MF, MachineOperand::CreateCImm(Val));
138 return *this;
139 }
140
141 const MachineInstrBuilder &addFPImm(const ConstantFP *Val) const {
142 MI->addOperand(*MF, MachineOperand::CreateFPImm(Val));
143 return *this;
144 }
145
147 unsigned TargetFlags = 0) const {
148 MI->addOperand(*MF, MachineOperand::CreateMBB(MBB, TargetFlags));
149 return *this;
150 }
151
153 MI->addOperand(*MF, MachineOperand::CreateFI(Idx));
154 return *this;
155 }
156
157 const MachineInstrBuilder &
158 addConstantPoolIndex(unsigned Idx, int Offset = 0,
159 unsigned TargetFlags = 0) const {
160 MI->addOperand(*MF, MachineOperand::CreateCPI(Idx, Offset, TargetFlags));
161 return *this;
162 }
163
164 const MachineInstrBuilder &addTargetIndex(unsigned Idx, int64_t Offset = 0,
165 unsigned TargetFlags = 0) const {
167 TargetFlags));
168 return *this;
169 }
170
172 unsigned TargetFlags = 0) const {
173 MI->addOperand(*MF, MachineOperand::CreateJTI(Idx, TargetFlags));
174 return *this;
175 }
176
178 int64_t Offset = 0,
179 unsigned TargetFlags = 0) const {
180 MI->addOperand(*MF, MachineOperand::CreateGA(GV, Offset, TargetFlags));
181 return *this;
182 }
183
184 const MachineInstrBuilder &addExternalSymbol(const char *FnName,
185 unsigned TargetFlags = 0) const {
186 MI->addOperand(*MF, MachineOperand::CreateES(FnName, TargetFlags));
187 return *this;
188 }
189
191 int64_t Offset = 0,
192 unsigned TargetFlags = 0) const {
193 MI->addOperand(*MF, MachineOperand::CreateBA(BA, Offset, TargetFlags));
194 return *this;
195 }
196
197 const MachineInstrBuilder &addRegMask(const uint32_t *Mask) const {
198 MI->addOperand(*MF, MachineOperand::CreateRegMask(Mask));
199 return *this;
200 }
201
203 MI->addMemOperand(*MF, MMO);
204 return *this;
205 }
206
207 const MachineInstrBuilder &
209 MI->setMemRefs(*MF, MMOs);
210 return *this;
211 }
212
213 const MachineInstrBuilder &cloneMemRefs(const MachineInstr &OtherMI) const {
214 MI->cloneMemRefs(*MF, OtherMI);
215 return *this;
216 }
217
218 const MachineInstrBuilder &
220 MI->cloneMergedMemRefs(*MF, OtherMIs);
221 return *this;
222 }
223
224 const MachineInstrBuilder &add(const MachineOperand &MO) const {
225 MI->addOperand(*MF, MO);
226 return *this;
227 }
228
230 for (const MachineOperand &MO : MOs) {
231 MI->addOperand(*MF, MO);
232 }
233 return *this;
234 }
235
236 const MachineInstrBuilder &addMetadata(const MDNode *MD) const {
237 MI->addOperand(*MF, MachineOperand::CreateMetadata(MD));
238 assert((MI->isDebugValueLike() ? static_cast<bool>(MI->getDebugVariable())
239 : true) &&
240 "first MDNode argument of a DBG_VALUE not a variable");
241 assert((MI->isDebugLabel() ? static_cast<bool>(MI->getDebugLabel())
242 : true) &&
243 "first MDNode argument of a DBG_LABEL not a label");
244 return *this;
245 }
246
247 const MachineInstrBuilder &addCFIIndex(unsigned CFIIndex) const {
248 MI->addOperand(*MF, MachineOperand::CreateCFIIndex(CFIIndex));
249 return *this;
250 }
251
253 MI->addOperand(*MF, MachineOperand::CreateIntrinsicID(ID));
254 return *this;
255 }
256
258 MI->addOperand(*MF, MachineOperand::CreatePredicate(Pred));
259 return *this;
260 }
261
263 MI->addOperand(*MF, MachineOperand::CreateShuffleMask(Val));
264 return *this;
265 }
266
268 unsigned char TargetFlags = 0) const {
269 MI->addOperand(*MF, MachineOperand::CreateMCSymbol(Sym, TargetFlags));
270 return *this;
271 }
272
273 const MachineInstrBuilder &setMIFlags(unsigned Flags) const {
274 MI->setFlags(Flags);
275 return *this;
276 }
277
279 MI->setFlag(Flag);
280 return *this;
281 }
282
283 // Add a displacement from an existing MachineOperand with an added offset.
284 const MachineInstrBuilder &addDisp(const MachineOperand &Disp, int64_t off,
285 unsigned char TargetFlags = 0) const {
286 // If caller specifies new TargetFlags then use it, otherwise the
287 // default behavior is to copy the target flags from the existing
288 // MachineOperand. This means if the caller wants to clear the
289 // target flags it needs to do so explicitly.
290 if (0 == TargetFlags)
291 TargetFlags = Disp.getTargetFlags();
292
293 switch (Disp.getType()) {
294 default:
295 llvm_unreachable("Unhandled operand type in addDisp()");
297 return addImm(Disp.getImm() + off);
299 return addConstantPoolIndex(Disp.getIndex(), Disp.getOffset() + off,
300 TargetFlags);
302 return addGlobalAddress(Disp.getGlobal(), Disp.getOffset() + off,
303 TargetFlags);
305 return addBlockAddress(Disp.getBlockAddress(), Disp.getOffset() + off,
306 TargetFlags);
308 assert(off == 0 && "cannot create offset into jump tables");
309 return addJumpTableIndex(Disp.getIndex(), TargetFlags);
310 }
311 }
312
314 if (MD)
315 MI->setPCSections(*MF, MD);
316 return *this;
317 }
318
319 /// Copy all the implicit operands from OtherMI onto this one.
320 const MachineInstrBuilder &
321 copyImplicitOps(const MachineInstr &OtherMI) const {
322 MI->copyImplicitOps(*MF, OtherMI);
323 return *this;
324 }
325
327 const TargetRegisterInfo &TRI,
328 const RegisterBankInfo &RBI) const {
330 }
331};
332
333/// Set of metadata that should be preserved when using BuildMI(). This provides
334/// a more convenient way of preserving DebugLoc and PCSections.
336public:
337 MIMetadata() = default;
338 MIMetadata(DebugLoc DL, MDNode *PCSections = nullptr)
339 : DL(std::move(DL)), PCSections(PCSections) {}
340 MIMetadata(const DILocation *DI, MDNode *PCSections = nullptr)
341 : DL(DI), PCSections(PCSections) {}
342 explicit MIMetadata(const Instruction &From)
343 : DL(From.getDebugLoc()),
344 PCSections(From.getMetadata(LLVMContext::MD_pcsections)) {}
345 explicit MIMetadata(const MachineInstr &From)
346 : DL(From.getDebugLoc()), PCSections(From.getPCSections()) {}
347
348 const DebugLoc &getDL() const { return DL; }
349 MDNode *getPCSections() const { return PCSections; }
350
351private:
352 DebugLoc DL;
353 MDNode *PCSections = nullptr;
354};
355
356/// Builder interface. Specify how to create the initial instruction itself.
358 const MCInstrDesc &MCID) {
359 return MachineInstrBuilder(MF, MF.CreateMachineInstr(MCID, MIMD.getDL()))
361}
362
363/// This version of the builder sets up the first operand as a
364/// destination virtual register.
366 const MCInstrDesc &MCID, Register DestReg) {
367 return MachineInstrBuilder(MF, MF.CreateMachineInstr(MCID, MIMD.getDL()))
369 .addReg(DestReg, RegState::Define);
370}
371
372/// This version of the builder inserts the newly-built instruction before
373/// the given position in the given MachineBasicBlock, and sets up the first
374/// operand as a destination virtual register.
377 const MIMetadata &MIMD,
378 const MCInstrDesc &MCID, Register DestReg) {
379 MachineFunction &MF = *BB.getParent();
380 MachineInstr *MI = MF.CreateMachineInstr(MCID, MIMD.getDL());
381 BB.insert(I, MI);
382 return MachineInstrBuilder(MF, MI)
384 .addReg(DestReg, RegState::Define);
385}
386
387/// This version of the builder inserts the newly-built instruction before
388/// the given position in the given MachineBasicBlock, and sets up the first
389/// operand as a destination virtual register.
390///
391/// If \c I is inside a bundle, then the newly inserted \a MachineInstr is
392/// added to the same bundle.
395 const MIMetadata &MIMD,
396 const MCInstrDesc &MCID, Register DestReg) {
397 MachineFunction &MF = *BB.getParent();
398 MachineInstr *MI = MF.CreateMachineInstr(MCID, MIMD.getDL());
399 BB.insert(I, MI);
400 return MachineInstrBuilder(MF, MI)
402 .addReg(DestReg, RegState::Define);
403}
404
406 const MIMetadata &MIMD,
407 const MCInstrDesc &MCID, Register DestReg) {
408 // Calling the overload for instr_iterator is always correct. However, the
409 // definition is not available in headers, so inline the check.
410 if (I.isInsideBundle())
411 return BuildMI(BB, MachineBasicBlock::instr_iterator(I), MIMD, MCID,
412 DestReg);
413 return BuildMI(BB, MachineBasicBlock::iterator(I), MIMD, MCID, DestReg);
414}
415
417 const MIMetadata &MIMD,
418 const MCInstrDesc &MCID, Register DestReg) {
419 return BuildMI(BB, *I, MIMD, MCID, DestReg);
420}
421
422/// This version of the builder inserts the newly-built instruction before the
423/// given position in the given MachineBasicBlock, and does NOT take a
424/// destination register.
427 const MIMetadata &MIMD,
428 const MCInstrDesc &MCID) {
429 MachineFunction &MF = *BB.getParent();
430 MachineInstr *MI = MF.CreateMachineInstr(MCID, MIMD.getDL());
431 BB.insert(I, MI);
433}
434
437 const MIMetadata &MIMD,
438 const MCInstrDesc &MCID) {
439 MachineFunction &MF = *BB.getParent();
440 MachineInstr *MI = MF.CreateMachineInstr(MCID, MIMD.getDL());
441 BB.insert(I, MI);
443}
444
446 const MIMetadata &MIMD,
447 const MCInstrDesc &MCID) {
448 // Calling the overload for instr_iterator is always correct. However, the
449 // definition is not available in headers, so inline the check.
450 if (I.isInsideBundle())
451 return BuildMI(BB, MachineBasicBlock::instr_iterator(I), MIMD, MCID);
452 return BuildMI(BB, MachineBasicBlock::iterator(I), MIMD, MCID);
453}
454
456 const MIMetadata &MIMD,
457 const MCInstrDesc &MCID) {
458 return BuildMI(BB, *I, MIMD, MCID);
459}
460
461/// This version of the builder inserts the newly-built instruction at the end
462/// of the given MachineBasicBlock, and does NOT take a destination register.
464 const MIMetadata &MIMD,
465 const MCInstrDesc &MCID) {
466 return BuildMI(*BB, BB->end(), MIMD, MCID);
467}
468
469/// This version of the builder inserts the newly-built instruction at the
470/// end of the given MachineBasicBlock, and sets up the first operand as a
471/// destination virtual register.
473 const MIMetadata &MIMD,
474 const MCInstrDesc &MCID, Register DestReg) {
475 return BuildMI(*BB, BB->end(), MIMD, MCID, DestReg);
476}
477
478/// This version of the builder builds a DBG_VALUE intrinsic
479/// for either a value in a register or a register-indirect
480/// address. The convention is that a DBG_VALUE is indirect iff the
481/// second operand is an immediate.
482MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL,
483 const MCInstrDesc &MCID, bool IsIndirect,
484 Register Reg, const MDNode *Variable,
485 const MDNode *Expr);
486
487/// This version of the builder builds a DBG_VALUE or DBG_VALUE_LIST intrinsic
488/// for a MachineOperand.
489MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL,
490 const MCInstrDesc &MCID, bool IsIndirect,
491 ArrayRef<MachineOperand> MOs,
492 const MDNode *Variable, const MDNode *Expr);
493
494/// This version of the builder builds a DBG_VALUE intrinsic
495/// for either a value in a register or a register-indirect
496/// address and inserts it at position I.
497MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
498 MachineBasicBlock::iterator I, const DebugLoc &DL,
499 const MCInstrDesc &MCID, bool IsIndirect,
500 Register Reg, const MDNode *Variable,
501 const MDNode *Expr);
502
503/// This version of the builder builds a DBG_VALUE, DBG_INSTR_REF, or
504/// DBG_VALUE_LIST intrinsic for a machine operand and inserts it at position I.
505MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
506 MachineBasicBlock::iterator I, const DebugLoc &DL,
507 const MCInstrDesc &MCID, bool IsIndirect,
508 ArrayRef<MachineOperand> MOs,
509 const MDNode *Variable, const MDNode *Expr);
510
511/// Clone a DBG_VALUE whose value has been spilled to FrameIndex.
512MachineInstr *buildDbgValueForSpill(MachineBasicBlock &BB,
514 const MachineInstr &Orig, int FrameIndex,
515 Register SpillReg);
516MachineInstr *
518 const MachineInstr &Orig, int FrameIndex,
519 SmallVectorImpl<const MachineOperand *> &SpilledOperands);
520
521/// Update a DBG_VALUE whose value has been spilled to FrameIndex. Useful when
522/// modifying an instruction in place while iterating over a basic block.
523void updateDbgValueForSpill(MachineInstr &Orig, int FrameIndex, Register Reg);
524
525inline unsigned getDefRegState(bool B) {
526 return B ? RegState::Define : 0;
527}
528inline unsigned getImplRegState(bool B) {
529 return B ? RegState::Implicit : 0;
530}
531inline unsigned getKillRegState(bool B) {
532 return B ? RegState::Kill : 0;
533}
534inline unsigned getDeadRegState(bool B) {
535 return B ? RegState::Dead : 0;
536}
537inline unsigned getUndefRegState(bool B) {
538 return B ? RegState::Undef : 0;
539}
540inline unsigned getInternalReadRegState(bool B) {
541 return B ? RegState::InternalRead : 0;
542}
543inline unsigned getDebugRegState(bool B) {
544 return B ? RegState::Debug : 0;
545}
546inline unsigned getRenamableRegState(bool B) {
547 return B ? RegState::Renamable : 0;
548}
549
550/// Get all register state flags from machine operand \p RegOp.
551inline unsigned getRegState(const MachineOperand &RegOp) {
552 assert(RegOp.isReg() && "Not a register operand");
553 return getDefRegState(RegOp.isDef()) | getImplRegState(RegOp.isImplicit()) |
554 getKillRegState(RegOp.isKill()) | getDeadRegState(RegOp.isDead()) |
555 getUndefRegState(RegOp.isUndef()) |
557 getDebugRegState(RegOp.isDebug()) |
559 RegOp.isRenamable());
560}
561
562/// Helper class for constructing bundles of MachineInstrs.
563///
564/// MIBundleBuilder can create a bundle from scratch by inserting new
565/// MachineInstrs one at a time, or it can create a bundle from a sequence of
566/// existing MachineInstrs in a basic block.
571
572public:
573 /// Create an MIBundleBuilder that inserts instructions into a new bundle in
574 /// BB above the bundle or instruction at Pos.
576 : MBB(BB), Begin(Pos.getInstrIterator()), End(Begin) {}
577
578 /// Create a bundle from the sequence of instructions between B and E.
581 : MBB(BB), Begin(B.getInstrIterator()), End(E.getInstrIterator()) {
582 assert(B != E && "No instructions to bundle");
583 ++B;
584 while (B != E) {
585 MachineInstr &MI = *B;
586 ++B;
587 MI.bundleWithPred();
588 }
589 }
590
591 /// Create an MIBundleBuilder representing an existing instruction or bundle
592 /// that has MI as its head.
594 : MBB(*MI->getParent()), Begin(MI),
595 End(getBundleEnd(MI->getIterator())) {}
596
597 /// Return a reference to the basic block containing this bundle.
598 MachineBasicBlock &getMBB() const { return MBB; }
599
600 /// Return true if no instructions have been inserted in this bundle yet.
601 /// Empty bundles aren't representable in a MachineBasicBlock.
602 bool empty() const { return Begin == End; }
603
604 /// Return an iterator to the first bundled instruction.
605 MachineBasicBlock::instr_iterator begin() const { return Begin; }
606
607 /// Return an iterator beyond the last bundled instruction.
609
610 /// Insert MI into this bundle before I which must point to an instruction in
611 /// the bundle, or end().
613 MachineInstr *MI) {
614 MBB.insert(I, MI);
615 if (I == Begin) {
616 if (!empty())
617 MI->bundleWithSucc();
618 Begin = MI->getIterator();
619 return *this;
620 }
621 if (I == End) {
622 MI->bundleWithPred();
623 return *this;
624 }
625 // MI was inserted in the middle of the bundle, so its neighbors' flags are
626 // already fine. Update MI's bundle flags manually.
629 return *this;
630 }
631
632 /// Insert MI into MBB by prepending it to the instructions in the bundle.
633 /// MI will become the first instruction in the bundle.
635 return insert(begin(), MI);
636 }
637
638 /// Insert MI into MBB by appending it to the instructions in the bundle.
639 /// MI will become the last instruction in the bundle.
641 return insert(end(), MI);
642 }
643};
644
645} // end namespace llvm
646
647#endif // LLVM_CODEGEN_MACHINEINSTRBUILDER_H
unsigned SubReg
MachineBasicBlock & MBB
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
static const Function * getParent(const Value *V)
BlockVerifier::State From
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
const HexagonInstrInfo * TII
IRTranslator LLVM IR MI
#define F(x, y, z)
Definition: MD5.cpp:55
#define I(x, y, z)
Definition: MD5.cpp:58
static DebugLoc getDebugLoc(MachineBasicBlock::instr_iterator FirstMI, MachineBasicBlock::instr_iterator LastMI)
Return the first found DebugLoc that has a DILocation, given a range of instructions.
unsigned const TargetRegisterInfo * TRI
unsigned Reg
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
The address of a basic block.
Definition: Constants.h:875
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:718
ConstantFP - Floating Point Values [float, double].
Definition: Constants.h:256
This is the shared class of boolean and integer constants.
Definition: Constants.h:78
Debug location.
A debug info location.
Definition: DebugLoc.h:33
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:67
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:198
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:41
Metadata node.
Definition: Metadata.h:943
Helper class for constructing bundles of MachineInstrs.
MachineBasicBlock::instr_iterator end() const
Return an iterator beyond the last bundled instruction.
MachineBasicBlock::instr_iterator begin() const
Return an iterator to the first bundled instruction.
MIBundleBuilder & append(MachineInstr *MI)
Insert MI into MBB by appending it to the instructions in the bundle.
MIBundleBuilder(MachineBasicBlock &BB, MachineBasicBlock::iterator B, MachineBasicBlock::iterator E)
Create a bundle from the sequence of instructions between B and E.
MIBundleBuilder(MachineBasicBlock &BB, MachineBasicBlock::iterator Pos)
Create an MIBundleBuilder that inserts instructions into a new bundle in BB above the bundle or instr...
MIBundleBuilder & insert(MachineBasicBlock::instr_iterator I, MachineInstr *MI)
Insert MI into this bundle before I which must point to an instruction in the bundle,...
MachineBasicBlock & getMBB() const
Return a reference to the basic block containing this bundle.
MIBundleBuilder & prepend(MachineInstr *MI)
Insert MI into MBB by prepending it to the instructions in the bundle.
bool empty() const
Return true if no instructions have been inserted in this bundle yet.
MIBundleBuilder(MachineInstr *MI)
Create an MIBundleBuilder representing an existing instruction or bundle that has MI as its head.
Set of metadata that should be preserved when using BuildMI().
const DebugLoc & getDL() const
MIMetadata()=default
MIMetadata(DebugLoc DL, MDNode *PCSections=nullptr)
MIMetadata(const DILocation *DI, MDNode *PCSections=nullptr)
MIMetadata(const Instruction &From)
MIMetadata(const MachineInstr &From)
MDNode * getPCSections() const
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
Instructions::iterator instr_iterator
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
MachineInstrBundleIterator< MachineInstr > iterator
MachineInstr * CreateMachineInstr(const MCInstrDesc &MCID, DebugLoc DL, bool NoImplicit=false)
CreateMachineInstr - Allocate a new MachineInstr.
const MachineInstrBuilder & cloneMergedMemRefs(ArrayRef< const MachineInstr * > OtherMIs) const
const MachineInstrBuilder & addTargetIndex(unsigned Idx, int64_t Offset=0, unsigned TargetFlags=0) const
Register getReg(unsigned Idx) const
Get the register for the operand index.
const MachineInstrBuilder & setMemRefs(ArrayRef< MachineMemOperand * > MMOs) const
const MachineInstrBuilder & addExternalSymbol(const char *FnName, unsigned TargetFlags=0) const
const MachineInstrBuilder & addCImm(const ConstantInt *Val) const
const MachineInstrBuilder & addCFIIndex(unsigned CFIIndex) const
MachineInstrBuilder(MachineFunction &F, MachineInstr *I)
Create a MachineInstrBuilder for manipulating an existing instruction.
const MachineInstrBuilder & setMIFlag(MachineInstr::MIFlag Flag) const
MachineInstr * operator->() const
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & addPredicate(CmpInst::Predicate Pred) const
const MachineInstrBuilder & addBlockAddress(const BlockAddress *BA, int64_t Offset=0, unsigned TargetFlags=0) const
const MachineInstrBuilder & add(const MachineOperand &MO) const
const MachineInstrBuilder & addIntrinsicID(Intrinsic::ID ID) const
const MachineInstrBuilder & addMetadata(const MDNode *MD) const
const MachineInstrBuilder & addSym(MCSymbol *Sym, unsigned char TargetFlags=0) const
const MachineInstrBuilder & addShuffleMask(ArrayRef< int > Val) const
MachineInstrBuilder(MachineFunction &F, MachineBasicBlock::iterator I)
const MachineInstrBuilder & addFrameIndex(int Idx) const
const MachineInstrBuilder & addConstantPoolIndex(unsigned Idx, int Offset=0, unsigned TargetFlags=0) const
const MachineInstrBuilder & addRegMask(const uint32_t *Mask) const
const MachineInstrBuilder & add(ArrayRef< MachineOperand > MOs) const
const MachineInstrBuilder & addGlobalAddress(const GlobalValue *GV, int64_t Offset=0, unsigned TargetFlags=0) const
const MachineInstrBuilder & addDisp(const MachineOperand &Disp, int64_t off, unsigned char TargetFlags=0) const
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
const MachineInstrBuilder & addFPImm(const ConstantFP *Val) const
bool constrainAllUses(const TargetInstrInfo &TII, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI) const
const MachineInstrBuilder & addJumpTableIndex(unsigned Idx, unsigned TargetFlags=0) const
const MachineInstrBuilder & setPCSections(MDNode *MD) const
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
const MachineInstrBuilder & cloneMemRefs(const MachineInstr &OtherMI) const
const MachineInstrBuilder & addUse(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register use operand.
const MachineInstrBuilder & setMIFlags(unsigned Flags) const
const MachineInstrBuilder & copyImplicitOps(const MachineInstr &OtherMI) const
Copy all the implicit operands from OtherMI onto this one.
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
MachineInstr * getInstr() const
If conversion operators fail, use this method to get the MachineInstr explicitly.
const MachineInstrBuilder & addDef(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register definition operand.
Representation of each machine instruction.
Definition: MachineInstr.h:68
A description of a memory reference used in the backend.
MachineOperand class - Representation of each machine instruction operand.
static MachineOperand CreateMCSymbol(MCSymbol *Sym, unsigned TargetFlags=0)
const GlobalValue * getGlobal() const
static MachineOperand CreateES(const char *SymName, unsigned TargetFlags=0)
static MachineOperand CreateFPImm(const ConstantFP *CFP)
int64_t getImm() const
bool isImplicit() const
static MachineOperand CreateCFIIndex(unsigned CFIIndex)
static MachineOperand CreateRegMask(const uint32_t *Mask)
CreateRegMask - Creates a register mask operand referencing Mask.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
static MachineOperand CreateCImm(const ConstantInt *CI)
bool isRenamable() const
isRenamable - Returns true if this register may be renamed, i.e.
static MachineOperand CreateMetadata(const MDNode *Meta)
const BlockAddress * getBlockAddress() const
static MachineOperand CreatePredicate(unsigned Pred)
unsigned getTargetFlags() const
static MachineOperand CreateImm(int64_t Val)
static MachineOperand CreateShuffleMask(ArrayRef< int > Mask)
MachineOperandType getType() const
getType - Returns the MachineOperandType for this operand.
static MachineOperand CreateJTI(unsigned Idx, unsigned TargetFlags=0)
Register getReg() const
getReg - Returns the register number.
static MachineOperand CreateGA(const GlobalValue *GV, int64_t Offset, unsigned TargetFlags=0)
bool isInternalRead() const
static MachineOperand CreateBA(const BlockAddress *BA, int64_t Offset, unsigned TargetFlags=0)
static MachineOperand CreateCPI(unsigned Idx, int Offset, unsigned TargetFlags=0)
@ MO_Immediate
Immediate operand.
@ MO_ConstantPoolIndex
Address of indexed Constant in Constant Pool.
@ MO_GlobalAddress
Address of a global value.
@ MO_BlockAddress
Address of a basic block.
@ MO_JumpTableIndex
Address of indexed Jump Table for switch.
static MachineOperand CreateReg(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)
static MachineOperand CreateTargetIndex(unsigned Idx, int64_t Offset, unsigned TargetFlags=0)
static MachineOperand CreateMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0)
int64_t getOffset() const
Return the offset from the symbol in this operand.
static MachineOperand CreateIntrinsicID(Intrinsic::ID ID)
static MachineOperand CreateFI(int Idx)
Holds all the information related to register banks.
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
bool isPhysical() const
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:97
TargetInstrInfo - Interface to description of machine instruction set.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ Implicit
Not emitted register (e.g. carry, or temporary result).
@ Debug
Register 'use' is for debugging purpose.
@ Dead
Unused definition.
@ Renamable
Register that may be renamed.
@ Define
Register definition.
@ InternalRead
Register reads a value that is defined inside the same instruction or bundle.
@ Kill
The last use of a register.
@ Undef
Value of the register doesn't matter.
@ EarlyClobber
Register definition happens before uses.
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Offset
Definition: DWP.cpp:406
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
void updateDbgValueForSpill(MachineInstr &Orig, int FrameIndex, Register Reg)
Update a DBG_VALUE whose value has been spilled to FrameIndex.
bool constrainSelectedInstRegOperands(MachineInstr &I, const TargetInstrInfo &TII, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI)
Mutate the newly-selected instruction I to constrain its (possibly generic) virtual register operands...
Definition: Utils.cpp:152
unsigned getDeadRegState(bool B)
unsigned getImplRegState(bool B)
MachineBasicBlock::instr_iterator getBundleEnd(MachineBasicBlock::instr_iterator I)
Returns an iterator pointing beyond the bundle containing I.
unsigned getInternalReadRegState(bool B)
unsigned getDebugRegState(bool B)
unsigned getUndefRegState(bool B)
unsigned getRegState(const MachineOperand &RegOp)
Get all register state flags from machine operand RegOp.
unsigned getDefRegState(bool B)
unsigned getKillRegState(bool B)
unsigned getRenamableRegState(bool B)
OutputIt move(R &&Range, OutputIt Out)
Provide wrappers to std::move which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1862
MachineInstr * buildDbgValueForSpill(MachineBasicBlock &BB, MachineBasicBlock::iterator I, const MachineInstr &Orig, int FrameIndex, Register SpillReg)
Clone a DBG_VALUE whose value has been spilled to FrameIndex.
Definition: BitVector.h:851