LLVM  13.0.0git
ARMBaseInfo.h
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1 //===-- ARMBaseInfo.h - Top level definitions for ARM -------- --*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains small standalone helper functions and enum definitions for
10 // the ARM target useful for the compiler back-end and the MC libraries.
11 // As such, it deliberately does not include references to LLVM core
12 // code gen types, passes, etc..
13 //
14 //===----------------------------------------------------------------------===//
15 
16 #ifndef LLVM_LIB_TARGET_ARM_MCTARGETDESC_ARMBASEINFO_H
17 #define LLVM_LIB_TARGET_ARM_MCTARGETDESC_ARMBASEINFO_H
18 
19 #include "ARMMCTargetDesc.h"
21 #include "Utils/ARMBaseInfo.h"
22 
23 namespace llvm {
24 
25 namespace ARM_PROC {
26  enum IMod {
27  IE = 2,
28  ID = 3
29  };
30 
31  enum IFlags {
32  F = 1,
33  I = 2,
34  A = 4
35  };
36 
37  inline static const char *IFlagsToString(unsigned val) {
38  switch (val) {
39  default: llvm_unreachable("Unknown iflags operand");
40  case F: return "f";
41  case I: return "i";
42  case A: return "a";
43  }
44  }
45 
46  inline static const char *IModToString(unsigned val) {
47  switch (val) {
48  default: llvm_unreachable("Unknown imod operand");
49  case IE: return "ie";
50  case ID: return "id";
51  }
52  }
53 }
54 
55 namespace ARM_MB {
56  // The Memory Barrier Option constants map directly to the 4-bit encoding of
57  // the option field for memory barrier operations.
58  enum MemBOpt {
60  OSHLD = 1,
61  OSHST = 2,
62  OSH = 3,
64  NSHLD = 5,
65  NSHST = 6,
66  NSH = 7,
68  ISHLD = 9,
69  ISHST = 10,
70  ISH = 11,
72  LD = 13,
73  ST = 14,
74  SY = 15
75  };
76 
77  inline static const char *MemBOptToString(unsigned val, bool HasV8) {
78  switch (val) {
79  default: llvm_unreachable("Unknown memory operation");
80  case SY: return "sy";
81  case ST: return "st";
82  case LD: return HasV8 ? "ld" : "#0xd";
83  case RESERVED_12: return "#0xc";
84  case ISH: return "ish";
85  case ISHST: return "ishst";
86  case ISHLD: return HasV8 ? "ishld" : "#0x9";
87  case RESERVED_8: return "#0x8";
88  case NSH: return "nsh";
89  case NSHST: return "nshst";
90  case NSHLD: return HasV8 ? "nshld" : "#0x5";
91  case RESERVED_4: return "#0x4";
92  case OSH: return "osh";
93  case OSHST: return "oshst";
94  case OSHLD: return HasV8 ? "oshld" : "#0x1";
95  case RESERVED_0: return "#0x0";
96  }
97  }
98 } // namespace ARM_MB
99 
100 namespace ARM_TSB {
102  CSYNC = 0
103  };
104 
105  inline static const char *TraceSyncBOptToString(unsigned val) {
106  switch (val) {
107  default:
108  llvm_unreachable("Unknown trace synchronization barrier operation");
109  case CSYNC: return "csync";
110  }
111  }
112 } // namespace ARM_TSB
113 
114 namespace ARM_ISB {
131  SY = 15
132  };
133 
134  inline static const char *InstSyncBOptToString(unsigned val) {
135  switch (val) {
136  default:
137  llvm_unreachable("Unknown memory operation");
138  case RESERVED_0: return "#0x0";
139  case RESERVED_1: return "#0x1";
140  case RESERVED_2: return "#0x2";
141  case RESERVED_3: return "#0x3";
142  case RESERVED_4: return "#0x4";
143  case RESERVED_5: return "#0x5";
144  case RESERVED_6: return "#0x6";
145  case RESERVED_7: return "#0x7";
146  case RESERVED_8: return "#0x8";
147  case RESERVED_9: return "#0x9";
148  case RESERVED_10: return "#0xa";
149  case RESERVED_11: return "#0xb";
150  case RESERVED_12: return "#0xc";
151  case RESERVED_13: return "#0xd";
152  case RESERVED_14: return "#0xe";
153  case SY: return "sy";
154  }
155  }
156 } // namespace ARM_ISB
157 
158 /// isARMLowRegister - Returns true if the register is a low register (r0-r7).
159 ///
160 static inline bool isARMLowRegister(unsigned Reg) {
161  using namespace ARM;
162  switch (Reg) {
163  case R0: case R1: case R2: case R3:
164  case R4: case R5: case R6: case R7:
165  return true;
166  default:
167  return false;
168  }
169 }
170 
171 /// ARMII - This namespace holds all of the target specific flags that
172 /// instruction info tracks.
173 ///
174 namespace ARMII {
175 
176  /// ARM Index Modes
177  enum IndexMode {
182  };
183 
184  /// ARM Addressing Modes
185  enum AddrMode {
196  AddrModeT1_s = 10, // i8 * 4 for pc and sp relative data
200  AddrModeT2_pc = 14, // +/- i12 for pc relative data
201  AddrModeT2_i8s4 = 15, // i8 * 4
203  AddrMode5FP16 = 17, // i8 * 2
204  AddrModeT2_ldrex = 18, // i8 * 4, with unscaled offset in MCInst
205  AddrModeT2_i7s4 = 19, // i7 * 4
206  AddrModeT2_i7s2 = 20, // i7 * 2
207  AddrModeT2_i7 = 21, // i7 * 1
208  };
209 
210  inline static const char *AddrModeToString(AddrMode addrmode) {
211  switch (addrmode) {
212  case AddrModeNone: return "AddrModeNone";
213  case AddrMode1: return "AddrMode1";
214  case AddrMode2: return "AddrMode2";
215  case AddrMode3: return "AddrMode3";
216  case AddrMode4: return "AddrMode4";
217  case AddrMode5: return "AddrMode5";
218  case AddrMode5FP16: return "AddrMode5FP16";
219  case AddrMode6: return "AddrMode6";
220  case AddrModeT1_1: return "AddrModeT1_1";
221  case AddrModeT1_2: return "AddrModeT1_2";
222  case AddrModeT1_4: return "AddrModeT1_4";
223  case AddrModeT1_s: return "AddrModeT1_s";
224  case AddrModeT2_i12: return "AddrModeT2_i12";
225  case AddrModeT2_i8: return "AddrModeT2_i8";
226  case AddrModeT2_so: return "AddrModeT2_so";
227  case AddrModeT2_pc: return "AddrModeT2_pc";
228  case AddrModeT2_i8s4: return "AddrModeT2_i8s4";
229  case AddrMode_i12: return "AddrMode_i12";
230  case AddrModeT2_ldrex:return "AddrModeT2_ldrex";
231  case AddrModeT2_i7s4: return "AddrModeT2_i7s4";
232  case AddrModeT2_i7s2: return "AddrModeT2_i7s2";
233  case AddrModeT2_i7: return "AddrModeT2_i7";
234  }
235  }
236 
237  /// Target Operand Flag enum.
238  enum TOF {
239  //===------------------------------------------------------------------===//
240  // ARM Specific MachineOperand flags.
241 
243 
244  /// MO_LO16 - On a symbol operand, this represents a relocation containing
245  /// lower 16 bit of the address. Used only via movw instruction.
246  MO_LO16 = 0x1,
247 
248  /// MO_HI16 - On a symbol operand, this represents a relocation containing
249  /// higher 16 bit of the address. Used only via movt instruction.
250  MO_HI16 = 0x2,
251 
252  /// MO_OPTION_MASK - Most flags are mutually exclusive; this mask selects
253  /// just that part of the flag set.
255 
256  /// MO_COFFSTUB - On a symbol operand "FOO", this indicates that the
257  /// reference is actually to the ".refptr.FOO" symbol. This is used for
258  /// stub symbols on windows.
259  MO_COFFSTUB = 0x4,
260 
261  /// MO_GOT - On a symbol operand, this represents a GOT relative relocation.
262  MO_GOT = 0x8,
263 
264  /// MO_SBREL - On a symbol operand, this represents a static base relative
265  /// relocation. Used in movw and movt instructions.
266  MO_SBREL = 0x10,
267 
268  /// MO_DLLIMPORT - On a symbol operand, this represents that the reference
269  /// to the symbol is for an import stub. This is used for DLL import
270  /// storage class indication on Windows.
271  MO_DLLIMPORT = 0x20,
272 
273  /// MO_SECREL - On a symbol operand this indicates that the immediate is
274  /// the offset from beginning of section.
275  ///
276  /// This is the TLS offset for the COFF/Windows TLS mechanism.
277  MO_SECREL = 0x40,
278 
279  /// MO_NONLAZY - This is an independent flag, on a symbol operand "FOO" it
280  /// represents a symbol which, if indirect, will get special Darwin mangling
281  /// as a non-lazy-ptr indirect symbol (i.e. "L_FOO$non_lazy_ptr"). Can be
282  /// combined with MO_LO16, MO_HI16 or MO_NO_FLAG (in a constant-pool, for
283  /// example).
284  MO_NONLAZY = 0x80,
285 
286  // It's undefined behaviour if an enum overflows the range between its
287  // smallest and largest values, but since these are |ed together, it can
288  // happen. Put a sentinel in (values of this enum are stored as "unsigned
289  // char").
291  };
292 
293  enum {
294  //===------------------------------------------------------------------===//
295  // Instruction Flags.
296 
297  //===------------------------------------------------------------------===//
298  // This four-bit field describes the addressing mode used.
299  AddrModeMask = 0x1f, // The AddrMode enums are declared in ARMBaseInfo.h
300 
301  // IndexMode - Unindex, pre-indexed, or post-indexed are valid for load
302  // and store ops only. Generic "updating" flag is used for ld/st multiple.
303  // The index mode enums are declared in ARMBaseInfo.h
306 
307  //===------------------------------------------------------------------===//
308  // Instruction encoding formats.
309  //
311  FormMask = 0x3f << FormShift,
312 
313  // Pseudo instructions
315 
316  // Multiply instructions
318 
319  // Branch instructions
320  BrFrm = 2 << FormShift,
322 
323  // Data Processing instructions
324  DPFrm = 4 << FormShift,
326 
327  // Load and Store
328  LdFrm = 6 << FormShift,
329  StFrm = 7 << FormShift,
333 
335 
336  // Miscellaneous arithmetic instructions
338  SatFrm = 13 << FormShift,
339 
340  // Extend instructions
341  ExtFrm = 14 << FormShift,
342 
343  // VFP formats
354 
355  // Thumb format
357 
358  // Miscelleaneous format
360 
361  // NEON formats
378 
379  //===------------------------------------------------------------------===//
380  // Misc flags.
381 
382  // UnaryDP - Indicates this is a unary data processing instruction, i.e.
383  // it doesn't have a Rn operand.
384  UnaryDP = 1 << 13,
385 
386  // Xform16Bit - Indicates this Thumb2 instruction may be transformed into
387  // a 16-bit Thumb instruction if certain conditions are met.
388  Xform16Bit = 1 << 14,
389 
390  // ThumbArithFlagSetting - The instruction is a 16-bit flag setting Thumb
391  // instruction. Used by the parser to determine whether to require the 'S'
392  // suffix on the mnemonic (when not in an IT block) or preclude it (when
393  // in an IT block).
395 
396  // Whether an instruction can be included in an MVE tail-predicated loop,
397  // though extra validity checks may need to be performed too.
399 
400  // Whether an instruction writes to the top/bottom half of a vector element
401  // and leaves the other half untouched.
403 
404  // Whether the instruction produces a scalar result from vector operands.
406 
407  // Whether this instruction produces a vector result that is larger than
408  // its input, typically reading from the top/bottom halves of the input(s).
409  DoubleWidthResult = 1 << 23,
410 
411  //===------------------------------------------------------------------===//
412  // Code domain.
420 
421  //===------------------------------------------------------------------===//
422  // Field shifts - such shifts are used to set field while generating
423  // machine instructions.
424  //
425  // FIXME: This list will need adjusting/fixing as the MC code emitter
426  // takes shape and the ARMCodeEmitter.cpp bits go away.
428 
449  };
450 
451 } // end namespace ARMII
452 
453 } // end namespace llvm;
454 
455 #endif
llvm::ARMII::UnaryDP
@ UnaryDP
Definition: ARMBaseInfo.h:384
llvm::ARMII::N3RegCplxFrm
@ N3RegCplxFrm
Definition: ARMBaseInfo.h:377
llvm::ARMII::Pseudo
@ Pseudo
Definition: ARMBaseInfo.h:314
llvm::ARMII::FormShift
@ FormShift
Definition: ARMBaseInfo.h:310
llvm::ARM_PROC::ID
@ ID
Definition: ARMBaseInfo.h:28
llvm::ARMII::TOF
TOF
Target Operand Flag enum.
Definition: ARMBaseInfo.h:238
llvm::ARMII::AddrMode4
@ AddrMode4
Definition: ARMBaseInfo.h:190
llvm
Definition: AllocatorList.h:23
llvm::ARMII::MO_HI16
@ MO_HI16
MO_HI16 - On a symbol operand, this represents a relocation containing higher 16 bit of the address.
Definition: ARMBaseInfo.h:250
Reg
unsigned Reg
Definition: MachineSink.cpp:1566
llvm::ARMII::VFPConv2Frm
@ VFPConv2Frm
Definition: ARMBaseInfo.h:347
llvm::ARM_ISB::InstSyncBOptToString
static const char * InstSyncBOptToString(unsigned val)
Definition: ARMBaseInfo.h:134
llvm::ARMII::AddrModeT2_ldrex
@ AddrModeT2_ldrex
Definition: ARMBaseInfo.h:204
llvm::ARMII::BrMiscFrm
@ BrMiscFrm
Definition: ARMBaseInfo.h:321
ARMMCTargetDesc.h
llvm::ARMII::DPFrm
@ DPFrm
Definition: ARMBaseInfo.h:324
llvm::ARM_MB::RESERVED_0
@ RESERVED_0
Definition: ARMBaseInfo.h:59
llvm::ARMII::AddrModeT2_pc
@ AddrModeT2_pc
Definition: ARMBaseInfo.h:200
llvm::ARMII::W_BitShift
@ W_BitShift
Definition: ARMBaseInfo.h:442
llvm::ARMII::ArithMiscFrm
@ ArithMiscFrm
Definition: ARMBaseInfo.h:337
llvm::ARMII::NGetLnFrm
@ NGetLnFrm
Definition: ARMBaseInfo.h:362
llvm::ARMII::ShiftImmShift
@ ShiftImmShift
Definition: ARMBaseInfo.h:430
llvm::ARMII::AddrModeT2_i8s4
@ AddrModeT2_i8s4
Definition: ARMBaseInfo.h:201
llvm::ARM_MB::LD
@ LD
Definition: ARMBaseInfo.h:72
llvm::ARMII::NLdStFrm
@ NLdStFrm
Definition: ARMBaseInfo.h:365
llvm::ARM_MB::SY
@ SY
Definition: ARMBaseInfo.h:74
llvm::ARMII::DomainShift
@ DomainShift
Definition: ARMBaseInfo.h:413
llvm::ARMII::MO_COFFSTUB
@ MO_COFFSTUB
MO_COFFSTUB - On a symbol operand "FOO", this indicates that the reference is actually to the "....
Definition: ARMBaseInfo.h:259
ErrorHandling.h
llvm::ARMII::CondShift
@ CondShift
Definition: ARMBaseInfo.h:448
llvm::ARMII::DoubleWidthResult
@ DoubleWidthResult
Definition: ARMBaseInfo.h:409
llvm::ARMII::I_BitShift
@ I_BitShift
Definition: ARMBaseInfo.h:447
llvm::ARMII::DomainNEONA8
@ DomainNEONA8
Definition: ARMBaseInfo.h:418
llvm::ARMII::MO_UNUSED_MAXIMUM
@ MO_UNUSED_MAXIMUM
Definition: ARMBaseInfo.h:290
llvm::ARMII::AddrMode3
@ AddrMode3
Definition: ARMBaseInfo.h:189
llvm::ARMII::D_BitShift
@ D_BitShift
Definition: ARMBaseInfo.h:444
llvm::ARMII::NVTBLFrm
@ NVTBLFrm
Definition: ARMBaseInfo.h:376
llvm::ARMII::AddrMode2
@ AddrMode2
Definition: ARMBaseInfo.h:188
R4
#define R4(n)
llvm::ARMII::MO_DLLIMPORT
@ MO_DLLIMPORT
MO_DLLIMPORT - On a symbol operand, this represents that the reference to the symbol is for an import...
Definition: ARMBaseInfo.h:271
llvm::ARMII::ThumbFrm
@ ThumbFrm
Definition: ARMBaseInfo.h:356
llvm::ARMII::AddrModeT1_4
@ AddrModeT1_4
Definition: ARMBaseInfo.h:195
llvm::ARMII::StFrm
@ StFrm
Definition: ARMBaseInfo.h:329
llvm::ARMII::AddrMode5FP16
@ AddrMode5FP16
Definition: ARMBaseInfo.h:203
llvm::ARMII::RegRsShift
@ RegRsShift
Definition: ARMBaseInfo.h:435
llvm::ARM_ISB::RESERVED_8
@ RESERVED_8
Definition: ARMBaseInfo.h:124
llvm::ARMII::IndexModeMask
@ IndexModeMask
Definition: ARMBaseInfo.h:305
llvm::ARMII::IndexMode
IndexMode
ARM Index Modes.
Definition: ARMBaseInfo.h:177
llvm::ARM_ISB::RESERVED_6
@ RESERVED_6
Definition: ARMBaseInfo.h:122
llvm::ARMII::N2RegVShLFrm
@ N2RegVShLFrm
Definition: ARMBaseInfo.h:370
llvm::ARMII::N3RegFrm
@ N3RegFrm
Definition: ARMBaseInfo.h:372
llvm::ARMII::RegRdHiShift
@ RegRdHiShift
Definition: ARMBaseInfo.h:439
llvm::ARMII::P_BitShift
@ P_BitShift
Definition: ARMBaseInfo.h:446
llvm::ARM_MB::OSHST
@ OSHST
Definition: ARMBaseInfo.h:61
llvm::ARMII::AddrMode_i12
@ AddrMode_i12
Definition: ARMBaseInfo.h:202
llvm::ARMII::MO_NO_FLAG
@ MO_NO_FLAG
Definition: ARMBaseInfo.h:242
llvm::ARMII::NVMulSLFrm
@ NVMulSLFrm
Definition: ARMBaseInfo.h:375
R2
#define R2(n)
llvm::ARMII::StMiscFrm
@ StMiscFrm
Definition: ARMBaseInfo.h:331
llvm::ARMII::ShiftTypeShift
@ ShiftTypeShift
Definition: ARMBaseInfo.h:427
llvm::ARM_PROC::A
@ A
Definition: ARMBaseInfo.h:34
llvm::ARM_ISB::RESERVED_10
@ RESERVED_10
Definition: ARMBaseInfo.h:126
llvm::ARMII::MulFrm
@ MulFrm
Definition: ARMBaseInfo.h:317
llvm::ARM_MB::RESERVED_12
@ RESERVED_12
Definition: ARMBaseInfo.h:71
llvm::ARMII::AddrModeT2_i7s4
@ AddrModeT2_i7s4
Definition: ARMBaseInfo.h:205
ARMBaseInfo.h
llvm::ARM_PROC::I
@ I
Definition: ARMBaseInfo.h:33
llvm::ARMII::BrFrm
@ BrFrm
Definition: ARMBaseInfo.h:320
llvm::ARMII::NDupFrm
@ NDupFrm
Definition: ARMBaseInfo.h:364
llvm::ARM_PROC::IFlags
IFlags
Definition: ARMBaseInfo.h:31
llvm::ARMII::NVDupLnFrm
@ NVDupLnFrm
Definition: ARMBaseInfo.h:369
llvm::ARMII::M_BitShift
@ M_BitShift
Definition: ARMBaseInfo.h:429
llvm::ARMII::ThumbArithFlagSetting
@ ThumbArithFlagSetting
Definition: ARMBaseInfo.h:394
llvm::ARMII::VFPConv5Frm
@ VFPConv5Frm
Definition: ARMBaseInfo.h:350
llvm::ARMII::S_BitShift
@ S_BitShift
Definition: ARMBaseInfo.h:441
llvm::ARMII::AddrModeT2_i7
@ AddrModeT2_i7
Definition: ARMBaseInfo.h:207
llvm::ARMII::NVCVTFrm
@ NVCVTFrm
Definition: ARMBaseInfo.h:368
llvm::ARMII::HorizontalReduction
@ HorizontalReduction
Definition: ARMBaseInfo.h:405
llvm::ARM_PROC::IMod
IMod
Definition: ARMBaseInfo.h:26
llvm::ARMII::N2RegVShRFrm
@ N2RegVShRFrm
Definition: ARMBaseInfo.h:371
llvm::ARMII::DomainGeneral
@ DomainGeneral
Definition: ARMBaseInfo.h:415
llvm::ARM_PROC::IE
@ IE
Definition: ARMBaseInfo.h:27
llvm::ARMII::LdStExFrm
@ LdStExFrm
Definition: ARMBaseInfo.h:334
llvm::ARM_PROC::F
@ F
Definition: ARMBaseInfo.h:32
llvm::ARM_ISB::RESERVED_7
@ RESERVED_7
Definition: ARMBaseInfo.h:123
llvm::ARM_PROC::IFlagsToString
static const char * IFlagsToString(unsigned val)
Definition: ARMBaseInfo.h:37
llvm::ARMII::VFPLdStFrm
@ VFPLdStFrm
Definition: ARMBaseInfo.h:351
val
The initial backend is deliberately restricted to z10 We should add support for later architectures at some point If an asm ties an i32 r result to an i64 the input will be treated as an leaving the upper bits uninitialised For i64 store i32 val
Definition: README.txt:15
llvm::ARMII::VFPConv1Frm
@ VFPConv1Frm
Definition: ARMBaseInfo.h:346
llvm::ARMII::RegRdLoShift
@ RegRdLoShift
Definition: ARMBaseInfo.h:437
llvm::ARMII::VFPMiscFrm
@ VFPMiscFrm
Definition: ARMBaseInfo.h:353
llvm::ARMII::LdMiscFrm
@ LdMiscFrm
Definition: ARMBaseInfo.h:330
llvm::ARM_MB::ST
@ ST
Definition: ARMBaseInfo.h:73
llvm::ARM_MB::RESERVED_8
@ RESERVED_8
Definition: ARMBaseInfo.h:67
llvm::ARMII::AddrModeT1_s
@ AddrModeT1_s
Definition: ARMBaseInfo.h:196
llvm::ARMII::RegRdShift
@ RegRdShift
Definition: ARMBaseInfo.h:438
llvm::ARMII::MO_NONLAZY
@ MO_NONLAZY
MO_NONLAZY - This is an independent flag, on a symbol operand "FOO" it represents a symbol which,...
Definition: ARMBaseInfo.h:284
llvm::ARMII::SatFrm
@ SatFrm
Definition: ARMBaseInfo.h:338
llvm::ARM_MB::MemBOptToString
static const char * MemBOptToString(unsigned val, bool HasV8)
Definition: ARMBaseInfo.h:77
llvm::ARMII::RegRnShift
@ RegRnShift
Definition: ARMBaseInfo.h:440
llvm::ARM_ISB::RESERVED_1
@ RESERVED_1
Definition: ARMBaseInfo.h:117
llvm::ARMII::IndexModeUpd
@ IndexModeUpd
Definition: ARMBaseInfo.h:181
llvm::ARMII::N3RegVShFrm
@ N3RegVShFrm
Definition: ARMBaseInfo.h:373
llvm::ARMII::DPSoRegFrm
@ DPSoRegFrm
Definition: ARMBaseInfo.h:325
llvm::ARMII::AddrModeT1_1
@ AddrModeT1_1
Definition: ARMBaseInfo.h:193
llvm::ARMII::MO_SECREL
@ MO_SECREL
MO_SECREL - On a symbol operand this indicates that the immediate is the offset from beginning of sec...
Definition: ARMBaseInfo.h:277
llvm::ARMII::DomainMask
@ DomainMask
Definition: ARMBaseInfo.h:414
llvm::ARMII::AddrModeNone
@ AddrModeNone
Definition: ARMBaseInfo.h:186
llvm::ARMII::AddrMode1
@ AddrMode1
Definition: ARMBaseInfo.h:187
llvm::ARMII::AM3_I_BitShift
@ AM3_I_BitShift
Definition: ARMBaseInfo.h:443
llvm::ARMII::AddrModeT2_i7s2
@ AddrModeT2_i7s2
Definition: ARMBaseInfo.h:206
llvm::ARMII::RetainsPreviousHalfElement
@ RetainsPreviousHalfElement
Definition: ARMBaseInfo.h:402
llvm::ARMII::AddrModeMask
@ AddrModeMask
Definition: ARMBaseInfo.h:299
R6
#define R6(n)
llvm::ARMII::ShiftShift
@ ShiftShift
Definition: ARMBaseInfo.h:431
llvm::ARM_TSB::TraceSyncBOpt
TraceSyncBOpt
Definition: ARMBaseInfo.h:101
llvm::ARMII::FormMask
@ FormMask
Definition: ARMBaseInfo.h:311
llvm::ARM_ISB::RESERVED_0
@ RESERVED_0
Definition: ARMBaseInfo.h:116
llvm::ARM_TSB::CSYNC
@ CSYNC
Definition: ARMBaseInfo.h:102
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:136
llvm::ARMII::VFPBinaryFrm
@ VFPBinaryFrm
Definition: ARMBaseInfo.h:345
llvm::ARM_ISB::RESERVED_14
@ RESERVED_14
Definition: ARMBaseInfo.h:130
llvm::ARM_ISB::RESERVED_13
@ RESERVED_13
Definition: ARMBaseInfo.h:129
llvm::ARMII::SoRotImmShift
@ SoRotImmShift
Definition: ARMBaseInfo.h:434
llvm::ARMII::N1RegModImmFrm
@ N1RegModImmFrm
Definition: ARMBaseInfo.h:366
llvm::ARM_MB::ISHLD
@ ISHLD
Definition: ARMBaseInfo.h:68
llvm::ARMII::AddrMode6
@ AddrMode6
Definition: ARMBaseInfo.h:192
llvm::ARM_ISB::SY
@ SY
Definition: ARMBaseInfo.h:131
llvm::ARMII::NSetLnFrm
@ NSetLnFrm
Definition: ARMBaseInfo.h:363
llvm::ARM_MB::NSH
@ NSH
Definition: ARMBaseInfo.h:66
llvm::ARMII::N_BitShift
@ N_BitShift
Definition: ARMBaseInfo.h:432
llvm::ARMII::AddrModeToString
static const char * AddrModeToString(AddrMode addrmode)
Definition: ARMBaseInfo.h:210
llvm::ARMII::MO_LO16
@ MO_LO16
MO_LO16 - On a symbol operand, this represents a relocation containing lower 16 bit of the address.
Definition: ARMBaseInfo.h:246
llvm::ARMII::IndexModeNone
@ IndexModeNone
Definition: ARMBaseInfo.h:178
llvm::ARM_ISB::RESERVED_2
@ RESERVED_2
Definition: ARMBaseInfo.h:118
llvm::ARMII::AddrMode5
@ AddrMode5
Definition: ARMBaseInfo.h:191
llvm::ARMII::AddrModeT2_i12
@ AddrModeT2_i12
Definition: ARMBaseInfo.h:197
llvm::ARMII::ExtRotImmShift
@ ExtRotImmShift
Definition: ARMBaseInfo.h:436
llvm::ARMII::AddrModeT2_i8
@ AddrModeT2_i8
Definition: ARMBaseInfo.h:198
llvm::ARM_TSB::TraceSyncBOptToString
static const char * TraceSyncBOptToString(unsigned val)
Definition: ARMBaseInfo.h:105
llvm::ARMII::AddrMode
AddrMode
ARM Addressing Modes.
Definition: ARMBaseInfo.h:185
llvm::ARMII::AddrModeT1_2
@ AddrModeT1_2
Definition: ARMBaseInfo.h:194
llvm::ARMII::DomainNEON
@ DomainNEON
Definition: ARMBaseInfo.h:417
llvm::ARMII::VFPUnaryFrm
@ VFPUnaryFrm
Definition: ARMBaseInfo.h:344
llvm::ARM_MB::ISHST
@ ISHST
Definition: ARMBaseInfo.h:69
llvm::ARM_MB::ISH
@ ISH
Definition: ARMBaseInfo.h:70
llvm::ARM_MB::OSHLD
@ OSHLD
Definition: ARMBaseInfo.h:60
llvm::ARMII::LdFrm
@ LdFrm
Definition: ARMBaseInfo.h:328
llvm::ARM_MB::OSH
@ OSH
Definition: ARMBaseInfo.h:62
llvm::ARM_ISB::RESERVED_3
@ RESERVED_3
Definition: ARMBaseInfo.h:119
llvm::ARMII::DomainMVE
@ DomainMVE
Definition: ARMBaseInfo.h:419
llvm::ARMII::IndexModePre
@ IndexModePre
Definition: ARMBaseInfo.h:179
llvm::ARM_ISB::RESERVED_9
@ RESERVED_9
Definition: ARMBaseInfo.h:125
llvm::ARMII::Xform16Bit
@ Xform16Bit
Definition: ARMBaseInfo.h:388
llvm::ARMII::AddrModeT2_so
@ AddrModeT2_so
Definition: ARMBaseInfo.h:199
llvm::ARMII::VFPConv3Frm
@ VFPConv3Frm
Definition: ARMBaseInfo.h:348
llvm::ARMII::NVExtFrm
@ NVExtFrm
Definition: ARMBaseInfo.h:374
llvm::ARMII::U_BitShift
@ U_BitShift
Definition: ARMBaseInfo.h:445
llvm::ARMII::MiscFrm
@ MiscFrm
Definition: ARMBaseInfo.h:359
llvm::ARM_PROC::IModToString
static const char * IModToString(unsigned val)
Definition: ARMBaseInfo.h:46
llvm::ARMII::IndexModeShift
@ IndexModeShift
Definition: ARMBaseInfo.h:304
llvm::ARMII::LdStMulFrm
@ LdStMulFrm
Definition: ARMBaseInfo.h:332
llvm::ARMII::IndexModePost
@ IndexModePost
Definition: ARMBaseInfo.h:180
llvm::ARM_ISB::InstSyncBOpt
InstSyncBOpt
Definition: ARMBaseInfo.h:115
llvm::ARMII::MO_SBREL
@ MO_SBREL
MO_SBREL - On a symbol operand, this represents a static base relative relocation.
Definition: ARMBaseInfo.h:266
llvm::ARMII::MO_GOT
@ MO_GOT
MO_GOT - On a symbol operand, this represents a GOT relative relocation.
Definition: ARMBaseInfo.h:262
llvm::isARMLowRegister
static bool isARMLowRegister(unsigned Reg)
isARMLowRegister - Returns true if the register is a low register (r0-r7).
Definition: ARMBaseInfo.h:160
llvm::ARM_MB::MemBOpt
MemBOpt
Definition: ARMBaseInfo.h:58
llvm::ARM_ISB::RESERVED_5
@ RESERVED_5
Definition: ARMBaseInfo.h:121
llvm::ARMII::ExtFrm
@ ExtFrm
Definition: ARMBaseInfo.h:341
llvm::ARM_ISB::RESERVED_11
@ RESERVED_11
Definition: ARMBaseInfo.h:127
llvm::ARM_MB::NSHST
@ NSHST
Definition: ARMBaseInfo.h:65
llvm::ARMII::ImmHiShift
@ ImmHiShift
Definition: ARMBaseInfo.h:433
llvm::ARMII::N2RegFrm
@ N2RegFrm
Definition: ARMBaseInfo.h:367
llvm::ARMII::VFPLdStMulFrm
@ VFPLdStMulFrm
Definition: ARMBaseInfo.h:352
llvm::ARMII::DomainVFP
@ DomainVFP
Definition: ARMBaseInfo.h:416
llvm::ARMII::ValidForTailPredication
@ ValidForTailPredication
Definition: ARMBaseInfo.h:398
llvm::ARM_ISB::RESERVED_4
@ RESERVED_4
Definition: ARMBaseInfo.h:120
llvm::ARM_MB::NSHLD
@ NSHLD
Definition: ARMBaseInfo.h:64
llvm::ARM_ISB::RESERVED_12
@ RESERVED_12
Definition: ARMBaseInfo.h:128
llvm::ARMII::MO_OPTION_MASK
@ MO_OPTION_MASK
MO_OPTION_MASK - Most flags are mutually exclusive; this mask selects just that part of the flag set.
Definition: ARMBaseInfo.h:254
llvm::ARMII::VFPConv4Frm
@ VFPConv4Frm
Definition: ARMBaseInfo.h:349
llvm::ARM_MB::RESERVED_4
@ RESERVED_4
Definition: ARMBaseInfo.h:63