LLVM  15.0.0git
PPCMCTargetDesc.h
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1 //===-- PPCMCTargetDesc.h - PowerPC Target Descriptions ---------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file provides PowerPC specific target descriptions.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_POWERPC_MCTARGETDESC_PPCMCTARGETDESC_H
14 #define LLVM_LIB_TARGET_POWERPC_MCTARGETDESC_PPCMCTARGETDESC_H
15 
16 // GCC #defines PPC on Linux but we use it as our namespace name
17 #undef PPC
18 
19 #include "llvm/MC/MCRegisterInfo.h"
20 #include "llvm/Support/MathExtras.h"
21 #include <cstdint>
22 #include <memory>
23 
24 namespace llvm {
25 
26 class MCAsmBackend;
27 class MCCodeEmitter;
28 class MCContext;
29 class MCInstrInfo;
30 class MCObjectTargetWriter;
31 class MCRegisterInfo;
32 class MCSubtargetInfo;
33 class MCTargetOptions;
34 class Target;
35 
36 MCCodeEmitter *createPPCMCCodeEmitter(const MCInstrInfo &MCII,
37  MCContext &Ctx);
38 
39 MCAsmBackend *createPPCAsmBackend(const Target &T, const MCSubtargetInfo &STI,
40  const MCRegisterInfo &MRI,
41  const MCTargetOptions &Options);
42 
43 /// Construct an PPC ELF object writer.
44 std::unique_ptr<MCObjectTargetWriter> createPPCELFObjectWriter(bool Is64Bit,
45  uint8_t OSABI);
46 /// Construct a PPC Mach-O object writer.
47 std::unique_ptr<MCObjectTargetWriter>
48 createPPCMachObjectWriter(bool Is64Bit, uint32_t CPUType, uint32_t CPUSubtype);
49 
50 /// Construct a PPC XCOFF object writer.
51 std::unique_ptr<MCObjectTargetWriter> createPPCXCOFFObjectWriter(bool Is64Bit);
52 
53 /// Returns true iff Val consists of one contiguous run of 1s with any number of
54 /// 0s on either side. The 1s are allowed to wrap from LSB to MSB, so
55 /// 0x000FFF0, 0x0000FFFF, and 0xFF0000FF are all runs. 0x0F0F0000 is not,
56 /// since all 1s are not contiguous.
57 static inline bool isRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME) {
58  if (!Val)
59  return false;
60 
61  if (isShiftedMask_32(Val)) {
62  // look for the first non-zero bit
63  MB = countLeadingZeros(Val);
64  // look for the first zero bit after the run of ones
65  ME = countLeadingZeros((Val - 1) ^ Val);
66  return true;
67  } else {
68  Val = ~Val; // invert mask
69  if (isShiftedMask_32(Val)) {
70  // effectively look for the first zero bit
71  ME = countLeadingZeros(Val) - 1;
72  // effectively look for the first one bit after the run of zeros
73  MB = countLeadingZeros((Val - 1) ^ Val) + 1;
74  return true;
75  }
76  }
77  // no run present
78  return false;
79 }
80 
81 static inline bool isRunOfOnes64(uint64_t Val, unsigned &MB, unsigned &ME) {
82  if (!Val)
83  return false;
84 
85  if (isShiftedMask_64(Val)) {
86  // look for the first non-zero bit
87  MB = countLeadingZeros(Val);
88  // look for the first zero bit after the run of ones
89  ME = countLeadingZeros((Val - 1) ^ Val);
90  return true;
91  } else {
92  Val = ~Val; // invert mask
93  if (isShiftedMask_64(Val)) {
94  // effectively look for the first zero bit
95  ME = countLeadingZeros(Val) - 1;
96  // effectively look for the first one bit after the run of zeros
97  MB = countLeadingZeros((Val - 1) ^ Val) + 1;
98  return true;
99  }
100  }
101  // no run present
102  return false;
103 }
104 
105 } // end namespace llvm
106 
107 // Generated files will use "namespace PPC". To avoid symbol clash,
108 // undefine PPC here. PPC may be predefined on some hosts.
109 #undef PPC
110 
111 // Defines symbolic names for PowerPC registers. This defines a mapping from
112 // register name to register number.
113 //
114 #define GET_REGINFO_ENUM
115 #include "PPCGenRegisterInfo.inc"
116 
117 // Defines symbolic names for the PowerPC instructions.
118 //
119 #define GET_INSTRINFO_ENUM
120 #define GET_INSTRINFO_SCHED_ENUM
121 #include "PPCGenInstrInfo.inc"
122 
123 #define GET_SUBTARGETINFO_ENUM
124 #include "PPCGenSubtargetInfo.inc"
125 
126 #define PPC_REGS0_7(X) \
127  { \
128  X##0, X##1, X##2, X##3, X##4, X##5, X##6, X##7 \
129  }
130 
131 #define PPC_REGS0_31(X) \
132  { \
133  X##0, X##1, X##2, X##3, X##4, X##5, X##6, X##7, X##8, X##9, X##10, X##11, \
134  X##12, X##13, X##14, X##15, X##16, X##17, X##18, X##19, X##20, X##21, \
135  X##22, X##23, X##24, X##25, X##26, X##27, X##28, X##29, X##30, X##31 \
136  }
137 
138 #define PPC_REGS_NO0_31(Z, X) \
139  { \
140  Z, X##1, X##2, X##3, X##4, X##5, X##6, X##7, X##8, X##9, X##10, X##11, \
141  X##12, X##13, X##14, X##15, X##16, X##17, X##18, X##19, X##20, X##21, \
142  X##22, X##23, X##24, X##25, X##26, X##27, X##28, X##29, X##30, X##31 \
143  }
144 
145 #define PPC_REGS_LO_HI(LO, HI) \
146  { \
147  LO##0, LO##1, LO##2, LO##3, LO##4, LO##5, LO##6, LO##7, LO##8, LO##9, \
148  LO##10, LO##11, LO##12, LO##13, LO##14, LO##15, LO##16, LO##17, \
149  LO##18, LO##19, LO##20, LO##21, LO##22, LO##23, LO##24, LO##25, \
150  LO##26, LO##27, LO##28, LO##29, LO##30, LO##31, HI##0, HI##1, HI##2, \
151  HI##3, HI##4, HI##5, HI##6, HI##7, HI##8, HI##9, HI##10, HI##11, \
152  HI##12, HI##13, HI##14, HI##15, HI##16, HI##17, HI##18, HI##19, \
153  HI##20, HI##21, HI##22, HI##23, HI##24, HI##25, HI##26, HI##27, \
154  HI##28, HI##29, HI##30, HI##31 \
155  }
156 
157 using llvm::MCPhysReg;
158 
159 #define DEFINE_PPC_REGCLASSES \
160  static const MCPhysReg RRegs[32] = PPC_REGS0_31(PPC::R); \
161  static const MCPhysReg XRegs[32] = PPC_REGS0_31(PPC::X); \
162  static const MCPhysReg FRegs[32] = PPC_REGS0_31(PPC::F); \
163  static const MCPhysReg VSRpRegs[32] = PPC_REGS0_31(PPC::VSRp); \
164  static const MCPhysReg SPERegs[32] = PPC_REGS0_31(PPC::S); \
165  static const MCPhysReg VFRegs[32] = PPC_REGS0_31(PPC::VF); \
166  static const MCPhysReg VRegs[32] = PPC_REGS0_31(PPC::V); \
167  static const MCPhysReg RRegsNoR0[32] = \
168  PPC_REGS_NO0_31(PPC::ZERO, PPC::R); \
169  static const MCPhysReg XRegsNoX0[32] = \
170  PPC_REGS_NO0_31(PPC::ZERO8, PPC::X); \
171  static const MCPhysReg VSRegs[64] = \
172  PPC_REGS_LO_HI(PPC::VSL, PPC::V); \
173  static const MCPhysReg VSFRegs[64] = \
174  PPC_REGS_LO_HI(PPC::F, PPC::VF); \
175  static const MCPhysReg VSSRegs[64] = \
176  PPC_REGS_LO_HI(PPC::F, PPC::VF); \
177  static const MCPhysReg CRBITRegs[32] = { \
178  PPC::CR0LT, PPC::CR0GT, PPC::CR0EQ, PPC::CR0UN, \
179  PPC::CR1LT, PPC::CR1GT, PPC::CR1EQ, PPC::CR1UN, \
180  PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN, \
181  PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN, \
182  PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN, \
183  PPC::CR5LT, PPC::CR5GT, PPC::CR5EQ, PPC::CR5UN, \
184  PPC::CR6LT, PPC::CR6GT, PPC::CR6EQ, PPC::CR6UN, \
185  PPC::CR7LT, PPC::CR7GT, PPC::CR7EQ, PPC::CR7UN}; \
186  static const MCPhysReg CRRegs[8] = PPC_REGS0_7(PPC::CR); \
187  static const MCPhysReg ACCRegs[8] = PPC_REGS0_7(PPC::ACC)
188 #endif // LLVM_LIB_TARGET_POWERPC_MCTARGETDESC_PPCMCTARGETDESC_H
MathExtras.h
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
llvm::isShiftedMask_32
constexpr bool isShiftedMask_32(uint32_t Value)
Return true if the argument contains a non-empty sequence of ones with the remainder zero (32 bit ver...
Definition: MathExtras.h:479
llvm::MachO::CPUType
CPUType
Definition: MachO.h:1441
llvm::AMDGPU::Exp::Target
Target
Definition: SIDefines.h:855
T
#define T
Definition: Mips16ISelLowering.cpp:341
llvm::isShiftedMask_64
constexpr bool isShiftedMask_64(uint64_t Value)
Return true if the argument contains a non-empty sequence of ones with the remainder zero (64 bit ver...
Definition: MathExtras.h:485
Options
const char LLVMTargetMachineRef LLVMPassBuilderOptionsRef Options
Definition: PassBuilderBindings.cpp:48
llvm::createPPCXCOFFObjectWriter
std::unique_ptr< MCObjectTargetWriter > createPPCXCOFFObjectWriter(bool Is64Bit)
Construct a PPC XCOFF object writer.
Definition: PPCXCOFFObjectWriter.cpp:37
uint64_t
llvm::MCPhysReg
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
Definition: MCRegister.h:21
MCRegisterInfo.h
llvm::createPPCMachObjectWriter
std::unique_ptr< MCObjectTargetWriter > createPPCMachObjectWriter(bool Is64Bit, uint32_t CPUType, uint32_t CPUSubtype)
Construct a PPC Mach-O object writer.
llvm::createPPCELFObjectWriter
std::unique_ptr< MCObjectTargetWriter > createPPCELFObjectWriter(bool Is64Bit, uint8_t OSABI)
Construct an PPC ELF object writer.
Definition: PPCELFObjectWriter.cpp:488
llvm::createPPCMCCodeEmitter
MCCodeEmitter * createPPCMCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx)
Definition: PPCMCCodeEmitter.cpp:36
llvm::isRunOfOnes
static bool isRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME)
Returns true iff Val consists of one contiguous run of 1s with any number of 0s on either side.
Definition: PPCMCTargetDesc.h:57
uint32_t
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::countLeadingZeros
unsigned countLeadingZeros(T Val, ZeroBehavior ZB=ZB_Width)
Count number of 0's from the most significant bit to the least stopping at the first 1.
Definition: MathExtras.h:225
llvm::createPPCAsmBackend
MCAsmBackend * createPPCAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
Definition: PPCAsmBackend.cpp:274
llvm::isRunOfOnes64
static bool isRunOfOnes64(uint64_t Val, unsigned &MB, unsigned &ME)
Definition: PPCMCTargetDesc.h:81
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