LLVM  13.0.0git
PPCMCTargetDesc.h
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1 //===-- PPCMCTargetDesc.h - PowerPC Target Descriptions ---------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file provides PowerPC specific target descriptions.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_POWERPC_MCTARGETDESC_PPCMCTARGETDESC_H
14 #define LLVM_LIB_TARGET_POWERPC_MCTARGETDESC_PPCMCTARGETDESC_H
15 
16 // GCC #defines PPC on Linux but we use it as our namespace name
17 #undef PPC
18 
19 #include "llvm/MC/MCRegisterInfo.h"
21 #include <cstdint>
22 #include <memory>
23 
24 namespace llvm {
25 
26 class MCAsmBackend;
27 class MCCodeEmitter;
28 class MCContext;
29 class MCInstrInfo;
30 class MCObjectTargetWriter;
31 class MCRegisterInfo;
32 class MCSubtargetInfo;
33 class MCTargetOptions;
34 class Target;
35 
36 MCCodeEmitter *createPPCMCCodeEmitter(const MCInstrInfo &MCII,
37  const MCRegisterInfo &MRI,
38  MCContext &Ctx);
39 
40 MCAsmBackend *createPPCAsmBackend(const Target &T, const MCSubtargetInfo &STI,
41  const MCRegisterInfo &MRI,
42  const MCTargetOptions &Options);
43 
44 /// Construct an PPC ELF object writer.
45 std::unique_ptr<MCObjectTargetWriter> createPPCELFObjectWriter(bool Is64Bit,
46  uint8_t OSABI);
47 /// Construct a PPC Mach-O object writer.
48 std::unique_ptr<MCObjectTargetWriter>
49 createPPCMachObjectWriter(bool Is64Bit, uint32_t CPUType, uint32_t CPUSubtype);
50 
51 /// Construct a PPC XCOFF object writer.
52 std::unique_ptr<MCObjectTargetWriter> createPPCXCOFFObjectWriter(bool Is64Bit);
53 
54 /// Returns true iff Val consists of one contiguous run of 1s with any number of
55 /// 0s on either side. The 1s are allowed to wrap from LSB to MSB, so
56 /// 0x000FFF0, 0x0000FFFF, and 0xFF0000FF are all runs. 0x0F0F0000 is not,
57 /// since all 1s are not contiguous.
58 static inline bool isRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME) {
59  if (!Val)
60  return false;
61 
62  if (isShiftedMask_32(Val)) {
63  // look for the first non-zero bit
64  MB = countLeadingZeros(Val);
65  // look for the first zero bit after the run of ones
66  ME = countLeadingZeros((Val - 1) ^ Val);
67  return true;
68  } else {
69  Val = ~Val; // invert mask
70  if (isShiftedMask_32(Val)) {
71  // effectively look for the first zero bit
72  ME = countLeadingZeros(Val) - 1;
73  // effectively look for the first one bit after the run of zeros
74  MB = countLeadingZeros((Val - 1) ^ Val) + 1;
75  return true;
76  }
77  }
78  // no run present
79  return false;
80 }
81 
82 static inline bool isRunOfOnes64(uint64_t Val, unsigned &MB, unsigned &ME) {
83  if (!Val)
84  return false;
85 
86  if (isShiftedMask_64(Val)) {
87  // look for the first non-zero bit
88  MB = countLeadingZeros(Val);
89  // look for the first zero bit after the run of ones
90  ME = countLeadingZeros((Val - 1) ^ Val);
91  return true;
92  } else {
93  Val = ~Val; // invert mask
94  if (isShiftedMask_64(Val)) {
95  // effectively look for the first zero bit
96  ME = countLeadingZeros(Val) - 1;
97  // effectively look for the first one bit after the run of zeros
98  MB = countLeadingZeros((Val - 1) ^ Val) + 1;
99  return true;
100  }
101  }
102  // no run present
103  return false;
104 }
105 
106 } // end namespace llvm
107 
108 // Generated files will use "namespace PPC". To avoid symbol clash,
109 // undefine PPC here. PPC may be predefined on some hosts.
110 #undef PPC
111 
112 // Defines symbolic names for PowerPC registers. This defines a mapping from
113 // register name to register number.
114 //
115 #define GET_REGINFO_ENUM
116 #include "PPCGenRegisterInfo.inc"
117 
118 // Defines symbolic names for the PowerPC instructions.
119 //
120 #define GET_INSTRINFO_ENUM
121 #define GET_INSTRINFO_SCHED_ENUM
122 #include "PPCGenInstrInfo.inc"
123 
124 #define GET_SUBTARGETINFO_ENUM
125 #include "PPCGenSubtargetInfo.inc"
126 
127 #define PPC_REGS0_7(X) \
128  { \
129  X##0, X##1, X##2, X##3, X##4, X##5, X##6, X##7 \
130  }
131 
132 #define PPC_REGS0_31(X) \
133  { \
134  X##0, X##1, X##2, X##3, X##4, X##5, X##6, X##7, X##8, X##9, X##10, X##11, \
135  X##12, X##13, X##14, X##15, X##16, X##17, X##18, X##19, X##20, X##21, \
136  X##22, X##23, X##24, X##25, X##26, X##27, X##28, X##29, X##30, X##31 \
137  }
138 
139 #define PPC_REGS_NO0_31(Z, X) \
140  { \
141  Z, X##1, X##2, X##3, X##4, X##5, X##6, X##7, X##8, X##9, X##10, X##11, \
142  X##12, X##13, X##14, X##15, X##16, X##17, X##18, X##19, X##20, X##21, \
143  X##22, X##23, X##24, X##25, X##26, X##27, X##28, X##29, X##30, X##31 \
144  }
145 
146 #define PPC_REGS_LO_HI(LO, HI) \
147  { \
148  LO##0, LO##1, LO##2, LO##3, LO##4, LO##5, LO##6, LO##7, LO##8, LO##9, \
149  LO##10, LO##11, LO##12, LO##13, LO##14, LO##15, LO##16, LO##17, \
150  LO##18, LO##19, LO##20, LO##21, LO##22, LO##23, LO##24, LO##25, \
151  LO##26, LO##27, LO##28, LO##29, LO##30, LO##31, HI##0, HI##1, HI##2, \
152  HI##3, HI##4, HI##5, HI##6, HI##7, HI##8, HI##9, HI##10, HI##11, \
153  HI##12, HI##13, HI##14, HI##15, HI##16, HI##17, HI##18, HI##19, \
154  HI##20, HI##21, HI##22, HI##23, HI##24, HI##25, HI##26, HI##27, \
155  HI##28, HI##29, HI##30, HI##31 \
156  }
157 
158 using llvm::MCPhysReg;
159 
160 #define DEFINE_PPC_REGCLASSES \
161  static const MCPhysReg RRegs[32] = PPC_REGS0_31(PPC::R); \
162  static const MCPhysReg XRegs[32] = PPC_REGS0_31(PPC::X); \
163  static const MCPhysReg FRegs[32] = PPC_REGS0_31(PPC::F); \
164  static const MCPhysReg VSRpRegs[32] = PPC_REGS0_31(PPC::VSRp); \
165  static const MCPhysReg SPERegs[32] = PPC_REGS0_31(PPC::S); \
166  static const MCPhysReg VFRegs[32] = PPC_REGS0_31(PPC::VF); \
167  static const MCPhysReg VRegs[32] = PPC_REGS0_31(PPC::V); \
168  static const MCPhysReg RRegsNoR0[32] = \
169  PPC_REGS_NO0_31(PPC::ZERO, PPC::R); \
170  static const MCPhysReg XRegsNoX0[32] = \
171  PPC_REGS_NO0_31(PPC::ZERO8, PPC::X); \
172  static const MCPhysReg VSRegs[64] = \
173  PPC_REGS_LO_HI(PPC::VSL, PPC::V); \
174  static const MCPhysReg VSFRegs[64] = \
175  PPC_REGS_LO_HI(PPC::F, PPC::VF); \
176  static const MCPhysReg VSSRegs[64] = \
177  PPC_REGS_LO_HI(PPC::F, PPC::VF); \
178  static const MCPhysReg CRBITRegs[32] = { \
179  PPC::CR0LT, PPC::CR0GT, PPC::CR0EQ, PPC::CR0UN, \
180  PPC::CR1LT, PPC::CR1GT, PPC::CR1EQ, PPC::CR1UN, \
181  PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN, \
182  PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN, \
183  PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN, \
184  PPC::CR5LT, PPC::CR5GT, PPC::CR5EQ, PPC::CR5UN, \
185  PPC::CR6LT, PPC::CR6GT, PPC::CR6EQ, PPC::CR6UN, \
186  PPC::CR7LT, PPC::CR7GT, PPC::CR7EQ, PPC::CR7UN}; \
187  static const MCPhysReg CRRegs[8] = PPC_REGS0_7(PPC::CR); \
188  static const MCPhysReg ACCRegs[8] = PPC_REGS0_7(PPC::ACC)
189 #endif // LLVM_LIB_TARGET_POWERPC_MCTARGETDESC_PPCMCTARGETDESC_H
MathExtras.h
llvm
---------------------— PointerInfo ------------------------------------—
Definition: AllocatorList.h:23
llvm::isShiftedMask_32
constexpr bool isShiftedMask_32(uint32_t Value)
Return true if the argument contains a non-empty sequence of ones with the remainder zero (32 bit ver...
Definition: MathExtras.h:479
llvm::MachO::CPUType
CPUType
Definition: MachO.h:1418
llvm::AMDGPU::Exp::Target
Target
Definition: SIDefines.h:732
T
#define T
Definition: Mips16ISelLowering.cpp:341
llvm::createPPCMCCodeEmitter
MCCodeEmitter * createPPCMCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, MCContext &Ctx)
Definition: PPCMCCodeEmitter.cpp:36
llvm::isShiftedMask_64
constexpr bool isShiftedMask_64(uint64_t Value)
Return true if the argument contains a non-empty sequence of ones with the remainder zero (64 bit ver...
Definition: MathExtras.h:485
Options
const char LLVMTargetMachineRef LLVMPassBuilderOptionsRef Options
Definition: PassBuilderBindings.cpp:48
llvm::createPPCXCOFFObjectWriter
std::unique_ptr< MCObjectTargetWriter > createPPCXCOFFObjectWriter(bool Is64Bit)
Construct a PPC XCOFF object writer.
Definition: PPCXCOFFObjectWriter.cpp:37
llvm::MCPhysReg
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
Definition: MCRegister.h:20
MCRegisterInfo.h
llvm::createPPCMachObjectWriter
std::unique_ptr< MCObjectTargetWriter > createPPCMachObjectWriter(bool Is64Bit, uint32_t CPUType, uint32_t CPUSubtype)
Construct a PPC Mach-O object writer.
llvm::createPPCELFObjectWriter
std::unique_ptr< MCObjectTargetWriter > createPPCELFObjectWriter(bool Is64Bit, uint8_t OSABI)
Construct an PPC ELF object writer.
Definition: PPCELFObjectWriter.cpp:486
llvm::isRunOfOnes
static bool isRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME)
Returns true iff Val consists of one contiguous run of 1s with any number of 0s on either side.
Definition: PPCMCTargetDesc.h:58
uint32_t
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::countLeadingZeros
unsigned countLeadingZeros(T Val, ZeroBehavior ZB=ZB_Width)
Count number of 0's from the most significant bit to the least stopping at the first 1.
Definition: MathExtras.h:225
llvm::createPPCAsmBackend
MCAsmBackend * createPPCAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
Definition: PPCAsmBackend.cpp:271
llvm::isRunOfOnes64
static bool isRunOfOnes64(uint64_t Val, unsigned &MB, unsigned &ME)
Definition: PPCMCTargetDesc.h:82