LLVM 17.0.0git
TargetPassConfig.h
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1//===- TargetPassConfig.h - Code Generation pass options --------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8/// \file
9/// Target-Independent Code Generator Pass Configuration Options pass.
10///
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_CODEGEN_TARGETPASSCONFIG_H
14#define LLVM_CODEGEN_TARGETPASSCONFIG_H
15
16#include "llvm/Pass.h"
18#include <cassert>
19#include <string>
20
21namespace llvm {
22
23class LLVMTargetMachine;
24struct MachineSchedContext;
25class PassConfigImpl;
26class ScheduleDAGInstrs;
27class CSEConfigBase;
28class PassInstrumentationCallbacks;
29
30// The old pass manager infrastructure is hidden in a legacy namespace now.
31namespace legacy {
32
33class PassManagerBase;
34
35} // end namespace legacy
36
38
39/// Discriminated union of Pass ID types.
40///
41/// The PassConfig API prefers dealing with IDs because they are safer and more
42/// efficient. IDs decouple configuration from instantiation. This way, when a
43/// pass is overriden, it isn't unnecessarily instantiated. It is also unsafe to
44/// refer to a Pass pointer after adding it to a pass manager, which deletes
45/// redundant pass instances.
46///
47/// However, it is convient to directly instantiate target passes with
48/// non-default ctors. These often don't have a registered PassInfo. Rather than
49/// force all target passes to implement the pass registry boilerplate, allow
50/// the PassConfig API to handle either type.
51///
52/// AnalysisID is sadly char*, so PointerIntPair won't work.
54 union {
57 };
58 bool IsInstance = false;
59
60public:
61 IdentifyingPassPtr() : P(nullptr) {}
62 IdentifyingPassPtr(AnalysisID IDPtr) : ID(IDPtr) {}
63 IdentifyingPassPtr(Pass *InstancePtr) : P(InstancePtr), IsInstance(true) {}
64
65 bool isValid() const { return P; }
66 bool isInstance() const { return IsInstance; }
67
68 AnalysisID getID() const {
69 assert(!IsInstance && "Not a Pass ID");
70 return ID;
71 }
72
73 Pass *getInstance() const {
74 assert(IsInstance && "Not a Pass Instance");
75 return P;
76 }
77};
78
79
80/// Target-Independent Code Generator Pass Configuration Options.
81///
82/// This is an ImmutablePass solely for the purpose of exposing CodeGen options
83/// to the internals of other CodeGen passes.
85private:
86 PassManagerBase *PM = nullptr;
87 AnalysisID StartBefore = nullptr;
88 AnalysisID StartAfter = nullptr;
89 AnalysisID StopBefore = nullptr;
90 AnalysisID StopAfter = nullptr;
91
92 unsigned StartBeforeInstanceNum = 0;
93 unsigned StartBeforeCount = 0;
94
95 unsigned StartAfterInstanceNum = 0;
96 unsigned StartAfterCount = 0;
97
98 unsigned StopBeforeInstanceNum = 0;
99 unsigned StopBeforeCount = 0;
100
101 unsigned StopAfterInstanceNum = 0;
102 unsigned StopAfterCount = 0;
103
104 bool Started = true;
105 bool Stopped = false;
106 bool AddingMachinePasses = false;
107 bool DebugifyIsSafe = true;
108
109 /// Set the StartAfter, StartBefore and StopAfter passes to allow running only
110 /// a portion of the normal code-gen pass sequence.
111 ///
112 /// If the StartAfter and StartBefore pass ID is zero, then compilation will
113 /// begin at the normal point; otherwise, clear the Started flag to indicate
114 /// that passes should not be added until the starting pass is seen. If the
115 /// Stop pass ID is zero, then compilation will continue to the end.
116 ///
117 /// This function expects that at least one of the StartAfter or the
118 /// StartBefore pass IDs is null.
119 void setStartStopPasses();
120
121protected:
123 PassConfigImpl *Impl = nullptr; // Internal data structures
124 bool Initialized = false; // Flagged after all passes are configured.
125
126 // Target Pass Options
127 // Targets provide a default setting, user flags override.
128 bool DisableVerify = false;
129
130 /// Default setting for -enable-tail-merge on this target.
131 bool EnableTailMerge = true;
132
133 /// Require processing of functions such that callees are generated before
134 /// callers.
136
137 /// Add the actual instruction selection passes. This does not include
138 /// preparation passes on IR.
139 bool addCoreISelPasses();
140
141public:
143 // Dummy constructor.
145
146 ~TargetPassConfig() override;
147
148 static char ID;
149
150 /// Get the right type of TargetMachine for this target.
151 template<typename TMC> TMC &getTM() const {
152 return *static_cast<TMC*>(TM);
153 }
154
155 //
156 void setInitialized() { Initialized = true; }
157
159
160 /// Returns true if one of the `-start-after`, `-start-before`, `-stop-after`
161 /// or `-stop-before` options is set.
162 static bool hasLimitedCodeGenPipeline();
163
164 /// Returns true if none of the `-stop-before` and `-stop-after` options is
165 /// set.
166 static bool willCompleteCodeGenPipeline();
167
168 /// If hasLimitedCodeGenPipeline is true, this method
169 /// returns a string with the name of the options, separated
170 /// by \p Separator that caused this pipeline to be limited.
171 static std::string
172 getLimitedCodeGenPipelineReason(const char *Separator = "/");
173
175
176 bool getEnableTailMerge() const { return EnableTailMerge; }
178
182 }
183
184 /// Allow the target to override a specific pass without overriding the pass
185 /// pipeline. When passes are added to the standard pipeline at the
186 /// point where StandardID is expected, add TargetID in its place.
187 void substitutePass(AnalysisID StandardID, IdentifyingPassPtr TargetID);
188
189 /// Insert InsertedPassID pass after TargetPassID pass.
190 void insertPass(AnalysisID TargetPassID, IdentifyingPassPtr InsertedPassID);
191
192 /// Allow the target to enable a specific standard pass by default.
193 void enablePass(AnalysisID PassID) { substitutePass(PassID, PassID); }
194
195 /// Allow the target to disable a specific standard pass by default.
196 void disablePass(AnalysisID PassID) {
198 }
199
200 /// Return the pass substituted for StandardID by the target.
201 /// If no substitution exists, return StandardID.
203
204 /// Return true if the pass has been substituted by the target or
205 /// overridden on the command line.
207
208 /// Return true if the optimized regalloc pipeline is enabled.
209 bool getOptimizeRegAlloc() const;
210
211 /// Return true if the default global register allocator is in use and
212 /// has not be overriden on the command line with '-regalloc=...'
213 bool usingDefaultRegAlloc() const;
214
215 /// High level function that adds all passes necessary to go from llvm IR
216 /// representation to the MI representation.
217 /// Adds IR based lowering and target specific optimization passes and finally
218 /// the core instruction selection passes.
219 /// \returns true if an error occurred, false otherwise.
220 bool addISelPasses();
221
222 /// Add common target configurable passes that perform LLVM IR to IR
223 /// transforms following machine independent optimization.
224 virtual void addIRPasses();
225
226 /// Add passes to lower exception handling for the code generator.
228
229 /// Add pass to prepare the LLVM IR for code generation. This should be done
230 /// before exception handling preparation passes.
231 virtual void addCodeGenPrepare();
232
233 /// Add common passes that perform LLVM IR to IR transforms in preparation for
234 /// instruction selection.
235 virtual void addISelPrepare();
236
237 /// addInstSelector - This method should install an instruction selector pass,
238 /// which converts from LLVM code to machine instructions.
239 virtual bool addInstSelector() {
240 return true;
241 }
242
243 /// This method should install an IR translator pass, which converts from
244 /// LLVM code to machine instructions with possibly generic opcodes.
245 virtual bool addIRTranslator() { return true; }
246
247 /// This method may be implemented by targets that want to run passes
248 /// immediately before legalization.
249 virtual void addPreLegalizeMachineIR() {}
250
251 /// This method should install a legalize pass, which converts the instruction
252 /// sequence into one that can be selected by the target.
253 virtual bool addLegalizeMachineIR() { return true; }
254
255 /// This method may be implemented by targets that want to run passes
256 /// immediately before the register bank selection.
257 virtual void addPreRegBankSelect() {}
258
259 /// This method should install a register bank selector pass, which
260 /// assigns register banks to virtual registers without a register
261 /// class or register banks.
262 virtual bool addRegBankSelect() { return true; }
263
264 /// This method may be implemented by targets that want to run passes
265 /// immediately before the (global) instruction selection.
267
268 /// This method should install a (global) instruction selector pass, which
269 /// converts possibly generic instructions to fully target-specific
270 /// instructions, thereby constraining all generic virtual registers to
271 /// register classes.
272 virtual bool addGlobalInstructionSelect() { return true; }
273
274 /// Add the complete, standard set of LLVM CodeGen passes.
275 /// Fully developed targets will not generally override this.
276 virtual void addMachinePasses();
277
278 /// Create an instance of ScheduleDAGInstrs to be run within the standard
279 /// MachineScheduler pass for this function and target at the current
280 /// optimization level.
281 ///
282 /// This can also be used to plug a new MachineSchedStrategy into an instance
283 /// of the standard ScheduleDAGMI:
284 /// return new ScheduleDAGMI(C, std::make_unique<MyStrategy>(C), /*RemoveKillFlags=*/false)
285 ///
286 /// Return NULL to select the default (generic) machine scheduler.
287 virtual ScheduleDAGInstrs *
289 return nullptr;
290 }
291
292 /// Similar to createMachineScheduler but used when postRA machine scheduling
293 /// is enabled.
294 virtual ScheduleDAGInstrs *
296 return nullptr;
297 }
298
299 /// printAndVerify - Add a pass to dump then verify the machine function, if
300 /// those steps are enabled.
301 void printAndVerify(const std::string &Banner);
302
303 /// Add a pass to print the machine function if printing is enabled.
304 void addPrintPass(const std::string &Banner);
305
306 /// Add a pass to perform basic verification of the machine function if
307 /// verification is enabled.
308 void addVerifyPass(const std::string &Banner);
309
310 /// Add a pass to add synthesized debug info to the MIR.
311 void addDebugifyPass();
312
313 /// Add a pass to remove debug info from the MIR.
314 void addStripDebugPass();
315
316 /// Add a pass to check synthesized debug info for MIR.
317 void addCheckDebugPass();
318
319 /// Add standard passes before a pass that's about to be added. For example,
320 /// the DebugifyMachineModulePass if it is enabled.
321 void addMachinePrePasses(bool AllowDebugify = true);
322
323 /// Add standard passes after a pass that has just been added. For example,
324 /// the MachineVerifier if it is enabled.
325 void addMachinePostPasses(const std::string &Banner);
326
327 /// Check whether or not GlobalISel should abort on error.
328 /// When this is disabled, GlobalISel will fall back on SDISel instead of
329 /// erroring out.
330 bool isGlobalISelAbortEnabled() const;
331
332 /// Check whether or not a diagnostic should be emitted when GlobalISel
333 /// uses the fallback path. In other words, it will emit a diagnostic
334 /// when GlobalISel failed and isGlobalISelAbortEnabled is false.
335 virtual bool reportDiagnosticWhenGlobalISelFallback() const;
336
337 /// Check whether continuous CSE should be enabled in GISel passes.
338 /// By default, it's enabled for non O0 levels.
339 virtual bool isGISelCSEEnabled() const;
340
341 /// Returns the CSEConfig object to use for the current optimization level.
342 virtual std::unique_ptr<CSEConfigBase> getCSEConfig() const;
343
344protected:
345 // Helper to verify the analysis is really immutable.
346 void setOpt(bool &Opt, bool Val);
347
348 /// Return true if register allocator is specified by -regalloc=override.
350
351 /// Methods with trivial inline returns are convenient points in the common
352 /// codegen pass pipeline where targets may insert passes. Methods with
353 /// out-of-line standard implementations are major CodeGen stages called by
354 /// addMachinePasses. Some targets may override major stages when inserting
355 /// passes is insufficient, but maintaining overriden stages is more work.
356 ///
357
358 /// addPreISelPasses - This method should add any "last minute" LLVM->LLVM
359 /// passes (which are run just before instruction selector).
360 virtual bool addPreISel() {
361 return true;
362 }
363
364 /// addMachineSSAOptimization - Add standard passes that optimize machine
365 /// instructions in SSA form.
366 virtual void addMachineSSAOptimization();
367
368 /// Add passes that optimize instruction level parallelism for out-of-order
369 /// targets. These passes are run while the machine code is still in SSA
370 /// form, so they can use MachineTraceMetrics to control their heuristics.
371 ///
372 /// All passes added here should preserve the MachineDominatorTree,
373 /// MachineLoopInfo, and MachineTraceMetrics analyses.
374 virtual bool addILPOpts() {
375 return false;
376 }
377
378 /// This method may be implemented by targets that want to run passes
379 /// immediately before register allocation.
380 virtual void addPreRegAlloc() { }
381
382 /// createTargetRegisterAllocator - Create the register allocator pass for
383 /// this target at the current optimization level.
384 virtual FunctionPass *createTargetRegisterAllocator(bool Optimized);
385
386 /// addFastRegAlloc - Add the minimum set of target-independent passes that
387 /// are required for fast register allocation.
388 virtual void addFastRegAlloc();
389
390 /// addOptimizedRegAlloc - Add passes related to register allocation.
391 /// LLVMTargetMachine provides standard regalloc passes for most targets.
392 virtual void addOptimizedRegAlloc();
393
394 /// addPreRewrite - Add passes to the optimized register allocation pipeline
395 /// after register allocation is complete, but before virtual registers are
396 /// rewritten to physical registers.
397 ///
398 /// These passes must preserve VirtRegMap and LiveIntervals, and when running
399 /// after RABasic or RAGreedy, they should take advantage of LiveRegMatrix.
400 /// When these passes run, VirtRegMap contains legal physreg assignments for
401 /// all virtual registers.
402 ///
403 /// Note if the target overloads addRegAssignAndRewriteOptimized, this may not
404 /// be honored. This is also not generally used for the the fast variant,
405 /// where the allocation and rewriting are done in one pass.
406 virtual bool addPreRewrite() {
407 return false;
408 }
409
410 /// addPostFastRegAllocRewrite - Add passes to the optimized register
411 /// allocation pipeline after fast register allocation is complete.
412 virtual bool addPostFastRegAllocRewrite() { return false; }
413
414 /// Add passes to be run immediately after virtual registers are rewritten
415 /// to physical registers.
416 virtual void addPostRewrite() { }
417
418 /// This method may be implemented by targets that want to run passes after
419 /// register allocation pass pipeline but before prolog-epilog insertion.
420 virtual void addPostRegAlloc() { }
421
422 /// Add passes that optimize machine instructions after register allocation.
423 virtual void addMachineLateOptimization();
424
425 /// This method may be implemented by targets that want to run passes after
426 /// prolog-epilog insertion and before the second instruction scheduling pass.
427 virtual void addPreSched2() { }
428
429 /// addGCPasses - Add late codegen passes that analyze code for garbage
430 /// collection. This should return true if GC info should be printed after
431 /// these passes.
432 virtual bool addGCPasses();
433
434 /// Add standard basic block placement passes.
435 virtual void addBlockPlacement();
436
437 /// This pass may be implemented by targets that want to run passes
438 /// immediately before machine code is emitted.
439 virtual void addPreEmitPass() { }
440
441 /// Targets may add passes immediately before machine code is emitted in this
442 /// callback. This is called even later than `addPreEmitPass`.
443 // FIXME: Rename `addPreEmitPass` to something more sensible given its actual
444 // position and remove the `2` suffix here as this callback is what
445 // `addPreEmitPass` *should* be but in reality isn't.
446 virtual void addPreEmitPass2() {}
447
448 /// Utilities for targets to add passes to the pass manager.
449 ///
450
451 /// Add a CodeGen pass at this point in the pipeline after checking overrides.
452 /// Return the pass that was added, or zero if no pass was added.
454
455 /// Add a pass to the PassManager if that pass is supposed to be run, as
456 /// determined by the StartAfter and StopAfter options. Takes ownership of the
457 /// pass.
458 void addPass(Pass *P);
459
460 /// addMachinePasses helper to create the target-selected or overriden
461 /// regalloc pass.
462 virtual FunctionPass *createRegAllocPass(bool Optimized);
463
464 /// Add core register allocator passes which do the actual register assignment
465 /// and rewriting. \returns true if any passes were added.
466 virtual bool addRegAssignAndRewriteFast();
467 virtual bool addRegAssignAndRewriteOptimized();
468};
469
470void registerCodeGenCallback(PassInstrumentationCallbacks &PIC,
471 LLVMTargetMachine &);
472
473} // end namespace llvm
474
475#endif // LLVM_CODEGEN_TARGETPASSCONFIG_H
basic Basic Alias true
#define P(N)
PassInstrumentationCallbacks PIC
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:311
Discriminated union of Pass ID types.
AnalysisID getID() const
IdentifyingPassPtr(AnalysisID IDPtr)
IdentifyingPassPtr(Pass *InstancePtr)
ImmutablePass class - This class is used to provide information that does not need to be run.
Definition: Pass.h:282
This class describes a target machine that is implemented with the LLVM target-independent code gener...
Pass interface - Implemented by all 'passes'.
Definition: Pass.h:94
A ScheduleDAG for scheduling lists of MachineInstr.
Target-Independent Code Generator Pass Configuration Options.
bool usingDefaultRegAlloc() const
Return true if the default global register allocator is in use and has not be overriden on the comman...
void enablePass(AnalysisID PassID)
Allow the target to enable a specific standard pass by default.
bool requiresCodeGenSCCOrder() const
void addCheckDebugPass()
Add a pass to check synthesized debug info for MIR.
LLVMTargetMachine * TM
virtual void addPreLegalizeMachineIR()
This method may be implemented by targets that want to run passes immediately before legalization.
void addPrintPass(const std::string &Banner)
Add a pass to print the machine function if printing is enabled.
virtual void addPreEmitPass2()
Targets may add passes immediately before machine code is emitted in this callback.
virtual std::unique_ptr< CSEConfigBase > getCSEConfig() const
Returns the CSEConfig object to use for the current optimization level.
bool RequireCodeGenSCCOrder
Require processing of functions such that callees are generated before callers.
void printAndVerify(const std::string &Banner)
printAndVerify - Add a pass to dump then verify the machine function, if those steps are enabled.
static std::string getLimitedCodeGenPipelineReason(const char *Separator="/")
If hasLimitedCodeGenPipeline is true, this method returns a string with the name of the options,...
bool getEnableTailMerge() const
static bool hasLimitedCodeGenPipeline()
Returns true if one of the -start-after, -start-before, -stop-after or -stop-before options is set.
virtual void addCodeGenPrepare()
Add pass to prepare the LLVM IR for code generation.
void insertPass(AnalysisID TargetPassID, IdentifyingPassPtr InsertedPassID)
Insert InsertedPassID pass after TargetPassID pass.
void addMachinePostPasses(const std::string &Banner)
Add standard passes after a pass that has just been added.
virtual void addPreSched2()
This method may be implemented by targets that want to run passes after prolog-epilog insertion and b...
virtual bool isGISelCSEEnabled() const
Check whether continuous CSE should be enabled in GISel passes.
virtual bool addILPOpts()
Add passes that optimize instruction level parallelism for out-of-order targets.
virtual void addPostRegAlloc()
This method may be implemented by targets that want to run passes after register allocation pass pipe...
void addDebugifyPass()
Add a pass to add synthesized debug info to the MIR.
virtual bool addInstSelector()
addInstSelector - This method should install an instruction selector pass, which converts from LLVM c...
virtual ScheduleDAGInstrs * createPostMachineScheduler(MachineSchedContext *C) const
Similar to createMachineScheduler but used when postRA machine scheduling is enabled.
virtual bool addPreISel()
Methods with trivial inline returns are convenient points in the common codegen pass pipeline where t...
void setOpt(bool &Opt, bool Val)
virtual void addBlockPlacement()
Add standard basic block placement passes.
virtual FunctionPass * createRegAllocPass(bool Optimized)
addMachinePasses helper to create the target-selected or overriden regalloc pass.
virtual void addOptimizedRegAlloc()
addOptimizedRegAlloc - Add passes related to register allocation.
virtual bool addRegAssignAndRewriteFast()
Add core register allocator passes which do the actual register assignment and rewriting.
virtual void addPreEmitPass()
This pass may be implemented by targets that want to run passes immediately before machine code is em...
bool isGlobalISelAbortEnabled() const
Check whether or not GlobalISel should abort on error.
bool getOptimizeRegAlloc() const
Return true if the optimized regalloc pipeline is enabled.
bool isCustomizedRegAlloc()
Return true if register allocator is specified by -regalloc=override.
virtual void addPreRegBankSelect()
This method may be implemented by targets that want to run passes immediately before the register ban...
virtual ScheduleDAGInstrs * createMachineScheduler(MachineSchedContext *C) const
Create an instance of ScheduleDAGInstrs to be run within the standard MachineScheduler pass for this ...
virtual bool reportDiagnosticWhenGlobalISelFallback() const
Check whether or not a diagnostic should be emitted when GlobalISel uses the fallback path.
virtual bool addPreRewrite()
addPreRewrite - Add passes to the optimized register allocation pipeline after register allocation is...
virtual bool addRegBankSelect()
This method should install a register bank selector pass, which assigns register banks to virtual reg...
CodeGenOpt::Level getOptLevel() const
void setRequiresCodeGenSCCOrder(bool Enable=true)
virtual void addMachineLateOptimization()
Add passes that optimize machine instructions after register allocation.
virtual void addMachinePasses()
Add the complete, standard set of LLVM CodeGen passes.
virtual void addIRPasses()
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
virtual void addPreGlobalInstructionSelect()
This method may be implemented by targets that want to run passes immediately before the (global) ins...
virtual void addFastRegAlloc()
addFastRegAlloc - Add the minimum set of target-independent passes that are required for fast registe...
virtual bool addLegalizeMachineIR()
This method should install a legalize pass, which converts the instruction sequence into one that can...
virtual void addMachineSSAOptimization()
addMachineSSAOptimization - Add standard passes that optimize machine instructions in SSA form.
void substitutePass(AnalysisID StandardID, IdentifyingPassPtr TargetID)
Allow the target to override a specific pass without overriding the pass pipeline.
virtual bool addRegAssignAndRewriteOptimized()
void disablePass(AnalysisID PassID)
Allow the target to disable a specific standard pass by default.
virtual bool addGlobalInstructionSelect()
This method should install a (global) instruction selector pass, which converts possibly generic inst...
virtual void addPreRegAlloc()
This method may be implemented by targets that want to run passes immediately before register allocat...
bool EnableTailMerge
Default setting for -enable-tail-merge on this target.
AnalysisID addPass(AnalysisID PassID)
Utilities for targets to add passes to the pass manager.
void addPassesToHandleExceptions()
Add passes to lower exception handling for the code generator.
void addStripDebugPass()
Add a pass to remove debug info from the MIR.
bool isPassSubstitutedOrOverridden(AnalysisID ID) const
Return true if the pass has been substituted by the target or overridden on the command line.
bool addCoreISelPasses()
Add the actual instruction selection passes.
void setEnableTailMerge(bool Enable)
void setDisableVerify(bool Disable)
TMC & getTM() const
Get the right type of TargetMachine for this target.
virtual void addISelPrepare()
Add common passes that perform LLVM IR to IR transforms in preparation for instruction selection.
static bool willCompleteCodeGenPipeline()
Returns true if none of the -stop-before and -stop-after options is set.
void addMachinePrePasses(bool AllowDebugify=true)
Add standard passes before a pass that's about to be added.
virtual bool addGCPasses()
addGCPasses - Add late codegen passes that analyze code for garbage collection.
virtual bool addIRTranslator()
This method should install an IR translator pass, which converts from LLVM code to machine instructio...
void addVerifyPass(const std::string &Banner)
Add a pass to perform basic verification of the machine function if verification is enabled.
virtual FunctionPass * createTargetRegisterAllocator(bool Optimized)
createTargetRegisterAllocator - Create the register allocator pass for this target at the current opt...
virtual bool addPostFastRegAllocRewrite()
addPostFastRegAllocRewrite - Add passes to the optimized register allocation pipeline after fast regi...
IdentifyingPassPtr getPassSubstitution(AnalysisID StandardID) const
Return the pass substituted for StandardID by the target.
bool addISelPasses()
High level function that adds all passes necessary to go from llvm IR representation to the MI repres...
virtual void addPostRewrite()
Add passes to be run immediately after virtual registers are rewritten to physical registers.
PassManagerBase - An abstract interface to allow code to add passes to a pass manager without having ...
@ C
The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
Level
Code generation optimization level.
Definition: CodeGen.h:57
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
void registerCodeGenCallback(PassInstrumentationCallbacks &PIC, LLVMTargetMachine &)
const void * AnalysisID
Definition: Pass.h:50
@ Enable
Enable colors.
@ Disable
Disable colors.
MachineSchedContext provides enough context from the MachineScheduler pass for the target to instanti...