LLVM  13.0.0git
TargetPassConfig.h
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1 //===- TargetPassConfig.h - Code Generation pass options --------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 /// Target-Independent Code Generator Pass Configuration Options pass.
10 ///
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_CODEGEN_TARGETPASSCONFIG_H
14 #define LLVM_CODEGEN_TARGETPASSCONFIG_H
15 
16 #include "llvm/Pass.h"
17 #include "llvm/Support/CodeGen.h"
18 #include <cassert>
19 #include <string>
20 
21 namespace llvm {
22 
23 class LLVMTargetMachine;
24 struct MachineSchedContext;
25 class PassConfigImpl;
26 class ScheduleDAGInstrs;
27 class CSEConfigBase;
28 class PassInstrumentationCallbacks;
29 
30 // The old pass manager infrastructure is hidden in a legacy namespace now.
31 namespace legacy {
32 
33 class PassManagerBase;
34 
35 } // end namespace legacy
36 
38 
39 /// Discriminated union of Pass ID types.
40 ///
41 /// The PassConfig API prefers dealing with IDs because they are safer and more
42 /// efficient. IDs decouple configuration from instantiation. This way, when a
43 /// pass is overriden, it isn't unnecessarily instantiated. It is also unsafe to
44 /// refer to a Pass pointer after adding it to a pass manager, which deletes
45 /// redundant pass instances.
46 ///
47 /// However, it is convient to directly instantiate target passes with
48 /// non-default ctors. These often don't have a registered PassInfo. Rather than
49 /// force all target passes to implement the pass registry boilerplate, allow
50 /// the PassConfig API to handle either type.
51 ///
52 /// AnalysisID is sadly char*, so PointerIntPair won't work.
54  union {
56  Pass *P;
57  };
58  bool IsInstance = false;
59 
60 public:
61  IdentifyingPassPtr() : P(nullptr) {}
62  IdentifyingPassPtr(AnalysisID IDPtr) : ID(IDPtr) {}
63  IdentifyingPassPtr(Pass *InstancePtr) : P(InstancePtr), IsInstance(true) {}
64 
65  bool isValid() const { return P; }
66  bool isInstance() const { return IsInstance; }
67 
68  AnalysisID getID() const {
69  assert(!IsInstance && "Not a Pass ID");
70  return ID;
71  }
72 
73  Pass *getInstance() const {
74  assert(IsInstance && "Not a Pass Instance");
75  return P;
76  }
77 };
78 
79 
80 /// Target-Independent Code Generator Pass Configuration Options.
81 ///
82 /// This is an ImmutablePass solely for the purpose of exposing CodeGen options
83 /// to the internals of other CodeGen passes.
85 private:
86  PassManagerBase *PM = nullptr;
87  AnalysisID StartBefore = nullptr;
88  AnalysisID StartAfter = nullptr;
89  AnalysisID StopBefore = nullptr;
90  AnalysisID StopAfter = nullptr;
91 
92  unsigned StartBeforeInstanceNum = 0;
93  unsigned StartBeforeCount = 0;
94 
95  unsigned StartAfterInstanceNum = 0;
96  unsigned StartAfterCount = 0;
97 
98  unsigned StopBeforeInstanceNum = 0;
99  unsigned StopBeforeCount = 0;
100 
101  unsigned StopAfterInstanceNum = 0;
102  unsigned StopAfterCount = 0;
103 
104  bool Started = true;
105  bool Stopped = false;
106  bool AddingMachinePasses = false;
107  bool DebugifyIsSafe = true;
108 
109  /// Set the StartAfter, StartBefore and StopAfter passes to allow running only
110  /// a portion of the normal code-gen pass sequence.
111  ///
112  /// If the StartAfter and StartBefore pass ID is zero, then compilation will
113  /// begin at the normal point; otherwise, clear the Started flag to indicate
114  /// that passes should not be added until the starting pass is seen. If the
115  /// Stop pass ID is zero, then compilation will continue to the end.
116  ///
117  /// This function expects that at least one of the StartAfter or the
118  /// StartBefore pass IDs is null.
119  void setStartStopPasses();
120 
121 protected:
123  PassConfigImpl *Impl = nullptr; // Internal data structures
124  bool Initialized = false; // Flagged after all passes are configured.
125 
126  // Target Pass Options
127  // Targets provide a default setting, user flags override.
128  bool DisableVerify = false;
129 
130  /// Default setting for -enable-tail-merge on this target.
131  bool EnableTailMerge = true;
132 
133  /// Require processing of functions such that callees are generated before
134  /// callers.
136 
137  /// Add the actual instruction selection passes. This does not include
138  /// preparation passes on IR.
139  bool addCoreISelPasses();
140 
141 public:
143  // Dummy constructor.
145 
146  ~TargetPassConfig() override;
147 
148  static char ID;
149 
150  /// Get the right type of TargetMachine for this target.
151  template<typename TMC> TMC &getTM() const {
152  return *static_cast<TMC*>(TM);
153  }
154 
155  //
156  void setInitialized() { Initialized = true; }
157 
159 
160  /// Returns true if one of the `-start-after`, `-start-before`, `-stop-after`
161  /// or `-stop-before` options is set.
162  static bool hasLimitedCodeGenPipeline();
163 
164  /// Returns true if none of the `-stop-before` and `-stop-after` options is
165  /// set.
166  static bool willCompleteCodeGenPipeline();
167 
168  /// If hasLimitedCodeGenPipeline is true, this method
169  /// returns a string with the name of the options, separated
170  /// by \p Separator that caused this pipeline to be limited.
171  static std::string
172  getLimitedCodeGenPipelineReason(const char *Separator = "/");
173 
174  void setDisableVerify(bool Disable) { setOpt(DisableVerify, Disable); }
175 
176  bool getEnableTailMerge() const { return EnableTailMerge; }
178 
180  void setRequiresCodeGenSCCOrder(bool Enable = true) {
182  }
183 
184  /// Allow the target to override a specific pass without overriding the pass
185  /// pipeline. When passes are added to the standard pipeline at the
186  /// point where StandardID is expected, add TargetID in its place.
187  void substitutePass(AnalysisID StandardID, IdentifyingPassPtr TargetID);
188 
189  /// Insert InsertedPassID pass after TargetPassID pass.
190  void insertPass(AnalysisID TargetPassID, IdentifyingPassPtr InsertedPassID,
191  bool VerifyAfter = true);
192 
193  /// Allow the target to enable a specific standard pass by default.
194  void enablePass(AnalysisID PassID) { substitutePass(PassID, PassID); }
195 
196  /// Allow the target to disable a specific standard pass by default.
197  void disablePass(AnalysisID PassID) {
199  }
200 
201  /// Return the pass substituted for StandardID by the target.
202  /// If no substitution exists, return StandardID.
204 
205  /// Return true if the pass has been substituted by the target or
206  /// overridden on the command line.
208 
209  /// Return true if the optimized regalloc pipeline is enabled.
210  bool getOptimizeRegAlloc() const;
211 
212  /// Return true if the default global register allocator is in use and
213  /// has not be overriden on the command line with '-regalloc=...'
214  bool usingDefaultRegAlloc() const;
215 
216  /// High level function that adds all passes necessary to go from llvm IR
217  /// representation to the MI representation.
218  /// Adds IR based lowering and target specific optimization passes and finally
219  /// the core instruction selection passes.
220  /// \returns true if an error occurred, false otherwise.
221  bool addISelPasses();
222 
223  /// Add common target configurable passes that perform LLVM IR to IR
224  /// transforms following machine independent optimization.
225  virtual void addIRPasses();
226 
227  /// Add passes to lower exception handling for the code generator.
229 
230  /// Add pass to prepare the LLVM IR for code generation. This should be done
231  /// before exception handling preparation passes.
232  virtual void addCodeGenPrepare();
233 
234  /// Add common passes that perform LLVM IR to IR transforms in preparation for
235  /// instruction selection.
236  virtual void addISelPrepare();
237 
238  /// addInstSelector - This method should install an instruction selector pass,
239  /// which converts from LLVM code to machine instructions.
240  virtual bool addInstSelector() {
241  return true;
242  }
243 
244  /// This method should install an IR translator pass, which converts from
245  /// LLVM code to machine instructions with possibly generic opcodes.
246  virtual bool addIRTranslator() { return true; }
247 
248  /// This method may be implemented by targets that want to run passes
249  /// immediately before legalization.
250  virtual void addPreLegalizeMachineIR() {}
251 
252  /// This method should install a legalize pass, which converts the instruction
253  /// sequence into one that can be selected by the target.
254  virtual bool addLegalizeMachineIR() { return true; }
255 
256  /// This method may be implemented by targets that want to run passes
257  /// immediately before the register bank selection.
258  virtual void addPreRegBankSelect() {}
259 
260  /// This method should install a register bank selector pass, which
261  /// assigns register banks to virtual registers without a register
262  /// class or register banks.
263  virtual bool addRegBankSelect() { return true; }
264 
265  /// This method may be implemented by targets that want to run passes
266  /// immediately before the (global) instruction selection.
268 
269  /// This method should install a (global) instruction selector pass, which
270  /// converts possibly generic instructions to fully target-specific
271  /// instructions, thereby constraining all generic virtual registers to
272  /// register classes.
273  virtual bool addGlobalInstructionSelect() { return true; }
274 
275  /// Add the complete, standard set of LLVM CodeGen passes.
276  /// Fully developed targets will not generally override this.
277  virtual void addMachinePasses();
278 
279  /// Create an instance of ScheduleDAGInstrs to be run within the standard
280  /// MachineScheduler pass for this function and target at the current
281  /// optimization level.
282  ///
283  /// This can also be used to plug a new MachineSchedStrategy into an instance
284  /// of the standard ScheduleDAGMI:
285  /// return new ScheduleDAGMI(C, std::make_unique<MyStrategy>(C), /*RemoveKillFlags=*/false)
286  ///
287  /// Return NULL to select the default (generic) machine scheduler.
288  virtual ScheduleDAGInstrs *
290  return nullptr;
291  }
292 
293  /// Similar to createMachineScheduler but used when postRA machine scheduling
294  /// is enabled.
295  virtual ScheduleDAGInstrs *
297  return nullptr;
298  }
299 
300  /// printAndVerify - Add a pass to dump then verify the machine function, if
301  /// those steps are enabled.
302  void printAndVerify(const std::string &Banner);
303 
304  /// Add a pass to print the machine function if printing is enabled.
305  void addPrintPass(const std::string &Banner);
306 
307  /// Add a pass to perform basic verification of the machine function if
308  /// verification is enabled.
309  void addVerifyPass(const std::string &Banner);
310 
311  /// Add a pass to add synthesized debug info to the MIR.
312  void addDebugifyPass();
313 
314  /// Add a pass to remove debug info from the MIR.
315  void addStripDebugPass();
316 
317  /// Add a pass to check synthesized debug info for MIR.
318  void addCheckDebugPass();
319 
320  /// Add standard passes before a pass that's about to be added. For example,
321  /// the DebugifyMachineModulePass if it is enabled.
322  void addMachinePrePasses(bool AllowDebugify = true);
323 
324  /// Add standard passes after a pass that has just been added. For example,
325  /// the MachineVerifier if it is enabled.
326  void addMachinePostPasses(const std::string &Banner, bool AllowVerify = true,
327  bool AllowStrip = true);
328 
329  /// Check whether or not GlobalISel should abort on error.
330  /// When this is disabled, GlobalISel will fall back on SDISel instead of
331  /// erroring out.
332  bool isGlobalISelAbortEnabled() const;
333 
334  /// Check whether or not a diagnostic should be emitted when GlobalISel
335  /// uses the fallback path. In other words, it will emit a diagnostic
336  /// when GlobalISel failed and isGlobalISelAbortEnabled is false.
337  virtual bool reportDiagnosticWhenGlobalISelFallback() const;
338 
339  /// Check whether continuous CSE should be enabled in GISel passes.
340  /// By default, it's enabled for non O0 levels.
341  virtual bool isGISelCSEEnabled() const;
342 
343  /// Returns the CSEConfig object to use for the current optimization level.
344  virtual std::unique_ptr<CSEConfigBase> getCSEConfig() const;
345 
346 protected:
347  // Helper to verify the analysis is really immutable.
348  void setOpt(bool &Opt, bool Val);
349 
350  /// Methods with trivial inline returns are convenient points in the common
351  /// codegen pass pipeline where targets may insert passes. Methods with
352  /// out-of-line standard implementations are major CodeGen stages called by
353  /// addMachinePasses. Some targets may override major stages when inserting
354  /// passes is insufficient, but maintaining overriden stages is more work.
355  ///
356 
357  /// addPreISelPasses - This method should add any "last minute" LLVM->LLVM
358  /// passes (which are run just before instruction selector).
359  virtual bool addPreISel() {
360  return true;
361  }
362 
363  /// addMachineSSAOptimization - Add standard passes that optimize machine
364  /// instructions in SSA form.
365  virtual void addMachineSSAOptimization();
366 
367  /// Add passes that optimize instruction level parallelism for out-of-order
368  /// targets. These passes are run while the machine code is still in SSA
369  /// form, so they can use MachineTraceMetrics to control their heuristics.
370  ///
371  /// All passes added here should preserve the MachineDominatorTree,
372  /// MachineLoopInfo, and MachineTraceMetrics analyses.
373  virtual bool addILPOpts() {
374  return false;
375  }
376 
377  /// This method may be implemented by targets that want to run passes
378  /// immediately before register allocation.
379  virtual void addPreRegAlloc() { }
380 
381  /// createTargetRegisterAllocator - Create the register allocator pass for
382  /// this target at the current optimization level.
383  virtual FunctionPass *createTargetRegisterAllocator(bool Optimized);
384 
385  /// addFastRegAlloc - Add the minimum set of target-independent passes that
386  /// are required for fast register allocation.
387  virtual void addFastRegAlloc();
388 
389  /// addOptimizedRegAlloc - Add passes related to register allocation.
390  /// LLVMTargetMachine provides standard regalloc passes for most targets.
391  virtual void addOptimizedRegAlloc();
392 
393  /// addPreRewrite - Add passes to the optimized register allocation pipeline
394  /// after register allocation is complete, but before virtual registers are
395  /// rewritten to physical registers.
396  ///
397  /// These passes must preserve VirtRegMap and LiveIntervals, and when running
398  /// after RABasic or RAGreedy, they should take advantage of LiveRegMatrix.
399  /// When these passes run, VirtRegMap contains legal physreg assignments for
400  /// all virtual registers.
401  ///
402  /// Note if the target overloads addRegAssignAndRewriteOptimized, this may not
403  /// be honored. This is also not generally used for the the fast variant,
404  /// where the allocation and rewriting are done in one pass.
405  virtual bool addPreRewrite() {
406  return false;
407  }
408 
409  /// addPostFastRegAllocRewrite - Add passes to the optimized register
410  /// allocation pipeline after fast register allocation is complete.
411  virtual bool addPostFastRegAllocRewrite() { return false; }
412 
413  /// Add passes to be run immediately after virtual registers are rewritten
414  /// to physical registers.
415  virtual void addPostRewrite() { }
416 
417  /// This method may be implemented by targets that want to run passes after
418  /// register allocation pass pipeline but before prolog-epilog insertion.
419  virtual void addPostRegAlloc() { }
420 
421  /// Add passes that optimize machine instructions after register allocation.
422  virtual void addMachineLateOptimization();
423 
424  /// This method may be implemented by targets that want to run passes after
425  /// prolog-epilog insertion and before the second instruction scheduling pass.
426  virtual void addPreSched2() { }
427 
428  /// addGCPasses - Add late codegen passes that analyze code for garbage
429  /// collection. This should return true if GC info should be printed after
430  /// these passes.
431  virtual bool addGCPasses();
432 
433  /// Add standard basic block placement passes.
434  virtual void addBlockPlacement();
435 
436  /// This pass may be implemented by targets that want to run passes
437  /// immediately before machine code is emitted.
438  virtual void addPreEmitPass() { }
439 
440  /// Targets may add passes immediately before machine code is emitted in this
441  /// callback. This is called even later than `addPreEmitPass`.
442  // FIXME: Rename `addPreEmitPass` to something more sensible given its actual
443  // position and remove the `2` suffix here as this callback is what
444  // `addPreEmitPass` *should* be but in reality isn't.
445  virtual void addPreEmitPass2() {}
446 
447  /// Utilities for targets to add passes to the pass manager.
448  ///
449 
450  /// Add a CodeGen pass at this point in the pipeline after checking overrides.
451  /// Return the pass that was added, or zero if no pass was added.
452  /// @p verifyAfter if true and adding a machine function pass add an extra
453  /// machine verification pass afterwards.
454  AnalysisID addPass(AnalysisID PassID, bool verifyAfter = true);
455 
456  /// Add a pass to the PassManager if that pass is supposed to be run, as
457  /// determined by the StartAfter and StopAfter options. Takes ownership of the
458  /// pass.
459  /// @p verifyAfter if true and adding a machine function pass add an extra
460  /// machine verification pass afterwards.
461  void addPass(Pass *P, bool verifyAfter = true);
462 
463  /// addMachinePasses helper to create the target-selected or overriden
464  /// regalloc pass.
465  virtual FunctionPass *createRegAllocPass(bool Optimized);
466 
467  /// Add core register allocator passes which do the actual register assignment
468  /// and rewriting. \returns true if any passes were added.
469  virtual bool addRegAssignAndRewriteFast();
470  virtual bool addRegAssignAndRewriteOptimized();
471 };
472 
473 void registerCodeGenCallback(PassInstrumentationCallbacks &PIC,
474  LLVMTargetMachine &);
475 
476 } // end namespace llvm
477 
478 #endif // LLVM_CODEGEN_TARGETPASSCONFIG_H
llvm::TargetPassConfig::addPostRegAlloc
virtual void addPostRegAlloc()
This method may be implemented by targets that want to run passes after register allocation pass pipe...
Definition: TargetPassConfig.h:419
llvm::TargetPassConfig::ID
static char ID
Definition: TargetPassConfig.h:148
llvm::IdentifyingPassPtr::IdentifyingPassPtr
IdentifyingPassPtr(Pass *InstancePtr)
Definition: TargetPassConfig.h:63
llvm
Definition: AllocatorList.h:23
llvm::IdentifyingPassPtr::IdentifyingPassPtr
IdentifyingPassPtr()
Definition: TargetPassConfig.h:61
llvm::IdentifyingPassPtr::getInstance
Pass * getInstance() const
Definition: TargetPassConfig.h:73
llvm::ImmutablePass
ImmutablePass class - This class is used to provide information that does not need to be run.
Definition: Pass.h:269
llvm::TargetPassConfig::willCompleteCodeGenPipeline
static bool willCompleteCodeGenPipeline()
Returns true if none of the -stop-before and -stop-after options is set.
Definition: TargetPassConfig.cpp:619
P
This currently compiles esp xmm0 movsd esp eax eax esp ret We should use not the dag combiner This is because dagcombine2 needs to be able to see through the X86ISD::Wrapper which DAGCombine can t really do The code for turning x load into a single vector load is target independent and should be moved to the dag combiner The code for turning x load into a vector load can only handle a direct load from a global or a direct load from the stack It should be generalized to handle any load from P
Definition: README-SSE.txt:411
Pass.h
llvm::IdentifyingPassPtr::isInstance
bool isInstance() const
Definition: TargetPassConfig.h:66
llvm::TargetPassConfig::addStripDebugPass
void addStripDebugPass()
Add a pass to remove debug info from the MIR.
Definition: TargetPassConfig.cpp:770
llvm::TargetPassConfig::addPreLegalizeMachineIR
virtual void addPreLegalizeMachineIR()
This method may be implemented by targets that want to run passes immediately before legalization.
Definition: TargetPassConfig.h:250
llvm::TargetPassConfig::addPreRewrite
virtual bool addPreRewrite()
addPreRewrite - Add passes to the optimized register allocation pipeline after register allocation is...
Definition: TargetPassConfig.h:405
llvm::TargetPassConfig::createRegAllocPass
virtual FunctionPass * createRegAllocPass(bool Optimized)
addMachinePasses helper to create the target-selected or overriden regalloc pass.
Definition: TargetPassConfig.cpp:1305
llvm::TargetPassConfig::addGCPasses
virtual bool addGCPasses()
addGCPasses - Add late codegen passes that analyze code for garbage collection.
Definition: TargetPassConfig.cpp:1442
llvm::AnalysisID
const void * AnalysisID
Definition: Pass.h:47
llvm::IdentifyingPassPtr::P
Pass * P
Definition: TargetPassConfig.h:56
llvm::TargetPassConfig::addPostRewrite
virtual void addPostRewrite()
Add passes to be run immediately after virtual registers are rewritten to physical registers.
Definition: TargetPassConfig.h:415
llvm::TargetPassConfig::addPreSched2
virtual void addPreSched2()
This method may be implemented by targets that want to run passes after prolog-epilog insertion and b...
Definition: TargetPassConfig.h:426
llvm::TargetPassConfig::setEnableTailMerge
void setEnableTailMerge(bool Enable)
Definition: TargetPassConfig.h:177
llvm::PassConfigImpl
Definition: TargetPassConfig.cpp:337
llvm::TargetPassConfig::createMachineScheduler
virtual ScheduleDAGInstrs * createMachineScheduler(MachineSchedContext *C) const
Create an instance of ScheduleDAGInstrs to be run within the standard MachineScheduler pass for this ...
Definition: TargetPassConfig.h:289
llvm::IdentifyingPassPtr
Discriminated union of Pass ID types.
Definition: TargetPassConfig.h:53
llvm::TargetPassConfig::addRegAssignAndRewriteFast
virtual bool addRegAssignAndRewriteFast()
Add core register allocator passes which do the actual register assignment and rewriting.
Definition: TargetPassConfig.cpp:1318
llvm::TargetPassConfig::addPreRegBankSelect
virtual void addPreRegBankSelect()
This method may be implemented by targets that want to run passes immediately before the register ban...
Definition: TargetPassConfig.h:258
llvm::TargetPassConfig::isGISelCSEEnabled
virtual bool isGISelCSEEnabled() const
Check whether continuous CSE should be enabled in GISel passes.
Definition: TargetPassConfig.cpp:1467
llvm::TargetPassConfig::addInstSelector
virtual bool addInstSelector()
addInstSelector - This method should install an instruction selector pass, which converts from LLVM c...
Definition: TargetPassConfig.h:240
llvm::TargetPassConfig::TM
LLVMTargetMachine * TM
Definition: TargetPassConfig.h:122
llvm::registerCodeGenCallback
void registerCodeGenCallback(PassInstrumentationCallbacks &PIC, LLVMTargetMachine &)
Definition: TargetPassConfig.cpp:528
llvm::IdentifyingPassPtr::ID
AnalysisID ID
Definition: TargetPassConfig.h:55
llvm::TargetPassConfig::printAndVerify
void printAndVerify(const std::string &Banner)
printAndVerify - Add a pass to dump then verify the machine function, if those steps are enabled.
Definition: TargetPassConfig.cpp:746
llvm::TargetPassConfig::substitutePass
void substitutePass(AnalysisID StandardID, IdentifyingPassPtr TargetID)
Allow the target to override a specific pass without overriding the pass pipeline.
Definition: TargetPassConfig.cpp:654
llvm::IdentifyingPassPtr::isValid
bool isValid() const
Definition: TargetPassConfig.h:65
llvm::TargetPassConfig::addVerifyPass
void addVerifyPass(const std::string &Banner)
Add a pass to perform basic verification of the machine function if verification is enabled.
Definition: TargetPassConfig.cpp:756
llvm::TargetPassConfig::setDisableVerify
void setDisableVerify(bool Disable)
Definition: TargetPassConfig.h:174
llvm::TargetPassConfig::hasLimitedCodeGenPipeline
static bool hasLimitedCodeGenPipeline()
Returns true if one of the -start-after, -start-before, -stop-after or -stop-before options is set.
Definition: TargetPassConfig.cpp:623
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
llvm::TargetPassConfig::createPostMachineScheduler
virtual ScheduleDAGInstrs * createPostMachineScheduler(MachineSchedContext *C) const
Similar to createMachineScheduler but used when postRA machine scheduling is enabled.
Definition: TargetPassConfig.h:296
llvm::TargetPassConfig::getEnableTailMerge
bool getEnableTailMerge() const
Definition: TargetPassConfig.h:176
llvm::TargetPassConfig::isGlobalISelAbortEnabled
bool isGlobalISelAbortEnabled() const
Check whether or not GlobalISel should abort on error.
Definition: TargetPassConfig.cpp:1459
llvm::IdentifyingPassPtr::IdentifyingPassPtr
IdentifyingPassPtr(AnalysisID IDPtr)
Definition: TargetPassConfig.h:62
llvm::TargetPassConfig::getPassSubstitution
IdentifyingPassPtr getPassSubstitution(AnalysisID StandardID) const
Return the pass substituted for StandardID by the target.
Definition: TargetPassConfig.cpp:659
llvm::TargetPassConfig::addMachinePrePasses
void addMachinePrePasses(bool AllowDebugify=true)
Add standard passes before a pass that's about to be added.
Definition: TargetPassConfig.cpp:778
llvm::TargetPassConfig::addPostFastRegAllocRewrite
virtual bool addPostFastRegAllocRewrite()
addPostFastRegAllocRewrite - Add passes to the optimized register allocation pipeline after fast regi...
Definition: TargetPassConfig.h:411
llvm::TargetPassConfig::setRequiresCodeGenSCCOrder
void setRequiresCodeGenSCCOrder(bool Enable=true)
Definition: TargetPassConfig.h:180
llvm::TargetPassConfig
Target-Independent Code Generator Pass Configuration Options.
Definition: TargetPassConfig.h:84
llvm::TargetPassConfig::usingDefaultRegAlloc
bool usingDefaultRegAlloc() const
Return true if the default global register allocator is in use and has not be overriden on the comman...
Definition: TargetPassConfig.cpp:1346
llvm::TargetPassConfig::DisableVerify
bool DisableVerify
Definition: TargetPassConfig.h:128
llvm::TargetPassConfig::addMachinePasses
virtual void addMachinePasses()
Add the complete, standard set of LLVM CodeGen passes.
Definition: TargetPassConfig.cpp:1084
llvm::TargetPassConfig::isPassSubstitutedOrOverridden
bool isPassSubstitutedOrOverridden(AnalysisID ID) const
Return true if the pass has been substituted by the target or overridden on the command line.
Definition: TargetPassConfig.cpp:667
llvm::TargetPassConfig::getLimitedCodeGenPipelineReason
static std::string getLimitedCodeGenPipelineReason(const char *Separator="/")
If hasLimitedCodeGenPipeline is true, this method returns a string with the name of the options,...
Definition: TargetPassConfig.cpp:629
llvm::TargetPassConfig::addRegBankSelect
virtual bool addRegBankSelect()
This method should install a register bank selector pass, which assigns register banks to virtual reg...
Definition: TargetPassConfig.h:263
llvm::TargetPassConfig::RequireCodeGenSCCOrder
bool RequireCodeGenSCCOrder
Require processing of functions such that callees are generated before callers.
Definition: TargetPassConfig.h:135
llvm::TargetPassConfig::addPreGlobalInstructionSelect
virtual void addPreGlobalInstructionSelect()
This method may be implemented by targets that want to run passes immediately before the (global) ins...
Definition: TargetPassConfig.h:267
llvm::TargetPassConfig::EnableTailMerge
bool EnableTailMerge
Default setting for -enable-tail-merge on this target.
Definition: TargetPassConfig.h:131
llvm::MachineSchedContext
MachineSchedContext provides enough context from the MachineScheduler pass for the target to instanti...
Definition: MachineScheduler.h:120
llvm::TargetPassConfig::addIRPasses
virtual void addIRPasses()
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
Definition: TargetPassConfig.cpp:800
llvm::TargetPassConfig::addOptimizedRegAlloc
virtual void addOptimizedRegAlloc()
addOptimizedRegAlloc - Add passes related to register allocation.
Definition: TargetPassConfig.cpp:1362
llvm::TargetPassConfig::addRegAssignAndRewriteOptimized
virtual bool addRegAssignAndRewriteOptimized()
Definition: TargetPassConfig.cpp:1331
llvm::TargetPassConfig::addPreEmitPass2
virtual void addPreEmitPass2()
Targets may add passes immediately before machine code is emitted in this callback.
Definition: TargetPassConfig.h:445
Enable
@ Enable
Definition: DwarfDebug.cpp:88
llvm::TargetPassConfig::addCodeGenPrepare
virtual void addCodeGenPrepare()
Add pass to prepare the LLVM IR for code generation.
Definition: TargetPassConfig.cpp:929
llvm::TargetPassConfig::getOptimizeRegAlloc
bool getOptimizeRegAlloc() const
Return true if the optimized regalloc pipeline is enabled.
Definition: TargetPassConfig.cpp:1258
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::TargetPassConfig::addCheckDebugPass
void addCheckDebugPass()
Add a pass to check synthesized debug info for MIR.
Definition: TargetPassConfig.cpp:774
llvm::TargetPassConfig::setInitialized
void setInitialized()
Definition: TargetPassConfig.h:156
llvm::TargetPassConfig::addIRTranslator
virtual bool addIRTranslator()
This method should install an IR translator pass, which converts from LLVM code to machine instructio...
Definition: TargetPassConfig.h:246
llvm::TargetPassConfig::addISelPasses
bool addISelPasses()
High level function that adds all passes necessary to go from llvm IR representation to the MI repres...
Definition: TargetPassConfig.cpp:1045
llvm::TargetPassConfig::getTM
TMC & getTM() const
Get the right type of TargetMachine for this target.
Definition: TargetPassConfig.h:151
llvm::TargetPassConfig::reportDiagnosticWhenGlobalISelFallback
virtual bool reportDiagnosticWhenGlobalISelFallback() const
Check whether or not a diagnostic should be emitted when GlobalISel uses the fallback path.
Definition: TargetPassConfig.cpp:1463
llvm::TargetPassConfig::addDebugifyPass
void addDebugifyPass()
Add a pass to add synthesized debug info to the MIR.
Definition: TargetPassConfig.cpp:766
adjust::pm
static void pm(uint64_t &Value)
Adjusts a program memory address.
Definition: AVRAsmBackend.cpp:192
llvm::CodeGenOpt::Level
Level
Definition: CodeGen.h:52
llvm::TargetPassConfig::addPreRegAlloc
virtual void addPreRegAlloc()
This method may be implemented by targets that want to run passes immediately before register allocat...
Definition: TargetPassConfig.h:379
Disable
@ Disable
Definition: DwarfDebug.cpp:88
llvm::TargetPassConfig::getCSEConfig
virtual std::unique_ptr< CSEConfigBase > getCSEConfig() const
Returns the CSEConfig object to use for the current optimization level.
Definition: TargetPassConfig.cpp:1471
llvm::TargetPassConfig::addPass
AnalysisID addPass(AnalysisID PassID, bool verifyAfter=true)
Utilities for targets to add passes to the pass manager.
Definition: TargetPassConfig.cpp:726
llvm::TargetPassConfig::requiresCodeGenSCCOrder
bool requiresCodeGenSCCOrder() const
Definition: TargetPassConfig.h:179
llvm::TargetPassConfig::Impl
PassConfigImpl * Impl
Definition: TargetPassConfig.h:123
llvm::TargetPassConfig::addMachineSSAOptimization
virtual void addMachineSSAOptimization()
addMachineSSAOptimization - Add standard passes that optimize machine instructions in SSA form.
Definition: TargetPassConfig.cpp:1216
llvm::TargetPassConfig::addLegalizeMachineIR
virtual bool addLegalizeMachineIR()
This method should install a legalize pass, which converts the instruction sequence into one that can...
Definition: TargetPassConfig.h:254
llvm::LLVMTargetMachine
This class describes a target machine that is implemented with the LLVM target-independent code gener...
Definition: TargetMachine.h:385
llvm::TargetPassConfig::disablePass
void disablePass(AnalysisID PassID)
Allow the target to disable a specific standard pass by default.
Definition: TargetPassConfig.h:197
llvm::IdentifyingPassPtr::getID
AnalysisID getID() const
Definition: TargetPassConfig.h:68
llvm::TargetPassConfig::addBlockPlacement
virtual void addBlockPlacement()
Add standard basic block placement passes.
Definition: TargetPassConfig.cpp:1448
CodeGen.h
llvm::TargetPassConfig::createTargetRegisterAllocator
virtual FunctionPass * createTargetRegisterAllocator(bool Optimized)
createTargetRegisterAllocator - Create the register allocator pass for this target at the current opt...
Definition: TargetPassConfig.cpp:1289
llvm::Pass
Pass interface - Implemented by all 'passes'.
Definition: Pass.h:91
llvm::TargetPassConfig::addISelPrepare
virtual void addISelPrepare()
Add common passes that perform LLVM IR to IR transforms in preparation for instruction selection.
Definition: TargetPassConfig.cpp:937
llvm::TargetPassConfig::addGlobalInstructionSelect
virtual bool addGlobalInstructionSelect()
This method should install a (global) instruction selector pass, which converts possibly generic inst...
Definition: TargetPassConfig.h:273
llvm::TargetPassConfig::addPreISel
virtual bool addPreISel()
Methods with trivial inline returns are convenient points in the common codegen pass pipeline where t...
Definition: TargetPassConfig.h:359
llvm::legacy::PassManagerBase
PassManagerBase - An abstract interface to allow code to add passes to a pass manager without having ...
Definition: LegacyPassManager.h:39
llvm::TargetPassConfig::addPassesToHandleExceptions
void addPassesToHandleExceptions()
Add passes to lower exception handling for the code generator.
Definition: TargetPassConfig.cpp:885
llvm::FunctionPass
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:298
llvm::TargetPassConfig::TargetPassConfig
TargetPassConfig()
Definition: TargetPassConfig.cpp:612
llvm::ScheduleDAGInstrs
A ScheduleDAG for scheduling lists of MachineInstr.
Definition: ScheduleDAGInstrs.h:119
llvm::TargetPassConfig::addPreEmitPass
virtual void addPreEmitPass()
This pass may be implemented by targets that want to run passes immediately before machine code is em...
Definition: TargetPassConfig.h:438
llvm::TargetPassConfig::Initialized
bool Initialized
Definition: TargetPassConfig.h:124
true
basic Basic Alias true
Definition: BasicAliasAnalysis.cpp:1797
llvm::TargetPassConfig::addFastRegAlloc
virtual void addFastRegAlloc()
addFastRegAlloc - Add the minimum set of target-independent passes that are required for fast registe...
Definition: TargetPassConfig.cpp:1352
llvm::TargetPassConfig::addCoreISelPasses
bool addCoreISelPasses()
Add the actual instruction selection passes.
Definition: TargetPassConfig.cpp:959
llvm::TargetPassConfig::insertPass
void insertPass(AnalysisID TargetPassID, IdentifyingPassPtr InsertedPassID, bool VerifyAfter=true)
Insert InsertedPassID pass after TargetPassID pass.
Definition: TargetPassConfig.cpp:593
llvm::TargetPassConfig::addPrintPass
void addPrintPass(const std::string &Banner)
Add a pass to print the machine function if printing is enabled.
Definition: TargetPassConfig.cpp:751
llvm::TargetPassConfig::addMachinePostPasses
void addMachinePostPasses(const std::string &Banner, bool AllowVerify=true, bool AllowStrip=true)
Add standard passes after a pass that has just been added.
Definition: TargetPassConfig.cpp:785
llvm::TargetPassConfig::addILPOpts
virtual bool addILPOpts()
Add passes that optimize instruction level parallelism for out-of-order targets.
Definition: TargetPassConfig.h:373
llvm::TargetPassConfig::getOptLevel
CodeGenOpt::Level getOptLevel() const
Definition: TargetPassConfig.cpp:588
llvm::TargetPassConfig::setOpt
void setOpt(bool &Opt, bool Val)
Definition: TargetPassConfig.cpp:649
llvm::TargetPassConfig::~TargetPassConfig
~TargetPassConfig() override
Definition: TargetPassConfig.cpp:356
llvm::TargetPassConfig::addMachineLateOptimization
virtual void addMachineLateOptimization()
Add passes that optimize machine instructions after register allocation.
Definition: TargetPassConfig.cpp:1426
llvm::TargetPassConfig::enablePass
void enablePass(AnalysisID PassID)
Allow the target to enable a specific standard pass by default.
Definition: TargetPassConfig.h:194