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13 #ifndef LLVM_CODEGEN_TARGETPASSCONFIG_H
14 #define LLVM_CODEGEN_TARGETPASSCONFIG_H
23 class LLVMTargetMachine;
24 struct MachineSchedContext;
26 class ScheduleDAGInstrs;
28 class PassInstrumentationCallbacks;
58 bool IsInstance =
false;
69 assert(!IsInstance &&
"Not a Pass ID");
74 assert(IsInstance &&
"Not a Pass Instance");
92 unsigned StartBeforeInstanceNum = 0;
93 unsigned StartBeforeCount = 0;
95 unsigned StartAfterInstanceNum = 0;
96 unsigned StartAfterCount = 0;
98 unsigned StopBeforeInstanceNum = 0;
99 unsigned StopBeforeCount = 0;
101 unsigned StopAfterInstanceNum = 0;
102 unsigned StopAfterCount = 0;
105 bool Stopped =
false;
106 bool AddingMachinePasses =
false;
107 bool DebugifyIsSafe =
true;
119 void setStartStopPasses();
151 template<
typename TMC> TMC &
getTM()
const {
152 return *
static_cast<TMC*
>(
TM);
342 virtual std::unique_ptr<CSEConfigBase>
getCSEConfig()
const;
346 void setOpt(
bool &Opt,
bool Val);
471 LLVMTargetMachine &);
475 #endif // LLVM_CODEGEN_TARGETPASSCONFIG_H
virtual void addPostRegAlloc()
This method may be implemented by targets that want to run passes after register allocation pass pipe...
IdentifyingPassPtr(Pass *InstancePtr)
This is an optimization pass for GlobalISel generic memory operations.
Pass * getInstance() const
ImmutablePass class - This class is used to provide information that does not need to be run.
static bool willCompleteCodeGenPipeline()
Returns true if none of the -stop-before and -stop-after options is set.
This currently compiles esp xmm0 movsd esp eax eax esp ret We should use not the dag combiner This is because dagcombine2 needs to be able to see through the X86ISD::Wrapper which DAGCombine can t really do The code for turning x load into a single vector load is target independent and should be moved to the dag combiner The code for turning x load into a vector load can only handle a direct load from a global or a direct load from the stack It should be generalized to handle any load from P
void addStripDebugPass()
Add a pass to remove debug info from the MIR.
virtual void addPreLegalizeMachineIR()
This method may be implemented by targets that want to run passes immediately before legalization.
virtual bool addPreRewrite()
addPreRewrite - Add passes to the optimized register allocation pipeline after register allocation is...
virtual FunctionPass * createRegAllocPass(bool Optimized)
addMachinePasses helper to create the target-selected or overriden regalloc pass.
virtual bool addGCPasses()
addGCPasses - Add late codegen passes that analyze code for garbage collection.
virtual void addPostRewrite()
Add passes to be run immediately after virtual registers are rewritten to physical registers.
virtual void addPreSched2()
This method may be implemented by targets that want to run passes after prolog-epilog insertion and b...
void setEnableTailMerge(bool Enable)
PassInstrumentationCallbacks PIC
virtual ScheduleDAGInstrs * createMachineScheduler(MachineSchedContext *C) const
Create an instance of ScheduleDAGInstrs to be run within the standard MachineScheduler pass for this ...
Discriminated union of Pass ID types.
virtual bool addRegAssignAndRewriteFast()
Add core register allocator passes which do the actual register assignment and rewriting.
virtual void addPreRegBankSelect()
This method may be implemented by targets that want to run passes immediately before the register ban...
virtual bool isGISelCSEEnabled() const
Check whether continuous CSE should be enabled in GISel passes.
virtual bool addInstSelector()
addInstSelector - This method should install an instruction selector pass, which converts from LLVM c...
void registerCodeGenCallback(PassInstrumentationCallbacks &PIC, LLVMTargetMachine &)
void printAndVerify(const std::string &Banner)
printAndVerify - Add a pass to dump then verify the machine function, if those steps are enabled.
void substitutePass(AnalysisID StandardID, IdentifyingPassPtr TargetID)
Allow the target to override a specific pass without overriding the pass pipeline.
void addVerifyPass(const std::string &Banner)
Add a pass to perform basic verification of the machine function if verification is enabled.
void setDisableVerify(bool Disable)
static bool hasLimitedCodeGenPipeline()
Returns true if one of the -start-after, -start-before, -stop-after or -stop-before options is set.
(vector float) vec_cmpeq(*A, *B) C
virtual ScheduleDAGInstrs * createPostMachineScheduler(MachineSchedContext *C) const
Similar to createMachineScheduler but used when postRA machine scheduling is enabled.
bool getEnableTailMerge() const
bool isGlobalISelAbortEnabled() const
Check whether or not GlobalISel should abort on error.
IdentifyingPassPtr(AnalysisID IDPtr)
IdentifyingPassPtr getPassSubstitution(AnalysisID StandardID) const
Return the pass substituted for StandardID by the target.
void addMachinePrePasses(bool AllowDebugify=true)
Add standard passes before a pass that's about to be added.
virtual bool addPostFastRegAllocRewrite()
addPostFastRegAllocRewrite - Add passes to the optimized register allocation pipeline after fast regi...
void setRequiresCodeGenSCCOrder(bool Enable=true)
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Target-Independent Code Generator Pass Configuration Options.
bool usingDefaultRegAlloc() const
Return true if the default global register allocator is in use and has not be overriden on the comman...
virtual void addMachinePasses()
Add the complete, standard set of LLVM CodeGen passes.
bool isPassSubstitutedOrOverridden(AnalysisID ID) const
Return true if the pass has been substituted by the target or overridden on the command line.
static std::string getLimitedCodeGenPipelineReason(const char *Separator="/")
If hasLimitedCodeGenPipeline is true, this method returns a string with the name of the options,...
virtual bool addRegBankSelect()
This method should install a register bank selector pass, which assigns register banks to virtual reg...
bool RequireCodeGenSCCOrder
Require processing of functions such that callees are generated before callers.
virtual void addPreGlobalInstructionSelect()
This method may be implemented by targets that want to run passes immediately before the (global) ins...
bool EnableTailMerge
Default setting for -enable-tail-merge on this target.
MachineSchedContext provides enough context from the MachineScheduler pass for the target to instanti...
virtual void addIRPasses()
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
virtual void addOptimizedRegAlloc()
addOptimizedRegAlloc - Add passes related to register allocation.
virtual bool addRegAssignAndRewriteOptimized()
virtual void addPreEmitPass2()
Targets may add passes immediately before machine code is emitted in this callback.
virtual void addCodeGenPrepare()
Add pass to prepare the LLVM IR for code generation.
bool getOptimizeRegAlloc() const
Return true if the optimized regalloc pipeline is enabled.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
void addCheckDebugPass()
Add a pass to check synthesized debug info for MIR.
virtual bool addIRTranslator()
This method should install an IR translator pass, which converts from LLVM code to machine instructio...
bool addISelPasses()
High level function that adds all passes necessary to go from llvm IR representation to the MI repres...
AnalysisID addPass(AnalysisID PassID)
Utilities for targets to add passes to the pass manager.
TMC & getTM() const
Get the right type of TargetMachine for this target.
virtual bool reportDiagnosticWhenGlobalISelFallback() const
Check whether or not a diagnostic should be emitted when GlobalISel uses the fallback path.
void addDebugifyPass()
Add a pass to add synthesized debug info to the MIR.
static void pm(uint64_t &Value)
Adjusts a program memory address.
virtual void addPreRegAlloc()
This method may be implemented by targets that want to run passes immediately before register allocat...
virtual std::unique_ptr< CSEConfigBase > getCSEConfig() const
Returns the CSEConfig object to use for the current optimization level.
bool requiresCodeGenSCCOrder() const
virtual void addMachineSSAOptimization()
addMachineSSAOptimization - Add standard passes that optimize machine instructions in SSA form.
virtual bool addLegalizeMachineIR()
This method should install a legalize pass, which converts the instruction sequence into one that can...
void addMachinePostPasses(const std::string &Banner)
Add standard passes after a pass that has just been added.
This class describes a target machine that is implemented with the LLVM target-independent code gener...
void disablePass(AnalysisID PassID)
Allow the target to disable a specific standard pass by default.
virtual void addBlockPlacement()
Add standard basic block placement passes.
virtual FunctionPass * createTargetRegisterAllocator(bool Optimized)
createTargetRegisterAllocator - Create the register allocator pass for this target at the current opt...
Pass interface - Implemented by all 'passes'.
virtual void addISelPrepare()
Add common passes that perform LLVM IR to IR transforms in preparation for instruction selection.
virtual bool addGlobalInstructionSelect()
This method should install a (global) instruction selector pass, which converts possibly generic inst...
virtual bool addPreISel()
Methods with trivial inline returns are convenient points in the common codegen pass pipeline where t...
PassManagerBase - An abstract interface to allow code to add passes to a pass manager without having ...
void addPassesToHandleExceptions()
Add passes to lower exception handling for the code generator.
FunctionPass class - This class is used to implement most global optimizations.
Level
Code generation optimization level.
A ScheduleDAG for scheduling lists of MachineInstr.
virtual void addPreEmitPass()
This pass may be implemented by targets that want to run passes immediately before machine code is em...
void insertPass(AnalysisID TargetPassID, IdentifyingPassPtr InsertedPassID)
Insert InsertedPassID pass after TargetPassID pass.
virtual void addFastRegAlloc()
addFastRegAlloc - Add the minimum set of target-independent passes that are required for fast registe...
bool addCoreISelPasses()
Add the actual instruction selection passes.
void addPrintPass(const std::string &Banner)
Add a pass to print the machine function if printing is enabled.
virtual bool addILPOpts()
Add passes that optimize instruction level parallelism for out-of-order targets.
CodeGenOpt::Level getOptLevel() const
bool isCustomizedRegAlloc()
Return true if register allocator is specified by -regalloc=override.
void setOpt(bool &Opt, bool Val)
~TargetPassConfig() override
virtual void addMachineLateOptimization()
Add passes that optimize machine instructions after register allocation.
void enablePass(AnalysisID PassID)
Allow the target to enable a specific standard pass by default.