LLVM  14.0.0git
ScheduleDAGInstrs.h
Go to the documentation of this file.
1 //===- ScheduleDAGInstrs.h - MachineInstr Scheduling ------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file Implements the ScheduleDAGInstrs class, which implements scheduling
10 /// for a MachineInstr-based dependency graph.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_CODEGEN_SCHEDULEDAGINSTRS_H
15 #define LLVM_CODEGEN_SCHEDULEDAGINSTRS_H
16 
17 #include "llvm/ADT/DenseMap.h"
19 #include "llvm/ADT/STLExtras.h"
20 #include "llvm/ADT/SmallVector.h"
22 #include "llvm/ADT/SparseSet.h"
28 #include "llvm/MC/LaneBitmask.h"
29 #include <cassert>
30 #include <cstdint>
31 #include <list>
32 #include <utility>
33 #include <vector>
34 
35 namespace llvm {
36 
37  class AAResults;
38  class LiveIntervals;
39  class MachineFrameInfo;
40  class MachineFunction;
41  class MachineInstr;
42  class MachineLoopInfo;
43  class MachineOperand;
44  struct MCSchedClassDesc;
45  class PressureDiffs;
46  class PseudoSourceValue;
47  class RegPressureTracker;
48  class UndefValue;
49  class Value;
50 
51  /// An individual mapping from virtual register number to SUnit.
52  struct VReg2SUnit {
53  unsigned VirtReg;
56 
58  : VirtReg(VReg), LaneMask(LaneMask), SU(SU) {}
59 
60  unsigned getSparseSetIndex() const {
62  }
63  };
64 
65  /// Mapping from virtual register to SUnit including an operand index.
66  struct VReg2SUnitOperIdx : public VReg2SUnit {
67  unsigned OperandIndex;
68 
70  unsigned OperandIndex, SUnit *SU)
72  };
73 
74  /// Record a physical register access.
75  /// For non-data-dependent uses, OpIdx == -1.
76  struct PhysRegSUOper {
78  int OpIdx;
79  unsigned Reg;
80 
81  PhysRegSUOper(SUnit *su, int op, unsigned R): SU(su), OpIdx(op), Reg(R) {}
82 
83  unsigned getSparseSetIndex() const { return Reg; }
84  };
85 
86  /// Use a SparseMultiSet to track physical registers. Storage is only
87  /// allocated once for the pass. It can be cleared in constant time and reused
88  /// without any frees.
89  using Reg2SUnitsMap =
91 
92  /// Use SparseSet as a SparseMap by relying on the fact that it never
93  /// compares ValueT's, only unsigned keys. This allows the set to be cleared
94  /// between scheduling regions in constant time as long as ValueT does not
95  /// require a destructor.
97 
98  /// Track local uses of virtual registers. These uses are gathered by the DAG
99  /// builder and may be consulted by the scheduler to avoid iterating an entire
100  /// vreg use list.
102 
105 
107 
108  struct UnderlyingObject : PointerIntPair<ValueType, 1, bool> {
109  UnderlyingObject(ValueType V, bool MayAlias)
110  : PointerIntPair<ValueType, 1, bool>(V, MayAlias) {}
111 
112  ValueType getValue() const { return getPointer(); }
113  bool mayAlias() const { return getInt(); }
114  };
115 
117 
118  /// A ScheduleDAG for scheduling lists of MachineInstr.
120  protected:
123 
124  /// TargetSchedModel provides an interface to the machine model.
126 
127  /// True if the DAG builder should remove kill flags (in preparation for
128  /// rescheduling).
130 
131  /// The standard DAG builder does not normally include terminators as DAG
132  /// nodes because it does not create the necessary dependencies to prevent
133  /// reordering. A specialized scheduler can override
134  /// TargetInstrInfo::isSchedulingBoundary then enable this flag to indicate
135  /// it has taken responsibility for scheduling the terminator correctly.
136  bool CanHandleTerminators = false;
137 
138  /// Whether lane masks should get tracked.
139  bool TrackLaneMasks = false;
140 
141  // State specific to the current scheduling region.
142  // ------------------------------------------------
143 
144  /// The block in which to insert instructions
146 
147  /// The beginning of the range to be scheduled.
149 
150  /// The end of the range to be scheduled.
152 
153  /// Instructions in this region (distance(RegionBegin, RegionEnd)).
154  unsigned NumRegionInstrs;
155 
156  /// After calling BuildSchedGraph, each machine instruction in the current
157  /// scheduling region is mapped to an SUnit.
159 
160  // State internal to DAG building.
161  // -------------------------------
162 
163  /// Defs, Uses - Remember where defs and uses of each register are as we
164  /// iterate upward through the instructions. This is allocated here instead
165  /// of inside BuildSchedGraph to avoid the need for it to be initialized and
166  /// destructed for each block.
169 
170  /// Tracks the last instruction(s) in this region defining each virtual
171  /// register. There may be multiple current definitions for a register with
172  /// disjunct lanemasks.
174  /// Tracks the last instructions in this region using each virtual register.
176 
177  AAResults *AAForDep = nullptr;
178 
179  /// Remember a generic side-effecting instruction as we proceed.
180  /// No other SU ever gets scheduled around it (except in the special
181  /// case of a huge region that gets reduced).
182  SUnit *BarrierChain = nullptr;
183 
184  public:
185  /// A list of SUnits, used in Value2SUsMap, during DAG construction.
186  /// Note: to gain speed it might be worth investigating an optimized
187  /// implementation of this data structure, such as a singly linked list
188  /// with a memory pool (SmallVector was tried but slow and SparseSet is not
189  /// applicable).
190  using SUList = std::list<SUnit *>;
191 
192  protected:
193  /// A map from ValueType to SUList, used during DAG construction, as
194  /// a means of remembering which SUs depend on which memory locations.
195  class Value2SUsMap;
196 
197  /// Reduces maps in FIFO order, by N SUs. This is better than turning
198  /// every Nth memory SU into BarrierChain in buildSchedGraph(), since
199  /// it avoids unnecessary edges between seen SUs above the new BarrierChain,
200  /// and those below it.
202  Value2SUsMap &loads, unsigned N);
203 
204  /// Adds a chain edge between SUa and SUb, but only if both
205  /// AAResults and Target fail to deny the dependency.
206  void addChainDependency(SUnit *SUa, SUnit *SUb,
207  unsigned Latency = 0);
208 
209  /// Adds dependencies as needed from all SUs in list to SU.
210  void addChainDependencies(SUnit *SU, SUList &SUs, unsigned Latency) {
211  for (SUnit *Entry : SUs)
212  addChainDependency(SU, Entry, Latency);
213  }
214 
215  /// Adds dependencies as needed from all SUs in map, to SU.
216  void addChainDependencies(SUnit *SU, Value2SUsMap &Val2SUsMap);
217 
218  /// Adds dependencies as needed to SU, from all SUs mapped to V.
219  void addChainDependencies(SUnit *SU, Value2SUsMap &Val2SUsMap,
220  ValueType V);
221 
222  /// Adds barrier chain edges from all SUs in map, and then clear the map.
223  /// This is equivalent to insertBarrierChain(), but optimized for the common
224  /// case where the new BarrierChain (a global memory object) has a higher
225  /// NodeNum than all SUs in map. It is assumed BarrierChain has been set
226  /// before calling this.
227  void addBarrierChain(Value2SUsMap &map);
228 
229  /// Inserts a barrier chain in a huge region, far below current SU.
230  /// Adds barrier chain edges from all SUs in map with higher NodeNums than
231  /// this new BarrierChain, and remove them from map. It is assumed
232  /// BarrierChain has been set before calling this.
233  void insertBarrierChain(Value2SUsMap &map);
234 
235  /// For an unanalyzable memory access, this Value is used in maps.
237 
238 
239  /// Topo - A topological ordering for SUnits which permits fast IsReachable
240  /// and similar queries.
242 
243  using DbgValueVector =
244  std::vector<std::pair<MachineInstr *, MachineInstr *>>;
245  /// Remember instruction that precedes DBG_VALUE.
246  /// These are generated by buildSchedGraph but persist so they can be
247  /// referenced when emitting the final schedule.
250 
251  /// Set of live physical registers for updating kill flags.
253 
254  public:
255  explicit ScheduleDAGInstrs(MachineFunction &mf,
256  const MachineLoopInfo *mli,
257  bool RemoveKillFlags = false);
258 
259  ~ScheduleDAGInstrs() override = default;
260 
261  /// Gets the machine model for instruction scheduling.
262  const TargetSchedModel *getSchedModel() const { return &SchedModel; }
263 
264  /// Resolves and cache a resolved scheduling class for an SUnit.
268  return SU->SchedClass;
269  }
270 
271  /// IsReachable - Checks if SU is reachable from TargetSU.
272  bool IsReachable(SUnit *SU, SUnit *TargetSU) {
273  return Topo.IsReachable(SU, TargetSU);
274  }
275 
276  /// Returns an iterator to the top of the current scheduling region.
278 
279  /// Returns an iterator to the bottom of the current scheduling region.
281 
282  /// Creates a new SUnit and return a ptr to it.
284 
285  /// Returns an existing SUnit for this MI, or nullptr.
286  SUnit *getSUnit(MachineInstr *MI) const;
287 
288  /// If this method returns true, handling of the scheduling regions
289  /// themselves (in case of a scheduling boundary in MBB) will be done
290  /// beginning with the topmost region of MBB.
291  virtual bool doMBBSchedRegionsTopDown() const { return false; }
292 
293  /// Prepares to perform scheduling in the given block.
294  virtual void startBlock(MachineBasicBlock *BB);
295 
296  /// Cleans up after scheduling in the given block.
297  virtual void finishBlock();
298 
299  /// Initialize the DAG and common scheduler state for a new
300  /// scheduling region. This does not actually create the DAG, only clears
301  /// it. The scheduling driver may call BuildSchedGraph multiple times per
302  /// scheduling region.
303  virtual void enterRegion(MachineBasicBlock *bb,
306  unsigned regioninstrs);
307 
308  /// Called when the scheduler has finished scheduling the current region.
309  virtual void exitRegion();
310 
311  /// Builds SUnits for the current region.
312  /// If \p RPTracker is non-null, compute register pressure as a side effect.
313  /// The DAG builder is an efficient place to do it because it already visits
314  /// operands.
315  void buildSchedGraph(AAResults *AA,
316  RegPressureTracker *RPTracker = nullptr,
317  PressureDiffs *PDiffs = nullptr,
318  LiveIntervals *LIS = nullptr,
319  bool TrackLaneMasks = false);
320 
321  /// Adds dependencies from instructions in the current list of
322  /// instructions being scheduled to scheduling barrier. We want to make sure
323  /// instructions which define registers that are either used by the
324  /// terminator or are live-out are properly scheduled. This is especially
325  /// important when the definition latency of the return value(s) are too
326  /// high to be hidden by the branch or when the liveout registers used by
327  /// instructions in the fallthrough block.
328  void addSchedBarrierDeps();
329 
330  /// Orders nodes according to selected style.
331  ///
332  /// Typically, a scheduling algorithm will implement schedule() without
333  /// overriding enterRegion() or exitRegion().
334  virtual void schedule() = 0;
335 
336  /// Allow targets to perform final scheduling actions at the level of the
337  /// whole MachineFunction. By default does nothing.
338  virtual void finalizeSchedule() {}
339 
340  void dumpNode(const SUnit &SU) const override;
341  void dump() const override;
342 
343  /// Returns a label for a DAG node that points to an instruction.
344  std::string getGraphNodeLabel(const SUnit *SU) const override;
345 
346  /// Returns a label for the region of code covered by the DAG.
347  std::string getDAGName() const override;
348 
349  /// Fixes register kill flags that scheduling has made invalid.
351 
352  /// True if an edge can be added from PredSU to SuccSU without creating
353  /// a cycle.
354  bool canAddEdge(SUnit *SuccSU, SUnit *PredSU);
355 
356  /// Add a DAG edge to the given SU with the given predecessor
357  /// dependence data.
358  ///
359  /// \returns true if the edge may be added without creating a cycle OR if an
360  /// equivalent edge already existed (false indicates failure).
361  bool addEdge(SUnit *SuccSU, const SDep &PredDep);
362 
363  protected:
364  void initSUnits();
365  void addPhysRegDataDeps(SUnit *SU, unsigned OperIdx);
366  void addPhysRegDeps(SUnit *SU, unsigned OperIdx);
367  void addVRegDefDeps(SUnit *SU, unsigned OperIdx);
368  void addVRegUseDeps(SUnit *SU, unsigned OperIdx);
369 
370  /// Returns a mask for which lanes get read/written by the given (register)
371  /// machine operand.
373 
374  /// Returns true if the def register in \p MO has no uses.
375  bool deadDefHasNoUse(const MachineOperand &MO);
376  };
377 
378  /// Creates a new SUnit and return a ptr to it.
380 #ifndef NDEBUG
381  const SUnit *Addr = SUnits.empty() ? nullptr : &SUnits[0];
382 #endif
383  SUnits.emplace_back(MI, (unsigned)SUnits.size());
384  assert((Addr == nullptr || Addr == &SUnits[0]) &&
385  "SUnits std::vector reallocated on the fly!");
386  return &SUnits.back();
387  }
388 
389  /// Returns an existing SUnit for this MI, or nullptr.
391  return MISUnitMap.lookup(MI);
392  }
393 
394 } // end namespace llvm
395 
396 #endif // LLVM_CODEGEN_SCHEDULEDAGINSTRS_H
llvm::ScheduleDAGInstrs::initSUnits
void initSUnits()
Creates an SUnit for each real instruction, numbered in top-down topological order.
Definition: ScheduleDAGInstrs.cpp:569
llvm::ScheduleDAGInstrs::FirstDbgValue
MachineInstr * FirstDbgValue
Definition: ScheduleDAGInstrs.h:249
llvm::LaneBitmask
Definition: LaneBitmask.h:40
llvm::ScheduleDAGInstrs::getDAGName
std::string getDAGName() const override
Returns a label for the region of code covered by the DAG.
Definition: ScheduleDAGInstrs.cpp:1197
llvm::VReg2SUnitOperIdx::OperandIndex
unsigned OperandIndex
Definition: ScheduleDAGInstrs.h:67
ScheduleDAG.h
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:103
llvm
---------------------— PointerInfo ------------------------------------—
Definition: AllocatorList.h:23
llvm::ScheduleDAGInstrs::addBarrierChain
void addBarrierChain(Value2SUsMap &map)
Adds barrier chain edges from all SUs in map, and then clear the map.
Definition: ScheduleDAGInstrs.cpp:686
llvm::ScheduleDAGInstrs::CurrentVRegUses
VReg2SUnitOperIdxMultiMap CurrentVRegUses
Tracks the last instructions in this region using each virtual register.
Definition: ScheduleDAGInstrs.h:175
llvm::Latency
@ Latency
Definition: SIMachineScheduler.h:34
llvm::ScheduleDAGInstrs::buildSchedGraph
void buildSchedGraph(AAResults *AA, RegPressureTracker *RPTracker=nullptr, PressureDiffs *PDiffs=nullptr, LiveIntervals *LIS=nullptr, bool TrackLaneMasks=false)
Builds SUnits for the current region.
Definition: ScheduleDAGInstrs.cpp:730
llvm::ScheduleDAGInstrs::begin
MachineBasicBlock::iterator begin() const
Returns an iterator to the top of the current scheduling region.
Definition: ScheduleDAGInstrs.h:277
llvm::UnderlyingObject
Definition: ScheduleDAGInstrs.h:108
op
#define op(i)
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1168
llvm::ScheduleDAGTopologicalSort::IsReachable
bool IsReachable(const SUnit *SU, const SUnit *TargetSU)
Checks if SU is reachable from TargetSU.
Definition: ScheduleDAG.cpp:724
llvm::ScheduleDAGInstrs::NumRegionInstrs
unsigned NumRegionInstrs
Instructions in this region (distance(RegionBegin, RegionEnd)).
Definition: ScheduleDAGInstrs.h:154
MachineBasicBlock.h
llvm::LivePhysRegs
A set of physical registers with utility functions to track liveness when walking backward/forward th...
Definition: LivePhysRegs.h:48
stores
hexagon widen stores
Definition: HexagonStoreWidening.cpp:118
llvm::ScheduleDAGInstrs::addEdge
bool addEdge(SUnit *SuccSU, const SDep &PredDep)
Add a DAG edge to the given SU with the given predecessor dependence data.
Definition: ScheduleDAGInstrs.cpp:1205
llvm::ScheduleDAGInstrs::Topo
ScheduleDAGTopologicalSort Topo
Topo - A topological ordering for SUnits which permits fast IsReachable and similar queries.
Definition: ScheduleDAGInstrs.h:241
llvm::ScheduleDAGInstrs::SUList
std::list< SUnit * > SUList
A list of SUnits, used in Value2SUsMap, during DAG construction.
Definition: ScheduleDAGInstrs.h:190
llvm::RegPressureTracker
Track the current register pressure at some position in the instruction stream, and remember the high...
Definition: RegisterPressure.h:358
DenseMap.h
llvm::ScheduleDAGInstrs::startBlock
virtual void startBlock(MachineBasicBlock *BB)
Prepares to perform scheduling in the given block.
Definition: ScheduleDAGInstrs.cpp:178
llvm::PressureDiffs
Array of PressureDiffs.
Definition: RegisterPressure.h:198
llvm::ScheduleDAGInstrs::getLaneMaskForMO
LaneBitmask getLaneMaskForMO(const MachineOperand &MO) const
Returns a mask for which lanes get read/written by the given (register) machine operand.
Definition: ScheduleDAGInstrs.cpp:368
STLExtras.h
llvm::ScheduleDAGInstrs::SchedModel
TargetSchedModel SchedModel
TargetSchedModel provides an interface to the machine model.
Definition: ScheduleDAGInstrs.h:125
llvm::PhysRegSUOper::getSparseSetIndex
unsigned getSparseSetIndex() const
Definition: ScheduleDAGInstrs.h:83
llvm::ScheduleDAGInstrs::end
MachineBasicBlock::iterator end() const
Returns an iterator to the bottom of the current scheduling region.
Definition: ScheduleDAGInstrs.h:280
llvm::MachineLoopInfo
Definition: MachineLoopInfo.h:90
PointerIntPair.h
llvm::ScheduleDAGTopologicalSort
This class can compute a topological ordering for SUnits and provides methods for dynamically updatin...
Definition: ScheduleDAG.h:694
bb
< i1 > br i1 label label bb bb
Definition: README.txt:978
llvm::ScheduleDAGInstrs::ScheduleDAGInstrs
ScheduleDAGInstrs(MachineFunction &mf, const MachineLoopInfo *mli, bool RemoveKillFlags=false)
Definition: ScheduleDAGInstrs.cpp:111
llvm::ScheduleDAGInstrs::addChainDependencies
void addChainDependencies(SUnit *SU, SUList &SUs, unsigned Latency)
Adds dependencies as needed from all SUs in list to SU.
Definition: ScheduleDAGInstrs.h:210
llvm::ScheduleDAGInstrs::addVRegDefDeps
void addVRegDefDeps(SUnit *SU, unsigned OperIdx)
Adds register output and data dependencies from this SUnit to instructions that occur later in the sa...
Definition: ScheduleDAGInstrs.cpp:395
llvm::VReg2SUnit::getSparseSetIndex
unsigned getSparseSetIndex() const
Definition: ScheduleDAGInstrs.h:60
llvm::AAResults
Definition: AliasAnalysis.h:508
llvm::ScheduleDAGInstrs::addSchedBarrierDeps
void addSchedBarrierDeps()
Adds dependencies from instructions in the current list of instructions being scheduled to scheduling...
Definition: ScheduleDAGInstrs.cpp:201
llvm::ScheduleDAGInstrs::UnknownValue
UndefValue * UnknownValue
For an unanalyzable memory access, this Value is used in maps.
Definition: ScheduleDAGInstrs.h:236
llvm::VReg2SUnit::LaneMask
LaneBitmask LaneMask
Definition: ScheduleDAGInstrs.h:54
llvm::PhysRegSUOper
Record a physical register access.
Definition: ScheduleDAGInstrs.h:76
llvm::ScheduleDAGInstrs::getGraphNodeLabel
std::string getGraphNodeLabel(const SUnit *SU) const override
Returns a label for a DAG node that points to an instruction.
Definition: ScheduleDAGInstrs.cpp:1183
llvm::ScheduleDAGInstrs::CanHandleTerminators
bool CanHandleTerminators
The standard DAG builder does not normally include terminators as DAG nodes because it does not creat...
Definition: ScheduleDAGInstrs.h:136
llvm::ScheduleDAGInstrs::exitRegion
virtual void exitRegion()
Called when the scheduler has finished scheduling the current region.
Definition: ScheduleDAGInstrs.cpp:197
llvm::ScheduleDAGInstrs::BarrierChain
SUnit * BarrierChain
Remember a generic side-effecting instruction as we proceed.
Definition: ScheduleDAGInstrs.h:182
llvm::MCSchedClassDesc
Summarize the scheduling resources required for an instruction of a particular scheduling class.
Definition: MCSchedule.h:110
llvm::ScheduleDAGInstrs::addPhysRegDeps
void addPhysRegDeps(SUnit *SU, unsigned OperIdx)
Adds register dependencies (data, anti, and output) from this SUnit to following instructions in the ...
Definition: ScheduleDAGInstrs.cpp:291
llvm::ScheduleDAGInstrs::getSUnit
SUnit * getSUnit(MachineInstr *MI) const
Returns an existing SUnit for this MI, or nullptr.
Definition: ScheduleDAGInstrs.h:390
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:49
llvm::VReg2SUnit::VReg2SUnit
VReg2SUnit(unsigned VReg, LaneBitmask LaneMask, SUnit *SU)
Definition: ScheduleDAGInstrs.h:57
llvm::ScheduleDAGInstrs::schedule
virtual void schedule()=0
Orders nodes according to selected style.
llvm::ScheduleDAGInstrs::RegionEnd
MachineBasicBlock::iterator RegionEnd
The end of the range to be scheduled.
Definition: ScheduleDAGInstrs.h:151
llvm::VReg2SUnit::VirtReg
unsigned VirtReg
Definition: ScheduleDAGInstrs.h:53
llvm::VReg2SUnit
An individual mapping from virtual register number to SUnit.
Definition: ScheduleDAGInstrs.h:52
llvm::UnderlyingObject::getValue
ValueType getValue() const
Definition: ScheduleDAGInstrs.h:112
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
llvm::PhysRegSUOper::SU
SUnit * SU
Definition: ScheduleDAGInstrs.h:77
llvm::PhysRegSUOper::Reg
unsigned Reg
Definition: ScheduleDAGInstrs.h:79
llvm::TargetSchedModel::resolveSchedClass
const MCSchedClassDesc * resolveSchedClass(const MachineInstr *MI) const
Return the MCSchedClassDesc for this instruction.
Definition: TargetSchedule.cpp:133
llvm::UnderlyingObject::mayAlias
bool mayAlias() const
Definition: ScheduleDAGInstrs.h:113
llvm::PointerIntPair< ValueType, 1, bool >::getPointer
ValueType getPointer() const
Definition: PointerIntPair.h:59
llvm::ScheduleDAGInstrs::LiveRegs
LivePhysRegs LiveRegs
Set of live physical registers for updating kill flags.
Definition: ScheduleDAGInstrs.h:252
TargetSchedule.h
llvm::SparseMultiSet
Fast multiset implementation for objects that can be identified by small unsigned keys.
Definition: SparseMultiSet.h:85
llvm::TargetSchedModel
Provide an instruction scheduling machine model to CodeGen passes.
Definition: TargetSchedule.h:31
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
Addr
uint64_t Addr
Definition: ELFObjHandler.cpp:80
llvm::ScheduleDAGInstrs::IsReachable
bool IsReachable(SUnit *SU, SUnit *TargetSU)
IsReachable - Checks if SU is reachable from TargetSU.
Definition: ScheduleDAGInstrs.h:272
llvm::DenseMap
Definition: DenseMap.h:714
llvm::SUnit::getInstr
MachineInstr * getInstr() const
Returns the representative MachineInstr for this SUnit.
Definition: ScheduleDAG.h:373
llvm::PointerIntPair< ValueType, 1, bool >::getInt
bool getInt() const
Definition: PointerIntPair.h:61
llvm::UndefValue
'undef' values are things that do not have specified contents.
Definition: Constants.h:1348
llvm::ScheduleDAGInstrs::Defs
Reg2SUnitsMap Defs
Defs, Uses - Remember where defs and uses of each register are as we iterate upward through the instr...
Definition: ScheduleDAGInstrs.h:167
llvm::ScheduleDAGInstrs::MFI
const MachineFrameInfo & MFI
Definition: ScheduleDAGInstrs.h:122
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::ScheduleDAGInstrs::canAddEdge
bool canAddEdge(SUnit *SuccSU, SUnit *PredSU)
True if an edge can be added from PredSU to SuccSU without creating a cycle.
Definition: ScheduleDAGInstrs.cpp:1201
llvm::ScheduleDAGInstrs::TrackLaneMasks
bool TrackLaneMasks
Whether lane masks should get tracked.
Definition: ScheduleDAGInstrs.h:139
llvm::ScheduleDAGInstrs::DbgValues
DbgValueVector DbgValues
Remember instruction that precedes DBG_VALUE.
Definition: ScheduleDAGInstrs.h:248
llvm::MachineFunction
Definition: MachineFunction.h:230
llvm::ScheduleDAG
Definition: ScheduleDAG.h:555
llvm::ScheduleDAGInstrs::finalizeSchedule
virtual void finalizeSchedule()
Allow targets to perform final scheduling actions at the level of the whole MachineFunction.
Definition: ScheduleDAGInstrs.h:338
llvm::VReg2SUnitOperIdx::VReg2SUnitOperIdx
VReg2SUnitOperIdx(unsigned VReg, LaneBitmask LaneMask, unsigned OperandIndex, SUnit *SU)
Definition: ScheduleDAGInstrs.h:69
llvm::VReg2SUnitOperIdx
Mapping from virtual register to SUnit including an operand index.
Definition: ScheduleDAGInstrs.h:66
llvm::VReg2SUnit::SU
SUnit * SU
Definition: ScheduleDAGInstrs.h:55
llvm::SUnit::SchedClass
const MCSchedClassDesc * SchedClass
nullptr or resolved SchedClass.
Definition: ScheduleDAG.h:253
llvm::ScheduleDAGInstrs::dump
void dump() const override
Definition: ScheduleDAGInstrs.cpp:1172
llvm::PhysRegSUOper::OpIdx
int OpIdx
Definition: ScheduleDAGInstrs.h:78
llvm::ScheduleDAGInstrs::getSchedClass
const MCSchedClassDesc * getSchedClass(SUnit *SU) const
Resolves and cache a resolved scheduling class for an SUnit.
Definition: ScheduleDAGInstrs.h:265
SparseSet.h
llvm::ScheduleDAGInstrs::MISUnitMap
DenseMap< MachineInstr *, SUnit * > MISUnitMap
After calling BuildSchedGraph, each machine instruction in the current scheduling region is mapped to...
Definition: ScheduleDAGInstrs.h:158
llvm::PointerUnion< const Value *, const PseudoSourceValue * >
llvm::ScheduleDAGInstrs::enterRegion
virtual void enterRegion(MachineBasicBlock *bb, MachineBasicBlock::iterator begin, MachineBasicBlock::iterator end, unsigned regioninstrs)
Initialize the DAG and common scheduler state for a new scheduling region.
Definition: ScheduleDAGInstrs.cpp:187
llvm::ScheduleDAGInstrs::addChainDependency
void addChainDependency(SUnit *SUa, SUnit *SUb, unsigned Latency=0)
Adds a chain edge between SUa and SUb, but only if both AAResults and Target fail to deny the depende...
Definition: ScheduleDAGInstrs.cpp:548
llvm::ScheduleDAGInstrs::newSUnit
SUnit * newSUnit(MachineInstr *MI)
Creates a new SUnit and return a ptr to it.
Definition: ScheduleDAGInstrs.h:379
llvm::ScheduleDAGInstrs::RemoveKillFlags
bool RemoveKillFlags
True if the DAG builder should remove kill flags (in preparation for rescheduling).
Definition: ScheduleDAGInstrs.h:129
llvm::SDep
Scheduling dependency.
Definition: ScheduleDAG.h:49
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::ScheduleDAGInstrs::AAForDep
AAResults * AAForDep
Definition: ScheduleDAGInstrs.h:177
llvm::ScheduleDAGInstrs::MLI
const MachineLoopInfo * MLI
Definition: ScheduleDAGInstrs.h:121
llvm::ScheduleDAG::SUnits
std::vector< SUnit > SUnits
The scheduling units.
Definition: ScheduleDAG.h:562
llvm::ScheduleDAGInstrs::RegionBegin
MachineBasicBlock::iterator RegionBegin
The beginning of the range to be scheduled.
Definition: ScheduleDAGInstrs.h:148
llvm::ScheduleDAGInstrs::DbgValueVector
std::vector< std::pair< MachineInstr *, MachineInstr * > > DbgValueVector
Definition: ScheduleDAGInstrs.h:244
uint16_t
llvm::TargetStackID::Value
Value
Definition: TargetFrameLowering.h:27
llvm::ScheduleDAGInstrs::Value2SUsMap
Definition: ScheduleDAGInstrs.cpp:615
llvm::ScheduleDAGInstrs::deadDefHasNoUse
bool deadDefHasNoUse(const MachineOperand &MO)
Returns true if the def register in MO has no uses.
Definition: ScheduleDAGInstrs.cpp:382
llvm::ScheduleDAGInstrs::~ScheduleDAGInstrs
~ScheduleDAGInstrs() override=default
llvm::LiveIntervals
Definition: LiveIntervals.h:54
SparseMultiSet.h
llvm::ScheduleDAGInstrs::doMBBSchedRegionsTopDown
virtual bool doMBBSchedRegionsTopDown() const
If this method returns true, handling of the scheduling regions themselves (in case of a scheduling b...
Definition: ScheduleDAGInstrs.h:291
llvm::ScheduleDAGInstrs::Uses
Reg2SUnitsMap Uses
Definition: ScheduleDAGInstrs.h:168
llvm::ScheduleDAGInstrs::BB
MachineBasicBlock * BB
The block in which to insert instructions.
Definition: ScheduleDAGInstrs.h:145
llvm::MachineFrameInfo
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Definition: MachineFrameInfo.h:107
llvm::PointerIntPair
PointerIntPair - This class implements a pair of a pointer and small integer.
Definition: PointerIntPair.h:45
llvm::ScheduleDAGInstrs::dumpNode
void dumpNode(const SUnit &SU) const override
Definition: ScheduleDAGInstrs.cpp:1164
SmallVector.h
llvm::ScheduleDAGInstrs::finishBlock
virtual void finishBlock()
Cleans up after scheduling in the given block.
Definition: ScheduleDAGInstrs.cpp:182
llvm::ScheduleDAGInstrs::addPhysRegDataDeps
void addPhysRegDataDeps(SUnit *SU, unsigned OperIdx)
MO is an operand of SU's instruction that defines a physical register.
Definition: ScheduleDAGInstrs.cpp:233
llvm::ScheduleDAGInstrs::CurrentVRegDefs
VReg2SUnitMultiMap CurrentVRegDefs
Tracks the last instruction(s) in this region defining each virtual register.
Definition: ScheduleDAGInstrs.h:173
N
#define N
llvm::ScheduleDAGInstrs::addVRegUseDeps
void addVRegUseDeps(SUnit *SU, unsigned OperIdx)
Adds a register data dependency if the instruction that defines the virtual register used at OperIdx ...
Definition: ScheduleDAGInstrs.cpp:515
LaneBitmask.h
llvm::ScheduleDAGInstrs::getSchedModel
const TargetSchedModel * getSchedModel() const
Gets the machine model for instruction scheduling.
Definition: ScheduleDAGInstrs.h:262
llvm::SparseSet
SparseSet - Fast set implementation for objects that can be identified by small unsigned keys.
Definition: SparseSet.h:123
llvm::PhysRegSUOper::PhysRegSUOper
PhysRegSUOper(SUnit *su, int op, unsigned R)
Definition: ScheduleDAGInstrs.h:81
llvm::SUnit
Scheduling unit. This is a node in the scheduling DAG.
Definition: ScheduleDAG.h:242
llvm::Register::virtReg2Index
static unsigned virtReg2Index(Register Reg)
Convert a virtual register number to a 0-based index.
Definition: Register.h:77
llvm::ScheduleDAGInstrs
A ScheduleDAG for scheduling lists of MachineInstr.
Definition: ScheduleDAGInstrs.h:119
llvm::ScheduleDAGInstrs::insertBarrierChain
void insertBarrierChain(Value2SUsMap &map)
Inserts a barrier chain in a huge region, far below current SU.
Definition: ScheduleDAGInstrs.cpp:697
llvm::ScheduleDAGInstrs::fixupKills
void fixupKills(MachineBasicBlock &MBB)
Fixes register kill flags that scheduling has made invalid.
Definition: ScheduleDAGInstrs.cpp:1113
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::ScheduleDAGInstrs::reduceHugeMemNodeMaps
void reduceHugeMemNodeMaps(Value2SUsMap &stores, Value2SUsMap &loads, unsigned N)
Reduces maps in FIFO order, by N SUs.
Definition: ScheduleDAGInstrs.cpp:1050
TargetRegisterInfo.h
llvm::UnderlyingObject::UnderlyingObject
UnderlyingObject(ValueType V, bool MayAlias)
Definition: ScheduleDAGInstrs.h:109
llvm::Reg2SUnitsMap
SparseMultiSet< PhysRegSUOper, identity< unsigned >, uint16_t > Reg2SUnitsMap
Use a SparseMultiSet to track physical registers.
Definition: ScheduleDAGInstrs.h:90
llvm::TargetSchedModel::hasInstrSchedModel
bool hasInstrSchedModel() const
Return true if this machine model includes an instruction-level scheduling model.
Definition: TargetSchedule.cpp:39
LivePhysRegs.h