LLVM  16.0.0git
ScheduleDAGInstrs.h
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1 //===- ScheduleDAGInstrs.h - MachineInstr Scheduling ------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file Implements the ScheduleDAGInstrs class, which implements scheduling
10 /// for a MachineInstr-based dependency graph.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_CODEGEN_SCHEDULEDAGINSTRS_H
15 #define LLVM_CODEGEN_SCHEDULEDAGINSTRS_H
16 
17 #include "llvm/ADT/DenseMap.h"
19 #include "llvm/ADT/SmallVector.h"
21 #include "llvm/ADT/SparseSet.h"
22 #include "llvm/ADT/identity.h"
28 #include "llvm/MC/LaneBitmask.h"
29 #include <cassert>
30 #include <cstdint>
31 #include <list>
32 #include <string>
33 #include <utility>
34 #include <vector>
35 
36 namespace llvm {
37 
38  class AAResults;
39  class LiveIntervals;
40  class MachineFrameInfo;
41  class MachineFunction;
42  class MachineInstr;
43  class MachineLoopInfo;
44  class MachineOperand;
45  struct MCSchedClassDesc;
46  class PressureDiffs;
47  class PseudoSourceValue;
48  class RegPressureTracker;
49  class UndefValue;
50  class Value;
51 
52  /// An individual mapping from virtual register number to SUnit.
53  struct VReg2SUnit {
54  unsigned VirtReg;
57 
59  : VirtReg(VReg), LaneMask(LaneMask), SU(SU) {}
60 
61  unsigned getSparseSetIndex() const {
63  }
64  };
65 
66  /// Mapping from virtual register to SUnit including an operand index.
67  struct VReg2SUnitOperIdx : public VReg2SUnit {
68  unsigned OperandIndex;
69 
71  unsigned OperandIndex, SUnit *SU)
73  };
74 
75  /// Record a physical register access.
76  /// For non-data-dependent uses, OpIdx == -1.
77  struct PhysRegSUOper {
79  int OpIdx;
80  unsigned Reg;
81 
82  PhysRegSUOper(SUnit *su, int op, unsigned R): SU(su), OpIdx(op), Reg(R) {}
83 
84  unsigned getSparseSetIndex() const { return Reg; }
85  };
86 
87  /// Use a SparseMultiSet to track physical registers. Storage is only
88  /// allocated once for the pass. It can be cleared in constant time and reused
89  /// without any frees.
90  using Reg2SUnitsMap =
92 
93  /// Use SparseSet as a SparseMap by relying on the fact that it never
94  /// compares ValueT's, only unsigned keys. This allows the set to be cleared
95  /// between scheduling regions in constant time as long as ValueT does not
96  /// require a destructor.
98 
99  /// Track local uses of virtual registers. These uses are gathered by the DAG
100  /// builder and may be consulted by the scheduler to avoid iterating an entire
101  /// vreg use list.
103 
106 
108 
109  struct UnderlyingObject : PointerIntPair<ValueType, 1, bool> {
110  UnderlyingObject(ValueType V, bool MayAlias)
111  : PointerIntPair<ValueType, 1, bool>(V, MayAlias) {}
112 
113  ValueType getValue() const { return getPointer(); }
114  bool mayAlias() const { return getInt(); }
115  };
116 
118 
119  /// A ScheduleDAG for scheduling lists of MachineInstr.
121  protected:
124 
125  /// TargetSchedModel provides an interface to the machine model.
127 
128  /// True if the DAG builder should remove kill flags (in preparation for
129  /// rescheduling).
131 
132  /// The standard DAG builder does not normally include terminators as DAG
133  /// nodes because it does not create the necessary dependencies to prevent
134  /// reordering. A specialized scheduler can override
135  /// TargetInstrInfo::isSchedulingBoundary then enable this flag to indicate
136  /// it has taken responsibility for scheduling the terminator correctly.
137  bool CanHandleTerminators = false;
138 
139  /// Whether lane masks should get tracked.
140  bool TrackLaneMasks = false;
141 
142  // State specific to the current scheduling region.
143  // ------------------------------------------------
144 
145  /// The block in which to insert instructions
147 
148  /// The beginning of the range to be scheduled.
150 
151  /// The end of the range to be scheduled.
153 
154  /// Instructions in this region (distance(RegionBegin, RegionEnd)).
155  unsigned NumRegionInstrs;
156 
157  /// After calling BuildSchedGraph, each machine instruction in the current
158  /// scheduling region is mapped to an SUnit.
160 
161  // State internal to DAG building.
162  // -------------------------------
163 
164  /// Defs, Uses - Remember where defs and uses of each register are as we
165  /// iterate upward through the instructions. This is allocated here instead
166  /// of inside BuildSchedGraph to avoid the need for it to be initialized and
167  /// destructed for each block.
170 
171  /// Tracks the last instruction(s) in this region defining each virtual
172  /// register. There may be multiple current definitions for a register with
173  /// disjunct lanemasks.
175  /// Tracks the last instructions in this region using each virtual register.
177 
178  AAResults *AAForDep = nullptr;
179 
180  /// Remember a generic side-effecting instruction as we proceed.
181  /// No other SU ever gets scheduled around it (except in the special
182  /// case of a huge region that gets reduced).
183  SUnit *BarrierChain = nullptr;
184 
185  public:
186  /// A list of SUnits, used in Value2SUsMap, during DAG construction.
187  /// Note: to gain speed it might be worth investigating an optimized
188  /// implementation of this data structure, such as a singly linked list
189  /// with a memory pool (SmallVector was tried but slow and SparseSet is not
190  /// applicable).
191  using SUList = std::list<SUnit *>;
192 
193  protected:
194  /// A map from ValueType to SUList, used during DAG construction, as
195  /// a means of remembering which SUs depend on which memory locations.
196  class Value2SUsMap;
197 
198  /// Reduces maps in FIFO order, by N SUs. This is better than turning
199  /// every Nth memory SU into BarrierChain in buildSchedGraph(), since
200  /// it avoids unnecessary edges between seen SUs above the new BarrierChain,
201  /// and those below it.
203  Value2SUsMap &loads, unsigned N);
204 
205  /// Adds a chain edge between SUa and SUb, but only if both
206  /// AAResults and Target fail to deny the dependency.
207  void addChainDependency(SUnit *SUa, SUnit *SUb,
208  unsigned Latency = 0);
209 
210  /// Adds dependencies as needed from all SUs in list to SU.
211  void addChainDependencies(SUnit *SU, SUList &SUs, unsigned Latency) {
212  for (SUnit *Entry : SUs)
213  addChainDependency(SU, Entry, Latency);
214  }
215 
216  /// Adds dependencies as needed from all SUs in map, to SU.
217  void addChainDependencies(SUnit *SU, Value2SUsMap &Val2SUsMap);
218 
219  /// Adds dependencies as needed to SU, from all SUs mapped to V.
220  void addChainDependencies(SUnit *SU, Value2SUsMap &Val2SUsMap,
221  ValueType V);
222 
223  /// Adds barrier chain edges from all SUs in map, and then clear the map.
224  /// This is equivalent to insertBarrierChain(), but optimized for the common
225  /// case where the new BarrierChain (a global memory object) has a higher
226  /// NodeNum than all SUs in map. It is assumed BarrierChain has been set
227  /// before calling this.
228  void addBarrierChain(Value2SUsMap &map);
229 
230  /// Inserts a barrier chain in a huge region, far below current SU.
231  /// Adds barrier chain edges from all SUs in map with higher NodeNums than
232  /// this new BarrierChain, and remove them from map. It is assumed
233  /// BarrierChain has been set before calling this.
234  void insertBarrierChain(Value2SUsMap &map);
235 
236  /// For an unanalyzable memory access, this Value is used in maps.
238 
239 
240  /// Topo - A topological ordering for SUnits which permits fast IsReachable
241  /// and similar queries.
243 
244  using DbgValueVector =
245  std::vector<std::pair<MachineInstr *, MachineInstr *>>;
246  /// Remember instruction that precedes DBG_VALUE.
247  /// These are generated by buildSchedGraph but persist so they can be
248  /// referenced when emitting the final schedule.
251 
252  /// Set of live physical registers for updating kill flags.
254 
255  public:
256  explicit ScheduleDAGInstrs(MachineFunction &mf,
257  const MachineLoopInfo *mli,
258  bool RemoveKillFlags = false);
259 
260  ~ScheduleDAGInstrs() override = default;
261 
262  /// Gets the machine model for instruction scheduling.
263  const TargetSchedModel *getSchedModel() const { return &SchedModel; }
264 
265  /// Resolves and cache a resolved scheduling class for an SUnit.
269  return SU->SchedClass;
270  }
271 
272  /// IsReachable - Checks if SU is reachable from TargetSU.
273  bool IsReachable(SUnit *SU, SUnit *TargetSU) {
274  return Topo.IsReachable(SU, TargetSU);
275  }
276 
277  /// Returns an iterator to the top of the current scheduling region.
279 
280  /// Returns an iterator to the bottom of the current scheduling region.
282 
283  /// Creates a new SUnit and return a ptr to it.
285 
286  /// Returns an existing SUnit for this MI, or nullptr.
287  SUnit *getSUnit(MachineInstr *MI) const;
288 
289  /// If this method returns true, handling of the scheduling regions
290  /// themselves (in case of a scheduling boundary in MBB) will be done
291  /// beginning with the topmost region of MBB.
292  virtual bool doMBBSchedRegionsTopDown() const { return false; }
293 
294  /// Prepares to perform scheduling in the given block.
295  virtual void startBlock(MachineBasicBlock *BB);
296 
297  /// Cleans up after scheduling in the given block.
298  virtual void finishBlock();
299 
300  /// Initialize the DAG and common scheduler state for a new
301  /// scheduling region. This does not actually create the DAG, only clears
302  /// it. The scheduling driver may call BuildSchedGraph multiple times per
303  /// scheduling region.
304  virtual void enterRegion(MachineBasicBlock *bb,
307  unsigned regioninstrs);
308 
309  /// Called when the scheduler has finished scheduling the current region.
310  virtual void exitRegion();
311 
312  /// Builds SUnits for the current region.
313  /// If \p RPTracker is non-null, compute register pressure as a side effect.
314  /// The DAG builder is an efficient place to do it because it already visits
315  /// operands.
317  RegPressureTracker *RPTracker = nullptr,
318  PressureDiffs *PDiffs = nullptr,
319  LiveIntervals *LIS = nullptr,
320  bool TrackLaneMasks = false);
321 
322  /// Adds dependencies from instructions in the current list of
323  /// instructions being scheduled to scheduling barrier. We want to make sure
324  /// instructions which define registers that are either used by the
325  /// terminator or are live-out are properly scheduled. This is especially
326  /// important when the definition latency of the return value(s) are too
327  /// high to be hidden by the branch or when the liveout registers used by
328  /// instructions in the fallthrough block.
329  void addSchedBarrierDeps();
330 
331  /// Orders nodes according to selected style.
332  ///
333  /// Typically, a scheduling algorithm will implement schedule() without
334  /// overriding enterRegion() or exitRegion().
335  virtual void schedule() = 0;
336 
337  /// Allow targets to perform final scheduling actions at the level of the
338  /// whole MachineFunction. By default does nothing.
339  virtual void finalizeSchedule() {}
340 
341  void dumpNode(const SUnit &SU) const override;
342  void dump() const override;
343 
344  /// Returns a label for a DAG node that points to an instruction.
345  std::string getGraphNodeLabel(const SUnit *SU) const override;
346 
347  /// Returns a label for the region of code covered by the DAG.
348  std::string getDAGName() const override;
349 
350  /// Fixes register kill flags that scheduling has made invalid.
352 
353  /// True if an edge can be added from PredSU to SuccSU without creating
354  /// a cycle.
355  bool canAddEdge(SUnit *SuccSU, SUnit *PredSU);
356 
357  /// Add a DAG edge to the given SU with the given predecessor
358  /// dependence data.
359  ///
360  /// \returns true if the edge may be added without creating a cycle OR if an
361  /// equivalent edge already existed (false indicates failure).
362  bool addEdge(SUnit *SuccSU, const SDep &PredDep);
363 
364  protected:
365  void initSUnits();
366  void addPhysRegDataDeps(SUnit *SU, unsigned OperIdx);
367  void addPhysRegDeps(SUnit *SU, unsigned OperIdx);
368  void addVRegDefDeps(SUnit *SU, unsigned OperIdx);
369  void addVRegUseDeps(SUnit *SU, unsigned OperIdx);
370 
371  /// Returns a mask for which lanes get read/written by the given (register)
372  /// machine operand.
374 
375  /// Returns true if the def register in \p MO has no uses.
376  bool deadDefHasNoUse(const MachineOperand &MO);
377  };
378 
379  /// Creates a new SUnit and return a ptr to it.
381 #ifndef NDEBUG
382  const SUnit *Addr = SUnits.empty() ? nullptr : &SUnits[0];
383 #endif
384  SUnits.emplace_back(MI, (unsigned)SUnits.size());
385  assert((Addr == nullptr || Addr == &SUnits[0]) &&
386  "SUnits std::vector reallocated on the fly!");
387  return &SUnits.back();
388  }
389 
390  /// Returns an existing SUnit for this MI, or nullptr.
392  return MISUnitMap.lookup(MI);
393  }
394 
395 } // end namespace llvm
396 
397 #endif // LLVM_CODEGEN_SCHEDULEDAGINSTRS_H
llvm::ScheduleDAGInstrs::initSUnits
void initSUnits()
Creates an SUnit for each real instruction, numbered in top-down topological order.
Definition: ScheduleDAGInstrs.cpp:559
llvm::ScheduleDAGInstrs::FirstDbgValue
MachineInstr * FirstDbgValue
Definition: ScheduleDAGInstrs.h:250
llvm::LaneBitmask
Definition: LaneBitmask.h:40
llvm::ScheduleDAGInstrs::getDAGName
std::string getDAGName() const override
Returns a label for the region of code covered by the DAG.
Definition: ScheduleDAGInstrs.cpp:1191
llvm::VReg2SUnitOperIdx::OperandIndex
unsigned OperandIndex
Definition: ScheduleDAGInstrs.h:68
ScheduleDAG.h
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:108
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::ScheduleDAGInstrs::addBarrierChain
void addBarrierChain(Value2SUsMap &map)
Adds barrier chain edges from all SUs in map, and then clear the map.
Definition: ScheduleDAGInstrs.cpp:676
llvm::ScheduleDAGInstrs::CurrentVRegUses
VReg2SUnitOperIdxMultiMap CurrentVRegUses
Tracks the last instructions in this region using each virtual register.
Definition: ScheduleDAGInstrs.h:176
llvm::Latency
@ Latency
Definition: SIMachineScheduler.h:34
llvm::ScheduleDAGInstrs::buildSchedGraph
void buildSchedGraph(AAResults *AA, RegPressureTracker *RPTracker=nullptr, PressureDiffs *PDiffs=nullptr, LiveIntervals *LIS=nullptr, bool TrackLaneMasks=false)
Builds SUnits for the current region.
Definition: ScheduleDAGInstrs.cpp:720
llvm::ScheduleDAGInstrs::begin
MachineBasicBlock::iterator begin() const
Returns an iterator to the top of the current scheduling region.
Definition: ScheduleDAGInstrs.h:278
llvm::UnderlyingObject
Definition: ScheduleDAGInstrs.h:109
op
#define op(i)
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1182
llvm::ScheduleDAGTopologicalSort::IsReachable
bool IsReachable(const SUnit *SU, const SUnit *TargetSU)
Checks if SU is reachable from TargetSU.
Definition: ScheduleDAG.cpp:723
llvm::ScheduleDAGInstrs::NumRegionInstrs
unsigned NumRegionInstrs
Instructions in this region (distance(RegionBegin, RegionEnd)).
Definition: ScheduleDAGInstrs.h:155
MachineBasicBlock.h
llvm::LivePhysRegs
A set of physical registers with utility functions to track liveness when walking backward/forward th...
Definition: LivePhysRegs.h:50
stores
hexagon widen stores
Definition: HexagonStoreWidening.cpp:118
llvm::ScheduleDAGInstrs::addEdge
bool addEdge(SUnit *SuccSU, const SDep &PredDep)
Add a DAG edge to the given SU with the given predecessor dependence data.
Definition: ScheduleDAGInstrs.cpp:1199
llvm::ScheduleDAGInstrs::Topo
ScheduleDAGTopologicalSort Topo
Topo - A topological ordering for SUnits which permits fast IsReachable and similar queries.
Definition: ScheduleDAGInstrs.h:242
llvm::ScheduleDAGInstrs::SUList
std::list< SUnit * > SUList
A list of SUnits, used in Value2SUsMap, during DAG construction.
Definition: ScheduleDAGInstrs.h:191
llvm::RegPressureTracker
Track the current register pressure at some position in the instruction stream, and remember the high...
Definition: RegisterPressure.h:357
DenseMap.h
llvm::ScheduleDAGInstrs::startBlock
virtual void startBlock(MachineBasicBlock *BB)
Prepares to perform scheduling in the given block.
Definition: ScheduleDAGInstrs.cpp:174
llvm::PressureDiffs
Array of PressureDiffs.
Definition: RegisterPressure.h:197
llvm::ScheduleDAGInstrs::getLaneMaskForMO
LaneBitmask getLaneMaskForMO(const MachineOperand &MO) const
Returns a mask for which lanes get read/written by the given (register) machine operand.
Definition: ScheduleDAGInstrs.cpp:359
llvm::ScheduleDAGInstrs::SchedModel
TargetSchedModel SchedModel
TargetSchedModel provides an interface to the machine model.
Definition: ScheduleDAGInstrs.h:126
llvm::PhysRegSUOper::getSparseSetIndex
unsigned getSparseSetIndex() const
Definition: ScheduleDAGInstrs.h:84
llvm::ScheduleDAGInstrs::end
MachineBasicBlock::iterator end() const
Returns an iterator to the bottom of the current scheduling region.
Definition: ScheduleDAGInstrs.h:281
llvm::MachineLoopInfo
Definition: MachineLoopInfo.h:89
PointerIntPair.h
llvm::ScheduleDAGTopologicalSort
This class can compute a topological ordering for SUnits and provides methods for dynamically updatin...
Definition: ScheduleDAG.h:693
bb
< i1 > br i1 label label bb bb
Definition: README.txt:978
llvm::ScheduleDAGInstrs::ScheduleDAGInstrs
ScheduleDAGInstrs(MachineFunction &mf, const MachineLoopInfo *mli, bool RemoveKillFlags=false)
Definition: ScheduleDAGInstrs.cpp:107
llvm::ScheduleDAGInstrs::addChainDependencies
void addChainDependencies(SUnit *SU, SUList &SUs, unsigned Latency)
Adds dependencies as needed from all SUs in list to SU.
Definition: ScheduleDAGInstrs.h:211
llvm::ScheduleDAGInstrs::addVRegDefDeps
void addVRegDefDeps(SUnit *SU, unsigned OperIdx)
Adds register output and data dependencies from this SUnit to instructions that occur later in the sa...
Definition: ScheduleDAGInstrs.cpp:386
llvm::VReg2SUnit::getSparseSetIndex
unsigned getSparseSetIndex() const
Definition: ScheduleDAGInstrs.h:61
llvm::AAResults
Definition: AliasAnalysis.h:518
llvm::ScheduleDAGInstrs::addSchedBarrierDeps
void addSchedBarrierDeps()
Adds dependencies from instructions in the current list of instructions being scheduled to scheduling...
Definition: ScheduleDAGInstrs.cpp:197
llvm::ScheduleDAGInstrs::UnknownValue
UndefValue * UnknownValue
For an unanalyzable memory access, this Value is used in maps.
Definition: ScheduleDAGInstrs.h:237
llvm::VReg2SUnit::LaneMask
LaneBitmask LaneMask
Definition: ScheduleDAGInstrs.h:55
llvm::PhysRegSUOper
Record a physical register access.
Definition: ScheduleDAGInstrs.h:77
llvm::ScheduleDAGInstrs::getGraphNodeLabel
std::string getGraphNodeLabel(const SUnit *SU) const override
Returns a label for a DAG node that points to an instruction.
Definition: ScheduleDAGInstrs.cpp:1177
llvm::ScheduleDAGInstrs::CanHandleTerminators
bool CanHandleTerminators
The standard DAG builder does not normally include terminators as DAG nodes because it does not creat...
Definition: ScheduleDAGInstrs.h:137
llvm::ScheduleDAGInstrs::exitRegion
virtual void exitRegion()
Called when the scheduler has finished scheduling the current region.
Definition: ScheduleDAGInstrs.cpp:193
llvm::ScheduleDAGInstrs::BarrierChain
SUnit * BarrierChain
Remember a generic side-effecting instruction as we proceed.
Definition: ScheduleDAGInstrs.h:183
llvm::MCSchedClassDesc
Summarize the scheduling resources required for an instruction of a particular scheduling class.
Definition: MCSchedule.h:109
llvm::ScheduleDAGInstrs::addPhysRegDeps
void addPhysRegDeps(SUnit *SU, unsigned OperIdx)
Adds register dependencies (data, anti, and output) from this SUnit to following instructions in the ...
Definition: ScheduleDAGInstrs.cpp:282
llvm::ScheduleDAGInstrs::getSUnit
SUnit * getSUnit(MachineInstr *MI) const
Returns an existing SUnit for this MI, or nullptr.
Definition: ScheduleDAGInstrs.h:391
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:48
llvm::VReg2SUnit::VReg2SUnit
VReg2SUnit(unsigned VReg, LaneBitmask LaneMask, SUnit *SU)
Definition: ScheduleDAGInstrs.h:58
llvm::ScheduleDAGInstrs::schedule
virtual void schedule()=0
Orders nodes according to selected style.
llvm::ScheduleDAGInstrs::RegionEnd
MachineBasicBlock::iterator RegionEnd
The end of the range to be scheduled.
Definition: ScheduleDAGInstrs.h:152
llvm::VReg2SUnit::VirtReg
unsigned VirtReg
Definition: ScheduleDAGInstrs.h:54
llvm::VReg2SUnit
An individual mapping from virtual register number to SUnit.
Definition: ScheduleDAGInstrs.h:53
llvm::UnderlyingObject::getValue
ValueType getValue() const
Definition: ScheduleDAGInstrs.h:113
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
llvm::PhysRegSUOper::SU
SUnit * SU
Definition: ScheduleDAGInstrs.h:78
llvm::PhysRegSUOper::Reg
unsigned Reg
Definition: ScheduleDAGInstrs.h:80
llvm::TargetSchedModel::resolveSchedClass
const MCSchedClassDesc * resolveSchedClass(const MachineInstr *MI) const
Return the MCSchedClassDesc for this instruction.
Definition: TargetSchedule.cpp:117
llvm::UnderlyingObject::mayAlias
bool mayAlias() const
Definition: ScheduleDAGInstrs.h:114
llvm::PointerIntPair< ValueType, 1, bool >::getPointer
ValueType getPointer() const
Definition: PointerIntPair.h:60
llvm::ScheduleDAGInstrs::LiveRegs
LivePhysRegs LiveRegs
Set of live physical registers for updating kill flags.
Definition: ScheduleDAGInstrs.h:253
TargetSchedule.h
llvm::SparseMultiSet
Fast multiset implementation for objects that can be identified by small unsigned keys.
Definition: SparseMultiSet.h:86
llvm::TargetSchedModel
Provide an instruction scheduling machine model to CodeGen passes.
Definition: TargetSchedule.h:30
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
Addr
uint64_t Addr
Definition: ELFObjHandler.cpp:78
llvm::ScheduleDAGInstrs::IsReachable
bool IsReachable(SUnit *SU, SUnit *TargetSU)
IsReachable - Checks if SU is reachable from TargetSU.
Definition: ScheduleDAGInstrs.h:273
llvm::DenseMap
Definition: DenseMap.h:714
llvm::SUnit::getInstr
MachineInstr * getInstr() const
Returns the representative MachineInstr for this SUnit.
Definition: ScheduleDAG.h:373
llvm::PointerIntPair< ValueType, 1, bool >::getInt
bool getInt() const
Definition: PointerIntPair.h:62
llvm::UndefValue
'undef' values are things that do not have specified contents.
Definition: Constants.h:1356
llvm::ScheduleDAGInstrs::Defs
Reg2SUnitsMap Defs
Defs, Uses - Remember where defs and uses of each register are as we iterate upward through the instr...
Definition: ScheduleDAGInstrs.h:168
llvm::ScheduleDAGInstrs::MFI
const MachineFrameInfo & MFI
Definition: ScheduleDAGInstrs.h:123
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::ScheduleDAGInstrs::canAddEdge
bool canAddEdge(SUnit *SuccSU, SUnit *PredSU)
True if an edge can be added from PredSU to SuccSU without creating a cycle.
Definition: ScheduleDAGInstrs.cpp:1195
llvm::ScheduleDAGInstrs::TrackLaneMasks
bool TrackLaneMasks
Whether lane masks should get tracked.
Definition: ScheduleDAGInstrs.h:140
llvm::ScheduleDAGInstrs::DbgValues
DbgValueVector DbgValues
Remember instruction that precedes DBG_VALUE.
Definition: ScheduleDAGInstrs.h:249
llvm::MachineFunction
Definition: MachineFunction.h:257
llvm::ScheduleDAG
Definition: ScheduleDAG.h:554
llvm::ScheduleDAGInstrs::finalizeSchedule
virtual void finalizeSchedule()
Allow targets to perform final scheduling actions at the level of the whole MachineFunction.
Definition: ScheduleDAGInstrs.h:339
llvm::VReg2SUnitOperIdx::VReg2SUnitOperIdx
VReg2SUnitOperIdx(unsigned VReg, LaneBitmask LaneMask, unsigned OperandIndex, SUnit *SU)
Definition: ScheduleDAGInstrs.h:70
llvm::VReg2SUnitOperIdx
Mapping from virtual register to SUnit including an operand index.
Definition: ScheduleDAGInstrs.h:67
llvm::VReg2SUnit::SU
SUnit * SU
Definition: ScheduleDAGInstrs.h:56
llvm::SUnit::SchedClass
const MCSchedClassDesc * SchedClass
nullptr or resolved SchedClass.
Definition: ScheduleDAG.h:253
llvm::ScheduleDAGInstrs::dump
void dump() const override
Definition: ScheduleDAGInstrs.cpp:1166
llvm::PhysRegSUOper::OpIdx
int OpIdx
Definition: ScheduleDAGInstrs.h:79
llvm::ScheduleDAGInstrs::getSchedClass
const MCSchedClassDesc * getSchedClass(SUnit *SU) const
Resolves and cache a resolved scheduling class for an SUnit.
Definition: ScheduleDAGInstrs.h:266
SparseSet.h
llvm::ScheduleDAGInstrs::MISUnitMap
DenseMap< MachineInstr *, SUnit * > MISUnitMap
After calling BuildSchedGraph, each machine instruction in the current scheduling region is mapped to...
Definition: ScheduleDAGInstrs.h:159
llvm::PointerUnion< const Value *, const PseudoSourceValue * >
llvm::ScheduleDAGInstrs::enterRegion
virtual void enterRegion(MachineBasicBlock *bb, MachineBasicBlock::iterator begin, MachineBasicBlock::iterator end, unsigned regioninstrs)
Initialize the DAG and common scheduler state for a new scheduling region.
Definition: ScheduleDAGInstrs.cpp:183
llvm::ScheduleDAGInstrs::addChainDependency
void addChainDependency(SUnit *SUa, SUnit *SUb, unsigned Latency=0)
Adds a chain edge between SUa and SUb, but only if both AAResults and Target fail to deny the depende...
Definition: ScheduleDAGInstrs.cpp:538
llvm::ScheduleDAGInstrs::newSUnit
SUnit * newSUnit(MachineInstr *MI)
Creates a new SUnit and return a ptr to it.
Definition: ScheduleDAGInstrs.h:380
llvm::ScheduleDAGInstrs::RemoveKillFlags
bool RemoveKillFlags
True if the DAG builder should remove kill flags (in preparation for rescheduling).
Definition: ScheduleDAGInstrs.h:130
llvm::SDep
Scheduling dependency.
Definition: ScheduleDAG.h:49
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::ScheduleDAGInstrs::AAForDep
AAResults * AAForDep
Definition: ScheduleDAGInstrs.h:178
llvm::ScheduleDAGInstrs::MLI
const MachineLoopInfo * MLI
Definition: ScheduleDAGInstrs.h:122
llvm::ScheduleDAG::SUnits
std::vector< SUnit > SUnits
The scheduling units.
Definition: ScheduleDAG.h:561
llvm::ScheduleDAGInstrs::RegionBegin
MachineBasicBlock::iterator RegionBegin
The beginning of the range to be scheduled.
Definition: ScheduleDAGInstrs.h:149
llvm::ScheduleDAGInstrs::DbgValueVector
std::vector< std::pair< MachineInstr *, MachineInstr * > > DbgValueVector
Definition: ScheduleDAGInstrs.h:245
uint16_t
llvm::TargetStackID::Value
Value
Definition: TargetFrameLowering.h:27
llvm::ScheduleDAGInstrs::Value2SUsMap
Definition: ScheduleDAGInstrs.cpp:605
llvm::ScheduleDAGInstrs::deadDefHasNoUse
bool deadDefHasNoUse(const MachineOperand &MO)
Returns true if the def register in MO has no uses.
Definition: ScheduleDAGInstrs.cpp:373
llvm::ScheduleDAGInstrs::~ScheduleDAGInstrs
~ScheduleDAGInstrs() override=default
llvm::LiveIntervals
Definition: LiveIntervals.h:53
SparseMultiSet.h
llvm::ScheduleDAGInstrs::doMBBSchedRegionsTopDown
virtual bool doMBBSchedRegionsTopDown() const
If this method returns true, handling of the scheduling regions themselves (in case of a scheduling b...
Definition: ScheduleDAGInstrs.h:292
llvm::ScheduleDAGInstrs::Uses
Reg2SUnitsMap Uses
Definition: ScheduleDAGInstrs.h:169
AA
llvm::ScheduleDAGInstrs::BB
MachineBasicBlock * BB
The block in which to insert instructions.
Definition: ScheduleDAGInstrs.h:146
llvm::MachineFrameInfo
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Definition: MachineFrameInfo.h:105
identity.h
llvm::PointerIntPair
PointerIntPair - This class implements a pair of a pointer and small integer.
Definition: PointerIntPair.h:46
llvm::ScheduleDAGInstrs::dumpNode
void dumpNode(const SUnit &SU) const override
Definition: ScheduleDAGInstrs.cpp:1158
SmallVector.h
llvm::ScheduleDAGInstrs::finishBlock
virtual void finishBlock()
Cleans up after scheduling in the given block.
Definition: ScheduleDAGInstrs.cpp:178
llvm::ScheduleDAGInstrs::addPhysRegDataDeps
void addPhysRegDataDeps(SUnit *SU, unsigned OperIdx)
MO is an operand of SU's instruction that defines a physical register.
Definition: ScheduleDAGInstrs.cpp:229
llvm::ScheduleDAGInstrs::CurrentVRegDefs
VReg2SUnitMultiMap CurrentVRegDefs
Tracks the last instruction(s) in this region defining each virtual register.
Definition: ScheduleDAGInstrs.h:174
N
#define N
llvm::ScheduleDAGInstrs::addVRegUseDeps
void addVRegUseDeps(SUnit *SU, unsigned OperIdx)
Adds a register data dependency if the instruction that defines the virtual register used at OperIdx ...
Definition: ScheduleDAGInstrs.cpp:505
LaneBitmask.h
llvm::ScheduleDAGInstrs::getSchedModel
const TargetSchedModel * getSchedModel() const
Gets the machine model for instruction scheduling.
Definition: ScheduleDAGInstrs.h:263
llvm::SparseSet
SparseSet - Fast set implementation for objects that can be identified by small unsigned keys.
Definition: SparseSet.h:124
llvm::PhysRegSUOper::PhysRegSUOper
PhysRegSUOper(SUnit *su, int op, unsigned R)
Definition: ScheduleDAGInstrs.h:82
llvm::SUnit
Scheduling unit. This is a node in the scheduling DAG.
Definition: ScheduleDAG.h:242
llvm::Register::virtReg2Index
static unsigned virtReg2Index(Register Reg)
Convert a virtual register number to a 0-based index.
Definition: Register.h:77
llvm::ScheduleDAGInstrs
A ScheduleDAG for scheduling lists of MachineInstr.
Definition: ScheduleDAGInstrs.h:120
llvm::ScheduleDAGInstrs::insertBarrierChain
void insertBarrierChain(Value2SUsMap &map)
Inserts a barrier chain in a huge region, far below current SU.
Definition: ScheduleDAGInstrs.cpp:687
llvm::ScheduleDAGInstrs::fixupKills
void fixupKills(MachineBasicBlock &MBB)
Fixes register kill flags that scheduling has made invalid.
Definition: ScheduleDAGInstrs.cpp:1107
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::ScheduleDAGInstrs::reduceHugeMemNodeMaps
void reduceHugeMemNodeMaps(Value2SUsMap &stores, Value2SUsMap &loads, unsigned N)
Reduces maps in FIFO order, by N SUs.
Definition: ScheduleDAGInstrs.cpp:1040
TargetRegisterInfo.h
llvm::UnderlyingObject::UnderlyingObject
UnderlyingObject(ValueType V, bool MayAlias)
Definition: ScheduleDAGInstrs.h:110
llvm::Reg2SUnitsMap
SparseMultiSet< PhysRegSUOper, identity< unsigned >, uint16_t > Reg2SUnitsMap
Use a SparseMultiSet to track physical registers.
Definition: ScheduleDAGInstrs.h:91
llvm::TargetSchedModel::hasInstrSchedModel
bool hasInstrSchedModel() const
Return true if this machine model includes an instruction-level scheduling model.
Definition: TargetSchedule.cpp:39
LivePhysRegs.h