LLVM 19.0.0git
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llvm::TargetPassConfig Class Reference

Target-Independent Code Generator Pass Configuration Options. More...

#include "llvm/CodeGen/TargetPassConfig.h"

Inheritance diagram for llvm::TargetPassConfig:
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Classes

struct  StartStopInfo
 

Public Member Functions

 TargetPassConfig (LLVMTargetMachine &TM, PassManagerBase &pm)
 
 TargetPassConfig ()
 
 ~TargetPassConfig () override
 
template<typename TMC >
TMC & getTM () const
 Get the right type of TargetMachine for this target.
 
void setInitialized ()
 
CodeGenOptLevel getOptLevel () const
 
void setDisableVerify (bool Disable)
 
bool getEnableTailMerge () const
 
void setEnableTailMerge (bool Enable)
 
bool getEnableSinkAndFold () const
 
void setEnableSinkAndFold (bool Enable)
 
bool requiresCodeGenSCCOrder () const
 
void setRequiresCodeGenSCCOrder (bool Enable=true)
 
void substitutePass (AnalysisID StandardID, IdentifyingPassPtr TargetID)
 Allow the target to override a specific pass without overriding the pass pipeline.
 
void insertPass (AnalysisID TargetPassID, IdentifyingPassPtr InsertedPassID)
 Insert InsertedPassID pass after TargetPassID pass.
 
void enablePass (AnalysisID PassID)
 Allow the target to enable a specific standard pass by default.
 
void disablePass (AnalysisID PassID)
 Allow the target to disable a specific standard pass by default.
 
IdentifyingPassPtr getPassSubstitution (AnalysisID StandardID) const
 Return the pass substituted for StandardID by the target.
 
bool isPassSubstitutedOrOverridden (AnalysisID ID) const
 Return true if the pass has been substituted by the target or overridden on the command line.
 
bool getOptimizeRegAlloc () const
 Return true if the optimized regalloc pipeline is enabled.
 
bool usingDefaultRegAlloc () const
 Return true if the default global register allocator is in use and has not be overriden on the command line with '-regalloc=...'.
 
bool addISelPasses ()
 High level function that adds all passes necessary to go from llvm IR representation to the MI representation.
 
virtual void addIRPasses ()
 Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization.
 
void addPassesToHandleExceptions ()
 Add passes to lower exception handling for the code generator.
 
virtual void addCodeGenPrepare ()
 Add pass to prepare the LLVM IR for code generation.
 
virtual void addISelPrepare ()
 Add common passes that perform LLVM IR to IR transforms in preparation for instruction selection.
 
virtual bool addInstSelector ()
 addInstSelector - This method should install an instruction selector pass, which converts from LLVM code to machine instructions.
 
virtual bool addIRTranslator ()
 This method should install an IR translator pass, which converts from LLVM code to machine instructions with possibly generic opcodes.
 
virtual void addPreLegalizeMachineIR ()
 This method may be implemented by targets that want to run passes immediately before legalization.
 
virtual bool addLegalizeMachineIR ()
 This method should install a legalize pass, which converts the instruction sequence into one that can be selected by the target.
 
virtual void addPreRegBankSelect ()
 This method may be implemented by targets that want to run passes immediately before the register bank selection.
 
virtual bool addRegBankSelect ()
 This method should install a register bank selector pass, which assigns register banks to virtual registers without a register class or register banks.
 
virtual void addPreGlobalInstructionSelect ()
 This method may be implemented by targets that want to run passes immediately before the (global) instruction selection.
 
virtual bool addGlobalInstructionSelect ()
 This method should install a (global) instruction selector pass, which converts possibly generic instructions to fully target-specific instructions, thereby constraining all generic virtual registers to register classes.
 
virtual void addMachinePasses ()
 Add the complete, standard set of LLVM CodeGen passes.
 
virtual ScheduleDAGInstrscreateMachineScheduler (MachineSchedContext *C) const
 Create an instance of ScheduleDAGInstrs to be run within the standard MachineScheduler pass for this function and target at the current optimization level.
 
virtual ScheduleDAGInstrscreatePostMachineScheduler (MachineSchedContext *C) const
 Similar to createMachineScheduler but used when postRA machine scheduling is enabled.
 
void printAndVerify (const std::string &Banner)
 printAndVerify - Add a pass to dump then verify the machine function, if those steps are enabled.
 
void addPrintPass (const std::string &Banner)
 Add a pass to print the machine function if printing is enabled.
 
void addVerifyPass (const std::string &Banner)
 Add a pass to perform basic verification of the machine function if verification is enabled.
 
void addDebugifyPass ()
 Add a pass to add synthesized debug info to the MIR.
 
void addStripDebugPass ()
 Add a pass to remove debug info from the MIR.
 
void addCheckDebugPass ()
 Add a pass to check synthesized debug info for MIR.
 
void addMachinePrePasses (bool AllowDebugify=true)
 Add standard passes before a pass that's about to be added.
 
void addMachinePostPasses (const std::string &Banner)
 Add standard passes after a pass that has just been added.
 
bool isGlobalISelAbortEnabled () const
 Check whether or not GlobalISel should abort on error.
 
virtual bool reportDiagnosticWhenGlobalISelFallback () const
 Check whether or not a diagnostic should be emitted when GlobalISel uses the fallback path.
 
virtual bool isGISelCSEEnabled () const
 Check whether continuous CSE should be enabled in GISel passes.
 
virtual std::unique_ptr< CSEConfigBasegetCSEConfig () const
 Returns the CSEConfig object to use for the current optimization level.
 
- Public Member Functions inherited from llvm::ImmutablePass
 ImmutablePass (char &pid)
 
 ~ImmutablePass () override
 
virtual void initializePass ()
 initializePass - This method may be overriden by immutable passes to allow them to perform various initialization actions they require.
 
ImmutablePassgetAsImmutablePass () override
 
bool runOnModule (Module &) override
 ImmutablePasses are never run.
 
- Public Member Functions inherited from llvm::ModulePass
 ModulePass (char &pid)
 
 ~ModulePass () override
 
PasscreatePrinterPass (raw_ostream &OS, const std::string &Banner) const override
 createPrinterPass - Get a module printer pass.
 
virtual bool runOnModule (Module &M)=0
 runOnModule - Virtual method overriden by subclasses to process the module being operated on.
 
void assignPassManager (PMStack &PMS, PassManagerType T) override
 Find appropriate Module Pass Manager in the PM Stack and add self into that manager.
 
PassManagerType getPotentialPassManagerType () const override
 Return what kind of Pass Manager can manage this pass.
 
- Public Member Functions inherited from llvm::Pass
 Pass (PassKind K, char &pid)
 
 Pass (const Pass &)=delete
 
Passoperator= (const Pass &)=delete
 
virtual ~Pass ()
 
PassKind getPassKind () const
 
virtual StringRef getPassName () const
 getPassName - Return a nice clean name for a pass.
 
AnalysisID getPassID () const
 getPassID - Return the PassID number that corresponds to this pass.
 
virtual bool doInitialization (Module &)
 doInitialization - Virtual method overridden by subclasses to do any necessary initialization before any pass is run.
 
virtual bool doFinalization (Module &)
 doFinalization - Virtual method overriden by subclasses to do any necessary clean up after all passes have run.
 
virtual void print (raw_ostream &OS, const Module *M) const
 print - Print out the internal state of the pass.
 
void dump () const
 
virtual PasscreatePrinterPass (raw_ostream &OS, const std::string &Banner) const =0
 createPrinterPass - Get a Pass appropriate to print the IR this pass operates on (Module, Function or MachineFunction).
 
virtual void assignPassManager (PMStack &, PassManagerType)
 Each pass is responsible for assigning a pass manager to itself.
 
virtual void preparePassManager (PMStack &)
 Check if available pass managers are suitable for this pass or not.
 
virtual PassManagerType getPotentialPassManagerType () const
 Return what kind of Pass Manager can manage this pass.
 
void setResolver (AnalysisResolver *AR)
 
AnalysisResolvergetResolver () const
 
virtual void getAnalysisUsage (AnalysisUsage &) const
 getAnalysisUsage - This function should be overriden by passes that need analysis information to do their job.
 
virtual void releaseMemory ()
 releaseMemory() - This member can be implemented by a pass if it wants to be able to release its memory when it is no longer needed.
 
virtual void * getAdjustedAnalysisPointer (AnalysisID ID)
 getAdjustedAnalysisPointer - This method is used when a pass implements an analysis interface through multiple inheritance.
 
virtual ImmutablePassgetAsImmutablePass ()
 
virtual PMDataManagergetAsPMDataManager ()
 
virtual void verifyAnalysis () const
 verifyAnalysis() - This member can be implemented by a analysis pass to check state of analysis information.
 
virtual void dumpPassStructure (unsigned Offset=0)
 
template<typename AnalysisType >
AnalysisType * getAnalysisIfAvailable () const
 getAnalysisIfAvailable<AnalysisType>() - Subclasses use this function to get analysis information that might be around, for example to update it.
 
bool mustPreserveAnalysisID (char &AID) const
 mustPreserveAnalysisID - This method serves the same function as getAnalysisIfAvailable, but works if you just have an AnalysisID.
 
template<typename AnalysisType >
AnalysisType & getAnalysis () const
 getAnalysis<AnalysisType>() - This function is used by subclasses to get to the analysis information that they claim to use by overriding the getAnalysisUsage function.
 
template<typename AnalysisType >
AnalysisType & getAnalysis (Function &F, bool *Changed=nullptr)
 getAnalysis<AnalysisType>() - This function is used by subclasses to get to the analysis information that they claim to use by overriding the getAnalysisUsage function.
 
template<typename AnalysisType >
AnalysisType & getAnalysisID (AnalysisID PI) const
 
template<typename AnalysisType >
AnalysisType & getAnalysisID (AnalysisID PI, Function &F, bool *Changed=nullptr)
 

Static Public Member Functions

static bool hasLimitedCodeGenPipeline ()
 Returns true if one of the -start-after, -start-before, -stop-after or -stop-before options is set.
 
static bool willCompleteCodeGenPipeline ()
 Returns true if none of the -stop-before and -stop-after options is set.
 
static std::string getLimitedCodeGenPipelineReason ()
 If hasLimitedCodeGenPipeline is true, this method returns a string with the name of the options that caused this pipeline to be limited.
 
static Expected< StartStopInfogetStartStopInfo (PassInstrumentationCallbacks &PIC)
 Returns pass name in -stop-before or -stop-after NOTE: New pass manager migration only.
 
- Static Public Member Functions inherited from llvm::Pass
static const PassInfolookupPassInfo (const void *TI)
 
static const PassInfolookupPassInfo (StringRef Arg)
 
static PasscreatePass (AnalysisID ID)
 

Static Public Attributes

static char ID
 

Protected Member Functions

bool addCoreISelPasses ()
 Add the actual instruction selection passes.
 
void setOpt (bool &Opt, bool Val)
 
bool isCustomizedRegAlloc ()
 Return true if register allocator is specified by -regalloc=override.
 
virtual bool addPreISel ()
 Methods with trivial inline returns are convenient points in the common codegen pass pipeline where targets may insert passes.
 
virtual void addMachineSSAOptimization ()
 addMachineSSAOptimization - Add standard passes that optimize machine instructions in SSA form.
 
virtual bool addILPOpts ()
 Add passes that optimize instruction level parallelism for out-of-order targets.
 
virtual void addPreRegAlloc ()
 This method may be implemented by targets that want to run passes immediately before register allocation.
 
virtual FunctionPasscreateTargetRegisterAllocator (bool Optimized)
 createTargetRegisterAllocator - Create the register allocator pass for this target at the current optimization level.
 
virtual void addFastRegAlloc ()
 addFastRegAlloc - Add the minimum set of target-independent passes that are required for fast register allocation.
 
virtual void addOptimizedRegAlloc ()
 addOptimizedRegAlloc - Add passes related to register allocation.
 
virtual bool addPreRewrite ()
 addPreRewrite - Add passes to the optimized register allocation pipeline after register allocation is complete, but before virtual registers are rewritten to physical registers.
 
virtual bool addPostFastRegAllocRewrite ()
 addPostFastRegAllocRewrite - Add passes to the optimized register allocation pipeline after fast register allocation is complete.
 
virtual void addPostRewrite ()
 Add passes to be run immediately after virtual registers are rewritten to physical registers.
 
virtual void addPostRegAlloc ()
 This method may be implemented by targets that want to run passes after register allocation pass pipeline but before prolog-epilog insertion.
 
virtual void addMachineLateOptimization ()
 Add passes that optimize machine instructions after register allocation.
 
virtual void addPreSched2 ()
 This method may be implemented by targets that want to run passes after prolog-epilog insertion and before the second instruction scheduling pass.
 
virtual bool addGCPasses ()
 addGCPasses - Add late codegen passes that analyze code for garbage collection.
 
virtual void addBlockPlacement ()
 Add standard basic block placement passes.
 
virtual void addPreEmitPass ()
 This pass may be implemented by targets that want to run passes immediately before machine code is emitted.
 
virtual void addPostBBSections ()
 This pass may be implemented by targets that want to run passes immediately after basic block sections are assigned.
 
virtual void addPreEmitPass2 ()
 Targets may add passes immediately before machine code is emitted in this callback.
 
AnalysisID addPass (AnalysisID PassID)
 Utilities for targets to add passes to the pass manager.
 
void addPass (Pass *P)
 Add a pass to the PassManager if that pass is supposed to be run, as determined by the StartAfter and StopAfter options.
 
virtual FunctionPasscreateRegAllocPass (bool Optimized)
 addMachinePasses helper to create the target-selected or overriden regalloc pass.
 
virtual bool addRegAssignAndRewriteFast ()
 Add core register allocator passes which do the actual register assignment and rewriting.
 
virtual bool addRegAssignAndRewriteOptimized ()
 
- Protected Member Functions inherited from llvm::ModulePass
bool skipModule (Module &M) const
 Optional passes call this function to check whether the pass should be skipped.
 

Protected Attributes

LLVMTargetMachineTM
 
PassConfigImplImpl = nullptr
 
bool Initialized = false
 
bool DisableVerify = false
 
bool EnableTailMerge = true
 Default setting for -enable-tail-merge on this target.
 
bool EnableSinkAndFold = false
 Enable sinking of instructions in MachineSink where a computation can be folded into the addressing mode of a memory load/store instruction or replace a copy.
 
bool RequireCodeGenSCCOrder = false
 Require processing of functions such that callees are generated before callers.
 

Detailed Description

Target-Independent Code Generator Pass Configuration Options.

This is an ImmutablePass solely for the purpose of exposing CodeGen options to the internals of other CodeGen passes.

Definition at line 85 of file TargetPassConfig.h.

Constructor & Destructor Documentation

◆ TargetPassConfig() [1/2]

TargetPassConfig::TargetPassConfig ( LLVMTargetMachine TM,
PassManagerBase pm 
)

◆ TargetPassConfig() [2/2]

TargetPassConfig::TargetPassConfig ( )

Definition at line 626 of file TargetPassConfig.cpp.

References llvm::report_fatal_error().

◆ ~TargetPassConfig()

TargetPassConfig::~TargetPassConfig ( )
override

Definition at line 405 of file TargetPassConfig.cpp.

References Impl.

Member Function Documentation

◆ addBlockPlacement()

void TargetPassConfig::addBlockPlacement ( )
protectedvirtual

◆ addCheckDebugPass()

void TargetPassConfig::addCheckDebugPass ( )

Add a pass to check synthesized debug info for MIR.

Definition at line 787 of file TargetPassConfig.cpp.

References llvm::legacy::PassManagerBase::add(), and llvm::createCheckDebugMachineModulePass().

Referenced by addMachinePostPasses().

◆ addCodeGenPrepare()

void TargetPassConfig::addCodeGenPrepare ( )
virtual

Add pass to prepare the LLVM IR for code generation.

This should be done before exception handling preparation passes.

Reimplemented in llvm::AMDGPUPassConfig, and DirectXPassConfig.

Definition at line 939 of file TargetPassConfig.cpp.

References addPass(), llvm::createCodeGenPrepareLegacyPass(), DisableCGP, getOptLevel(), and llvm::None.

Referenced by llvm::AMDGPUPassConfig::addCodeGenPrepare(), addISelPasses(), and llvm::DirectXTargetMachine::addPassesToEmitFile().

◆ addCoreISelPasses()

bool TargetPassConfig::addCoreISelPasses ( )
protected

◆ addDebugifyPass()

void TargetPassConfig::addDebugifyPass ( )

Add a pass to add synthesized debug info to the MIR.

Definition at line 779 of file TargetPassConfig.cpp.

References llvm::legacy::PassManagerBase::add(), and llvm::createDebugifyMachineModulePass().

Referenced by addMachinePrePasses().

◆ addFastRegAlloc()

void TargetPassConfig::addFastRegAlloc ( )
protectedvirtual

addFastRegAlloc - Add the minimum set of target-independent passes that are required for fast register allocation.

Add the minimum set of target-independent passes that are required for register allocation.

No coalescing or scheduling.

Definition at line 1421 of file TargetPassConfig.cpp.

References addPass(), addRegAssignAndRewriteFast(), llvm::PHIEliminationID, and llvm::TwoAddressInstructionPassID.

Referenced by addMachinePasses().

◆ addGCPasses()

bool TargetPassConfig::addGCPasses ( )
protectedvirtual

addGCPasses - Add late codegen passes that analyze code for garbage collection.

Add standard GC passes.

This should return true if GC info should be printed after these passes.

Reimplemented in llvm::AMDGPUPassConfig.

Definition at line 1513 of file TargetPassConfig.cpp.

References addPass(), and llvm::GCMachineCodeAnalysisID.

Referenced by addMachinePasses().

◆ addGlobalInstructionSelect()

virtual bool llvm::TargetPassConfig::addGlobalInstructionSelect ( )
inlinevirtual

This method should install a (global) instruction selector pass, which converts possibly generic instructions to fully target-specific instructions, thereby constraining all generic virtual registers to register classes.

Definition at line 294 of file TargetPassConfig.h.

Referenced by addCoreISelPasses().

◆ addILPOpts()

virtual bool llvm::TargetPassConfig::addILPOpts ( )
inlineprotectedvirtual

Add passes that optimize instruction level parallelism for out-of-order targets.

These passes are run while the machine code is still in SSA form, so they can use MachineTraceMetrics to control their heuristics.

All passes added here should preserve the MachineDominatorTree, MachineLoopInfo, and MachineTraceMetrics analyses.

Definition at line 396 of file TargetPassConfig.h.

Referenced by addMachineSSAOptimization().

◆ addInstSelector()

virtual bool llvm::TargetPassConfig::addInstSelector ( )
inlinevirtual

addInstSelector - This method should install an instruction selector pass, which converts from LLVM code to machine instructions.

Reimplemented in llvm::AMDGPUPassConfig.

Definition at line 261 of file TargetPassConfig.h.

Referenced by addCoreISelPasses().

◆ addIRPasses()

void TargetPassConfig::addIRPasses ( )
virtual

◆ addIRTranslator()

virtual bool llvm::TargetPassConfig::addIRTranslator ( )
inlinevirtual

This method should install an IR translator pass, which converts from LLVM code to machine instructions with possibly generic opcodes.

Definition at line 267 of file TargetPassConfig.h.

Referenced by addCoreISelPasses().

◆ addISelPasses()

bool TargetPassConfig::addISelPasses ( )

High level function that adds all passes necessary to go from llvm IR representation to the MI representation.

Adds IR based lowering and target specific optimization passes and finally the core instruction selection passes.

Returns
true if an error occurred, false otherwise.

Definition at line 1057 of file TargetPassConfig.cpp.

References llvm::legacy::PassManagerBase::add(), addCodeGenPrepare(), addCoreISelPasses(), addIRPasses(), addISelPrepare(), addPass(), addPassesToHandleExceptions(), llvm::createExpandLargeDivRemPass(), llvm::createExpandLargeFpConvertPass(), llvm::createLowerEmuTLSPass(), llvm::createPreISelIntrinsicLoweringPass(), llvm::createTargetTransformInfoWrapperPass(), llvm::TargetMachine::getTargetIRAnalysis(), TM, and llvm::TargetMachine::useEmulatedTLS().

Referenced by addPassesToGenerateCode().

◆ addISelPrepare()

void TargetPassConfig::addISelPrepare ( )
virtual

Add common passes that perform LLVM IR to IR transforms in preparation for instruction selection.

Definition at line 946 of file TargetPassConfig.cpp.

References addPass(), addPreISel(), llvm::createCallBrPass(), llvm::createPrintFunctionPass(), llvm::createSafeStackPass(), llvm::createStackProtectorPass(), llvm::createVerifierPass(), llvm::dbgs(), DisableVerify, PrintISelInput, and requiresCodeGenSCCOrder().

Referenced by addISelPasses().

◆ addLegalizeMachineIR()

virtual bool llvm::TargetPassConfig::addLegalizeMachineIR ( )
inlinevirtual

This method should install a legalize pass, which converts the instruction sequence into one that can be selected by the target.

Definition at line 275 of file TargetPassConfig.h.

Referenced by addCoreISelPasses().

◆ addMachineLateOptimization()

void TargetPassConfig::addMachineLateOptimization ( )
protectedvirtual

Add passes that optimize machine instructions after register allocation.

Post RegAlloc Pass Configuration.

Add passes that optimize machine instructions after register allocation.

Definition at line 1494 of file TargetPassConfig.cpp.

References addPass(), llvm::BranchFolderPassID, llvm::MachineCopyPropagationID, llvm::MachineLateInstrsCleanupID, llvm::TargetMachine::requiresStructuredCFG(), llvm::TailDuplicateID, and TM.

Referenced by addMachinePasses().

◆ addMachinePasses()

void TargetPassConfig::addMachinePasses ( )
virtual

Add the complete, standard set of LLVM CodeGen passes.

Add the complete set of target-independent postISel code generator passes.

Fully developed targets will not generally override this.

This can be read as the standard order of major LLVM CodeGen stages. Stages with nontrivial configuration or multiple passes are broken out below in addStage routines.

Any TargetPassConfig::addXX routine may be overriden by the Target. The addPre/Post methods with empty header implementations allow injecting target-specific fixups just before or after major stages. Additionally, targets have the flexibility to change pass order within a stage by overriding default implementation of addStage routines below. Each technique has maintainability tradeoffs because alternate pass orders are not well supported. addPre/Post works better if the target pass is easily tied to a common pass. But if it has subtle dependencies on multiple passes, the target should override the stage instead.

TODO: We could use a single addPre/Post(ID) hook to allow pass injection before/after any target-independent pass. But it's currently overkill.

Add passes that optimize machine instructions after register allocation.

Definition at line 1098 of file TargetPassConfig.cpp.

References llvm::legacy::PassManagerBase::add(), addBlockPlacement(), addFastRegAlloc(), addGCPasses(), addMachineLateOptimization(), addMachineSSAOptimization(), addOptimizedRegAlloc(), addPass(), addPostBBSections(), addPostRegAlloc(), addPreEmitPass(), addPreEmitPass2(), addPreRegAlloc(), addPreSched2(), llvm::AlwaysOutline, llvm::TargetOptions::BBAddrMap, llvm::createBasicBlockPathCloningPass(), llvm::createBasicBlockSectionsPass(), llvm::createBasicBlockSectionsProfileReaderWrapperPass(), llvm::createCFIFixup(), llvm::createGCEmptyBasicBlocksPass(), llvm::createMachineFunctionSplitterPass(), llvm::createMachineOutlinerPass(), llvm::createMIRAddFSDiscriminatorsPass(), llvm::createMIRProfileLoaderPass(), llvm::createPrologEpilogInserterPass(), llvm::createRegUsageInfoCollector(), llvm::createRegUsageInfoPropPass(), llvm::createStackFrameLayoutAnalysisPass(), DisableCFIFixup, DisableRAFSProfileLoader, llvm::TargetOptions::EnableCFIFixup, llvm::EnableFSDiscriminator, EnableImplicitNullChecks, llvm::TargetOptions::EnableIPRA, llvm::TargetOptions::EnableMachineFunctionSplitter, EnableMachineFunctionSplitter, llvm::TargetOptions::EnableMachineOutliner, EnableMachineOutliner, llvm::ExpandPostRAPseudosID, llvm::FEntryInserterID, llvm::FixupStatepointCallerSavedID, llvm::FuncletLayoutID, GCEmptyBlocks, llvm::TargetMachine::getBBSectionsFuncListBuf(), llvm::TargetMachine::getBBSectionsType(), getFSProfileFile(), getFSRemappingFile(), getOptimizeRegAlloc(), getOptLevel(), llvm::ImplicitNullChecksID, isPassSubstitutedOrOverridden(), llvm::List, llvm::LiveDebugValuesID, llvm::LocalStackSlotAllocationID, llvm::MachineSanitizerBinaryMetadataID, MISchedPostRA, llvm::NeverOutline, llvm::None, llvm::TargetMachine::Options, llvm::sampleprof::Pass1, llvm::sampleprof::PassLast, llvm::PatchableFunctionID, llvm::PostMachineSchedulerID, llvm::PostRAMachineSinkingID, llvm::PostRASchedulerID, llvm::PrologEpilogCodeInserterID, llvm::RemoveRedundantDebugValuesID, llvm::ShrinkWrapID, llvm::StackMapLivenessID, llvm::TargetOptions::SupportsDefaultOutlining, llvm::TargetMachine::targetSchedulesPostRAScheduling(), TM, llvm::WithColor::warning(), and llvm::XRayInstrumentationID.

Referenced by addPassesToGenerateCode().

◆ addMachinePostPasses()

void TargetPassConfig::addMachinePostPasses ( const std::string &  Banner)

Add standard passes after a pass that has just been added.

For example, the MachineVerifier if it is enabled.

Definition at line 798 of file TargetPassConfig.cpp.

References addCheckDebugPass(), addStripDebugPass(), addVerifyPass(), llvm::cl::BOU_TRUE, DebugifyAndStripAll, and DebugifyCheckAndStripAll.

Referenced by addPass().

◆ addMachinePrePasses()

void TargetPassConfig::addMachinePrePasses ( bool  AllowDebugify = true)

Add standard passes before a pass that's about to be added.

For example, the DebugifyMachineModulePass if it is enabled.

Definition at line 791 of file TargetPassConfig.cpp.

References addDebugifyPass(), llvm::cl::BOU_TRUE, DebugifyAndStripAll, and DebugifyCheckAndStripAll.

Referenced by addPass().

◆ addMachineSSAOptimization()

void TargetPassConfig::addMachineSSAOptimization ( )
protectedvirtual

addMachineSSAOptimization - Add standard passes that optimize machine instructions in SSA form.

Add passes that optimize machine instructions in SSA form.

Definition at line 1276 of file TargetPassConfig.cpp.

References addILPOpts(), addPass(), llvm::DeadMachineInstructionElimID, llvm::EarlyMachineLICMID, llvm::EarlyTailDuplicateID, llvm::LocalStackSlotAllocationID, llvm::MachineCSEID, llvm::MachineSinkingID, llvm::OptimizePHIsID, llvm::PeepholeOptimizerID, and llvm::StackColoringID.

Referenced by addMachinePasses().

◆ addOptimizedRegAlloc()

void TargetPassConfig::addOptimizedRegAlloc ( )
protectedvirtual

addOptimizedRegAlloc - Add passes related to register allocation.

Add standard target-independent passes that are tightly coupled with optimized register allocation, including coalescing, machine instruction scheduling, and register allocation itself.

LLVMTargetMachine provides standard regalloc passes for most targets.

Definition at line 1431 of file TargetPassConfig.cpp.

References addPass(), addPostRewrite(), addRegAssignAndRewriteOptimized(), llvm::DetectDeadLanesID, EarlyLiveIntervals, llvm::InitUndefID, llvm::LiveIntervalsID, llvm::LiveVariablesID, llvm::MachineCopyPropagationID, llvm::MachineLICMID, llvm::MachineLoopInfoID, llvm::MachineSchedulerID, llvm::PHIEliminationID, llvm::ProcessImplicitDefsID, llvm::RegisterCoalescerID, llvm::RenameIndependentSubregsID, llvm::StackSlotColoringID, llvm::TwoAddressInstructionPassID, and llvm::UnreachableMachineBlockElimID.

Referenced by addMachinePasses().

◆ addPass() [1/2]

AnalysisID TargetPassConfig::addPass ( AnalysisID  PassID)
protected

◆ addPass() [2/2]

void TargetPassConfig::addPass ( Pass P)
protected

Add a pass to the PassManager if that pass is supposed to be run, as determined by the StartAfter and StopAfter options.

Add a pass to the PassManager if that pass is supposed to be run.

Takes ownership of the pass.

If the Started/Stopped flags indicate either that the compilation should start at a later pass or that it should stop after an earlier pass, then do not add the pass. Finally, compare the current pass against the StartAfter and StopAfter options and change the Started/Stopped flags accordingly.

Definition at line 692 of file TargetPassConfig.cpp.

References llvm::legacy::PassManagerBase::add(), addMachinePostPasses(), addMachinePrePasses(), addPass(), assert(), Impl, Initialized, llvm::PassConfigImpl::InsertedPasses, P, and llvm::report_fatal_error().

◆ addPassesToHandleExceptions()

void TargetPassConfig::addPassesToHandleExceptions ( )

◆ addPostBBSections()

virtual void llvm::TargetPassConfig::addPostBBSections ( )
inlineprotectedvirtual

This pass may be implemented by targets that want to run passes immediately after basic block sections are assigned.

Definition at line 465 of file TargetPassConfig.h.

Referenced by addMachinePasses().

◆ addPostFastRegAllocRewrite()

virtual bool llvm::TargetPassConfig::addPostFastRegAllocRewrite ( )
inlineprotectedvirtual

addPostFastRegAllocRewrite - Add passes to the optimized register allocation pipeline after fast register allocation is complete.

Definition at line 434 of file TargetPassConfig.h.

Referenced by addRegAssignAndRewriteFast().

◆ addPostRegAlloc()

virtual void llvm::TargetPassConfig::addPostRegAlloc ( )
inlineprotectedvirtual

This method may be implemented by targets that want to run passes after register allocation pass pipeline but before prolog-epilog insertion.

Definition at line 442 of file TargetPassConfig.h.

Referenced by addMachinePasses().

◆ addPostRewrite()

virtual void llvm::TargetPassConfig::addPostRewrite ( )
inlineprotectedvirtual

Add passes to be run immediately after virtual registers are rewritten to physical registers.

Definition at line 438 of file TargetPassConfig.h.

Referenced by addOptimizedRegAlloc().

◆ addPreEmitPass()

virtual void llvm::TargetPassConfig::addPreEmitPass ( )
inlineprotectedvirtual

This pass may be implemented by targets that want to run passes immediately before machine code is emitted.

Definition at line 461 of file TargetPassConfig.h.

Referenced by addMachinePasses().

◆ addPreEmitPass2()

virtual void llvm::TargetPassConfig::addPreEmitPass2 ( )
inlineprotectedvirtual

Targets may add passes immediately before machine code is emitted in this callback.

This is called even later than addPreEmitPass.

Definition at line 472 of file TargetPassConfig.h.

Referenced by addMachinePasses().

◆ addPreGlobalInstructionSelect()

virtual void llvm::TargetPassConfig::addPreGlobalInstructionSelect ( )
inlinevirtual

This method may be implemented by targets that want to run passes immediately before the (global) instruction selection.

Definition at line 288 of file TargetPassConfig.h.

Referenced by addCoreISelPasses().

◆ addPreISel()

virtual bool llvm::TargetPassConfig::addPreISel ( )
inlineprotectedvirtual

Methods with trivial inline returns are convenient points in the common codegen pass pipeline where targets may insert passes.

Methods with out-of-line standard implementations are major CodeGen stages called by addMachinePasses. Some targets may override major stages when inserting passes is insufficient, but maintaining overriden stages is more work. addPreISelPasses - This method should add any "last minute" LLVM->LLVM passes (which are run just before instruction selector).

Reimplemented in llvm::AMDGPUPassConfig.

Definition at line 382 of file TargetPassConfig.h.

Referenced by addISelPrepare().

◆ addPreLegalizeMachineIR()

virtual void llvm::TargetPassConfig::addPreLegalizeMachineIR ( )
inlinevirtual

This method may be implemented by targets that want to run passes immediately before legalization.

Definition at line 271 of file TargetPassConfig.h.

Referenced by addCoreISelPasses().

◆ addPreRegAlloc()

virtual void llvm::TargetPassConfig::addPreRegAlloc ( )
inlineprotectedvirtual

This method may be implemented by targets that want to run passes immediately before register allocation.

Definition at line 402 of file TargetPassConfig.h.

Referenced by addMachinePasses().

◆ addPreRegBankSelect()

virtual void llvm::TargetPassConfig::addPreRegBankSelect ( )
inlinevirtual

This method may be implemented by targets that want to run passes immediately before the register bank selection.

Definition at line 279 of file TargetPassConfig.h.

Referenced by addCoreISelPasses().

◆ addPreRewrite()

virtual bool llvm::TargetPassConfig::addPreRewrite ( )
inlineprotectedvirtual

addPreRewrite - Add passes to the optimized register allocation pipeline after register allocation is complete, but before virtual registers are rewritten to physical registers.

These passes must preserve VirtRegMap and LiveIntervals, and when running after RABasic or RAGreedy, they should take advantage of LiveRegMatrix. When these passes run, VirtRegMap contains legal physreg assignments for all virtual registers.

Note if the target overloads addRegAssignAndRewriteOptimized, this may not be honored. This is also not generally used for the fast variant, where the allocation and rewriting are done in one pass.

Definition at line 428 of file TargetPassConfig.h.

Referenced by addRegAssignAndRewriteOptimized().

◆ addPreSched2()

virtual void llvm::TargetPassConfig::addPreSched2 ( )
inlineprotectedvirtual

This method may be implemented by targets that want to run passes after prolog-epilog insertion and before the second instruction scheduling pass.

Definition at line 449 of file TargetPassConfig.h.

Referenced by addMachinePasses().

◆ addPrintPass()

void TargetPassConfig::addPrintPass ( const std::string &  Banner)

Add a pass to print the machine function if printing is enabled.

Definition at line 764 of file TargetPassConfig.cpp.

References llvm::legacy::PassManagerBase::add(), llvm::createMachineFunctionPrinterPass(), llvm::dbgs(), and PrintAfterISel.

Referenced by printAndVerify().

◆ addRegAssignAndRewriteFast()

bool TargetPassConfig::addRegAssignAndRewriteFast ( )
protectedvirtual

Add core register allocator passes which do the actual register assignment and rewriting.

Returns
true if any passes were added.

Definition at line 1384 of file TargetPassConfig.cpp.

References addPass(), addPostFastRegAllocRewrite(), llvm::createFastRegisterAllocator(), createRegAllocPass(), RegAlloc, llvm::report_fatal_error(), and useDefaultRegisterAllocator().

Referenced by addFastRegAlloc().

◆ addRegAssignAndRewriteOptimized()

bool TargetPassConfig::addRegAssignAndRewriteOptimized ( )
protectedvirtual

◆ addRegBankSelect()

virtual bool llvm::TargetPassConfig::addRegBankSelect ( )
inlinevirtual

This method should install a register bank selector pass, which assigns register banks to virtual registers without a register class or register banks.

Definition at line 284 of file TargetPassConfig.h.

Referenced by addCoreISelPasses().

◆ addStripDebugPass()

void TargetPassConfig::addStripDebugPass ( )

Add a pass to remove debug info from the MIR.

Definition at line 783 of file TargetPassConfig.cpp.

References llvm::legacy::PassManagerBase::add(), and llvm::createStripDebugMachineModulePass().

Referenced by addMachinePostPasses().

◆ addVerifyPass()

void TargetPassConfig::addVerifyPass ( const std::string &  Banner)

Add a pass to perform basic verification of the machine function if verification is enabled.

Definition at line 769 of file TargetPassConfig.cpp.

References llvm::legacy::PassManagerBase::add(), llvm::cl::BOU_TRUE, llvm::cl::BOU_UNSET, llvm::createMachineVerifierPass(), llvm::LLVMTargetMachine::isMachineVerifierClean(), TM, Verify, and VerifyMachineCode.

Referenced by addMachinePostPasses(), and printAndVerify().

◆ createMachineScheduler()

virtual ScheduleDAGInstrs * llvm::TargetPassConfig::createMachineScheduler ( MachineSchedContext C) const
inlinevirtual

Create an instance of ScheduleDAGInstrs to be run within the standard MachineScheduler pass for this function and target at the current optimization level.

This can also be used to plug a new MachineSchedStrategy into an instance of the standard ScheduleDAGMI: return new ScheduleDAGMI(C, std::make_unique<MyStrategy>(C), /*RemoveKillFlags=*‍/false)

Return NULL to select the default (generic) machine scheduler.

Reimplemented in llvm::AMDGPUPassConfig.

Definition at line 310 of file TargetPassConfig.h.

◆ createPostMachineScheduler()

virtual ScheduleDAGInstrs * llvm::TargetPassConfig::createPostMachineScheduler ( MachineSchedContext C) const
inlinevirtual

Similar to createMachineScheduler but used when postRA machine scheduling is enabled.

Definition at line 317 of file TargetPassConfig.h.

◆ createRegAllocPass()

FunctionPass * TargetPassConfig::createRegAllocPass ( bool  Optimized)
protectedvirtual

addMachinePasses helper to create the target-selected or overriden regalloc pass.

Find and instantiate the register allocation pass requested by this target at the current optimization level.

Different register allocators are defined as separate passes because they may require different analysis.

This helper ensures that the regalloc= option is always available, even for targets that override the default allocator.

FIXME: When MachinePassRegistry register pass IDs instead of function ptrs, this can be folded into addPass.

Definition at line 1366 of file TargetPassConfig.cpp.

References llvm::call_once(), createTargetRegisterAllocator(), llvm::RegisterRegAllocBase< RegisterRegAlloc >::getDefault(), InitializeDefaultRegisterAllocatorFlag, initializeDefaultRegisterAllocatorOnce(), and useDefaultRegisterAllocator().

Referenced by addRegAssignAndRewriteFast(), and addRegAssignAndRewriteOptimized().

◆ createTargetRegisterAllocator()

FunctionPass * TargetPassConfig::createTargetRegisterAllocator ( bool  Optimized)
protectedvirtual

createTargetRegisterAllocator - Create the register allocator pass for this target at the current optimization level.

Instantiate the default register allocator pass for this target for either the optimized or unoptimized allocation path.

This will be added to the pass manager by addFastRegAlloc in the unoptimized case or addOptimizedRegAlloc in the optimized case.

A target that uses the standard regalloc pass order for fast or optimized allocation may still override this for per-target regalloc selection. But -regalloc=... always takes precedence.

Reimplemented in DirectXPassConfig.

Definition at line 1350 of file TargetPassConfig.cpp.

References llvm::createFastRegisterAllocator(), and llvm::createGreedyRegisterAllocator().

Referenced by createRegAllocPass().

◆ disablePass()

void llvm::TargetPassConfig::disablePass ( AnalysisID  PassID)
inline

Allow the target to disable a specific standard pass by default.

Definition at line 218 of file TargetPassConfig.h.

References substitutePass().

Referenced by llvm::AMDGPUPassConfig::addIRPasses(), and llvm::AMDGPUPassConfig::AMDGPUPassConfig().

◆ enablePass()

void llvm::TargetPassConfig::enablePass ( AnalysisID  PassID)
inline

Allow the target to enable a specific standard pass by default.

Definition at line 215 of file TargetPassConfig.h.

References substitutePass().

◆ getCSEConfig()

std::unique_ptr< CSEConfigBase > TargetPassConfig::getCSEConfig ( ) const
virtual

Returns the CSEConfig object to use for the current optimization level.

Reimplemented in llvm::AMDGPUPassConfig.

Definition at line 1551 of file TargetPassConfig.cpp.

Referenced by llvm::IRTranslator::runOnMachineFunction(), and llvm::Legalizer::runOnMachineFunction().

◆ getEnableSinkAndFold()

bool llvm::TargetPassConfig::getEnableSinkAndFold ( ) const
inline

Definition at line 198 of file TargetPassConfig.h.

References EnableSinkAndFold.

◆ getEnableTailMerge()

bool llvm::TargetPassConfig::getEnableTailMerge ( ) const
inline

Definition at line 195 of file TargetPassConfig.h.

References EnableTailMerge.

Referenced by INITIALIZE_PASS().

◆ getLimitedCodeGenPipelineReason()

std::string TargetPassConfig::getLimitedCodeGenPipelineReason ( )
static

If hasLimitedCodeGenPipeline is true, this method returns a string with the name of the options that caused this pipeline to be limited.

Definition at line 642 of file TargetPassConfig.cpp.

References hasLimitedCodeGenPipeline(), Idx, StartAfterOpt, StartAfterOptName, StartBeforeOpt, StartBeforeOptName, StopAfterOpt, StopAfterOptName, StopBeforeOpt, and StopBeforeOptName.

◆ getOptimizeRegAlloc()

bool TargetPassConfig::getOptimizeRegAlloc ( ) const

Return true if the optimized regalloc pipeline is enabled.

Register Allocation Pass Configuration.

Definition at line 1318 of file TargetPassConfig.cpp.

References llvm::cl::BOU_FALSE, llvm::cl::BOU_TRUE, llvm::cl::BOU_UNSET, getOptLevel(), llvm_unreachable, llvm::None, and OptimizeRegAlloc.

Referenced by addMachinePasses().

◆ getOptLevel()

CodeGenOptLevel TargetPassConfig::getOptLevel ( ) const

◆ getPassSubstitution()

IdentifyingPassPtr TargetPassConfig::getPassSubstitution ( AnalysisID  StandardID) const

Return the pass substituted for StandardID by the target.

If no substitution exists, return StandardID.

Definition at line 672 of file TargetPassConfig.cpp.

References I, ID, Impl, and llvm::PassConfigImpl::TargetPasses.

Referenced by addPass(), and isPassSubstitutedOrOverridden().

◆ getStartStopInfo()

Expected< TargetPassConfig::StartStopInfo > TargetPassConfig::getStartStopInfo ( PassInstrumentationCallbacks PIC)
static

Returns pass name in -stop-before or -stop-after NOTE: New pass manager migration only.

Definition at line 540 of file TargetPassConfig.cpp.

References getPassNameAndInstanceNum(), StartAfterOpt, StartAfterOptName, StartBeforeOpt, StartBeforeOptName, StopAfterOpt, StopAfterOptName, StopBeforeOpt, and StopBeforeOptName.

Referenced by llvm::CodeGenPassBuilder< DerivedT >::buildPipeline().

◆ getTM()

template<typename TMC >
TMC & llvm::TargetPassConfig::getTM ( ) const
inline

Get the right type of TargetMachine for this target.

Definition at line 157 of file TargetPassConfig.h.

References TM.

Referenced by TransferTracker::TransferTracker().

◆ hasLimitedCodeGenPipeline()

bool TargetPassConfig::hasLimitedCodeGenPipeline ( )
static

Returns true if one of the -start-after, -start-before, -stop-after or -stop-before options is set.

Definition at line 637 of file TargetPassConfig.cpp.

References StartAfterOpt, StartBeforeOpt, and willCompleteCodeGenPipeline().

Referenced by getLimitedCodeGenPipelineReason().

◆ insertPass()

void TargetPassConfig::insertPass ( AnalysisID  TargetPassID,
IdentifyingPassPtr  InsertedPassID 
)

◆ isCustomizedRegAlloc()

bool TargetPassConfig::isCustomizedRegAlloc ( )
protected

Return true if register allocator is specified by -regalloc=override.

Definition at line 1379 of file TargetPassConfig.cpp.

References RegAlloc, and useDefaultRegisterAllocator().

◆ isGISelCSEEnabled()

bool TargetPassConfig::isGISelCSEEnabled ( ) const
virtual

Check whether continuous CSE should be enabled in GISel passes.

By default, it's enabled for non O0 levels.

Definition at line 1547 of file TargetPassConfig.cpp.

Referenced by llvm::IRTranslator::runOnMachineFunction(), and llvm::Legalizer::runOnMachineFunction().

◆ isGlobalISelAbortEnabled()

bool TargetPassConfig::isGlobalISelAbortEnabled ( ) const

Check whether or not GlobalISel should abort on error.

GlobalISel Configuration.

When this is disabled, GlobalISel will fall back on SDISel instead of erroring out.

Definition at line 1539 of file TargetPassConfig.cpp.

References llvm::Enable, llvm::TargetOptions::GlobalISelAbort, llvm::TargetMachine::Options, and TM.

Referenced by addCoreISelPasses(), llvm::RegBankSelect::findBestMapping(), reportGISelDiagnostic(), and llvm::reportGISelFailure().

◆ isPassSubstitutedOrOverridden()

bool TargetPassConfig::isPassSubstitutedOrOverridden ( AnalysisID  ID) const

Return true if the pass has been substituted by the target or overridden on the command line.

Definition at line 680 of file TargetPassConfig.cpp.

References llvm::IdentifyingPassPtr::getID(), getPassSubstitution(), ID, llvm::IdentifyingPassPtr::isInstance(), llvm::IdentifyingPassPtr::isValid(), and overridePass().

Referenced by addMachinePasses().

◆ printAndVerify()

void TargetPassConfig::printAndVerify ( const std::string &  Banner)

printAndVerify - Add a pass to dump then verify the machine function, if those steps are enabled.

Definition at line 759 of file TargetPassConfig.cpp.

References addPrintPass(), and addVerifyPass().

Referenced by addCoreISelPasses().

◆ reportDiagnosticWhenGlobalISelFallback()

bool TargetPassConfig::reportDiagnosticWhenGlobalISelFallback ( ) const
virtual

Check whether or not a diagnostic should be emitted when GlobalISel uses the fallback path.

In other words, it will emit a diagnostic when GlobalISel failed and isGlobalISelAbortEnabled is false.

Definition at line 1543 of file TargetPassConfig.cpp.

References llvm::DisableWithDiag, llvm::TargetOptions::GlobalISelAbort, llvm::TargetMachine::Options, and TM.

Referenced by addCoreISelPasses().

◆ requiresCodeGenSCCOrder()

bool llvm::TargetPassConfig::requiresCodeGenSCCOrder ( ) const
inline

Definition at line 201 of file TargetPassConfig.h.

References RequireCodeGenSCCOrder.

Referenced by addISelPrepare().

◆ setDisableVerify()

void llvm::TargetPassConfig::setDisableVerify ( bool  Disable)
inline

Definition at line 193 of file TargetPassConfig.h.

References llvm::Disable, DisableVerify, and setOpt().

Referenced by addPassesToGenerateCode().

◆ setEnableSinkAndFold()

void llvm::TargetPassConfig::setEnableSinkAndFold ( bool  Enable)
inline

Definition at line 199 of file TargetPassConfig.h.

References llvm::Enable, EnableSinkAndFold, and setOpt().

◆ setEnableTailMerge()

void llvm::TargetPassConfig::setEnableTailMerge ( bool  Enable)
inline

Definition at line 196 of file TargetPassConfig.h.

References llvm::Enable, EnableTailMerge, and setOpt().

◆ setInitialized()

void llvm::TargetPassConfig::setInitialized ( )
inline

Definition at line 162 of file TargetPassConfig.h.

References Initialized.

Referenced by addPassesToGenerateCode().

◆ setOpt()

void TargetPassConfig::setOpt ( bool Opt,
bool  Val 
)
protected

◆ setRequiresCodeGenSCCOrder()

void llvm::TargetPassConfig::setRequiresCodeGenSCCOrder ( bool  Enable = true)
inline

Definition at line 202 of file TargetPassConfig.h.

References llvm::Enable, RequireCodeGenSCCOrder, and setOpt().

Referenced by TargetPassConfig().

◆ substitutePass()

void TargetPassConfig::substitutePass ( AnalysisID  StandardID,
IdentifyingPassPtr  TargetID 
)

Allow the target to override a specific pass without overriding the pass pipeline.

When passes are added to the standard pipeline at the point where StandardID is expected, add TargetID in its place.

Definition at line 667 of file TargetPassConfig.cpp.

References Impl, and llvm::PassConfigImpl::TargetPasses.

Referenced by disablePass(), and enablePass().

◆ usingDefaultRegAlloc()

bool TargetPassConfig::usingDefaultRegAlloc ( ) const

Return true if the default global register allocator is in use and has not be overriden on the command line with '-regalloc=...'.

Definition at line 1415 of file TargetPassConfig.cpp.

References RegAlloc.

◆ willCompleteCodeGenPipeline()

bool TargetPassConfig::willCompleteCodeGenPipeline ( )
static

Member Data Documentation

◆ DisableVerify

bool llvm::TargetPassConfig::DisableVerify = false
protected

Definition at line 129 of file TargetPassConfig.h.

Referenced by addIRPasses(), addISelPrepare(), and setDisableVerify().

◆ EnableSinkAndFold

bool llvm::TargetPassConfig::EnableSinkAndFold = false
protected

Enable sinking of instructions in MachineSink where a computation can be folded into the addressing mode of a memory load/store instruction or replace a copy.

Definition at line 137 of file TargetPassConfig.h.

Referenced by getEnableSinkAndFold(), and setEnableSinkAndFold().

◆ EnableTailMerge

bool llvm::TargetPassConfig::EnableTailMerge = true
protected

Default setting for -enable-tail-merge on this target.

Definition at line 132 of file TargetPassConfig.h.

Referenced by getEnableTailMerge(), and setEnableTailMerge().

◆ ID

char llvm::TargetPassConfig::ID
static

Definition at line 154 of file TargetPassConfig.h.

Referenced by getPassSubstitution(), and isPassSubstitutedOrOverridden().

◆ Impl

PassConfigImpl* llvm::TargetPassConfig::Impl = nullptr
protected

◆ Initialized

bool llvm::TargetPassConfig::Initialized = false
protected

Definition at line 125 of file TargetPassConfig.h.

Referenced by addPass(), setInitialized(), and setOpt().

◆ RequireCodeGenSCCOrder

bool llvm::TargetPassConfig::RequireCodeGenSCCOrder = false
protected

Require processing of functions such that callees are generated before callers.

Definition at line 141 of file TargetPassConfig.h.

Referenced by requiresCodeGenSCCOrder(), and setRequiresCodeGenSCCOrder().

◆ TM

LLVMTargetMachine* llvm::TargetPassConfig::TM
protected

The documentation for this class was generated from the following files: