LLVM  14.0.0git
TargetPassConfig.cpp
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1 //===- TargetPassConfig.cpp - Target independent code generation passes ---===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines interfaces to access the target independent code
10 // generation passes provided by the LLVM backend.
11 //
12 //===---------------------------------------------------------------------===//
13 
15 #include "llvm/ADT/DenseMap.h"
16 #include "llvm/ADT/SmallVector.h"
17 #include "llvm/ADT/StringRef.h"
28 #include "llvm/CodeGen/Passes.h"
33 #include "llvm/IR/Verifier.h"
34 #include "llvm/InitializePasses.h"
35 #include "llvm/MC/MCAsmInfo.h"
37 #include "llvm/Pass.h"
38 #include "llvm/Support/CodeGen.h"
40 #include "llvm/Support/Compiler.h"
41 #include "llvm/Support/Debug.h"
45 #include "llvm/Support/Threading.h"
48 #include "llvm/Transforms/Scalar.h"
49 #include "llvm/Transforms/Utils.h"
51 #include <cassert>
52 #include <string>
53 
54 using namespace llvm;
55 
56 static cl::opt<bool>
57  EnableIPRA("enable-ipra", cl::init(false), cl::Hidden,
58  cl::desc("Enable interprocedural register allocation "
59  "to reduce load/store at procedure calls."));
60 static cl::opt<bool> DisablePostRASched("disable-post-ra", cl::Hidden,
61  cl::desc("Disable Post Regalloc Scheduler"));
62 static cl::opt<bool> DisableBranchFold("disable-branch-fold", cl::Hidden,
63  cl::desc("Disable branch folding"));
64 static cl::opt<bool> DisableTailDuplicate("disable-tail-duplicate", cl::Hidden,
65  cl::desc("Disable tail duplication"));
66 static cl::opt<bool> DisableEarlyTailDup("disable-early-taildup", cl::Hidden,
67  cl::desc("Disable pre-register allocation tail duplication"));
68 static cl::opt<bool> DisableBlockPlacement("disable-block-placement",
69  cl::Hidden, cl::desc("Disable probability-driven block placement"));
70 static cl::opt<bool> EnableBlockPlacementStats("enable-block-placement-stats",
71  cl::Hidden, cl::desc("Collect probability-driven block placement stats"));
72 static cl::opt<bool> DisableSSC("disable-ssc", cl::Hidden,
73  cl::desc("Disable Stack Slot Coloring"));
74 static cl::opt<bool> DisableMachineDCE("disable-machine-dce", cl::Hidden,
75  cl::desc("Disable Machine Dead Code Elimination"));
76 static cl::opt<bool> DisableEarlyIfConversion("disable-early-ifcvt", cl::Hidden,
77  cl::desc("Disable Early If-conversion"));
78 static cl::opt<bool> DisableMachineLICM("disable-machine-licm", cl::Hidden,
79  cl::desc("Disable Machine LICM"));
80 static cl::opt<bool> DisableMachineCSE("disable-machine-cse", cl::Hidden,
81  cl::desc("Disable Machine Common Subexpression Elimination"));
83  "optimize-regalloc", cl::Hidden,
84  cl::desc("Enable optimized register allocation compilation path."));
85 static cl::opt<bool> DisablePostRAMachineLICM("disable-postra-machine-licm",
86  cl::Hidden,
87  cl::desc("Disable Machine LICM"));
88 static cl::opt<bool> DisableMachineSink("disable-machine-sink", cl::Hidden,
89  cl::desc("Disable Machine Sinking"));
90 static cl::opt<bool> DisablePostRAMachineSink("disable-postra-machine-sink",
91  cl::Hidden,
92  cl::desc("Disable PostRA Machine Sinking"));
93 static cl::opt<bool> DisableLSR("disable-lsr", cl::Hidden,
94  cl::desc("Disable Loop Strength Reduction Pass"));
95 static cl::opt<bool> DisableConstantHoisting("disable-constant-hoisting",
96  cl::Hidden, cl::desc("Disable ConstantHoisting"));
97 static cl::opt<bool> DisableCGP("disable-cgp", cl::Hidden,
98  cl::desc("Disable Codegen Prepare"));
99 static cl::opt<bool> DisableCopyProp("disable-copyprop", cl::Hidden,
100  cl::desc("Disable Copy Propagation pass"));
101 static cl::opt<bool> DisablePartialLibcallInlining("disable-partial-libcall-inlining",
102  cl::Hidden, cl::desc("Disable Partial Libcall Inlining"));
104  "enable-implicit-null-checks",
105  cl::desc("Fold null checks into faulting memory operations"),
106  cl::init(false), cl::Hidden);
107 static cl::opt<bool> DisableMergeICmps("disable-mergeicmps",
108  cl::desc("Disable MergeICmps Pass"),
109  cl::init(false), cl::Hidden);
110 static cl::opt<bool> PrintLSR("print-lsr-output", cl::Hidden,
111  cl::desc("Print LLVM IR produced by the loop-reduce pass"));
112 static cl::opt<bool> PrintISelInput("print-isel-input", cl::Hidden,
113  cl::desc("Print LLVM IR input to isel pass"));
114 static cl::opt<bool> PrintGCInfo("print-gc", cl::Hidden,
115  cl::desc("Dump garbage collector data"));
117  VerifyMachineCode("verify-machineinstrs", cl::Hidden,
118  cl::desc("Verify generated machine code"),
121  "debugify-and-strip-all-safe", cl::Hidden,
122  cl::desc(
123  "Debugify MIR before and Strip debug after "
124  "each pass except those known to be unsafe when debug info is present"),
127  "debugify-check-and-strip-all-safe", cl::Hidden,
128  cl::desc(
129  "Debugify MIR before, by checking and stripping the debug info after, "
130  "each pass except those known to be unsafe when debug info is present"),
132 // Enable or disable the MachineOutliner.
134  "enable-machine-outliner", cl::desc("Enable the machine outliner"),
137  "Run on all functions guaranteed to be beneficial"),
139  "Disable all outlining"),
140  // Sentinel value for unspecified option.
142 // Enable or disable FastISel. Both options are needed, because
143 // FastISel is enabled by default with -fast, and we wish to be
144 // able to enable or disable fast-isel independently from -O0.
146 EnableFastISelOption("fast-isel", cl::Hidden,
147  cl::desc("Enable the \"fast\" instruction selector"));
148 
150  "global-isel", cl::Hidden,
151  cl::desc("Enable the \"global\" instruction selector"));
152 
153 // FIXME: remove this after switching to NPM or GlobalISel, whichever gets there
154 // first...
155 static cl::opt<bool>
156  PrintAfterISel("print-after-isel", cl::init(false), cl::Hidden,
157  cl::desc("Print machine instrs after ISel"));
158 
160  "global-isel-abort", cl::Hidden,
161  cl::desc("Enable abort calls when \"global\" instruction selection "
162  "fails to lower/select an instruction"),
163  cl::values(
164  clEnumValN(GlobalISelAbortMode::Disable, "0", "Disable the abort"),
165  clEnumValN(GlobalISelAbortMode::Enable, "1", "Enable the abort"),
167  "Disable the abort but emit a diagnostic on failure")));
168 
169 // An option that disables inserting FS-AFDO discriminators before emit.
170 // This is mainly for debugging and tuning purpose.
171 static cl::opt<bool>
172  FSNoFinalDiscrim("fs-no-final-discrim", cl::init(false), cl::Hidden,
173  cl::desc("Do not insert FS-AFDO discriminators before "
174  "emit."));
175 // Disable MIRProfileLoader before RegAlloc. This is for for debugging and
176 // tuning purpose.
178  "disable-ra-fsprofile-loader", cl::init(true), cl::Hidden,
179  cl::desc("Disable MIRProfileLoader before RegAlloc"));
180 // Disable MIRProfileLoader before BloackPlacement. This is for for debugging
181 // and tuning purpose.
183  "disable-layout-fsprofile-loader", cl::init(true), cl::Hidden,
184  cl::desc("Disable MIRProfileLoader before BlockPlacement"));
185 // Specify FSProfile file name.
187  FSProfileFile("fs-profile-file", cl::init(""), cl::value_desc("filename"),
188  cl::desc("Flow Sensitive profile file name."), cl::Hidden);
189 // Specify Remapping file for FSProfile.
191  "fs-remapping-file", cl::init(""), cl::value_desc("filename"),
192  cl::desc("Flow Sensitive profile remapping file name."), cl::Hidden);
193 
194 // Temporary option to allow experimenting with MachineScheduler as a post-RA
195 // scheduler. Targets can "properly" enable this with
196 // substitutePass(&PostRASchedulerID, &PostMachineSchedulerID).
197 // Targets can return true in targetSchedulesPostRAScheduling() and
198 // insert a PostRA scheduling pass wherever it wants.
200  "misched-postra", cl::Hidden,
201  cl::desc(
202  "Run MachineScheduler post regalloc (independent of preRA sched)"));
203 
204 // Experimental option to run live interval analysis early.
205 static cl::opt<bool> EarlyLiveIntervals("early-live-intervals", cl::Hidden,
206  cl::desc("Run live interval analysis earlier in the pipeline"));
207 
208 // Experimental option to use CFL-AA in codegen
210  "use-cfl-aa-in-codegen", cl::init(CFLAAType::None), cl::Hidden,
211  cl::desc("Enable the new, experimental CFL alias analysis in CodeGen"),
212  cl::values(clEnumValN(CFLAAType::None, "none", "Disable CFL-AA"),
214  "Enable unification-based CFL-AA"),
216  "Enable inclusion-based CFL-AA"),
217  clEnumValN(CFLAAType::Both, "both",
218  "Enable both variants of CFL-AA")));
219 
220 /// Option names for limiting the codegen pipeline.
221 /// Those are used in error reporting and we didn't want
222 /// to duplicate their names all over the place.
223 static const char StartAfterOptName[] = "start-after";
224 static const char StartBeforeOptName[] = "start-before";
225 static const char StopAfterOptName[] = "stop-after";
226 static const char StopBeforeOptName[] = "stop-before";
227 
230  cl::desc("Resume compilation after a specific pass"),
231  cl::value_desc("pass-name"), cl::init(""), cl::Hidden);
232 
235  cl::desc("Resume compilation before a specific pass"),
236  cl::value_desc("pass-name"), cl::init(""), cl::Hidden);
237 
240  cl::desc("Stop compilation after a specific pass"),
241  cl::value_desc("pass-name"), cl::init(""), cl::Hidden);
242 
245  cl::desc("Stop compilation before a specific pass"),
246  cl::value_desc("pass-name"), cl::init(""), cl::Hidden);
247 
248 /// Enable the machine function splitter pass.
250  "enable-split-machine-functions", cl::Hidden,
251  cl::desc("Split out cold blocks from machine functions based on profile "
252  "information."));
253 
254 /// Disable the expand reductions pass for testing.
256  "disable-expand-reductions", cl::init(false), cl::Hidden,
257  cl::desc("Disable the expand reduction intrinsics pass from running"));
258 
259 /// Allow standard passes to be disabled by command line options. This supports
260 /// simple binary flags that either suppress the pass or do nothing.
261 /// i.e. -disable-mypass=false has no effect.
262 /// These should be converted to boolOrDefault in order to use applyOverride.
264  bool Override) {
265  if (Override)
266  return IdentifyingPassPtr();
267  return PassID;
268 }
269 
270 /// Allow standard passes to be disabled by the command line, regardless of who
271 /// is adding the pass.
272 ///
273 /// StandardID is the pass identified in the standard pass pipeline and provided
274 /// to addPass(). It may be a target-specific ID in the case that the target
275 /// directly adds its own pass, but in that case we harmlessly fall through.
276 ///
277 /// TargetID is the pass that the target has configured to override StandardID.
278 ///
279 /// StandardID may be a pseudo ID. In that case TargetID is the name of the real
280 /// pass to run. This allows multiple options to control a single pass depending
281 /// on where in the pipeline that pass is added.
283  IdentifyingPassPtr TargetID) {
284  if (StandardID == &PostRASchedulerID)
285  return applyDisable(TargetID, DisablePostRASched);
286 
287  if (StandardID == &BranchFolderPassID)
288  return applyDisable(TargetID, DisableBranchFold);
289 
290  if (StandardID == &TailDuplicateID)
291  return applyDisable(TargetID, DisableTailDuplicate);
292 
293  if (StandardID == &EarlyTailDuplicateID)
294  return applyDisable(TargetID, DisableEarlyTailDup);
295 
296  if (StandardID == &MachineBlockPlacementID)
297  return applyDisable(TargetID, DisableBlockPlacement);
298 
299  if (StandardID == &StackSlotColoringID)
300  return applyDisable(TargetID, DisableSSC);
301 
302  if (StandardID == &DeadMachineInstructionElimID)
303  return applyDisable(TargetID, DisableMachineDCE);
304 
305  if (StandardID == &EarlyIfConverterID)
306  return applyDisable(TargetID, DisableEarlyIfConversion);
307 
308  if (StandardID == &EarlyMachineLICMID)
309  return applyDisable(TargetID, DisableMachineLICM);
310 
311  if (StandardID == &MachineCSEID)
312  return applyDisable(TargetID, DisableMachineCSE);
313 
314  if (StandardID == &MachineLICMID)
315  return applyDisable(TargetID, DisablePostRAMachineLICM);
316 
317  if (StandardID == &MachineSinkingID)
318  return applyDisable(TargetID, DisableMachineSink);
319 
320  if (StandardID == &PostRAMachineSinkingID)
321  return applyDisable(TargetID, DisablePostRAMachineSink);
322 
323  if (StandardID == &MachineCopyPropagationID)
324  return applyDisable(TargetID, DisableCopyProp);
325 
326  return TargetID;
327 }
328 
329 // Find the FSProfile file name. The internal option takes the precedence
330 // before getting from TargetMachine.
331 static std::string getFSProfileFile(const TargetMachine *TM) {
332  if (!FSProfileFile.empty())
333  return FSProfileFile.getValue();
334  const Optional<PGOOptions> &PGOOpt = TM->getPGOOption();
335  if (PGOOpt == None || PGOOpt->Action != PGOOptions::SampleUse)
336  return std::string();
337  return PGOOpt->ProfileFile;
338 }
339 
340 // Find the Profile remapping file name. The internal option takes the
341 // precedence before getting from TargetMachine.
342 static std::string getFSRemappingFile(const TargetMachine *TM) {
343  if (!FSRemappingFile.empty())
344  return FSRemappingFile.getValue();
345  const Optional<PGOOptions> &PGOOpt = TM->getPGOOption();
346  if (PGOOpt == None || PGOOpt->Action != PGOOptions::SampleUse)
347  return std::string();
348  return PGOOpt->ProfileRemappingFile;
349 }
350 
351 //===---------------------------------------------------------------------===//
352 /// TargetPassConfig
353 //===---------------------------------------------------------------------===//
354 
355 INITIALIZE_PASS(TargetPassConfig, "targetpassconfig",
356  "Target Pass Configuration", false, false)
357 char TargetPassConfig::ID = 0;
358 
359 namespace {
360 
361 struct InsertedPass {
364 
365  InsertedPass(AnalysisID TargetPassID, IdentifyingPassPtr InsertedPassID)
366  : TargetPassID(TargetPassID), InsertedPassID(InsertedPassID) {}
367 
369  assert(InsertedPassID.isValid() && "Illegal Pass ID!");
370  if (InsertedPassID.isInstance())
371  return InsertedPassID.getInstance();
372  Pass *NP = Pass::createPass(InsertedPassID.getID());
373  assert(NP && "Pass ID not registered");
374  return NP;
375  }
376 };
377 
378 } // end anonymous namespace
379 
380 namespace llvm {
381 
383 
385 public:
386  // List of passes explicitly substituted by this target. Normally this is
387  // empty, but it is a convenient way to suppress or replace specific passes
388  // that are part of a standard pass pipeline without overridding the entire
389  // pipeline. This mechanism allows target options to inherit a standard pass's
390  // user interface. For example, a target may disable a standard pass by
391  // default by substituting a pass ID of zero, and the user may still enable
392  // that standard pass with an explicit command line option.
394 
395  /// Store the pairs of <AnalysisID, AnalysisID> of which the second pass
396  /// is inserted after each instance of the first one.
398 };
399 
400 } // end namespace llvm
401 
402 // Out of line virtual method.
404  delete Impl;
405 }
406 
408  if (PassName.empty())
409  return nullptr;
410 
412  const PassInfo *PI = PR.getPassInfo(PassName);
413  if (!PI)
415  Twine("\" pass is not registered."));
416  return PI;
417 }
418 
420  const PassInfo *PI = getPassInfo(PassName);
421  return PI ? PI->getTypeInfo() : nullptr;
422 }
423 
424 static std::pair<StringRef, unsigned>
426  StringRef Name, InstanceNumStr;
427  std::tie(Name, InstanceNumStr) = PassName.split(',');
428 
429  unsigned InstanceNum = 0;
430  if (!InstanceNumStr.empty() && InstanceNumStr.getAsInteger(10, InstanceNum))
431  report_fatal_error("invalid pass instance specifier " + PassName);
432 
433  return std::make_pair(Name, InstanceNum);
434 }
435 
436 void TargetPassConfig::setStartStopPasses() {
437  StringRef StartBeforeName;
438  std::tie(StartBeforeName, StartBeforeInstanceNum) =
440 
441  StringRef StartAfterName;
442  std::tie(StartAfterName, StartAfterInstanceNum) =
444 
445  StringRef StopBeforeName;
446  std::tie(StopBeforeName, StopBeforeInstanceNum)
448 
449  StringRef StopAfterName;
450  std::tie(StopAfterName, StopAfterInstanceNum)
452 
453  StartBefore = getPassIDFromName(StartBeforeName);
454  StartAfter = getPassIDFromName(StartAfterName);
455  StopBefore = getPassIDFromName(StopBeforeName);
456  StopAfter = getPassIDFromName(StopAfterName);
457  if (StartBefore && StartAfter)
459  Twine(StartAfterOptName) + Twine(" specified!"));
460  if (StopBefore && StopAfter)
462  Twine(StopAfterOptName) + Twine(" specified!"));
463  Started = (StartAfter == nullptr) && (StartBefore == nullptr);
464 }
465 
468 
469 #define SET_OPTION(Option) \
470  if (Option.getNumOccurrences()) \
471  Opt.Option = Option;
472 
479 
480 #define SET_BOOLEAN_OPTION(Option) Opt.Option = Option;
481 
496 
497  return Opt;
498 }
499 
501  LLVMTargetMachine &LLVMTM) {
502  StringRef StartBefore;
503  StringRef StartAfter;
504  StringRef StopBefore;
505  StringRef StopAfter;
506 
507  unsigned StartBeforeInstanceNum = 0;
508  unsigned StartAfterInstanceNum = 0;
509  unsigned StopBeforeInstanceNum = 0;
510  unsigned StopAfterInstanceNum = 0;
511 
512  std::tie(StartBefore, StartBeforeInstanceNum) =
514  std::tie(StartAfter, StartAfterInstanceNum) =
516  std::tie(StopBefore, StopBeforeInstanceNum) =
518  std::tie(StopAfter, StopAfterInstanceNum) =
520 
521  if (StartBefore.empty() && StartAfter.empty() && StopBefore.empty() &&
522  StopAfter.empty())
523  return;
524 
525  std::tie(StartBefore, std::ignore) =
526  LLVMTM.getPassNameFromLegacyName(StartBefore);
527  std::tie(StartAfter, std::ignore) =
528  LLVMTM.getPassNameFromLegacyName(StartAfter);
529  std::tie(StopBefore, std::ignore) =
530  LLVMTM.getPassNameFromLegacyName(StopBefore);
531  std::tie(StopAfter, std::ignore) =
532  LLVMTM.getPassNameFromLegacyName(StopAfter);
533  if (!StartBefore.empty() && !StartAfter.empty())
535  Twine(StartAfterOptName) + Twine(" specified!"));
536  if (!StopBefore.empty() && !StopAfter.empty())
538  Twine(StopAfterOptName) + Twine(" specified!"));
539 
541  [=, EnableCurrent = StartBefore.empty() && StartAfter.empty(),
542  EnableNext = Optional<bool>(), StartBeforeCount = 0u,
543  StartAfterCount = 0u, StopBeforeCount = 0u,
544  StopAfterCount = 0u](StringRef P, Any) mutable {
545  bool StartBeforePass = !StartBefore.empty() && P.contains(StartBefore);
546  bool StartAfterPass = !StartAfter.empty() && P.contains(StartAfter);
547  bool StopBeforePass = !StopBefore.empty() && P.contains(StopBefore);
548  bool StopAfterPass = !StopAfter.empty() && P.contains(StopAfter);
549 
550  // Implement -start-after/-stop-after
551  if (EnableNext) {
552  EnableCurrent = *EnableNext;
553  EnableNext.reset();
554  }
555 
556  // Using PIC.registerAfterPassCallback won't work because if this
557  // callback returns false, AfterPassCallback is also skipped.
558  if (StartAfterPass && StartAfterCount++ == StartAfterInstanceNum) {
559  assert(!EnableNext && "Error: assign to EnableNext more than once");
560  EnableNext = true;
561  }
562  if (StopAfterPass && StopAfterCount++ == StopAfterInstanceNum) {
563  assert(!EnableNext && "Error: assign to EnableNext more than once");
564  EnableNext = false;
565  }
566 
567  if (StartBeforePass && StartBeforeCount++ == StartBeforeInstanceNum)
568  EnableCurrent = true;
569  if (StopBeforePass && StopBeforeCount++ == StopBeforeInstanceNum)
570  EnableCurrent = false;
571  return EnableCurrent;
572  });
573 }
574 
576  LLVMTargetMachine &LLVMTM) {
577 
578  // Register a callback for disabling passes.
580 
581 #define DISABLE_PASS(Option, Name) \
582  if (Option && P.contains(#Name)) \
583  return false;
584  DISABLE_PASS(DisableBlockPlacement, MachineBlockPlacementPass)
585  DISABLE_PASS(DisableBranchFold, BranchFolderPass)
586  DISABLE_PASS(DisableCopyProp, MachineCopyPropagationPass)
587  DISABLE_PASS(DisableEarlyIfConversion, EarlyIfConverterPass)
588  DISABLE_PASS(DisableEarlyTailDup, EarlyTailDuplicatePass)
589  DISABLE_PASS(DisableMachineCSE, MachineCSEPass)
590  DISABLE_PASS(DisableMachineDCE, DeadMachineInstructionElimPass)
591  DISABLE_PASS(DisableMachineLICM, EarlyMachineLICMPass)
592  DISABLE_PASS(DisableMachineSink, MachineSinkingPass)
593  DISABLE_PASS(DisablePostRAMachineLICM, MachineLICMPass)
594  DISABLE_PASS(DisablePostRAMachineSink, PostRAMachineSinkingPass)
595  DISABLE_PASS(DisablePostRASched, PostRASchedulerPass)
596  DISABLE_PASS(DisableSSC, StackSlotColoringPass)
597  DISABLE_PASS(DisableTailDuplicate, TailDuplicatePass)
598 
599  return true;
600  });
601 
603 }
604 
605 // Out of line constructor provides default values for pass options and
606 // registers all common codegen passes.
607 TargetPassConfig::TargetPassConfig(LLVMTargetMachine &TM, PassManagerBase &pm)
608  : ImmutablePass(ID), PM(&pm), TM(&TM) {
609  Impl = new PassConfigImpl();
610 
611  // Register all target independent codegen passes to activate their PassIDs,
612  // including this pass itself.
614 
615  // Also register alias analysis passes required by codegen passes.
618 
621  else {
622  // If not explicitly specified, use target default.
624  }
625 
626  if (TM.Options.EnableIPRA)
628 
629  if (EnableGlobalISelAbort.getNumOccurrences())
631 
632  setStartStopPasses();
633 }
634 
636  return TM->getOptLevel();
637 }
638 
639 /// Insert InsertedPassID pass after TargetPassID.
641  IdentifyingPassPtr InsertedPassID) {
642  assert(((!InsertedPassID.isInstance() &&
643  TargetPassID != InsertedPassID.getID()) ||
644  (InsertedPassID.isInstance() &&
645  TargetPassID != InsertedPassID.getInstance()->getPassID())) &&
646  "Insert a pass after itself!");
647  Impl->InsertedPasses.emplace_back(TargetPassID, InsertedPassID);
648 }
649 
650 /// createPassConfig - Create a pass configuration object to be used by
651 /// addPassToEmitX methods for generating a pipeline of CodeGen passes.
652 ///
653 /// Targets may override this to extend TargetPassConfig.
655  return new TargetPassConfig(*this, PM);
656 }
657 
659  : ImmutablePass(ID) {
660  report_fatal_error("Trying to construct TargetPassConfig without a target "
661  "machine. Scheduling a CodeGen pass without a target "
662  "triple set?");
663 }
664 
666  return StopBeforeOpt.empty() && StopAfterOpt.empty();
667 }
668 
670  return !StartBeforeOpt.empty() || !StartAfterOpt.empty() ||
672 }
673 
674 std::string
677  return std::string();
678  std::string Res;
679  static cl::opt<std::string> *PassNames[] = {&StartAfterOpt, &StartBeforeOpt,
681  static const char *OptNames[] = {StartAfterOptName, StartBeforeOptName,
683  bool IsFirst = true;
684  for (int Idx = 0; Idx < 4; ++Idx)
685  if (!PassNames[Idx]->empty()) {
686  if (!IsFirst)
687  Res += Separator;
688  IsFirst = false;
689  Res += OptNames[Idx];
690  }
691  return Res;
692 }
693 
694 // Helper to verify the analysis is really immutable.
695 void TargetPassConfig::setOpt(bool &Opt, bool Val) {
696  assert(!Initialized && "PassConfig is immutable");
697  Opt = Val;
698 }
699 
701  IdentifyingPassPtr TargetID) {
702  Impl->TargetPasses[StandardID] = TargetID;
703 }
704 
707  I = Impl->TargetPasses.find(ID);
708  if (I == Impl->TargetPasses.end())
709  return ID;
710  return I->second;
711 }
712 
715  IdentifyingPassPtr FinalPtr = overridePass(ID, TargetID);
716  return !FinalPtr.isValid() || FinalPtr.isInstance() ||
717  FinalPtr.getID() != ID;
718 }
719 
720 /// Add a pass to the PassManager if that pass is supposed to be run. If the
721 /// Started/Stopped flags indicate either that the compilation should start at
722 /// a later pass or that it should stop after an earlier pass, then do not add
723 /// the pass. Finally, compare the current pass against the StartAfter
724 /// and StopAfter options and change the Started/Stopped flags accordingly.
726  assert(!Initialized && "PassConfig is immutable");
727 
728  // Cache the Pass ID here in case the pass manager finds this pass is
729  // redundant with ones already scheduled / available, and deletes it.
730  // Fundamentally, once we add the pass to the manager, we no longer own it
731  // and shouldn't reference it.
732  AnalysisID PassID = P->getPassID();
733 
734  if (StartBefore == PassID && StartBeforeCount++ == StartBeforeInstanceNum)
735  Started = true;
736  if (StopBefore == PassID && StopBeforeCount++ == StopBeforeInstanceNum)
737  Stopped = true;
738  if (Started && !Stopped) {
739  if (AddingMachinePasses)
741  std::string Banner;
742  // Construct banner message before PM->add() as that may delete the pass.
743  if (AddingMachinePasses)
744  Banner = std::string("After ") + std::string(P->getPassName());
745  PM->add(P);
746  if (AddingMachinePasses)
747  addMachinePostPasses(Banner);
748 
749  // Add the passes after the pass P if there is any.
750  for (const auto &IP : Impl->InsertedPasses) {
751  if (IP.TargetPassID == PassID)
752  addPass(IP.getInsertedPass());
753  }
754  } else {
755  delete P;
756  }
757 
758  if (StopAfter == PassID && StopAfterCount++ == StopAfterInstanceNum)
759  Stopped = true;
760 
761  if (StartAfter == PassID && StartAfterCount++ == StartAfterInstanceNum)
762  Started = true;
763  if (Stopped && !Started)
764  report_fatal_error("Cannot stop compilation after pass that is not run");
765 }
766 
767 /// Add a CodeGen pass at this point in the pipeline after checking for target
768 /// and command line overrides.
769 ///
770 /// addPass cannot return a pointer to the pass instance because is internal the
771 /// PassManager and the instance we create here may already be freed.
773  IdentifyingPassPtr TargetID = getPassSubstitution(PassID);
774  IdentifyingPassPtr FinalPtr = overridePass(PassID, TargetID);
775  if (!FinalPtr.isValid())
776  return nullptr;
777 
778  Pass *P;
779  if (FinalPtr.isInstance())
780  P = FinalPtr.getInstance();
781  else {
782  P = Pass::createPass(FinalPtr.getID());
783  if (!P)
784  llvm_unreachable("Pass ID not registered");
785  }
786  AnalysisID FinalID = P->getPassID();
787  addPass(P); // Ends the lifetime of P.
788 
789  return FinalID;
790 }
791 
792 void TargetPassConfig::printAndVerify(const std::string &Banner) {
793  addPrintPass(Banner);
794  addVerifyPass(Banner);
795 }
796 
797 void TargetPassConfig::addPrintPass(const std::string &Banner) {
798  if (PrintAfterISel)
799  PM->add(createMachineFunctionPrinterPass(dbgs(), Banner));
800 }
801 
802 void TargetPassConfig::addVerifyPass(const std::string &Banner) {
804 #ifdef EXPENSIVE_CHECKS
807 #endif
808  if (Verify)
809  PM->add(createMachineVerifierPass(Banner));
810 }
811 
814 }
815 
817  PM->add(createStripDebugMachineModulePass(/*OnlyDebugified=*/true));
818 }
819 
822 }
823 
824 void TargetPassConfig::addMachinePrePasses(bool AllowDebugify) {
825  if (AllowDebugify && DebugifyIsSafe &&
828  addDebugifyPass();
829 }
830 
831 void TargetPassConfig::addMachinePostPasses(const std::string &Banner) {
832  if (DebugifyIsSafe) {
836  } else if (DebugifyAndStripAll == cl::BOU_TRUE)
838  }
839  addVerifyPass(Banner);
840 }
841 
842 /// Add common target configurable passes that perform LLVM IR to IR transforms
843 /// following machine independent optimization.
845  // Before running any passes, run the verifier to determine if the input
846  // coming from the front-end and/or optimizer is valid.
847  if (!DisableVerify)
849 
850  if (getOptLevel() != CodeGenOpt::None) {
851  switch (UseCFLAA) {
854  break;
855  case CFLAAType::Andersen:
857  break;
858  case CFLAAType::Both:
861  break;
862  default:
863  break;
864  }
865 
866  // Basic AliasAnalysis support.
867  // Add TypeBasedAliasAnalysis before BasicAliasAnalysis so that
868  // BasicAliasAnalysis wins if they disagree. This is intended to help
869  // support "obvious" type-punning idioms.
873 
874  // Run loop strength reduction before anything else.
875  if (!DisableLSR) {
878  if (PrintLSR)
880  "\n\n*** Code after LSR ***\n"));
881  }
882 
883  // The MergeICmpsPass tries to create memcmp calls by grouping sequences of
884  // loads and compares. ExpandMemCmpPass then tries to expand those calls
885  // into optimally-sized loads and compares. The transforms are enabled by a
886  // target lowering hook.
887  if (!DisableMergeICmps)
890  }
891 
892  // Run GC lowering passes for builtin collectors
893  // TODO: add a pass insertion point here
897 
898  // Make sure that no unreachable blocks are instruction selected.
900 
901  // Prepare expensive constants for SelectionDAG.
904 
905  if (getOptLevel() != CodeGenOpt::None)
907 
910 
911  // Expand vector predication intrinsics into standard IR instructions.
912  // This pass has to run before ScalarizeMaskedMemIntrin and ExpandReduction
913  // passes since it emits those kinds of intrinsics.
915 
916  // Add scalarization of target's unsupported masked memory intrinsics pass.
917  // the unsupported intrinsic will be replaced with a chain of basic blocks,
918  // that stores/loads element one-by-one if the appropriate mask bit is set.
920 
921  // Expand reduction intrinsics into shuffle sequences if the target wants to.
922  // Allow disabling it for testing purposes.
925 }
926 
927 /// Turn exception handling constructs into something the code generators can
928 /// handle.
930  const MCAsmInfo *MCAI = TM->getMCAsmInfo();
931  assert(MCAI && "No MCAsmInfo");
932  switch (MCAI->getExceptionHandlingType()) {
934  // SjLj piggy-backs on dwarf for this bit. The cleanups done apply to both
935  // Dwarf EH prepare needs to be run after SjLj prepare. Otherwise,
936  // catch info can get misplaced when a selector ends up more than one block
937  // removed from the parent invoke(s). This could happen when a landing
938  // pad is shared by multiple invokes and is also a target of a normal
939  // edge from elsewhere.
946  break;
948  // We support using both GCC-style and MSVC-style exceptions on Windows, so
949  // add both preparation passes. Each pass will only actually run if it
950  // recognizes the personality function.
953  break;
955  // Wasm EH uses Windows EH instructions, but it does not need to demote PHIs
956  // on catchpads and cleanuppads because it does not outline them into
957  // funclets. Catchswitch blocks are not lowered in SelectionDAG, so we
958  // should remove PHIs there.
959  addPass(createWinEHPass(/*DemoteCatchSwitchPHIOnly=*/false));
961  break;
964 
965  // The lower invoke pass may create unreachable code. Remove it.
967  break;
968  }
969 }
970 
971 /// Add pass to prepare the LLVM IR for code generation. This should be done
972 /// before exception handling preparation passes.
976 }
977 
978 /// Add common passes that perform LLVM IR to IR transforms in preparation for
979 /// instruction selection.
981  addPreISel();
982 
983  // Force codegen to run according to the callgraph.
985  addPass(new DummyCGSCCPass);
986 
987  // Add both the safe stack and the stack protection passes: each of them will
988  // only protect functions that have corresponding attributes.
991 
992  if (PrintISelInput)
994  dbgs(), "\n\n*** Final LLVM Code input to ISel ***\n"));
995 
996  // All passes which modify the LLVM IR are now complete; run the verifier
997  // to ensure that the IR is valid.
998  if (!DisableVerify)
1000 }
1001 
1003  // Enable FastISel with -fast-isel, but allow that to be overridden.
1005 
1006  // Determine an instruction selector.
1007  enum class SelectorType { SelectionDAG, FastISel, GlobalISel };
1008  SelectorType Selector;
1009 
1011  Selector = SelectorType::FastISel;
1012  else if (EnableGlobalISelOption == cl::BOU_TRUE ||
1015  Selector = SelectorType::GlobalISel;
1016  else if (TM->getOptLevel() == CodeGenOpt::None && TM->getO0WantsFastISel())
1017  Selector = SelectorType::FastISel;
1018  else
1019  Selector = SelectorType::SelectionDAG;
1020 
1021  // Set consistently TM->Options.EnableFastISel and EnableGlobalISel.
1022  if (Selector == SelectorType::FastISel) {
1023  TM->setFastISel(true);
1024  TM->setGlobalISel(false);
1025  } else if (Selector == SelectorType::GlobalISel) {
1026  TM->setFastISel(false);
1027  TM->setGlobalISel(true);
1028  }
1029 
1030  // FIXME: Injecting into the DAGISel pipeline seems to cause issues with
1031  // analyses needing to be re-run. This can result in being unable to
1032  // schedule passes (particularly with 'Function Alias Analysis
1033  // Results'). It's not entirely clear why but AFAICT this seems to be
1034  // due to one FunctionPassManager not being able to use analyses from a
1035  // previous one. As we're injecting a ModulePass we break the usual
1036  // pass manager into two. GlobalISel with the fallback path disabled
1037  // and -run-pass seem to be unaffected. The majority of GlobalISel
1038  // testing uses -run-pass so this probably isn't too bad.
1039  SaveAndRestore<bool> SavedDebugifyIsSafe(DebugifyIsSafe);
1040  if (Selector != SelectorType::GlobalISel || !isGlobalISelAbortEnabled())
1041  DebugifyIsSafe = false;
1042 
1043  // Add instruction selector passes.
1044  if (Selector == SelectorType::GlobalISel) {
1045  SaveAndRestore<bool> SavedAddingMachinePasses(AddingMachinePasses, true);
1046  if (addIRTranslator())
1047  return true;
1048 
1050 
1051  if (addLegalizeMachineIR())
1052  return true;
1053 
1054  // Before running the register bank selector, ask the target if it
1055  // wants to run some passes.
1057 
1058  if (addRegBankSelect())
1059  return true;
1060 
1062 
1064  return true;
1065 
1066  // Pass to reset the MachineFunction if the ISel failed.
1069 
1070  // Provide a fallback path when we do not want to abort on
1071  // not-yet-supported input.
1073  return true;
1074 
1075  } else if (addInstSelector())
1076  return true;
1077 
1078  // Expand pseudo-instructions emitted by ISel. Don't run the verifier before
1079  // FinalizeISel.
1081 
1082  // Print the instruction selected machine code...
1083  printAndVerify("After Instruction Selection");
1084 
1085  return false;
1086 }
1087 
1089  if (TM->useEmulatedTLS())
1091 
1094  addIRPasses();
1097  addISelPrepare();
1098 
1099  return addCoreISelPasses();
1100 }
1101 
1102 /// -regalloc=... command line option.
1103 static FunctionPass *useDefaultRegisterAllocator() { return nullptr; }
1107  cl::desc("Register allocator to use"));
1108 
1109 /// Add the complete set of target-independent postISel code generator passes.
1110 ///
1111 /// This can be read as the standard order of major LLVM CodeGen stages. Stages
1112 /// with nontrivial configuration or multiple passes are broken out below in
1113 /// add%Stage routines.
1114 ///
1115 /// Any TargetPassConfig::addXX routine may be overriden by the Target. The
1116 /// addPre/Post methods with empty header implementations allow injecting
1117 /// target-specific fixups just before or after major stages. Additionally,
1118 /// targets have the flexibility to change pass order within a stage by
1119 /// overriding default implementation of add%Stage routines below. Each
1120 /// technique has maintainability tradeoffs because alternate pass orders are
1121 /// not well supported. addPre/Post works better if the target pass is easily
1122 /// tied to a common pass. But if it has subtle dependencies on multiple passes,
1123 /// the target should override the stage instead.
1124 ///
1125 /// TODO: We could use a single addPre/Post(ID) hook to allow pass injection
1126 /// before/after any target-independent pass. But it's currently overkill.
1128  AddingMachinePasses = true;
1129 
1130  // Add passes that optimize machine instructions in SSA form.
1131  if (getOptLevel() != CodeGenOpt::None) {
1133  } else {
1134  // If the target requests it, assign local variables to stack slots relative
1135  // to one another and simplify frame index references where possible.
1137  }
1138 
1139  if (TM->Options.EnableIPRA)
1141 
1142  // Run pre-ra passes.
1143  addPreRegAlloc();
1144 
1145  // Debugifying the register allocator passes seems to provoke some
1146  // non-determinism that affects CodeGen and there doesn't seem to be a point
1147  // where it becomes safe again so stop debugifying here.
1148  DebugifyIsSafe = false;
1149 
1150  // Add a FSDiscriminator pass right before RA, so that we could get
1151  // more precise SampleFDO profile for RA.
1152  if (EnableFSDiscriminator) {
1155  const std::string ProfileFile = getFSProfileFile(TM);
1156  if (!ProfileFile.empty() && !DisableRAFSProfileLoader)
1157  addPass(
1160  }
1161 
1162  // Run register allocation and passes that are tightly coupled with it,
1163  // including phi elimination and scheduling.
1164  if (getOptimizeRegAlloc())
1166  else
1167  addFastRegAlloc();
1168 
1169  // Run post-ra passes.
1170  addPostRegAlloc();
1171 
1173 
1175 
1176  // Insert prolog/epilog code. Eliminate abstract frame index references...
1177  if (getOptLevel() != CodeGenOpt::None) {
1180  }
1181 
1182  // Prolog/Epilog inserter needs a TargetMachine to instantiate. But only
1183  // do so if it hasn't been disabled, substituted, or overridden.
1186 
1187  /// Add passes that optimize machine instructions after register allocation.
1188  if (getOptLevel() != CodeGenOpt::None)
1190 
1191  // Expand pseudo instructions before second scheduling pass.
1193 
1194  // Run pre-sched2 passes.
1195  addPreSched2();
1196 
1199 
1200  // Second pass scheduler.
1201  // Let Target optionally insert this pass by itself at some other
1202  // point.
1203  if (getOptLevel() != CodeGenOpt::None &&
1205  if (MISchedPostRA)
1207  else
1209  }
1210 
1211  // GC
1212  if (addGCPasses()) {
1213  if (PrintGCInfo)
1215  }
1216 
1217  // Basic block placement.
1218  if (getOptLevel() != CodeGenOpt::None)
1220 
1221  // Insert before XRay Instrumentation.
1223 
1226 
1228  // Add FS discriminators here so that all the instruction duplicates
1229  // in different BBs get their own discriminators. With this, we can "sum"
1230  // the SampleFDO counters instead of using MAX. This will improve the
1231  // SampleFDO profile quality.
1234 
1235  addPreEmitPass();
1236 
1237  if (TM->Options.EnableIPRA)
1238  // Collect register usage information and produce a register mask of
1239  // clobbered registers, to be used to optimize call sites.
1241 
1242  // FIXME: Some backends are incompatible with running the verifier after
1243  // addPreEmitPass. Maybe only pass "false" here for those targets?
1245 
1248 
1251  bool RunOnAllFunctions =
1253  bool AddOutliner =
1254  RunOnAllFunctions || TM->Options.SupportsDefaultOutlining;
1255  if (AddOutliner)
1256  addPass(createMachineOutlinerPass(RunOnAllFunctions));
1257  }
1258 
1259  // Machine function splitter uses the basic block sections feature. Both
1260  // cannot be enabled at the same time. Basic block sections takes precedence.
1261  // FIXME: In principle, BasicBlockSection::Labels and splitting can used
1262  // together. Update this check once we have addressed any issues.
1268  }
1269 
1270  // Add passes that directly emit MI after all other MI passes.
1271  addPreEmitPass2();
1272 
1273  AddingMachinePasses = false;
1274 }
1275 
1276 /// Add passes that optimize machine instructions in SSA form.
1278  // Pre-ra tail duplication.
1280 
1281  // Optimize PHIs before DCE: removing dead PHI cycles may make more
1282  // instructions dead.
1284 
1285  // This pass merges large allocas. StackSlotColoring is a different pass
1286  // which merges spill slots.
1288 
1289  // If the target requests it, assign local variables to stack slots relative
1290  // to one another and simplify frame index references where possible.
1292 
1293  // With optimization, dead code should already be eliminated. However
1294  // there is one known exception: lowered code for arguments that are only
1295  // used by tail calls, where the tail calls reuse the incoming stack
1296  // arguments directly (see t11 in test/CodeGen/X86/sibcall.ll).
1298 
1299  // Allow targets to insert passes that improve instruction level parallelism,
1300  // like if-conversion. Such passes will typically need dominator trees and
1301  // loop info, just like LICM and CSE below.
1302  addILPOpts();
1303 
1306 
1308 
1310  // Clean-up the dead code that may have been generated by peephole
1311  // rewriting.
1313 }
1314 
1315 //===---------------------------------------------------------------------===//
1316 /// Register Allocation Pass Configuration
1317 //===---------------------------------------------------------------------===//
1318 
1320  switch (OptimizeRegAlloc) {
1321  case cl::BOU_UNSET: return getOptLevel() != CodeGenOpt::None;
1322  case cl::BOU_TRUE: return true;
1323  case cl::BOU_FALSE: return false;
1324  }
1325  llvm_unreachable("Invalid optimize-regalloc state");
1326 }
1327 
1328 /// A dummy default pass factory indicates whether the register allocator is
1329 /// overridden on the command line.
1331 
1332 static RegisterRegAlloc
1333 defaultRegAlloc("default",
1334  "pick register allocator based on -O option",
1336 
1340 }
1341 
1342 /// Instantiate the default register allocator pass for this target for either
1343 /// the optimized or unoptimized allocation path. This will be added to the pass
1344 /// manager by addFastRegAlloc in the unoptimized case or addOptimizedRegAlloc
1345 /// in the optimized case.
1346 ///
1347 /// A target that uses the standard regalloc pass order for fast or optimized
1348 /// allocation may still override this for per-target regalloc
1349 /// selection. But -regalloc=... always takes precedence.
1351  if (Optimized)
1353  else
1354  return createFastRegisterAllocator();
1355 }
1356 
1357 /// Find and instantiate the register allocation pass requested by this target
1358 /// at the current optimization level. Different register allocators are
1359 /// defined as separate passes because they may require different analysis.
1360 ///
1361 /// This helper ensures that the regalloc= option is always available,
1362 /// even for targets that override the default allocator.
1363 ///
1364 /// FIXME: When MachinePassRegistry register pass IDs instead of function ptrs,
1365 /// this can be folded into addPass.
1367  // Initialize the global default.
1370 
1372  if (Ctor != useDefaultRegisterAllocator)
1373  return Ctor();
1374 
1375  // With no -regalloc= override, ask the target for a regalloc pass.
1376  return createTargetRegisterAllocator(Optimized);
1377 }
1378 
1382  report_fatal_error("Must use fast (default) register allocator for unoptimized regalloc.");
1383 
1384  addPass(createRegAllocPass(false));
1385 
1386  // Allow targets to change the register assignments after
1387  // fast register allocation.
1389  return true;
1390 }
1391 
1393  // Add the selected register allocation pass.
1394  addPass(createRegAllocPass(true));
1395 
1396  // Allow targets to change the register assignments before rewriting.
1397  addPreRewrite();
1398 
1399  // Finally rewrite virtual registers.
1401 
1402  // Regalloc scoring for ML-driven eviction - noop except when learning a new
1403  // eviction policy.
1405  return true;
1406 }
1407 
1408 /// Return true if the default global register allocator is in use and
1409 /// has not be overriden on the command line with '-regalloc=...'
1411  return RegAlloc.getNumOccurrences() == 0;
1412 }
1413 
1414 /// Add the minimum set of target-independent passes that are required for
1415 /// register allocation. No coalescing or scheduling.
1419 
1421 }
1422 
1423 /// Add standard target-independent passes that are tightly coupled with
1424 /// optimized register allocation, including coalescing, machine instruction
1425 /// scheduling, and register allocation itself.
1428 
1430 
1431  // LiveVariables currently requires pure SSA form.
1432  //
1433  // FIXME: Once TwoAddressInstruction pass no longer uses kill flags,
1434  // LiveVariables can be removed completely, and LiveIntervals can be directly
1435  // computed. (We still either need to regenerate kill flags after regalloc, or
1436  // preferably fix the scavenger to not depend on them).
1437  // FIXME: UnreachableMachineBlockElim is a dependant pass of LiveVariables.
1438  // When LiveVariables is removed this has to be removed/moved either.
1439  // Explicit addition of UnreachableMachineBlockElim allows stopping before or
1440  // after it with -stop-before/-stop-after.
1443 
1444  // Edge splitting is smarter with machine loop info.
1447 
1448  // Eventually, we want to run LiveIntervals before PHI elimination.
1449  if (EarlyLiveIntervals)
1451 
1454 
1455  // The machine scheduler may accidentally create disconnected components
1456  // when moving subregister definitions around, avoid this by splitting them to
1457  // separate vregs before. Splitting can also improve reg. allocation quality.
1459 
1460  // PreRA instruction scheduling.
1462 
1464  // Perform stack slot coloring and post-ra machine LICM.
1466 
1467  // Allow targets to expand pseudo instructions depending on the choice of
1468  // registers before MachineCopyPropagation.
1469  addPostRewrite();
1470 
1471  // Copy propagate to forward register uses and try to eliminate COPYs that
1472  // were not coalesced.
1474 
1475  // Run post-ra machine LICM to hoist reloads / remats.
1476  //
1477  // FIXME: can this move into MachineLateOptimization?
1479  }
1480 }
1481 
1482 //===---------------------------------------------------------------------===//
1483 /// Post RegAlloc Pass Configuration
1484 //===---------------------------------------------------------------------===//
1485 
1486 /// Add passes that optimize machine instructions after register allocation.
1488  // Branch folding must be run after regalloc and prolog/epilog insertion.
1490 
1491  // Tail duplication.
1492  // Note that duplicating tail just increases code size and degrades
1493  // performance for targets that require Structured Control Flow.
1494  // In addition it can also make CFG irreducible. Thus we disable it.
1495  if (!TM->requiresStructuredCFG())
1497 
1498  // Copy propagation.
1500 }
1501 
1502 /// Add standard GC passes.
1505  return true;
1506 }
1507 
1508 /// Add standard basic block placement passes.
1510  if (EnableFSDiscriminator) {
1513  const std::string ProfileFile = getFSProfileFile(TM);
1514  if (!ProfileFile.empty() && !DisableLayoutFSProfileLoader)
1515  addPass(
1518  }
1520  // Run a separate pass to collect block placement statistics.
1523  }
1524 }
1525 
1526 //===---------------------------------------------------------------------===//
1527 /// GlobalISel Configuration
1528 //===---------------------------------------------------------------------===//
1531 }
1532 
1535 }
1536 
1538  return true;
1539 }
1540 
1541 std::unique_ptr<CSEConfigBase> TargetPassConfig::getCSEConfig() const {
1542  return std::make_unique<CSEConfigBase>();
1543 }
DisableCGP
static cl::opt< bool > DisableCGP("disable-cgp", cl::Hidden, cl::desc("Disable Codegen Prepare"))
DisableMachineSink
static cl::opt< bool > DisableMachineSink("disable-machine-sink", cl::Hidden, cl::desc("Disable Machine Sinking"))
llvm::TargetMachine::requiresStructuredCFG
bool requiresStructuredCFG() const
Definition: TargetMachine.h:219
llvm::TargetPassConfig::addPostRegAlloc
virtual void addPostRegAlloc()
This method may be implemented by targets that want to run passes after register allocation pass pipe...
Definition: TargetPassConfig.h:417
TypeBasedAliasAnalysis.h
SymbolRewriter.h
llvm::TargetMachine::getOptLevel
CodeGenOpt::Level getOptLevel() const
Returns the optimization level: None, Less, Default, or Aggressive.
Definition: TargetMachine.cpp:188
llvm::TargetPassConfig::ID
static char ID
Definition: TargetPassConfig.h:148
EnableMachineOutliner
static cl::opt< RunOutliner > EnableMachineOutliner("enable-machine-outliner", cl::desc("Enable the machine outliner"), cl::Hidden, cl::ValueOptional, cl::init(RunOutliner::TargetDefault), cl::values(clEnumValN(RunOutliner::AlwaysOutline, "always", "Run on all functions guaranteed to be beneficial"), clEnumValN(RunOutliner::NeverOutline, "never", "Disable all outlining"), clEnumValN(RunOutliner::AlwaysOutline, "", "")))
llvm::createFastRegisterAllocator
FunctionPass * createFastRegisterAllocator()
FastRegisterAllocation Pass - This pass register allocates as fast as possible.
Definition: RegAllocFast.cpp:1565
llvm::createCheckDebugMachineModulePass
ModulePass * createCheckDebugMachineModulePass()
Creates MIR Check Debug pass.
Definition: MachineCheckDebugify.cpp:124
llvm::RegisterRegAllocBase< RegisterRegAlloc >::setDefault
static void setDefault(FunctionPassCtor C)
Definition: RegAllocRegistry.h:54
DebugifyAndStripAll
static cl::opt< cl::boolOrDefault > DebugifyAndStripAll("debugify-and-strip-all-safe", cl::Hidden, cl::desc("Debugify MIR before and Strip debug after " "each pass except those known to be unsafe when debug info is present"), cl::ZeroOrMore)
llvm::PassInfo::getTypeInfo
const void * getTypeInfo() const
getTypeInfo - Return the id object for the pass...
Definition: PassInfo.h:71
llvm::OptimizePHIsID
char & OptimizePHIsID
OptimizePHIs - This pass optimizes machine instruction PHIs to take advantage of opportunities create...
Definition: OptimizePHIs.cpp:69
llvm::createLowerInvokePass
FunctionPass * createLowerInvokePass()
Definition: LowerInvoke.cpp:87
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AllocatorList.h:23
llvm::createGreedyRegisterAllocator
FunctionPass * createGreedyRegisterAllocator()
Greedy register allocation pass - This pass implements a global register allocator for optimized buil...
Definition: RegAllocGreedy.cpp:177
llvm::TargetMachine::useEmulatedTLS
bool useEmulatedTLS() const
Returns true if this target uses emulated TLS.
Definition: TargetMachine.cpp:152
MCTargetOptions.h
llvm::createMachineFunctionSplitterPass
MachineFunctionPass * createMachineFunctionSplitterPass()
createMachineFunctionSplitterPass - This pass splits machine functions using profile information.
llvm::PeepholeOptimizerID
char & PeepholeOptimizerID
PeepholeOptimizer - This pass performs peephole optimizations - like extension and comparison elimina...
Definition: PeepholeOptimizer.cpp:443
DisableConstantHoisting
static cl::opt< bool > DisableConstantHoisting("disable-constant-hoisting", cl::Hidden, cl::desc("Disable ConstantHoisting"))
llvm::IdentifyingPassPtr::getInstance
Pass * getInstance() const
Definition: TargetPassConfig.h:73
llvm::createCFLAndersAAWrapperPass
ImmutablePass * createCFLAndersAAWrapperPass()
llvm::ImmutablePass
ImmutablePass class - This class is used to provide information that does not need to be run.
Definition: Pass.h:269
Scalar.h
llvm::ExceptionHandling::SjLj
@ SjLj
setjmp/longjmp based exceptions
llvm::TargetPassConfig::willCompleteCodeGenPipeline
static bool willCompleteCodeGenPipeline()
Returns true if none of the -stop-before and -stop-after options is set.
Definition: TargetPassConfig.cpp:665
MachinePassRegistry.h
llvm::TargetMachine::targetSchedulesPostRAScheduling
virtual bool targetSchedulesPostRAScheduling() const
True if subtarget inserts the final scheduling pass on its own.
Definition: TargetMachine.h:390
llvm::Pass::getPassID
AnalysisID getPassID() const
getPassID - Return the PassID number that corresponds to this pass.
Definition: Pass.h:110
StringRef.h
P
This currently compiles esp xmm0 movsd esp eax eax esp ret We should use not the dag combiner This is because dagcombine2 needs to be able to see through the X86ISD::Wrapper which DAGCombine can t really do The code for turning x load into a single vector load is target independent and should be moved to the dag combiner The code for turning x load into a vector load can only handle a direct load from a global or a direct load from the stack It should be generalized to handle any load from P
Definition: README-SSE.txt:411
llvm::cl::BOU_FALSE
@ BOU_FALSE
Definition: CommandLine.h:623
Pass.h
llvm::PHIEliminationID
char & PHIEliminationID
PHIElimination - This pass eliminates machine instruction PHI nodes by inserting copy instructions.
Definition: PHIElimination.cpp:130
INITIALIZE_PASS::InsertedPass::TargetPassID
AnalysisID TargetPassID
Definition: TargetPassConfig.cpp:362
CSEConfigBase.h
llvm::IdentifyingPassPtr::isInstance
bool isInstance() const
Definition: TargetPassConfig.h:66
llvm::MCAsmInfo
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:56
llvm::TargetPassConfig::addStripDebugPass
void addStripDebugPass()
Add a pass to remove debug info from the MIR.
Definition: TargetPassConfig.cpp:816
llvm::SmallVector< InsertedPass, 4 >
llvm::TargetMachine::getO0WantsFastISel
bool getO0WantsFastISel()
Definition: TargetMachine.h:247
FSNoFinalDiscrim
static cl::opt< bool > FSNoFinalDiscrim("fs-no-final-discrim", cl::init(false), cl::Hidden, cl::desc("Do not insert FS-AFDO discriminators before " "emit."))
llvm::initializeBasicAAWrapperPassPass
void initializeBasicAAWrapperPassPass(PassRegistry &)
EnableFastISelOption
static cl::opt< cl::boolOrDefault > EnableFastISelOption("fast-isel", cl::Hidden, cl::desc("Enable the \"fast\" instruction selector"))
ErrorHandling.h
llvm::TargetPassConfig::addPreLegalizeMachineIR
virtual void addPreLegalizeMachineIR()
This method may be implemented by targets that want to run passes immediately before legalization.
Definition: TargetPassConfig.h:249
EnableMachineFunctionSplitter
static cl::opt< bool > EnableMachineFunctionSplitter("enable-split-machine-functions", cl::Hidden, cl::desc("Split out cold blocks from machine functions based on profile " "information."))
Enable the machine function splitter pass.
llvm::LLVMTargetMachine::createPassConfig
virtual TargetPassConfig * createPassConfig(PassManagerBase &PM)
Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of ...
Definition: TargetPassConfig.cpp:654
llvm::cl::ValueOptional
@ ValueOptional
Definition: CommandLine.h:136
llvm::ExpandPostRAPseudosID
char & ExpandPostRAPseudosID
ExpandPostRAPseudos - This pass expands pseudo instructions after register allocation.
Definition: ExpandPostRAPseudos.cpp:59
llvm::TargetPassConfig::addPreRewrite
virtual bool addPreRewrite()
addPreRewrite - Add passes to the optimized register allocation pipeline after register allocation is...
Definition: TargetPassConfig.h:403
CGPassBuilderOption.h
llvm::TargetPassConfig::createRegAllocPass
virtual FunctionPass * createRegAllocPass(bool Optimized)
addMachinePasses helper to create the target-selected or overriden regalloc pass.
Definition: TargetPassConfig.cpp:1366
llvm::TargetPassConfig::addGCPasses
virtual bool addGCPasses()
addGCPasses - Add late codegen passes that analyze code for garbage collection.
Definition: TargetPassConfig.cpp:1503
llvm::AnalysisID
const void * AnalysisID
Definition: Pass.h:47
llvm::TargetPassConfig::addPostRewrite
virtual void addPostRewrite()
Add passes to be run immediately after virtual registers are rewritten to physical registers.
Definition: TargetPassConfig.h:413
llvm::RunOutliner::TargetDefault
@ TargetDefault
llvm::TargetPassConfig::addPreSched2
virtual void addPreSched2()
This method may be implemented by targets that want to run passes after prolog-epilog insertion and b...
Definition: TargetPassConfig.h:424
llvm::cl::Hidden
@ Hidden
Definition: CommandLine.h:143
DisableTailDuplicate
static cl::opt< bool > DisableTailDuplicate("disable-tail-duplicate", cl::Hidden, cl::desc("Disable tail duplication"))
llvm::PassConfigImpl::InsertedPasses
SmallVector< InsertedPass, 4 > InsertedPasses
Store the pairs of <AnalysisID, AnalysisID> of which the second pass is inserted after each instance ...
Definition: TargetPassConfig.cpp:397
llvm::EnableFSDiscriminator
cl::opt< bool > EnableFSDiscriminator
Definition: TargetPassConfig.cpp:382
getPassNameAndInstanceNum
static std::pair< StringRef, unsigned > getPassNameAndInstanceNum(StringRef PassName)
Definition: TargetPassConfig.cpp:425
llvm::Pass::createPass
static Pass * createPass(AnalysisID ID)
Definition: Pass.cpp:184
llvm::createPrologEpilogInserterPass
MachineFunctionPass * createPrologEpilogInserterPass()
Definition: PrologEpilogInserter.cpp:150
Discriminator.h
llvm::DenseMapIterator
Definition: DenseMap.h:56
llvm::PassConfigImpl
Definition: TargetPassConfig.cpp:384
DisableBranchFold
static cl::opt< bool > DisableBranchFold("disable-branch-fold", cl::Hidden, cl::desc("Disable branch folding"))
DenseMap.h
llvm::createCFLSteensAAWrapperPass
ImmutablePass * createCFLSteensAAWrapperPass()
MISchedPostRA
static cl::opt< bool > MISchedPostRA("misched-postra", cl::Hidden, cl::desc("Run MachineScheduler post regalloc (independent of preRA sched)"))
llvm::ShadowStackGCLoweringID
char & ShadowStackGCLoweringID
ShadowStackGCLowering - Implements the custom lowering mechanism used by the shadow stack GC.
Definition: ShadowStackGCLowering.cpp:92
FSRemappingFile
static cl::opt< std::string > FSRemappingFile("fs-remapping-file", cl::init(""), cl::value_desc("filename"), cl::desc("Flow Sensitive profile remapping file name."), cl::Hidden)
llvm::LocalStackSlotAllocationID
char & LocalStackSlotAllocationID
LocalStackSlotAllocation - This pass assigns local frame indices to stack slots relative to one anoth...
Definition: LocalStackSlotAllocation.cpp:109
llvm::CFLAAType::Andersen
@ Andersen
llvm::createGCInfoPrinter
FunctionPass * createGCInfoPrinter(raw_ostream &OS)
Creates a pass to print GC metadata.
Definition: GCMetadata.cpp:92
PIC
PassInstrumentationCallbacks PIC
Definition: PassBuilderBindings.cpp:55
llvm::LLVMTargetMachine::isMachineVerifierClean
virtual bool isMachineVerifierClean() const
Returns true if the target is expected to pass all machine verifier checks.
Definition: TargetMachine.h:463
llvm::PassInfo
PassInfo class - An instance of this class exists for every pass known by the system,...
Definition: PassInfo.h:30
llvm::UseCFLAA
static cl::opt<::CFLAAType > UseCFLAA("use-cfl-aa", cl::init(::CFLAAType::None), cl::Hidden, cl::desc("Enable the new, experimental CFL alias analysis"), cl::values(clEnumValN(::CFLAAType::None, "none", "Disable CFL-AA"), clEnumValN(::CFLAAType::Steensgaard, "steens", "Enable unification-based CFL-AA"), clEnumValN(::CFLAAType::Andersen, "anders", "Enable inclusion-based CFL-AA"), clEnumValN(::CFLAAType::Both, "both", "Enable both variants of CFL-AA")))
DisableExpandReductions
static cl::opt< bool > DisableExpandReductions("disable-expand-reductions", cl::init(false), cl::Hidden, cl::desc("Disable the expand reduction intrinsics pass from running"))
Disable the expand reductions pass for testing.
llvm::createLoopStrengthReducePass
Pass * createLoopStrengthReducePass()
Definition: LoopStrengthReduce.cpp:6445
llvm::ExceptionHandling::ARM
@ ARM
ARM EHABI.
llvm::Optional
Definition: APInt.h:33
llvm::RunOutliner::NeverOutline
@ NeverOutline
llvm::IdentifyingPassPtr
Discriminated union of Pass ID types.
Definition: TargetPassConfig.h:53
llvm::CFLAAType::Both
@ Both
getPassInfo
static const PassInfo * getPassInfo(StringRef PassName)
Definition: TargetPassConfig.cpp:407
INITIALIZE_PASS::InsertedPass
Definition: TargetPassConfig.cpp:361
INITIALIZE_PASS::InsertedPass::InsertedPassID
IdentifyingPassPtr InsertedPassID
Definition: TargetPassConfig.cpp:363
llvm::TargetPassConfig::addRegAssignAndRewriteFast
virtual bool addRegAssignAndRewriteFast()
Add core register allocator passes which do the actual register assignment and rewriting.
Definition: TargetPassConfig.cpp:1379
llvm::StackSlotColoringID
char & StackSlotColoringID
StackSlotColoring - This pass performs stack slot coloring.
Definition: StackSlotColoring.cpp:132
llvm::MachineCopyPropagationID
char & MachineCopyPropagationID
MachineCopyPropagation - This pass performs copy propagation on machine instructions.
Definition: MachineCopyPropagation.cpp:308
FSProfileFile
static cl::opt< std::string > FSProfileFile("fs-profile-file", cl::init(""), cl::value_desc("filename"), cl::desc("Flow Sensitive profile file name."), cl::Hidden)
llvm::PGOOptions::SampleUse
@ SampleUse
Definition: PGOOptions.h:23
BasicAliasAnalysis.h
LegacyPassManager.h
llvm::TwoAddressInstructionPassID
char & TwoAddressInstructionPassID
TwoAddressInstruction - This pass reduces two-address instructions to use two operands.
Definition: TwoAddressInstructionPass.cpp:194
llvm::MachineLICMID
char & MachineLICMID
This pass performs loop invariant code motion on machine instructions.
Definition: MachineLICM.cpp:297
llvm::TargetOptions::EnableMachineFunctionSplitter
unsigned EnableMachineFunctionSplitter
Enables the MachineFunctionSplitter pass.
Definition: TargetOptions.h:300
llvm::BasicBlockSection::None
@ None
llvm::createUnreachableBlockEliminationPass
FunctionPass * createUnreachableBlockEliminationPass()
createUnreachableBlockEliminationPass - The LLVM code generator does not work well with unreachable b...
llvm::RegisterRegAlloc
Definition: RegAllocRegistry.h:61
llvm::TargetPassConfig::addPreRegBankSelect
virtual void addPreRegBankSelect()
This method may be implemented by targets that want to run passes immediately before the register ban...
Definition: TargetPassConfig.h:257
llvm::TargetPassConfig::isGISelCSEEnabled
virtual bool isGISelCSEEnabled() const
Check whether continuous CSE should be enabled in GISel passes.
Definition: TargetPassConfig.cpp:1537
llvm::createExpandMemCmpPass
FunctionPass * createExpandMemCmpPass()
Definition: ExpandMemCmp.cpp:917
PrintISelInput
static cl::opt< bool > PrintISelInput("print-isel-input", cl::Hidden, cl::desc("Print LLVM IR input to isel pass"))
llvm::ExceptionHandling::AIX
@ AIX
AIX Exception Handling.
llvm::dbgs
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
DisablePostRAMachineSink
static cl::opt< bool > DisablePostRAMachineSink("disable-postra-machine-sink", cl::Hidden, cl::desc("Disable PostRA Machine Sinking"))
llvm::TargetPassConfig::addInstSelector
virtual bool addInstSelector()
addInstSelector - This method should install an instruction selector pass, which converts from LLVM c...
Definition: TargetPassConfig.h:239
CommandLine.h
llvm::LiveDebugValuesID
char & LiveDebugValuesID
LiveDebugValues pass.
Definition: LiveDebugValues.cpp:93
llvm::createLowerEmuTLSPass
ModulePass * createLowerEmuTLSPass()
LowerEmuTLS - This pass generates __emutls_[vt].xyz variables for all TLS variables for the emulated ...
llvm::createDwarfEHPass
FunctionPass * createDwarfEHPass(CodeGenOpt::Level OptLevel)
createDwarfEHPass - This pass mulches exception handling code into a form adapted to code generation.
Definition: DwarfEHPrepare.cpp:370
llvm::TargetPassConfig::TM
LLVMTargetMachine * TM
Definition: TargetPassConfig.h:122
llvm::registerCodeGenCallback
void registerCodeGenCallback(PassInstrumentationCallbacks &PIC, LLVMTargetMachine &)
Definition: TargetPassConfig.cpp:575
DisablePostRAMachineLICM
static cl::opt< bool > DisablePostRAMachineLICM("disable-postra-machine-licm", cl::Hidden, cl::desc("Disable Machine LICM"))
TargetMachine.h
llvm::PassRegistry::getPassRegistry
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
Definition: PassRegistry.cpp:31
llvm::SelectionDAG
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:216
llvm::TargetPassConfig::printAndVerify
void printAndVerify(const std::string &Banner)
printAndVerify - Add a pass to dump then verify the machine function, if those steps are enabled.
Definition: TargetPassConfig.cpp:792
llvm::PrologEpilogCodeInserterID
char & PrologEpilogCodeInserterID
PrologEpilogCodeInserter - This pass inserts prolog and epilog code, and eliminates abstract frame re...
Definition: PrologEpilogInserter.cpp:139
llvm::FEntryInserterID
char & FEntryInserterID
This pass inserts FEntry calls.
Definition: FEntryInserter.cpp:51
llvm::createConstantHoistingPass
FunctionPass * createConstantHoistingPass()
Definition: ConstantHoisting.cpp:138
EarlyLiveIntervals
static cl::opt< bool > EarlyLiveIntervals("early-live-intervals", cl::Hidden, cl::desc("Run live interval analysis earlier in the pipeline"))
llvm::TargetPassConfig::substitutePass
void substitutePass(AnalysisID StandardID, IdentifyingPassPtr TargetID)
Allow the target to override a specific pass without overriding the pass pipeline.
Definition: TargetPassConfig.cpp:700
llvm::IdentifyingPassPtr::isValid
bool isValid() const
Definition: TargetPassConfig.h:65
llvm::TargetPassConfig::addVerifyPass
void addVerifyPass(const std::string &Banner)
Add a pass to perform basic verification of the machine function if verification is enabled.
Definition: TargetPassConfig.cpp:802
StopBeforeOptName
static const char StopBeforeOptName[]
Definition: TargetPassConfig.cpp:226
llvm::createPreISelIntrinsicLoweringPass
ModulePass * createPreISelIntrinsicLoweringPass()
This pass lowers the @llvm.load.relative and @llvm.objc.
llvm::TargetPassConfig::hasLimitedCodeGenPipeline
static bool hasLimitedCodeGenPipeline()
Returns true if one of the -start-after, -start-before, -stop-after or -stop-before options is set.
Definition: TargetPassConfig.cpp:669
llvm::TargetOptions::EnableIPRA
unsigned EnableIPRA
This flag enables InterProcedural Register Allocation (IPRA).
Definition: TargetOptions.h:291
PrintGCInfo
static cl::opt< bool > PrintGCInfo("print-gc", cl::Hidden, cl::desc("Dump garbage collector data"))
llvm::FuncletLayoutID
char & FuncletLayoutID
This pass lays out funclets contiguously.
Definition: FuncletLayout.cpp:39
llvm::GCMachineCodeAnalysisID
char & GCMachineCodeAnalysisID
GCMachineCodeAnalysis - Target-independent pass to mark safe points in machine code.
Definition: GCRootLowering.cpp:241
llvm::TargetOptions::SupportsDefaultOutlining
unsigned SupportsDefaultOutlining
Set if the target supports default outlining behaviour.
Definition: TargetOptions.h:303
PassInstrumentation.h
INITIALIZE_PASS
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:37
initializeDefaultRegisterAllocatorOnce
static void initializeDefaultRegisterAllocatorOnce()
Definition: TargetPassConfig.cpp:1337
DisablePartialLibcallInlining
static cl::opt< bool > DisablePartialLibcallInlining("disable-partial-libcall-inlining", cl::Hidden, cl::desc("Disable Partial Libcall Inlining"))
llvm::createReplaceWithVeclibLegacyPass
FunctionPass * createReplaceWithVeclibLegacyPass()
Definition: ReplaceWithVeclib.cpp:252
IP
Definition: NVPTXLowerArgs.cpp:166
llvm::createResetMachineFunctionPass
MachineFunctionPass * createResetMachineFunctionPass(bool EmitFallbackDiag, bool AbortOnFailedISel)
This pass resets a MachineFunction when it has the FailedISel property as if it was just created.
DISABLE_PASS
#define DISABLE_PASS(Option, Name)
llvm::RegisterCoalescerID
char & RegisterCoalescerID
RegisterCoalescer - This pass merges live ranges to eliminate copies.
Definition: RegisterCoalescer.cpp:410
useDefaultRegisterAllocator
static FunctionPass * useDefaultRegisterAllocator()
-regalloc=... command line option.
Definition: TargetPassConfig.cpp:1103
llvm::EarlyIfConverterID
char & EarlyIfConverterID
EarlyIfConverter - This pass performs if-conversion on SSA form by inserting cmov instructions.
Definition: EarlyIfConversion.cpp:784
llvm::sampleprof::Pass2
@ Pass2
Definition: Discriminator.h:61
PrintLSR
static cl::opt< bool > PrintLSR("print-lsr-output", cl::Hidden, cl::desc("Print LLVM IR produced by the loop-reduce pass"))
llvm::createMIRProfileLoaderPass
FunctionPass * createMIRProfileLoaderPass(std::string File, std::string RemappingFile, sampleprof::FSDiscriminatorPass P)
Read Flow Sensitive Profile.
Definition: MIRSampleProfile.cpp:67
llvm::TargetPassConfig::isGlobalISelAbortEnabled
bool isGlobalISelAbortEnabled() const
Check whether or not GlobalISel should abort on error.
Definition: TargetPassConfig.cpp:1529
llvm::TargetPassConfig::getPassSubstitution
IdentifyingPassPtr getPassSubstitution(AnalysisID StandardID) const
Return the pass substituted for StandardID by the target.
Definition: TargetPassConfig.cpp:705
llvm::PassRegistry
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
Definition: PassRegistry.h:38
llvm::TargetPassConfig::addMachinePrePasses
void addMachinePrePasses(bool AllowDebugify=true)
Add standard passes before a pass that's about to be added.
Definition: TargetPassConfig.cpp:824
llvm::report_fatal_error
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:143
IRPrintingPasses.h
llvm::ExceptionHandling::Wasm
@ Wasm
WebAssembly Exception Handling.
llvm::cl::Option::getNumOccurrences
int getNumOccurrences() const
Definition: CommandLine.h:402
llvm::createRegAllocScoringPass
FunctionPass * createRegAllocScoringPass()
When learning an eviction policy, extract score(reward) information, otherwise this does nothing.
Definition: MLRegallocEvictAdvisor.cpp:95
StartAfterOpt
static cl::opt< std::string > StartAfterOpt(StringRef(StartAfterOptName), cl::desc("Resume compilation after a specific pass"), cl::value_desc("pass-name"), cl::init(""), cl::Hidden)
getFSProfileFile
static std::string getFSProfileFile(const TargetMachine *TM)
Definition: TargetPassConfig.cpp:331
llvm::StackMapLivenessID
char & StackMapLivenessID
StackMapLiveness - This pass analyses the register live-out set of stackmap/patchpoint intrinsics and...
Definition: StackMapLivenessAnalysis.cpp:86
llvm::CGPassBuilderOption
Definition: CGPassBuilderOption.h:29
llvm::PassInstrumentationCallbacks::registerShouldRunOptionalPassCallback
void registerShouldRunOptionalPassCallback(CallableT C)
Definition: PassInstrumentation.h:96
StopBeforeOpt
static cl::opt< std::string > StopBeforeOpt(StringRef(StopBeforeOptName), cl::desc("Stop compilation before a specific pass"), cl::value_desc("pass-name"), cl::init(""), cl::Hidden)
llvm::TargetPassConfig::addPostFastRegAllocRewrite
virtual bool addPostFastRegAllocRewrite()
addPostFastRegAllocRewrite - Add passes to the optimized register allocation pipeline after fast regi...
Definition: TargetPassConfig.h:409
CFLAndersAliasAnalysis.h
Utils.h
ScopedNoAliasAA.h
llvm::RegisterPassParser
RegisterPassParser class - Handle the addition of new machine passes.
Definition: MachinePassRegistry.h:135
llvm::StringRef::getAsInteger
std::enable_if_t< std::numeric_limits< T >::is_signed, bool > getAsInteger(unsigned Radix, T &Result) const
Parse the current string as an integer of the specified radix.
Definition: StringRef.h:509
llvm::None
const NoneType None
Definition: None.h:23
llvm::TargetPassConfig::setRequiresCodeGenSCCOrder
void setRequiresCodeGenSCCOrder(bool Enable=true)
Definition: TargetPassConfig.h:180
llvm::createMachineOutlinerPass
ModulePass * createMachineOutlinerPass(bool RunOnAllFunctions=true)
This pass performs outlining on machine instructions directly before printing assembly.
Definition: MachineOutliner.cpp:443
llvm::initializeCodeGen
void initializeCodeGen(PassRegistry &)
Initialize all passes linked into the CodeGen library.
Definition: CodeGen.cpp:21
DisableMergeICmps
static cl::opt< bool > DisableMergeICmps("disable-mergeicmps", cl::desc("Disable MergeICmps Pass"), cl::init(false), cl::Hidden)
llvm::createMachineFunctionPrinterPass
MachineFunctionPass * createMachineFunctionPrinterPass(raw_ostream &OS, const std::string &Banner="")
MachineFunctionPrinter pass - This pass prints out the machine function to the given stream as a debu...
llvm::legacy::PassManagerBase::add
virtual void add(Pass *P)=0
Add a pass to the queue of passes to run.
InitializeDefaultRegisterAllocatorFlag
static llvm::once_flag InitializeDefaultRegisterAllocatorFlag
A dummy default pass factory indicates whether the register allocator is overridden on the command li...
Definition: TargetPassConfig.cpp:1330
llvm::createCanonicalizeFreezeInLoopsPass
Pass * createCanonicalizeFreezeInLoopsPass()
Definition: CanonicalizeFreezeInLoops.cpp:245
StartAfterOptName
static const char StartAfterOptName[]
Option names for limiting the codegen pipeline.
Definition: TargetPassConfig.cpp:223
llvm::EarlyTailDuplicateID
char & EarlyTailDuplicateID
Duplicate blocks with unconditional branches into tails of their predecessors.
Definition: TailDuplication.cpp:77
llvm::createTargetTransformInfoWrapperPass
ImmutablePass * createTargetTransformInfoWrapperPass(TargetIRAnalysis TIRA)
Create an analysis pass wrapper around a TTI object.
Definition: TargetTransformInfo.cpp:1204
llvm::cl::ZeroOrMore
@ ZeroOrMore
Definition: CommandLine.h:120
getPassIDFromName
static AnalysisID getPassIDFromName(StringRef PassName)
Definition: TargetPassConfig.cpp:419
Passes.h
llvm::VirtRegRewriterID
char & VirtRegRewriterID
VirtRegRewriter pass.
Definition: VirtRegMap.cpp:227
llvm::TargetPassConfig
Target-Independent Code Generator Pass Configuration Options.
Definition: TargetPassConfig.h:84
StartBeforeOpt
static cl::opt< std::string > StartBeforeOpt(StringRef(StartBeforeOptName), cl::desc("Resume compilation before a specific pass"), cl::value_desc("pass-name"), cl::init(""), cl::Hidden)
llvm::sampleprof::PassLast
@ PassLast
Definition: Discriminator.h:64
StartBeforeOptName
static const char StartBeforeOptName[]
Definition: TargetPassConfig.cpp:224
llvm::TargetPassConfig::usingDefaultRegAlloc
bool usingDefaultRegAlloc() const
Return true if the default global register allocator is in use and has not be overriden on the comman...
Definition: TargetPassConfig.cpp:1410
llvm::MachineLoopInfoID
char & MachineLoopInfoID
MachineLoopInfo - This pass is a loop analysis pass.
Definition: MachineLoopInfo.cpp:44
llvm::cl::opt< bool >
llvm::TargetOptions::EnableGlobalISel
unsigned EnableGlobalISel
EnableGlobalISel - This flag enables global instruction selection.
Definition: TargetOptions.h:233
llvm::TargetPassConfig::DisableVerify
bool DisableVerify
Definition: TargetPassConfig.h:128
llvm::TargetPassConfig::addMachinePasses
virtual void addMachinePasses()
Add the complete, standard set of LLVM CodeGen passes.
Definition: TargetPassConfig.cpp:1127
llvm::TargetPassConfig::isPassSubstitutedOrOverridden
bool isPassSubstitutedOrOverridden(AnalysisID ID) const
Return true if the pass has been substituted by the target or overridden on the command line.
Definition: TargetPassConfig.cpp:713
llvm::GCLoweringID
char & GCLoweringID
GCLowering Pass - Used by gc.root to perform its default lowering operations.
Definition: GCRootLowering.cpp:88
llvm::CFLAAType::None
@ None
registerPartialPipelineCallback
static void registerPartialPipelineCallback(PassInstrumentationCallbacks &PIC, LLVMTargetMachine &LLVMTM)
Definition: TargetPassConfig.cpp:500
Verify
ppc ctr loops PowerPC CTR Loops Verify
Definition: PPCCTRLoops.cpp:77
Threading.h
llvm::TargetPassConfig::getLimitedCodeGenPipelineReason
static std::string getLimitedCodeGenPipelineReason(const char *Separator="/")
If hasLimitedCodeGenPipeline is true, this method returns a string with the name of the options,...
Definition: TargetPassConfig.cpp:675
llvm::TargetPassConfig::addRegBankSelect
virtual bool addRegBankSelect()
This method should install a register bank selector pass, which assigns register banks to virtual reg...
Definition: TargetPassConfig.h:262
llvm::TargetMachine::setO0WantsFastISel
void setO0WantsFastISel(bool Enable)
Definition: TargetMachine.h:248
llvm::cl::values
ValuesClass values(OptsTy... Options)
Helper to build a ValuesClass by forwarding a variable number of arguments as an initializer list to ...
Definition: CommandLine.h:697
llvm::cl::BOU_UNSET
@ BOU_UNSET
Definition: CommandLine.h:623
llvm::StackColoringID
char & StackColoringID
StackSlotColoring - This pass performs stack coloring and merging.
Definition: StackColoring.cpp:551
llvm::TargetMachine::getTargetIRAnalysis
TargetIRAnalysis getTargetIRAnalysis()
Get a TargetIRAnalysis appropriate for the target.
Definition: TargetMachine.cpp:220
llvm::StringRef::empty
constexpr LLVM_NODISCARD bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:152
DisableEarlyTailDup
static cl::opt< bool > DisableEarlyTailDup("disable-early-taildup", cl::Hidden, cl::desc("Disable pre-register allocation tail duplication"))
SaveAndRestore.h
EnableGlobalISelOption
static cl::opt< cl::boolOrDefault > EnableGlobalISelOption("global-isel", cl::Hidden, cl::desc("Enable the \"global\" instruction selector"))
defaultRegAlloc
static RegisterRegAlloc defaultRegAlloc("default", "pick register allocator based on -O option", useDefaultRegisterAllocator)
DisableLayoutFSProfileLoader
static cl::opt< bool > DisableLayoutFSProfileLoader("disable-layout-fsprofile-loader", cl::init(true), cl::Hidden, cl::desc("Disable MIRProfileLoader before BlockPlacement"))
llvm::RegisterRegAllocBase< RegisterRegAlloc >::FunctionPassCtor
FunctionPass *(*)() FunctionPassCtor
Definition: RegAllocRegistry.h:32
llvm::MachineSinkingID
char & MachineSinkingID
MachineSinking - This pass performs sinking on machine instructions.
Definition: MachineSink.cpp:256
llvm::DetectDeadLanesID
char & DetectDeadLanesID
This pass adds dead/undef flags after analyzing subregister lanes.
Definition: DetectDeadLanes.cpp:128
llvm::TargetPassConfig::addPreGlobalInstructionSelect
virtual void addPreGlobalInstructionSelect()
This method may be implemented by targets that want to run passes immediately before the (global) ins...
Definition: TargetPassConfig.h:266
applyDisable
static IdentifyingPassPtr applyDisable(IdentifyingPassPtr PassID, bool Override)
Allow standard passes to be disabled by command line options.
Definition: TargetPassConfig.cpp:263
llvm::DenseMap
Definition: DenseMap.h:714
llvm::PGOOptions::ProfileFile
std::string ProfileFile
Definition: PGOOptions.h:55
INITIALIZE_PASS::InsertedPass::getInsertedPass
Pass * getInsertedPass() const
Definition: TargetPassConfig.cpp:368
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::TargetPassConfig::addIRPasses
virtual void addIRPasses()
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
Definition: TargetPassConfig.cpp:844
EnableBlockPlacementStats
static cl::opt< bool > EnableBlockPlacementStats("enable-block-placement-stats", cl::Hidden, cl::desc("Collect probability-driven block placement stats"))
llvm::cl::init
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:441
llvm::TargetPassConfig::addOptimizedRegAlloc
virtual void addOptimizedRegAlloc()
addOptimizedRegAlloc - Add passes related to register allocation.
Definition: TargetPassConfig.cpp:1426
llvm::TargetPassConfig::addRegAssignAndRewriteOptimized
virtual bool addRegAssignAndRewriteOptimized()
Definition: TargetPassConfig.cpp:1392
llvm::createPartiallyInlineLibCallsPass
FunctionPass * createPartiallyInlineLibCallsPass()
Definition: PartiallyInlineLibCalls.cpp:212
llvm::createRegUsageInfoPropPass
FunctionPass * createRegUsageInfoPropPass()
Return a MachineFunction pass that identifies call sites and propagates register usage information of...
Definition: RegUsageInfoPropagate.cpp:153
llvm::createMachineVerifierPass
FunctionPass * createMachineVerifierPass(const std::string &Banner)
createMachineVerifierPass - This pass verifies cenerated machine code instructions for correctness.
llvm::LiveVariablesID
char & LiveVariablesID
LiveVariables pass - This pass computes the set of blocks in which each variable is life and sets mac...
Definition: LiveVariables.cpp:45
overridePass
static IdentifyingPassPtr overridePass(AnalysisID StandardID, IdentifyingPassPtr TargetID)
Allow standard passes to be disabled by the command line, regardless of who is adding the pass.
Definition: TargetPassConfig.cpp:282
TargetPassConfig.h
MachineFunctionPass.h
llvm::TargetPassConfig::addPreEmitPass2
virtual void addPreEmitPass2()
Targets may add passes immediately before machine code is emitted in this callback.
Definition: TargetPassConfig.h:443
llvm::MachineCSEID
char & MachineCSEID
MachineCSE - This pass performs global CSE on machine instructions.
Definition: MachineCSE.cpp:153
llvm::FinalizeISelID
char & FinalizeISelID
This pass expands pseudo-instructions, reserves registers and adjusts machine frame information.
Definition: FinalizeISel.cpp:44
llvm::TargetMachine::Options
TargetOptions Options
Definition: TargetMachine.h:121
llvm::TargetPassConfig::addCodeGenPrepare
virtual void addCodeGenPrepare()
Add pass to prepare the LLVM IR for code generation.
Definition: TargetPassConfig.cpp:973
llvm::TargetPassConfig::getOptimizeRegAlloc
bool getOptimizeRegAlloc() const
Return true if the optimized regalloc pipeline is enabled.
Definition: TargetPassConfig.cpp:1319
llvm::createExpandReductionsPass
FunctionPass * createExpandReductionsPass()
This pass expands the experimental reduction intrinsics into sequences of shuffles.
Definition: ExpandReductions.cpp:202
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::TargetMachine
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:80
llvm::DummyCGSCCPass
This pass is required by interprocedural register allocation.
Definition: CallGraphSCCPass.h:122
DisableEarlyIfConversion
static cl::opt< bool > DisableEarlyIfConversion("disable-early-ifcvt", cl::Hidden, cl::desc("Disable Early If-conversion"))
llvm::TargetPassConfig::addCheckDebugPass
void addCheckDebugPass()
Add a pass to check synthesized debug info for MIR.
Definition: TargetPassConfig.cpp:820
llvm::createExpandVectorPredicationPass
FunctionPass * createExpandVectorPredicationPass()
This pass expands the vector predication intrinsics into unpredicated instructions with selects or ju...
Definition: ExpandVectorPredication.cpp:594
EnableGlobalISelAbort
static cl::opt< GlobalISelAbortMode > EnableGlobalISelAbort("global-isel-abort", cl::Hidden, cl::desc("Enable abort calls when \"global\" instruction selection " "fails to lower/select an instruction"), cl::values(clEnumValN(GlobalISelAbortMode::Disable, "0", "Disable the abort"), clEnumValN(GlobalISelAbortMode::Enable, "1", "Enable the abort"), clEnumValN(GlobalISelAbortMode::DisableWithDiag, "2", "Disable the abort but emit a diagnostic on failure")))
getFSRemappingFile
static std::string getFSRemappingFile(const TargetMachine *TM)
Definition: TargetPassConfig.cpp:342
llvm::createTypeBasedAAWrapperPass
ImmutablePass * createTypeBasedAAWrapperPass()
llvm::ProcessImplicitDefsID
char & ProcessImplicitDefsID
ProcessImpicitDefs pass - This pass removes IMPLICIT_DEFs.
Definition: ProcessImplicitDefs.cpp:52
llvm::FastISel
This is a fast-path instruction selection class that generates poor code and doesn't support illegal ...
Definition: FastISel.h:65
llvm::RegisterRegAllocBase< RegisterRegAlloc >::getDefault
static FunctionPassCtor getDefault()
Definition: RegAllocRegistry.h:52
llvm::TargetPassConfig::addIRTranslator
virtual bool addIRTranslator()
This method should install an IR translator pass, which converts from LLVM code to machine instructio...
Definition: TargetPassConfig.h:245
llvm::PatchableFunctionID
char & PatchableFunctionID
This pass implements the "patchable-function" attribute.
Definition: PatchableFunction.cpp:96
llvm::MachineBlockPlacementStatsID
char & MachineBlockPlacementStatsID
MachineBlockPlacementStats - This pass collects statistics about the basic block placement using bran...
Definition: MachineBlockPlacement.cpp:3649
llvm::CFLAAType::Steensgaard
@ Steensgaard
llvm::CodeGenOpt::None
@ None
Definition: CodeGen.h:53
llvm::TargetPassConfig::addISelPasses
bool addISelPasses()
High level function that adds all passes necessary to go from llvm IR representation to the MI repres...
Definition: TargetPassConfig.cpp:1088
llvm::createSjLjEHPreparePass
FunctionPass * createSjLjEHPreparePass(const TargetMachine *TM)
createSjLjEHPreparePass - This pass adapts exception handling code to use the GCC-style builtin setjm...
llvm::TargetMachine::getMCAsmInfo
const MCAsmInfo * getMCAsmInfo() const
Return target specific asm information.
Definition: TargetMachine.h:208
llvm::TargetPassConfig::addPass
AnalysisID addPass(AnalysisID PassID)
Utilities for targets to add passes to the pass manager.
Definition: TargetPassConfig.cpp:772
llvm::initializeAAResultsWrapperPassPass
void initializeAAResultsWrapperPassPass(PassRegistry &)
MCAsmInfo.h
llvm::XRayInstrumentationID
char & XRayInstrumentationID
This pass inserts the XRay instrumentation sleds if they are supported by the target platform.
Definition: XRayInstrumentation.cpp:264
llvm::UnreachableMachineBlockElimID
char & UnreachableMachineBlockElimID
UnreachableMachineBlockElimination - This pass removes unreachable machine basic blocks.
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:57
SET_OPTION
#define SET_OPTION(Option)
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:134
if
if(llvm_vc STREQUAL "") set(fake_version_inc "$
Definition: CMakeLists.txt:14
llvm::createStripDebugMachineModulePass
ModulePass * createStripDebugMachineModulePass(bool OnlyDebugified)
Creates MIR Strip Debug pass.
Definition: MachineStripDebug.cpp:106
llvm::BranchFolderPassID
char & BranchFolderPassID
BranchFolding - This pass performs machine code CFG based optimizations to delete branches to branche...
Definition: BranchFolding.cpp:114
Compiler.h
llvm::MachineBlockPlacementID
char & MachineBlockPlacementID
MachineBlockPlacement - This pass places basic blocks based on branch probabilities.
Definition: MachineBlockPlacement.cpp:611
clEnumValN
#define clEnumValN(ENUMVAL, FLAGNAME, DESC)
Definition: CommandLine.h:672
llvm::ShrinkWrapID
char & ShrinkWrapID
ShrinkWrap pass. Look for the best place to insert save and restore.
Definition: ShrinkWrap.cpp:250
llvm::createWinEHPass
FunctionPass * createWinEHPass(bool DemoteCatchSwitchPHIOnly=false)
createWinEHPass - Prepares personality functions used by MSVC on Windows, in addition to the Itanium ...
llvm::RunOutliner::AlwaysOutline
@ AlwaysOutline
llvm::TargetPassConfig::reportDiagnosticWhenGlobalISelFallback
virtual bool reportDiagnosticWhenGlobalISelFallback() const
Check whether or not a diagnostic should be emitted when GlobalISel uses the fallback path.
Definition: TargetPassConfig.cpp:1533
llvm::SaveAndRestore
A utility class that uses RAII to save and restore the value of a variable.
Definition: SaveAndRestore.h:21
llvm::TargetPassConfig::addDebugifyPass
void addDebugifyPass()
Add a pass to add synthesized debug info to the MIR.
Definition: TargetPassConfig.cpp:812
llvm::createDebugifyMachineModulePass
ModulePass * createDebugifyMachineModulePass()
Creates MIR Debugify pass.
Definition: MachineDebugify.cpp:200
DisableLSR
static cl::opt< bool > DisableLSR("disable-lsr", cl::Hidden, cl::desc("Disable Loop Strength Reduction Pass"))
llvm::GlobalISelAbortMode::DisableWithDiag
@ DisableWithDiag
llvm::once_flag
std::once_flag once_flag
Definition: Threading.h:60
OptimizeRegAlloc
static cl::opt< cl::boolOrDefault > OptimizeRegAlloc("optimize-regalloc", cl::Hidden, cl::desc("Enable optimized register allocation compilation path."))
llvm::getCGPassBuilderOption
CGPassBuilderOption getCGPassBuilderOption()
Definition: TargetPassConfig.cpp:466
adjust::pm
static void pm(uint64_t &Value)
Adjusts a program memory address.
Definition: AVRAsmBackend.cpp:192
llvm::CodeGenOpt::Level
Level
Definition: CodeGen.h:52
CallGraphSCCPass.h
llvm::createVerifierPass
FunctionPass * createVerifierPass(bool FatalErrors=true)
Definition: Verifier.cpp:6341
llvm::TargetMachine::setFastISel
void setFastISel(bool Enable)
Definition: TargetMachine.h:246
llvm::TargetPassConfig::addPreRegAlloc
virtual void addPreRegAlloc()
This method may be implemented by targets that want to run passes immediately before register allocat...
Definition: TargetPassConfig.h:377
LLVM_FALLTHROUGH
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:290
INITIALIZE_PASS::InsertedPass::InsertedPass
InsertedPass(AnalysisID TargetPassID, IdentifyingPassPtr InsertedPassID)
Definition: TargetPassConfig.cpp:365
llvm::PGOOptions::Action
PGOAction Action
Definition: PGOOptions.h:58
llvm::RenameIndependentSubregsID
char & RenameIndependentSubregsID
This pass detects subregister lanes in a virtual register that are used independently of other lanes ...
Definition: RenameIndependentSubregs.cpp:113
DisableMachineCSE
static cl::opt< bool > DisableMachineCSE("disable-machine-cse", cl::Hidden, cl::desc("Disable Machine Common Subexpression Elimination"))
llvm::FixupStatepointCallerSavedID
char & FixupStatepointCallerSavedID
The pass fixups statepoint machine instruction to replace usage of caller saved registers with stack ...
Definition: FixupStatepointCallerSaved.cpp:87
llvm::PassConfigImpl::TargetPasses
DenseMap< AnalysisID, IdentifyingPassPtr > TargetPasses
Definition: TargetPassConfig.cpp:393
llvm::TargetPassConfig::getCSEConfig
virtual std::unique_ptr< CSEConfigBase > getCSEConfig() const
Returns the CSEConfig object to use for the current optimization level.
Definition: TargetPassConfig.cpp:1541
llvm::createBasicAAWrapperPass
FunctionPass * createBasicAAWrapperPass()
Definition: BasicAliasAnalysis.cpp:1888
llvm::createRegUsageInfoCollector
FunctionPass * createRegUsageInfoCollector()
This pass is executed POST-RA to collect which physical registers are preserved by given machine func...
Definition: RegUsageInfoCollector.cpp:76
llvm::createMIRAddFSDiscriminatorsPass
FunctionPass * createMIRAddFSDiscriminatorsPass(sampleprof::FSDiscriminatorPass P)
Add Flow Sensitive Discriminators.
llvm::Twine
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:83
llvm::Any
Definition: Any.h:26
Verifier.h
llvm::empty
constexpr bool empty(const T &RangeOrContainer)
Test whether RangeOrContainer is empty. Similar to C++17 std::empty.
Definition: STLExtras.h:309
llvm::TargetPassConfig::requiresCodeGenSCCOrder
bool requiresCodeGenSCCOrder() const
Definition: TargetPassConfig.h:179
llvm::GraphProgram::Name
Name
Definition: GraphWriter.h:52
llvm::call_once
void call_once(once_flag &flag, Function &&F, Args &&... ArgList)
Execute the function specified as a parameter once.
Definition: Threading.h:90
llvm::TargetPassConfig::Impl
PassConfigImpl * Impl
Definition: TargetPassConfig.h:123
llvm::TargetPassConfig::addMachineSSAOptimization
virtual void addMachineSSAOptimization()
addMachineSSAOptimization - Add standard passes that optimize machine instructions in SSA form.
Definition: TargetPassConfig.cpp:1277
llvm::createBasicBlockSectionsPass
MachineFunctionPass * createBasicBlockSectionsPass(const MemoryBuffer *Buf)
createBasicBlockSections Pass - This pass assigns sections to machine basic blocks and is enabled wit...
Definition: BasicBlockSections.cpp:531
llvm::createScalarizeMaskedMemIntrinLegacyPass
FunctionPass * createScalarizeMaskedMemIntrinLegacyPass()
Definition: ScalarizeMaskedMemIntrin.cpp:89
llvm::TargetOptions::GlobalISelAbort
GlobalISelAbortMode GlobalISelAbort
EnableGlobalISelAbort - Control abort behaviour when global instruction selection fails to lower/sele...
Definition: TargetOptions.h:237
llvm::createScopedNoAliasAAWrapperPass
ImmutablePass * createScopedNoAliasAAWrapperPass()
llvm::createWasmEHPass
FunctionPass * createWasmEHPass()
createWasmEHPass - This pass adapts exception handling code to use WebAssembly's exception handling s...
Definition: WasmEHPrepare.cpp:134
VerifyMachineCode
static cl::opt< cl::boolOrDefault > VerifyMachineCode("verify-machineinstrs", cl::Hidden, cl::desc("Verify generated machine code"), cl::ZeroOrMore)
llvm::TargetPassConfig::addLegalizeMachineIR
virtual bool addLegalizeMachineIR()
This method should install a legalize pass, which converts the instruction sequence into one that can...
Definition: TargetPassConfig.h:253
DisableRAFSProfileLoader
static cl::opt< bool > DisableRAFSProfileLoader("disable-ra-fsprofile-loader", cl::init(true), cl::Hidden, cl::desc("Disable MIRProfileLoader before RegAlloc"))
llvm::ExceptionHandling::WinEH
@ WinEH
Windows Exception Handling.
llvm::TargetPassConfig::addMachinePostPasses
void addMachinePostPasses(const std::string &Banner)
Add standard passes after a pass that has just been added.
Definition: TargetPassConfig.cpp:831
llvm::TailDuplicateID
char & TailDuplicateID
TailDuplicate - Duplicate blocks with unconditional branches into tails of their predecessors.
Definition: TailDuplication.cpp:76
llvm::LLVMTargetMachine
This class describes a target machine that is implemented with the LLVM target-independent code gener...
Definition: TargetMachine.h:406
llvm::IdentifyingPassPtr::getID
AnalysisID getID() const
Definition: TargetPassConfig.h:68
llvm::cl::value_desc
Definition: CommandLine.h:422
llvm::TargetMachine::setGlobalISel
void setGlobalISel(bool Enable)
Definition: TargetMachine.h:249
llvm::DeadMachineInstructionElimID
char & DeadMachineInstructionElimID
DeadMachineInstructionElim - This pass removes dead machine instructions.
Definition: DeadMachineInstructionElim.cpp:57
llvm::TargetOptions::EnableMachineOutliner
unsigned EnableMachineOutliner
Enables the MachineOutliner pass.
Definition: TargetOptions.h:297
DisableSSC
static cl::opt< bool > DisableSSC("disable-ssc", cl::Hidden, cl::desc("Disable Stack Slot Coloring"))
llvm::TargetPassConfig::addBlockPlacement
virtual void addBlockPlacement()
Add standard basic block placement passes.
Definition: TargetPassConfig.cpp:1509
llvm::ExceptionHandling::None
@ None
No exception support.
llvm::TargetMachine::getBBSectionsFuncListBuf
const MemoryBuffer * getBBSectionsFuncListBuf() const
Get the list of functions and basic block ids that need unique sections.
Definition: TargetMachine.h:303
llvm::MachineSchedulerID
char & MachineSchedulerID
MachineScheduler - This pass schedules machine instructions.
Definition: MachineScheduler.cpp:214
CodeGen.h
llvm::sampleprof::Pass1
@ Pass1
Definition: Discriminator.h:60
llvm::MCAsmInfo::getExceptionHandlingType
ExceptionHandling getExceptionHandlingType() const
Definition: MCAsmInfo.h:762
DisableMachineDCE
static cl::opt< bool > DisableMachineDCE("disable-machine-dce", cl::Hidden, cl::desc("Disable Machine Dead Code Elimination"))
llvm::TargetPassConfig::createTargetRegisterAllocator
virtual FunctionPass * createTargetRegisterAllocator(bool Optimized)
createTargetRegisterAllocator - Create the register allocator pass for this target at the current opt...
Definition: TargetPassConfig.cpp:1350
llvm::cl::BOU_TRUE
@ BOU_TRUE
Definition: CommandLine.h:623
llvm::GlobalISelAbortMode::Enable
@ Enable
llvm::Pass
Pass interface - Implemented by all 'passes'.
Definition: Pass.h:91
llvm::TargetPassConfig::addISelPrepare
virtual void addISelPrepare()
Add common passes that perform LLVM IR to IR transforms in preparation for instruction selection.
Definition: TargetPassConfig.cpp:980
llvm::TargetPassConfig::addGlobalInstructionSelect
virtual bool addGlobalInstructionSelect()
This method should install a (global) instruction selector pass, which converts possibly generic inst...
Definition: TargetPassConfig.h:272
llvm::PostRASchedulerID
char & PostRASchedulerID
PostRAScheduler - This pass performs post register allocation scheduling.
Definition: PostRASchedulerList.cpp:199
SmallVector.h
llvm::createLowerConstantIntrinsicsPass
FunctionPass * createLowerConstantIntrinsicsPass()
Definition: LowerConstantIntrinsics.cpp:203
llvm::PassInstrumentationCallbacks
This class manages callbacks registration, as well as provides a way for PassInstrumentation to pass ...
Definition: PassInstrumentation.h:66
llvm::LLVMTargetMachine::getPassNameFromLegacyName
virtual std::pair< StringRef, bool > getPassNameFromLegacyName(StringRef)
Definition: TargetMachine.h:446
llvm::PGOOptions::ProfileRemappingFile
std::string ProfileRemappingFile
Definition: PGOOptions.h:57
DisableMachineLICM
static cl::opt< bool > DisableMachineLICM("disable-machine-licm", cl::Hidden, cl::desc("Disable Machine LICM"))
RegAlloc
static cl::opt< RegisterRegAlloc::FunctionPassCtor, false, RegisterPassParser< RegisterRegAlloc > > RegAlloc("regalloc", cl::Hidden, cl::init(&useDefaultRegisterAllocator), cl::desc("Register allocator to use"))
TargetTransformInfo.h
llvm::TargetPassConfig::addPreISel
virtual bool addPreISel()
Methods with trivial inline returns are convenient points in the common codegen pass pipeline where t...
Definition: TargetPassConfig.h:357
llvm::legacy::PassManagerBase
PassManagerBase - An abstract interface to allow code to add passes to a pass manager without having ...
Definition: LegacyPassManager.h:39
llvm::TargetPassConfig::addPassesToHandleExceptions
void addPassesToHandleExceptions()
Add passes to lower exception handling for the code generator.
Definition: TargetPassConfig.cpp:929
llvm::GlobalISelAbortMode::Disable
@ Disable
DebugifyCheckAndStripAll
static cl::opt< cl::boolOrDefault > DebugifyCheckAndStripAll("debugify-check-and-strip-all-safe", cl::Hidden, cl::desc("Debugify MIR before, by checking and stripping the debug info after, " "each pass except those known to be unsafe when debug info is present"), cl::ZeroOrMore)
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::FunctionPass
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:298
EnableImplicitNullChecks
static cl::opt< bool > EnableImplicitNullChecks("enable-implicit-null-checks", cl::desc("Fold null checks into faulting memory operations"), cl::init(false), cl::Hidden)
llvm::ImplicitNullChecksID
char & ImplicitNullChecksID
ImplicitNullChecks - This pass folds null pointer checks into nearby memory operations.
Definition: ImplicitNullChecks.cpp:816
llvm::EarlyMachineLICMID
char & EarlyMachineLICMID
This pass performs loop invariant code motion on machine instructions.
Definition: MachineLICM.cpp:298
llvm::TargetPassConfig::TargetPassConfig
TargetPassConfig()
Definition: TargetPassConfig.cpp:658
llvm::PostMachineSchedulerID
char & PostMachineSchedulerID
PostMachineScheduler - This pass schedules machine instructions postRA.
Definition: MachineScheduler.cpp:245
llvm::PostRAMachineSinkingID
char & PostRAMachineSinkingID
This pass perform post-ra machine sink for COPY instructions.
Definition: MachineSink.cpp:1558
llvm::RemoveRedundantDebugValuesID
char & RemoveRedundantDebugValuesID
RemoveRedundantDebugValues pass.
Definition: RemoveRedundantDebugValues.cpp:62
llvm::cl::desc
Definition: CommandLine.h:412
llvm::PassRegistry::getPassInfo
const PassInfo * getPassInfo(const void *TI) const
getPassInfo - Look up a pass' corresponding PassInfo, indexed by the pass' type identifier (&MyPass::...
Definition: PassRegistry.cpp:41
llvm::TargetPassConfig::addPreEmitPass
virtual void addPreEmitPass()
This pass may be implemented by targets that want to run passes immediately before machine code is em...
Definition: TargetPassConfig.h:436
llvm::TargetPassConfig::insertPass
void insertPass(AnalysisID TargetPassID, IdentifyingPassPtr InsertedPassID)
Insert InsertedPassID pass after TargetPassID pass.
Definition: TargetPassConfig.cpp:640
llvm::createSafeStackPass
FunctionPass * createSafeStackPass()
This pass splits the stack into a safe stack and an unsafe stack to protect against stack-based overf...
Definition: SafeStack.cpp:943
llvm::TargetPassConfig::Initialized
bool Initialized
Definition: TargetPassConfig.h:124
llvm::TargetPassConfig::addFastRegAlloc
virtual void addFastRegAlloc()
addFastRegAlloc - Add the minimum set of target-independent passes that are required for fast registe...
Definition: TargetPassConfig.cpp:1416
llvm::TargetPassConfig::addCoreISelPasses
bool addCoreISelPasses()
Add the actual instruction selection passes.
Definition: TargetPassConfig.cpp:1002
SET_BOOLEAN_OPTION
#define SET_BOOLEAN_OPTION(Option)
llvm::LiveIntervalsID
char & LiveIntervalsID
LiveIntervals - This analysis keeps track of the live ranges of virtual and physical registers.
Definition: LiveIntervals.cpp:64
EnableIPRA
static cl::opt< bool > EnableIPRA("enable-ipra", cl::init(false), cl::Hidden, cl::desc("Enable interprocedural register allocation " "to reduce load/store at procedure calls."))
InitializePasses.h
llvm::LLVMTargetMachine::useIPRA
virtual bool useIPRA() const
True if the target wants to use interprocedural register allocation by default.
Definition: TargetMachine.h:485
llvm::TargetPassConfig::addPrintPass
void addPrintPass(const std::string &Banner)
Add a pass to print the machine function if printing is enabled.
Definition: TargetPassConfig.cpp:797
llvm::ExceptionHandling::DwarfCFI
@ DwarfCFI
DWARF-like instruction based exceptions.
StopAfterOptName
static const char StopAfterOptName[]
Definition: TargetPassConfig.cpp:225
Debug.h
llvm::TargetPassConfig::addILPOpts
virtual bool addILPOpts()
Add passes that optimize instruction level parallelism for out-of-order targets.
Definition: TargetPassConfig.h:371
llvm::TargetPassConfig::getOptLevel
CodeGenOpt::Level getOptLevel() const
Definition: TargetPassConfig.cpp:635
PassName
static const char PassName[]
Definition: X86LowerAMXIntrinsics.cpp:670
CFLSteensAliasAnalysis.h
llvm::TargetPassConfig::setOpt
void setOpt(bool &Opt, bool Val)
Definition: TargetPassConfig.cpp:695
llvm::createCodeGenPreparePass
FunctionPass * createCodeGenPreparePass()
createCodeGenPreparePass - Transform the code to expose more pattern matching during instruction sele...
Definition: CodeGenPrepare.cpp:453
RegAllocRegistry.h
StopAfterOpt
static cl::opt< std::string > StopAfterOpt(StringRef(StopAfterOptName), cl::desc("Stop compilation after a specific pass"), cl::value_desc("pass-name"), cl::init(""), cl::Hidden)
llvm::TargetPassConfig::~TargetPassConfig
~TargetPassConfig() override
Definition: TargetPassConfig.cpp:403
llvm::TargetMachine::getBBSectionsType
llvm::BasicBlockSection getBBSectionsType() const
If basic blocks should be emitted into their own section, corresponding to -fbasic-block-sections.
Definition: TargetMachine.h:298
llvm::createStackProtectorPass
FunctionPass * createStackProtectorPass()
createStackProtectorPass - This pass adds stack protectors to functions.
Definition: StackProtector.cpp:77
llvm::TargetPassConfig::addMachineLateOptimization
virtual void addMachineLateOptimization()
Add passes that optimize machine instructions after register allocation.
Definition: TargetPassConfig.cpp:1487
llvm::SmallVectorImpl::emplace_back
reference emplace_back(ArgTypes &&... Args)
Definition: SmallVector.h:917
llvm::createPrintFunctionPass
FunctionPass * createPrintFunctionPass(raw_ostream &OS, const std::string &Banner="")
Create and return a pass that prints functions to the specified raw_ostream as they are processed.
Definition: IRPrintingPasses.cpp:130
llvm::Intrinsic::ID
unsigned ID
Definition: TargetTransformInfo.h:38
PrintAfterISel
static cl::opt< bool > PrintAfterISel("print-after-isel", cl::init(false), cl::Hidden, cl::desc("Print machine instrs after ISel"))
llvm::createMergeICmpsLegacyPass
Pass * createMergeICmpsLegacyPass()
Definition: MergeICmps.cpp:890
DisablePostRASched
static cl::opt< bool > DisablePostRASched("disable-post-ra", cl::Hidden, cl::desc("Disable Post Regalloc Scheduler"))
DisableCopyProp
static cl::opt< bool > DisableCopyProp("disable-copyprop", cl::Hidden, cl::desc("Disable Copy Propagation pass"))
DisableBlockPlacement
static cl::opt< bool > DisableBlockPlacement("disable-block-placement", cl::Hidden, cl::desc("Disable probability-driven block placement"))