LLVM 17.0.0git
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1//===- TargetPassConfig.cpp - Target independent code generation passes ---===//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
9// This file defines interfaces to access the target independent code
10// generation passes provided by the LLVM backend.
15#include "llvm/ADT/DenseMap.h"
17#include "llvm/ADT/StringRef.h"
27#include "llvm/CodeGen/Passes.h"
32#include "llvm/IR/Verifier.h"
34#include "llvm/MC/MCAsmInfo.h"
36#include "llvm/Pass.h"
40#include "llvm/Support/Debug.h"
50#include <cassert>
51#include <optional>
52#include <string>
54using namespace llvm;
56static cl::opt<bool>
57 EnableIPRA("enable-ipra", cl::init(false), cl::Hidden,
58 cl::desc("Enable interprocedural register allocation "
59 "to reduce load/store at procedure calls."));
61 cl::desc("Disable Post Regalloc Scheduler"));
62static cl::opt<bool> DisableBranchFold("disable-branch-fold", cl::Hidden,
63 cl::desc("Disable branch folding"));
64static cl::opt<bool> DisableTailDuplicate("disable-tail-duplicate", cl::Hidden,
65 cl::desc("Disable tail duplication"));
66static cl::opt<bool> DisableEarlyTailDup("disable-early-taildup", cl::Hidden,
67 cl::desc("Disable pre-register allocation tail duplication"));
68static cl::opt<bool> DisableBlockPlacement("disable-block-placement",
69 cl::Hidden, cl::desc("Disable probability-driven block placement"));
70static cl::opt<bool> EnableBlockPlacementStats("enable-block-placement-stats",
71 cl::Hidden, cl::desc("Collect probability-driven block placement stats"));
72static cl::opt<bool> DisableSSC("disable-ssc", cl::Hidden,
73 cl::desc("Disable Stack Slot Coloring"));
74static cl::opt<bool> DisableMachineDCE("disable-machine-dce", cl::Hidden,
75 cl::desc("Disable Machine Dead Code Elimination"));
77 cl::desc("Disable Early If-conversion"));
78static cl::opt<bool> DisableMachineLICM("disable-machine-licm", cl::Hidden,
79 cl::desc("Disable Machine LICM"));
80static cl::opt<bool> DisableMachineCSE("disable-machine-cse", cl::Hidden,
81 cl::desc("Disable Machine Common Subexpression Elimination"));
83 "optimize-regalloc", cl::Hidden,
84 cl::desc("Enable optimized register allocation compilation path."));
85static cl::opt<bool> DisablePostRAMachineLICM("disable-postra-machine-licm",
87 cl::desc("Disable Machine LICM"));
88static cl::opt<bool> DisableMachineSink("disable-machine-sink", cl::Hidden,
89 cl::desc("Disable Machine Sinking"));
90static cl::opt<bool> DisablePostRAMachineSink("disable-postra-machine-sink",
92 cl::desc("Disable PostRA Machine Sinking"));
93static cl::opt<bool> DisableLSR("disable-lsr", cl::Hidden,
94 cl::desc("Disable Loop Strength Reduction Pass"));
95static cl::opt<bool> DisableConstantHoisting("disable-constant-hoisting",
96 cl::Hidden, cl::desc("Disable ConstantHoisting"));
97static cl::opt<bool> DisableCGP("disable-cgp", cl::Hidden,
98 cl::desc("Disable Codegen Prepare"));
99static cl::opt<bool> DisableCopyProp("disable-copyprop", cl::Hidden,
100 cl::desc("Disable Copy Propagation pass"));
101static cl::opt<bool> DisablePartialLibcallInlining("disable-partial-libcall-inlining",
102 cl::Hidden, cl::desc("Disable Partial Libcall Inlining"));
104 "disable-atexit-based-global-dtor-lowering", cl::Hidden,
105 cl::desc("For MachO, disable atexit()-based global destructor lowering"));
107 "enable-implicit-null-checks",
108 cl::desc("Fold null checks into faulting memory operations"),
109 cl::init(false), cl::Hidden);
110static cl::opt<bool> DisableMergeICmps("disable-mergeicmps",
111 cl::desc("Disable MergeICmps Pass"),
112 cl::init(false), cl::Hidden);
113static cl::opt<bool> PrintLSR("print-lsr-output", cl::Hidden,
114 cl::desc("Print LLVM IR produced by the loop-reduce pass"));
115static cl::opt<bool> PrintISelInput("print-isel-input", cl::Hidden,
116 cl::desc("Print LLVM IR input to isel pass"));
118 cl::desc("Dump garbage collector data"));
120 VerifyMachineCode("verify-machineinstrs", cl::Hidden,
121 cl::desc("Verify generated machine code"));
123 DebugifyAndStripAll("debugify-and-strip-all-safe", cl::Hidden,
124 cl::desc("Debugify MIR before and Strip debug after "
125 "each pass except those known to be unsafe "
126 "when debug info is present"));
128 "debugify-check-and-strip-all-safe", cl::Hidden,
129 cl::desc(
130 "Debugify MIR before, by checking and stripping the debug info after, "
131 "each pass except those known to be unsafe when debug info is "
132 "present"));
133// Enable or disable the MachineOutliner.
135 "enable-machine-outliner", cl::desc("Enable the machine outliner"),
136 cl::Hidden, cl::ValueOptional, cl::init(RunOutliner::TargetDefault),
137 cl::values(clEnumValN(RunOutliner::AlwaysOutline, "always",
138 "Run on all functions guaranteed to be beneficial"),
139 clEnumValN(RunOutliner::NeverOutline, "never",
140 "Disable all outlining"),
141 // Sentinel value for unspecified option.
142 clEnumValN(RunOutliner::AlwaysOutline, "", "")));
143// Disable the pass to fix unwind information. Whether the pass is included in
144// the pipeline is controlled via the target options, this option serves as
145// manual override.
146static cl::opt<bool> DisableCFIFixup("disable-cfi-fixup", cl::Hidden,
147 cl::desc("Disable the CFI fixup pass"));
148// Enable or disable FastISel. Both options are needed, because
149// FastISel is enabled by default with -fast, and we wish to be
150// able to enable or disable fast-isel independently from -O0.
153 cl::desc("Enable the \"fast\" instruction selector"));
156 "global-isel", cl::Hidden,
157 cl::desc("Enable the \"global\" instruction selector"));
159// FIXME: remove this after switching to NPM or GlobalISel, whichever gets there
160// first...
161static cl::opt<bool>
162 PrintAfterISel("print-after-isel", cl::init(false), cl::Hidden,
163 cl::desc("Print machine instrs after ISel"));
166 "global-isel-abort", cl::Hidden,
167 cl::desc("Enable abort calls when \"global\" instruction selection "
168 "fails to lower/select an instruction"),
170 clEnumValN(GlobalISelAbortMode::Disable, "0", "Disable the abort"),
171 clEnumValN(GlobalISelAbortMode::Enable, "1", "Enable the abort"),
172 clEnumValN(GlobalISelAbortMode::DisableWithDiag, "2",
173 "Disable the abort but emit a diagnostic on failure")));
175// An option that disables inserting FS-AFDO discriminators before emit.
176// This is mainly for debugging and tuning purpose.
177static cl::opt<bool>
178 FSNoFinalDiscrim("fs-no-final-discrim", cl::init(false), cl::Hidden,
179 cl::desc("Do not insert FS-AFDO discriminators before "
180 "emit."));
181// Disable MIRProfileLoader before RegAlloc. This is for for debugging and
182// tuning purpose.
184 "disable-ra-fsprofile-loader", cl::init(false), cl::Hidden,
185 cl::desc("Disable MIRProfileLoader before RegAlloc"));
186// Disable MIRProfileLoader before BloackPlacement. This is for for debugging
187// and tuning purpose.
189 "disable-layout-fsprofile-loader", cl::init(false), cl::Hidden,
190 cl::desc("Disable MIRProfileLoader before BlockPlacement"));
191// Specify FSProfile file name.
193 FSProfileFile("fs-profile-file", cl::init(""), cl::value_desc("filename"),
194 cl::desc("Flow Sensitive profile file name."), cl::Hidden);
195// Specify Remapping file for FSProfile.
197 "fs-remapping-file", cl::init(""), cl::value_desc("filename"),
198 cl::desc("Flow Sensitive profile remapping file name."), cl::Hidden);
200// Temporary option to allow experimenting with MachineScheduler as a post-RA
201// scheduler. Targets can "properly" enable this with
202// substitutePass(&PostRASchedulerID, &PostMachineSchedulerID).
203// Targets can return true in targetSchedulesPostRAScheduling() and
204// insert a PostRA scheduling pass wherever it wants.
206 "misched-postra", cl::Hidden,
207 cl::desc(
208 "Run MachineScheduler post regalloc (independent of preRA sched)"));
210// Experimental option to run live interval analysis early.
211static cl::opt<bool> EarlyLiveIntervals("early-live-intervals", cl::Hidden,
212 cl::desc("Run live interval analysis earlier in the pipeline"));
214/// Option names for limiting the codegen pipeline.
215/// Those are used in error reporting and we didn't want
216/// to duplicate their names all over the place.
217static const char StartAfterOptName[] = "start-after";
218static const char StartBeforeOptName[] = "start-before";
219static const char StopAfterOptName[] = "stop-after";
220static const char StopBeforeOptName[] = "stop-before";
224 cl::desc("Resume compilation after a specific pass"),
225 cl::value_desc("pass-name"), cl::init(""), cl::Hidden);
229 cl::desc("Resume compilation before a specific pass"),
230 cl::value_desc("pass-name"), cl::init(""), cl::Hidden);
234 cl::desc("Stop compilation after a specific pass"),
235 cl::value_desc("pass-name"), cl::init(""), cl::Hidden);
239 cl::desc("Stop compilation before a specific pass"),
240 cl::value_desc("pass-name"), cl::init(""), cl::Hidden);
242/// Enable the machine function splitter pass.
244 "enable-split-machine-functions", cl::Hidden,
245 cl::desc("Split out cold blocks from machine functions based on profile "
246 "information."));
248/// Disable the expand reductions pass for testing.
250 "disable-expand-reductions", cl::init(false), cl::Hidden,
251 cl::desc("Disable the expand reduction intrinsics pass from running"));
253/// Disable the select optimization pass.
255 "disable-select-optimize", cl::init(true), cl::Hidden,
256 cl::desc("Disable the select-optimization pass from running"));
258/// Allow standard passes to be disabled by command line options. This supports
259/// simple binary flags that either suppress the pass or do nothing.
260/// i.e. -disable-mypass=false has no effect.
261/// These should be converted to boolOrDefault in order to use applyOverride.
263 bool Override) {
264 if (Override)
265 return IdentifyingPassPtr();
266 return PassID;
269/// Allow standard passes to be disabled by the command line, regardless of who
270/// is adding the pass.
272/// StandardID is the pass identified in the standard pass pipeline and provided
273/// to addPass(). It may be a target-specific ID in the case that the target
274/// directly adds its own pass, but in that case we harmlessly fall through.
276/// TargetID is the pass that the target has configured to override StandardID.
278/// StandardID may be a pseudo ID. In that case TargetID is the name of the real
279/// pass to run. This allows multiple options to control a single pass depending
280/// on where in the pipeline that pass is added.
282 IdentifyingPassPtr TargetID) {
283 if (StandardID == &PostRASchedulerID)
284 return applyDisable(TargetID, DisablePostRASched);
286 if (StandardID == &BranchFolderPassID)
287 return applyDisable(TargetID, DisableBranchFold);
289 if (StandardID == &TailDuplicateID)
290 return applyDisable(TargetID, DisableTailDuplicate);
292 if (StandardID == &EarlyTailDuplicateID)
293 return applyDisable(TargetID, DisableEarlyTailDup);
295 if (StandardID == &MachineBlockPlacementID)
296 return applyDisable(TargetID, DisableBlockPlacement);
298 if (StandardID == &StackSlotColoringID)
299 return applyDisable(TargetID, DisableSSC);
301 if (StandardID == &DeadMachineInstructionElimID)
302 return applyDisable(TargetID, DisableMachineDCE);
304 if (StandardID == &EarlyIfConverterID)
305 return applyDisable(TargetID, DisableEarlyIfConversion);
307 if (StandardID == &EarlyMachineLICMID)
308 return applyDisable(TargetID, DisableMachineLICM);
310 if (StandardID == &MachineCSEID)
311 return applyDisable(TargetID, DisableMachineCSE);
313 if (StandardID == &MachineLICMID)
314 return applyDisable(TargetID, DisablePostRAMachineLICM);
316 if (StandardID == &MachineSinkingID)
317 return applyDisable(TargetID, DisableMachineSink);
319 if (StandardID == &PostRAMachineSinkingID)
320 return applyDisable(TargetID, DisablePostRAMachineSink);
322 if (StandardID == &MachineCopyPropagationID)
323 return applyDisable(TargetID, DisableCopyProp);
325 return TargetID;
328// Find the FSProfile file name. The internal option takes the precedence
329// before getting from TargetMachine.
330static std::string getFSProfileFile(const TargetMachine *TM) {
331 if (!FSProfileFile.empty())
332 return FSProfileFile.getValue();
333 const std::optional<PGOOptions> &PGOOpt = TM->getPGOOption();
334 if (PGOOpt == std::nullopt || PGOOpt->Action != PGOOptions::SampleUse)
335 return std::string();
336 return PGOOpt->ProfileFile;
339// Find the Profile remapping file name. The internal option takes the
340// precedence before getting from TargetMachine.
341static std::string getFSRemappingFile(const TargetMachine *TM) {
342 if (!FSRemappingFile.empty())
343 return FSRemappingFile.getValue();
344 const std::optional<PGOOptions> &PGOOpt = TM->getPGOOption();
345 if (PGOOpt == std::nullopt || PGOOpt->Action != PGOOptions::SampleUse)
346 return std::string();
347 return PGOOpt->ProfileRemappingFile;
351/// TargetPassConfig
354INITIALIZE_PASS(TargetPassConfig, "targetpassconfig",
355 "Target Pass Configuration", false, false)
358namespace {
364 InsertedPass(AnalysisID TargetPassID, IdentifyingPassPtr InsertedPassID)
365 : TargetPassID(TargetPassID), InsertedPassID(InsertedPassID) {}
368 assert(InsertedPassID.isValid() && "Illegal Pass ID!");
369 if (InsertedPassID.isInstance())
370 return InsertedPassID.getInstance();
371 Pass *NP = Pass::createPass(InsertedPassID.getID());
372 assert(NP && "Pass ID not registered");
373 return NP;
374 }
377} // end anonymous namespace
379namespace llvm {
385 // List of passes explicitly substituted by this target. Normally this is
386 // empty, but it is a convenient way to suppress or replace specific passes
387 // that are part of a standard pass pipeline without overridding the entire
388 // pipeline. This mechanism allows target options to inherit a standard pass's
389 // user interface. For example, a target may disable a standard pass by
390 // default by substituting a pass ID of zero, and the user may still enable
391 // that standard pass with an explicit command line option.
394 /// Store the pairs of <AnalysisID, AnalysisID> of which the second pass
395 /// is inserted after each instance of the first one.
399} // end namespace llvm
401// Out of line virtual method.
403 delete Impl;
407 if (PassName.empty())
408 return nullptr;
411 const PassInfo *PI = PR.getPassInfo(PassName);
412 if (!PI)
414 Twine("\" pass is not registered."));
415 return PI;
419 const PassInfo *PI = getPassInfo(PassName);
420 return PI ? PI->getTypeInfo() : nullptr;
423static std::pair<StringRef, unsigned>
425 StringRef Name, InstanceNumStr;
426 std::tie(Name, InstanceNumStr) = PassName.split(',');
428 unsigned InstanceNum = 0;
429 if (!InstanceNumStr.empty() && InstanceNumStr.getAsInteger(10, InstanceNum))
430 report_fatal_error("invalid pass instance specifier " + PassName);
432 return std::make_pair(Name, InstanceNum);
435void TargetPassConfig::setStartStopPasses() {
436 StringRef StartBeforeName;
437 std::tie(StartBeforeName, StartBeforeInstanceNum) =
440 StringRef StartAfterName;
441 std::tie(StartAfterName, StartAfterInstanceNum) =
444 StringRef StopBeforeName;
445 std::tie(StopBeforeName, StopBeforeInstanceNum)
448 StringRef StopAfterName;
449 std::tie(StopAfterName, StopAfterInstanceNum)
452 StartBefore = getPassIDFromName(StartBeforeName);
453 StartAfter = getPassIDFromName(StartAfterName);
454 StopBefore = getPassIDFromName(StopBeforeName);
455 StopAfter = getPassIDFromName(StopAfterName);
456 if (StartBefore && StartAfter)
458 Twine(StartAfterOptName) + Twine(" specified!"));
459 if (StopBefore && StopAfter)
461 Twine(StopAfterOptName) + Twine(" specified!"));
462 Started = (StartAfter == nullptr) && (StartBefore == nullptr);
468#define SET_OPTION(Option) \
469 if (Option.getNumOccurrences()) \
470 Opt.Option = Option;
479#define SET_BOOLEAN_OPTION(Option) Opt.Option = Option;
496 return Opt;
500 LLVMTargetMachine &LLVMTM) {
501 StringRef StartBefore;
502 StringRef StartAfter;
503 StringRef StopBefore;
504 StringRef StopAfter;
506 unsigned StartBeforeInstanceNum = 0;
507 unsigned StartAfterInstanceNum = 0;
508 unsigned StopBeforeInstanceNum = 0;
509 unsigned StopAfterInstanceNum = 0;
511 std::tie(StartBefore, StartBeforeInstanceNum) =
513 std::tie(StartAfter, StartAfterInstanceNum) =
515 std::tie(StopBefore, StopBeforeInstanceNum) =
517 std::tie(StopAfter, StopAfterInstanceNum) =
520 if (StartBefore.empty() && StartAfter.empty() && StopBefore.empty() &&
521 StopAfter.empty())
522 return;
524 std::tie(StartBefore, std::ignore) =
525 LLVMTM.getPassNameFromLegacyName(StartBefore);
526 std::tie(StartAfter, std::ignore) =
527 LLVMTM.getPassNameFromLegacyName(StartAfter);
528 std::tie(StopBefore, std::ignore) =
529 LLVMTM.getPassNameFromLegacyName(StopBefore);
530 std::tie(StopAfter, std::ignore) =
531 LLVMTM.getPassNameFromLegacyName(StopAfter);
532 if (!StartBefore.empty() && !StartAfter.empty())
534 Twine(StartAfterOptName) + Twine(" specified!"));
535 if (!StopBefore.empty() && !StopAfter.empty())
537 Twine(StopAfterOptName) + Twine(" specified!"));
540 [=, EnableCurrent = StartBefore.empty() && StartAfter.empty(),
541 EnableNext = std::optional<bool>(), StartBeforeCount = 0u,
542 StartAfterCount = 0u, StopBeforeCount = 0u,
543 StopAfterCount = 0u](StringRef P, Any) mutable {
544 bool StartBeforePass = !StartBefore.empty() && P.contains(StartBefore);
545 bool StartAfterPass = !StartAfter.empty() && P.contains(StartAfter);
546 bool StopBeforePass = !StopBefore.empty() && P.contains(StopBefore);
547 bool StopAfterPass = !StopAfter.empty() && P.contains(StopAfter);
549 // Implement -start-after/-stop-after
550 if (EnableNext) {
551 EnableCurrent = *EnableNext;
552 EnableNext.reset();
553 }
555 // Using PIC.registerAfterPassCallback won't work because if this
556 // callback returns false, AfterPassCallback is also skipped.
557 if (StartAfterPass && StartAfterCount++ == StartAfterInstanceNum) {
558 assert(!EnableNext && "Error: assign to EnableNext more than once");
559 EnableNext = true;
560 }
561 if (StopAfterPass && StopAfterCount++ == StopAfterInstanceNum) {
562 assert(!EnableNext && "Error: assign to EnableNext more than once");
563 EnableNext = false;
564 }
566 if (StartBeforePass && StartBeforeCount++ == StartBeforeInstanceNum)
567 EnableCurrent = true;
568 if (StopBeforePass && StopBeforeCount++ == StopBeforeInstanceNum)
569 EnableCurrent = false;
570 return EnableCurrent;
571 });
575 LLVMTargetMachine &LLVMTM) {
577 // Register a callback for disabling passes.
580#define DISABLE_PASS(Option, Name) \
581 if (Option && P.contains(#Name)) \
582 return false;
583 DISABLE_PASS(DisableBlockPlacement, MachineBlockPlacementPass)
584 DISABLE_PASS(DisableBranchFold, BranchFolderPass)
585 DISABLE_PASS(DisableCopyProp, MachineCopyPropagationPass)
586 DISABLE_PASS(DisableEarlyIfConversion, EarlyIfConverterPass)
587 DISABLE_PASS(DisableEarlyTailDup, EarlyTailDuplicatePass)
588 DISABLE_PASS(DisableMachineCSE, MachineCSEPass)
589 DISABLE_PASS(DisableMachineDCE, DeadMachineInstructionElimPass)
590 DISABLE_PASS(DisableMachineLICM, EarlyMachineLICMPass)
591 DISABLE_PASS(DisableMachineSink, MachineSinkingPass)
592 DISABLE_PASS(DisablePostRAMachineLICM, MachineLICMPass)
593 DISABLE_PASS(DisablePostRAMachineSink, PostRAMachineSinkingPass)
594 DISABLE_PASS(DisablePostRASched, PostRASchedulerPass)
595 DISABLE_PASS(DisableSSC, StackSlotColoringPass)
596 DISABLE_PASS(DisableTailDuplicate, TailDuplicatePass)
598 return true;
599 });
604// Out of line constructor provides default values for pass options and
605// registers all common codegen passes.
607 : ImmutablePass(ID), PM(&pm), TM(&TM) {
608 Impl = new PassConfigImpl();
610 // Register all target independent codegen passes to activate their PassIDs,
611 // including this pass itself.
614 // Also register alias analysis passes required by codegen passes.
618 if (EnableIPRA.getNumOccurrences())
620 else {
621 // If not explicitly specified, use target default.
623 }
628 if (EnableGlobalISelAbort.getNumOccurrences())
631 setStartStopPasses();
635 return TM->getOptLevel();
638/// Insert InsertedPassID pass after TargetPassID.
640 IdentifyingPassPtr InsertedPassID) {
641 assert(((!InsertedPassID.isInstance() &&
642 TargetPassID != InsertedPassID.getID()) ||
643 (InsertedPassID.isInstance() &&
644 TargetPassID != InsertedPassID.getInstance()->getPassID())) &&
645 "Insert a pass after itself!");
646 Impl->InsertedPasses.emplace_back(TargetPassID, InsertedPassID);
649/// createPassConfig - Create a pass configuration object to be used by
650/// addPassToEmitX methods for generating a pipeline of CodeGen passes.
652/// Targets may override this to extend TargetPassConfig.
654 return new TargetPassConfig(*this, PM);
658 : ImmutablePass(ID) {
659 report_fatal_error("Trying to construct TargetPassConfig without a target "
660 "machine. Scheduling a CodeGen pass without a target "
661 "triple set?");
665 return StopBeforeOpt.empty() && StopAfterOpt.empty();
669 return !StartBeforeOpt.empty() || !StartAfterOpt.empty() ||
676 return std::string();
677 std::string Res;
678 static cl::opt<std::string> *PassNames[] = {&StartAfterOpt, &StartBeforeOpt,
680 static const char *OptNames[] = {StartAfterOptName, StartBeforeOptName,
682 bool IsFirst = true;
683 for (int Idx = 0; Idx < 4; ++Idx)
684 if (!PassNames[Idx]->empty()) {
685 if (!IsFirst)
686 Res += Separator;
687 IsFirst = false;
688 Res += OptNames[Idx];
689 }
690 return Res;
693// Helper to verify the analysis is really immutable.
694void TargetPassConfig::setOpt(bool &Opt, bool Val) {
695 assert(!Initialized && "PassConfig is immutable");
696 Opt = Val;
700 IdentifyingPassPtr TargetID) {
701 Impl->TargetPasses[StandardID] = TargetID;
706 I = Impl->TargetPasses.find(ID);
707 if (I == Impl->TargetPasses.end())
708 return ID;
709 return I->second;
714 IdentifyingPassPtr FinalPtr = overridePass(ID, TargetID);
715 return !FinalPtr.isValid() || FinalPtr.isInstance() ||
716 FinalPtr.getID() != ID;
719/// Add a pass to the PassManager if that pass is supposed to be run. If the
720/// Started/Stopped flags indicate either that the compilation should start at
721/// a later pass or that it should stop after an earlier pass, then do not add
722/// the pass. Finally, compare the current pass against the StartAfter
723/// and StopAfter options and change the Started/Stopped flags accordingly.
725 assert(!Initialized && "PassConfig is immutable");
727 // Cache the Pass ID here in case the pass manager finds this pass is
728 // redundant with ones already scheduled / available, and deletes it.
729 // Fundamentally, once we add the pass to the manager, we no longer own it
730 // and shouldn't reference it.
731 AnalysisID PassID = P->getPassID();
733 if (StartBefore == PassID && StartBeforeCount++ == StartBeforeInstanceNum)
734 Started = true;
735 if (StopBefore == PassID && StopBeforeCount++ == StopBeforeInstanceNum)
736 Stopped = true;
737 if (Started && !Stopped) {
738 if (AddingMachinePasses) {
739 // Construct banner message before PM->add() as that may delete the pass.
740 std::string Banner =
741 std::string("After ") + std::string(P->getPassName());
743 PM->add(P);
744 addMachinePostPasses(Banner);
745 } else {
746 PM->add(P);
747 }
749 // Add the passes after the pass P if there is any.
750 for (const auto &IP : Impl->InsertedPasses)
751 if (IP.TargetPassID == PassID)
752 addPass(IP.getInsertedPass());
753 } else {
754 delete P;
755 }
757 if (StopAfter == PassID && StopAfterCount++ == StopAfterInstanceNum)
758 Stopped = true;
760 if (StartAfter == PassID && StartAfterCount++ == StartAfterInstanceNum)
761 Started = true;
762 if (Stopped && !Started)
763 report_fatal_error("Cannot stop compilation after pass that is not run");
766/// Add a CodeGen pass at this point in the pipeline after checking for target
767/// and command line overrides.
769/// addPass cannot return a pointer to the pass instance because is internal the
770/// PassManager and the instance we create here may already be freed.
772 IdentifyingPassPtr TargetID = getPassSubstitution(PassID);
773 IdentifyingPassPtr FinalPtr = overridePass(PassID, TargetID);
774 if (!FinalPtr.isValid())
775 return nullptr;
777 Pass *P;
778 if (FinalPtr.isInstance())
779 P = FinalPtr.getInstance();
780 else {
781 P = Pass::createPass(FinalPtr.getID());
782 if (!P)
783 llvm_unreachable("Pass ID not registered");
784 }
785 AnalysisID FinalID = P->getPassID();
786 addPass(P); // Ends the lifetime of P.
788 return FinalID;
791void TargetPassConfig::printAndVerify(const std::string &Banner) {
792 addPrintPass(Banner);
793 addVerifyPass(Banner);
796void TargetPassConfig::addPrintPass(const std::string &Banner) {
797 if (PrintAfterISel)
801void TargetPassConfig::addVerifyPass(const std::string &Banner) {
807 if (Verify)
808 PM->add(createMachineVerifierPass(Banner));
816 PM->add(createStripDebugMachineModulePass(/*OnlyDebugified=*/true));
824 if (AllowDebugify && DebugifyIsSafe &&
830void TargetPassConfig::addMachinePostPasses(const std::string &Banner) {
831 if (DebugifyIsSafe) {
835 } else if (DebugifyAndStripAll == cl::BOU_TRUE)
837 }
838 addVerifyPass(Banner);
841/// Add common target configurable passes that perform LLVM IR to IR transforms
842/// following machine independent optimization.
844 // Before running any passes, run the verifier to determine if the input
845 // coming from the front-end and/or optimizer is valid.
846 if (!DisableVerify)
849 if (getOptLevel() != CodeGenOpt::None) {
850 // Basic AliasAnalysis support.
851 // Add TypeBasedAliasAnalysis before BasicAliasAnalysis so that
852 // BasicAliasAnalysis wins if they disagree. This is intended to help
853 // support "obvious" type-punning idioms.
858 // Run loop strength reduction before anything else.
859 if (!DisableLSR) {
862 if (PrintLSR)
864 "\n\n*** Code after LSR ***\n"));
865 }
867 // The MergeICmpsPass tries to create memcmp calls by grouping sequences of
868 // loads and compares. ExpandMemCmpPass then tries to expand those calls
869 // into optimally-sized loads and compares. The transforms are enabled by a
870 // target lowering hook.
874 }
876 // Run GC lowering passes for builtin collectors
877 // TODO: add a pass insertion point here
882 // For MachO, lower @llvm.global_dtors into @llvm.global_ctors with
883 // __cxa_atexit() calls to avoid emitting the deprecated __mod_term_func.
888 // Make sure that no unreachable blocks are instruction selected.
891 // Prepare expensive constants for SelectionDAG.
901 // Expand vector predication intrinsics into standard IR instructions.
902 // This pass has to run before ScalarizeMaskedMemIntrin and ExpandReduction
903 // passes since it emits those kinds of intrinsics.
906 // Add scalarization of target's unsupported masked memory intrinsics pass.
907 // the unsupported intrinsic will be replaced with a chain of basic blocks,
908 // that stores/loads element one-by-one if the appropriate mask bit is set.
911 // Expand reduction intrinsics into shuffle sequences if the target wants to.
912 // Allow disabling it for testing purposes.
919 // Convert conditional moves to conditional jumps when profitable.
924/// Turn exception handling constructs into something the code generators can
925/// handle.
927 const MCAsmInfo *MCAI = TM->getMCAsmInfo();
928 assert(MCAI && "No MCAsmInfo");
929 switch (MCAI->getExceptionHandlingType()) {
931 // SjLj piggy-backs on dwarf for this bit. The cleanups done apply to both
932 // Dwarf EH prepare needs to be run after SjLj prepare. Otherwise,
933 // catch info can get misplaced when a selector ends up more than one block
934 // removed from the parent invoke(s). This could happen when a landing
935 // pad is shared by multiple invokes and is also a target of a normal
936 // edge from elsewhere.
938 [[fallthrough]];
943 break;
945 // We support using both GCC-style and MSVC-style exceptions on Windows, so
946 // add both preparation passes. Each pass will only actually run if it
947 // recognizes the personality function.
950 break;
952 // Wasm EH uses Windows EH instructions, but it does not need to demote PHIs
953 // on catchpads and cleanuppads because it does not outline them into
954 // funclets. Catchswitch blocks are not lowered in SelectionDAG, so we
955 // should remove PHIs there.
956 addPass(createWinEHPass(/*DemoteCatchSwitchPHIOnly=*/false));
958 break;
962 // The lower invoke pass may create unreachable code. Remove it.
964 break;
965 }
968/// Add pass to prepare the LLVM IR for code generation. This should be done
969/// before exception handling preparation passes.
975/// Add common passes that perform LLVM IR to IR transforms in preparation for
976/// instruction selection.
978 addPreISel();
980 // Force codegen to run according to the callgraph.
986 // Add both the safe stack and the stack protection passes: each of them will
987 // only protect functions that have corresponding attributes.
991 if (PrintISelInput)
993 dbgs(), "\n\n*** Final LLVM Code input to ISel ***\n"));
995 // All passes which modify the LLVM IR are now complete; run the verifier
996 // to ensure that the IR is valid.
997 if (!DisableVerify)
1002 // Enable FastISel with -fast-isel, but allow that to be overridden.
1005 // Determine an instruction selector.
1006 enum class SelectorType { SelectionDAG, FastISel, GlobalISel };
1007 SelectorType Selector;
1010 Selector = SelectorType::FastISel;
1014 Selector = SelectorType::GlobalISel;
1016 Selector = SelectorType::FastISel;
1017 else
1018 Selector = SelectorType::SelectionDAG;
1020 // Set consistently TM->Options.EnableFastISel and EnableGlobalISel.
1021 if (Selector == SelectorType::FastISel) {
1022 TM->setFastISel(true);
1023 TM->setGlobalISel(false);
1024 } else if (Selector == SelectorType::GlobalISel) {
1025 TM->setFastISel(false);
1026 TM->setGlobalISel(true);
1027 }
1029 // FIXME: Injecting into the DAGISel pipeline seems to cause issues with
1030 // analyses needing to be re-run. This can result in being unable to
1031 // schedule passes (particularly with 'Function Alias Analysis
1032 // Results'). It's not entirely clear why but AFAICT this seems to be
1033 // due to one FunctionPassManager not being able to use analyses from a
1034 // previous one. As we're injecting a ModulePass we break the usual
1035 // pass manager into two. GlobalISel with the fallback path disabled
1036 // and -run-pass seem to be unaffected. The majority of GlobalISel
1037 // testing uses -run-pass so this probably isn't too bad.
1038 SaveAndRestore SavedDebugifyIsSafe(DebugifyIsSafe);
1039 if (Selector != SelectorType::GlobalISel || !isGlobalISelAbortEnabled())
1040 DebugifyIsSafe = false;
1042 // Add instruction selector passes.
1043 if (Selector == SelectorType::GlobalISel) {
1044 SaveAndRestore SavedAddingMachinePasses(AddingMachinePasses, true);
1045 if (addIRTranslator())
1046 return true;
1051 return true;
1053 // Before running the register bank selector, ask the target if it
1054 // wants to run some passes.
1057 if (addRegBankSelect())
1058 return true;
1063 return true;
1065 // Pass to reset the MachineFunction if the ISel failed.
1069 // Provide a fallback path when we do not want to abort on
1070 // not-yet-supported input.
1072 return true;
1074 } else if (addInstSelector())
1075 return true;
1077 // Expand pseudo-instructions emitted by ISel. Don't run the verifier before
1078 // FinalizeISel.
1081 // Print the instruction selected machine code...
1082 printAndVerify("After Instruction Selection");
1084 return false;
1088 if (TM->useEmulatedTLS())
1095 addIRPasses();
1100 return addCoreISelPasses();
1103/// -regalloc=... command line option.
1104static FunctionPass *useDefaultRegisterAllocator() { return nullptr; }
1108 cl::desc("Register allocator to use"));
1110/// Add the complete set of target-independent postISel code generator passes.
1112/// This can be read as the standard order of major LLVM CodeGen stages. Stages
1113/// with nontrivial configuration or multiple passes are broken out below in
1114/// add%Stage routines.
1116/// Any TargetPassConfig::addXX routine may be overriden by the Target. The
1117/// addPre/Post methods with empty header implementations allow injecting
1118/// target-specific fixups just before or after major stages. Additionally,
1119/// targets have the flexibility to change pass order within a stage by
1120/// overriding default implementation of add%Stage routines below. Each
1121/// technique has maintainability tradeoffs because alternate pass orders are
1122/// not well supported. addPre/Post works better if the target pass is easily
1123/// tied to a common pass. But if it has subtle dependencies on multiple passes,
1124/// the target should override the stage instead.
1126/// TODO: We could use a single addPre/Post(ID) hook to allow pass injection
1127/// before/after any target-independent pass. But it's currently overkill.
1129 AddingMachinePasses = true;
1131 // Add passes that optimize machine instructions in SSA form.
1132 if (getOptLevel() != CodeGenOpt::None) {
1134 } else {
1135 // If the target requests it, assign local variables to stack slots relative
1136 // to one another and simplify frame index references where possible.
1138 }
1140 if (TM->Options.EnableIPRA)
1143 // Run pre-ra passes.
1146 // Debugifying the register allocator passes seems to provoke some
1147 // non-determinism that affects CodeGen and there doesn't seem to be a point
1148 // where it becomes safe again so stop debugifying here.
1149 DebugifyIsSafe = false;
1151 // Add a FSDiscriminator pass right before RA, so that we could get
1152 // more precise SampleFDO profile for RA.
1156 const std::string ProfileFile = getFSProfileFile(TM);
1157 if (!ProfileFile.empty() && !DisableRAFSProfileLoader)
1160 nullptr));
1161 }
1163 // Run register allocation and passes that are tightly coupled with it,
1164 // including phi elimination and scheduling.
1165 if (getOptimizeRegAlloc())
1167 else
1170 // Run post-ra passes.
1177 // Insert prolog/epilog code. Eliminate abstract frame index references...
1178 if (getOptLevel() != CodeGenOpt::None) {
1181 }
1183 // Prolog/Epilog inserter needs a TargetMachine to instantiate. But only
1184 // do so if it hasn't been disabled, substituted, or overridden.
1188 /// Add passes that optimize machine instructions after register allocation.
1192 // Expand pseudo instructions before second scheduling pass.
1195 // Run pre-sched2 passes.
1196 addPreSched2();
1201 // Second pass scheduler.
1202 // Let Target optionally insert this pass by itself at some other
1203 // point.
1204 if (getOptLevel() != CodeGenOpt::None &&
1206 if (MISchedPostRA)
1208 else
1210 }
1212 // GC
1213 if (addGCPasses()) {
1214 if (PrintGCInfo)
1216 }
1218 // Basic block placement.
1222 // Insert before XRay Instrumentation.
1229 // Add FS discriminators here so that all the instruction duplicates
1230 // in different BBs get their own discriminators. With this, we can "sum"
1231 // the SampleFDO counters instead of using MAX. This will improve the
1232 // SampleFDO profile quality.
1238 if (TM->Options.EnableIPRA)
1239 // Collect register usage information and produce a register mask of
1240 // clobbered registers, to be used to optimize call sites.
1243 // FIXME: Some backends are incompatible with running the verifier after
1244 // addPreEmitPass. Maybe only pass "false" here for those targets?
1253 bool RunOnAllFunctions =
1255 bool AddOutliner =
1256 RunOnAllFunctions || TM->Options.SupportsDefaultOutlining;
1257 if (AddOutliner)
1258 addPass(createMachineOutlinerPass(RunOnAllFunctions));
1259 }
1261 // Machine function splitter uses the basic block sections feature. Both
1262 // cannot be enabled at the same time. Basic block sections takes precedence.
1263 // FIXME: In principle, BasicBlockSection::Labels and splitting can used
1264 // together. Update this check once we have addressed any issues.
1269 }
1274 }
1281 // Add passes that directly emit MI after all other MI passes.
1284 AddingMachinePasses = false;
1287/// Add passes that optimize machine instructions in SSA form.
1289 // Pre-ra tail duplication.
1292 // Optimize PHIs before DCE: removing dead PHI cycles may make more
1293 // instructions dead.
1296 // This pass merges large allocas. StackSlotColoring is a different pass
1297 // which merges spill slots.
1300 // If the target requests it, assign local variables to stack slots relative
1301 // to one another and simplify frame index references where possible.
1304 // With optimization, dead code should already be eliminated. However
1305 // there is one known exception: lowered code for arguments that are only
1306 // used by tail calls, where the tail calls reuse the incoming stack
1307 // arguments directly (see t11 in test/CodeGen/X86/sibcall.ll).
1310 // Allow targets to insert passes that improve instruction level parallelism,
1311 // like if-conversion. Such passes will typically need dominator trees and
1312 // loop info, just like LICM and CSE below.
1313 addILPOpts();
1321 // Clean-up the dead code that may have been generated by peephole
1322 // rewriting.
1327/// Register Allocation Pass Configuration
1331 switch (OptimizeRegAlloc) {
1332 case cl::BOU_UNSET: return getOptLevel() != CodeGenOpt::None;
1333 case cl::BOU_TRUE: return true;
1334 case cl::BOU_FALSE: return false;
1335 }
1336 llvm_unreachable("Invalid optimize-regalloc state");
1339/// A dummy default pass factory indicates whether the register allocator is
1340/// overridden on the command line.
1343static RegisterRegAlloc
1345 "pick register allocator based on -O option",
1353/// Instantiate the default register allocator pass for this target for either
1354/// the optimized or unoptimized allocation path. This will be added to the pass
1355/// manager by addFastRegAlloc in the unoptimized case or addOptimizedRegAlloc
1356/// in the optimized case.
1358/// A target that uses the standard regalloc pass order for fast or optimized
1359/// allocation may still override this for per-target regalloc
1360/// selection. But -regalloc=... always takes precedence.
1362 if (Optimized)
1364 else
1368/// Find and instantiate the register allocation pass requested by this target
1369/// at the current optimization level. Different register allocators are
1370/// defined as separate passes because they may require different analysis.
1372/// This helper ensures that the regalloc= option is always available,
1373/// even for targets that override the default allocator.
1375/// FIXME: When MachinePassRegistry register pass IDs instead of function ptrs,
1376/// this can be folded into addPass.
1378 // Initialize the global default.
1383 if (Ctor != useDefaultRegisterAllocator)
1384 return Ctor();
1386 // With no -regalloc= override, ask the target for a regalloc pass.
1387 return createTargetRegisterAllocator(Optimized);
1391 return RegAlloc !=
1398 report_fatal_error("Must use fast (default) register allocator for unoptimized regalloc.");
1402 // Allow targets to change the register assignments after
1403 // fast register allocation.
1405 return true;
1409 // Add the selected register allocation pass.
1412 // Allow targets to change the register assignments before rewriting.
1413 addPreRewrite();
1415 // Finally rewrite virtual registers.
1418 // Regalloc scoring for ML-driven eviction - noop except when learning a new
1419 // eviction policy.
1421 return true;
1424/// Return true if the default global register allocator is in use and
1425/// has not be overriden on the command line with '-regalloc=...'
1427 return RegAlloc.getNumOccurrences() == 0;
1430/// Add the minimum set of target-independent passes that are required for
1431/// register allocation. No coalescing or scheduling.
1439/// Add standard target-independent passes that are tightly coupled with
1440/// optimized register allocation, including coalescing, machine instruction
1441/// scheduling, and register allocation itself.
1447 // LiveVariables currently requires pure SSA form.
1448 //
1449 // FIXME: Once TwoAddressInstruction pass no longer uses kill flags,
1450 // LiveVariables can be removed completely, and LiveIntervals can be directly
1451 // computed. (We still either need to regenerate kill flags after regalloc, or
1452 // preferably fix the scavenger to not depend on them).
1453 // FIXME: UnreachableMachineBlockElim is a dependant pass of LiveVariables.
1454 // When LiveVariables is removed this has to be removed/moved either.
1455 // Explicit addition of UnreachableMachineBlockElim allows stopping before or
1456 // after it with -stop-before/-stop-after.
1460 // Edge splitting is smarter with machine loop info.
1464 // Eventually, we want to run LiveIntervals before PHI elimination.
1471 // The machine scheduler may accidentally create disconnected components
1472 // when moving subregister definitions around, avoid this by splitting them to
1473 // separate vregs before. Splitting can also improve reg. allocation quality.
1476 // PreRA instruction scheduling.
1480 // Perform stack slot coloring and post-ra machine LICM.
1483 // Allow targets to expand pseudo instructions depending on the choice of
1484 // registers before MachineCopyPropagation.
1487 // Copy propagate to forward register uses and try to eliminate COPYs that
1488 // were not coalesced.
1491 // Run post-ra machine LICM to hoist reloads / remats.
1492 //
1493 // FIXME: can this move into MachineLateOptimization?
1495 }
1499/// Post RegAlloc Pass Configuration
1502/// Add passes that optimize machine instructions after register allocation.
1504 // Cleanup of redundant immediate/address loads.
1507 // Branch folding must be run after regalloc and prolog/epilog insertion.
1510 // Tail duplication.
1511 // Note that duplicating tail just increases code size and degrades
1512 // performance for targets that require Structured Control Flow.
1513 // In addition it can also make CFG irreducible. Thus we disable it.
1514 if (!TM->requiresStructuredCFG())
1517 // Copy propagation.
1521/// Add standard GC passes.
1524 return true;
1527/// Add standard basic block placement passes.
1532 const std::string ProfileFile = getFSProfileFile(TM);
1533 if (!ProfileFile.empty() && !DisableLayoutFSProfileLoader)
1536 nullptr));
1537 }
1539 // Run a separate pass to collect block placement statistics.
1542 }
1546/// GlobalISel Configuration
1557 return true;
1560std::unique_ptr<CSEConfigBase> TargetPassConfig::getCSEConfig() const {
1561 return std::make_unique<CSEConfigBase>();
This is the interface for LLVM's primary stateless and local alias analysis.
Definition: CommandLine.h:678
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
This file defines the DenseMap class.
std::string Name
This file contains an interface for creating legacy passes to print out IR in various granularities.
#define I(x, y, z)
Definition: MD5.cpp:58
#define P(N)
ppc ctr loops PowerPC CTR Loops Verify
const char LLVMTargetMachineRef TM
PassInstrumentationCallbacks PIC
This file defines the Pass Instrumentation classes that provide instrumentation points into the pass ...
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:38
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file provides utility classes that use RAII to save and restore values.
This is the interface for a metadata-based scoped no-alias analysis.
This file defines the SmallVector class.
static const char StopAfterOptName[]
static cl::opt< bool > DisableExpandReductions("disable-expand-reductions", cl::init(false), cl::Hidden, cl::desc("Disable the expand reduction intrinsics pass from running"))
Disable the expand reductions pass for testing.
static cl::opt< bool > EnableImplicitNullChecks("enable-implicit-null-checks", cl::desc("Fold null checks into faulting memory operations"), cl::init(false), cl::Hidden)
static cl::opt< bool > DisableMachineSink("disable-machine-sink", cl::Hidden, cl::desc("Disable Machine Sinking"))
static cl::opt< cl::boolOrDefault > DebugifyAndStripAll("debugify-and-strip-all-safe", cl::Hidden, cl::desc("Debugify MIR before and Strip debug after " "each pass except those known to be unsafe " "when debug info is present"))
static llvm::once_flag InitializeDefaultRegisterAllocatorFlag
A dummy default pass factory indicates whether the register allocator is overridden on the command li...
static cl::opt< bool > DisableAtExitBasedGlobalDtorLowering("disable-atexit-based-global-dtor-lowering", cl::Hidden, cl::desc("For MachO, disable atexit()-based global destructor lowering"))
static cl::opt< RegisterRegAlloc::FunctionPassCtor, false, RegisterPassParser< RegisterRegAlloc > > RegAlloc("regalloc", cl::Hidden, cl::init(&useDefaultRegisterAllocator), cl::desc("Register allocator to use"))
static cl::opt< bool > PrintISelInput("print-isel-input", cl::Hidden, cl::desc("Print LLVM IR input to isel pass"))
static FunctionPass * useDefaultRegisterAllocator()
-regalloc=... command line option.
static cl::opt< bool > DisablePostRASched("disable-post-ra", cl::Hidden, cl::desc("Disable Post Regalloc Scheduler"))
static cl::opt< bool > EnableBlockPlacementStats("enable-block-placement-stats", cl::Hidden, cl::desc("Collect probability-driven block placement stats"))
static cl::opt< bool > DisableMachineDCE("disable-machine-dce", cl::Hidden, cl::desc("Disable Machine Dead Code Elimination"))
static void registerPartialPipelineCallback(PassInstrumentationCallbacks &PIC, LLVMTargetMachine &LLVMTM)
static std::string getFSRemappingFile(const TargetMachine *TM)
static const char StopBeforeOptName[]
static AnalysisID getPassIDFromName(StringRef PassName)
static cl::opt< bool > DisableEarlyIfConversion("disable-early-ifcvt", cl::Hidden, cl::desc("Disable Early If-conversion"))
static cl::opt< bool > EnableMachineFunctionSplitter("enable-split-machine-functions", cl::Hidden, cl::desc("Split out cold blocks from machine functions based on profile " "information."))
Enable the machine function splitter pass.
static IdentifyingPassPtr overridePass(AnalysisID StandardID, IdentifyingPassPtr TargetID)
Allow standard passes to be disabled by the command line, regardless of who is adding the pass.
static cl::opt< bool > PrintGCInfo("print-gc", cl::Hidden, cl::desc("Dump garbage collector data"))
static std::pair< StringRef, unsigned > getPassNameAndInstanceNum(StringRef PassName)
static cl::opt< bool > PrintAfterISel("print-after-isel", cl::init(false), cl::Hidden, cl::desc("Print machine instrs after ISel"))
static cl::opt< cl::boolOrDefault > VerifyMachineCode("verify-machineinstrs", cl::Hidden, cl::desc("Verify generated machine code"))
static cl::opt< bool > DisablePartialLibcallInlining("disable-partial-libcall-inlining", cl::Hidden, cl::desc("Disable Partial Libcall Inlining"))
#define SET_BOOLEAN_OPTION(Option)
static cl::opt< std::string > StartAfterOpt(StringRef(StartAfterOptName), cl::desc("Resume compilation after a specific pass"), cl::value_desc("pass-name"), cl::init(""), cl::Hidden)
static cl::opt< bool > DisableBlockPlacement("disable-block-placement", cl::Hidden, cl::desc("Disable probability-driven block placement"))
static cl::opt< bool > DisableRAFSProfileLoader("disable-ra-fsprofile-loader", cl::init(false), cl::Hidden, cl::desc("Disable MIRProfileLoader before RegAlloc"))
static cl::opt< std::string > StopAfterOpt(StringRef(StopAfterOptName), cl::desc("Stop compilation after a specific pass"), cl::value_desc("pass-name"), cl::init(""), cl::Hidden)
static void initializeDefaultRegisterAllocatorOnce()
static cl::opt< bool > PrintLSR("print-lsr-output", cl::Hidden, cl::desc("Print LLVM IR produced by the loop-reduce pass"))
static cl::opt< bool > DisableSelectOptimize("disable-select-optimize", cl::init(true), cl::Hidden, cl::desc("Disable the select-optimization pass from running"))
Disable the select optimization pass.
static cl::opt< std::string > FSRemappingFile("fs-remapping-file", cl::init(""), cl::value_desc("filename"), cl::desc("Flow Sensitive profile remapping file name."), cl::Hidden)
static cl::opt< bool > DisableCFIFixup("disable-cfi-fixup", cl::Hidden, cl::desc("Disable the CFI fixup pass"))
static cl::opt< bool > FSNoFinalDiscrim("fs-no-final-discrim", cl::init(false), cl::Hidden, cl::desc("Do not insert FS-AFDO discriminators before " "emit."))
static cl::opt< bool > DisablePostRAMachineLICM("disable-postra-machine-licm", cl::Hidden, cl::desc("Disable Machine LICM"))
static const char StartBeforeOptName[]
static const PassInfo * getPassInfo(StringRef PassName)
static cl::opt< bool > EarlyLiveIntervals("early-live-intervals", cl::Hidden, cl::desc("Run live interval analysis earlier in the pipeline"))
static cl::opt< bool > DisableMachineLICM("disable-machine-licm", cl::Hidden, cl::desc("Disable Machine LICM"))
static cl::opt< cl::boolOrDefault > EnableGlobalISelOption("global-isel", cl::Hidden, cl::desc("Enable the \"global\" instruction selector"))
static cl::opt< bool > DisableTailDuplicate("disable-tail-duplicate", cl::Hidden, cl::desc("Disable tail duplication"))
static cl::opt< bool > DisablePostRAMachineSink("disable-postra-machine-sink", cl::Hidden, cl::desc("Disable PostRA Machine Sinking"))
static const char StartAfterOptName[]
Option names for limiting the codegen pipeline.
static cl::opt< bool > EnableIPRA("enable-ipra", cl::init(false), cl::Hidden, cl::desc("Enable interprocedural register allocation " "to reduce load/store at procedure calls."))
static cl::opt< bool > DisableCGP("disable-cgp", cl::Hidden, cl::desc("Disable Codegen Prepare"))
static std::string getFSProfileFile(const TargetMachine *TM)
static cl::opt< std::string > StartBeforeOpt(StringRef(StartBeforeOptName), cl::desc("Resume compilation before a specific pass"), cl::value_desc("pass-name"), cl::init(""), cl::Hidden)
static IdentifyingPassPtr applyDisable(IdentifyingPassPtr PassID, bool Override)
Allow standard passes to be disabled by command line options.
static cl::opt< GlobalISelAbortMode > EnableGlobalISelAbort("global-isel-abort", cl::Hidden, cl::desc("Enable abort calls when \"global\" instruction selection " "fails to lower/select an instruction"), cl::values(clEnumValN(GlobalISelAbortMode::Disable, "0", "Disable the abort"), clEnumValN(GlobalISelAbortMode::Enable, "1", "Enable the abort"), clEnumValN(GlobalISelAbortMode::DisableWithDiag, "2", "Disable the abort but emit a diagnostic on failure")))
static cl::opt< bool > DisableEarlyTailDup("disable-early-taildup", cl::Hidden, cl::desc("Disable pre-register allocation tail duplication"))
static cl::opt< bool > DisableConstantHoisting("disable-constant-hoisting", cl::Hidden, cl::desc("Disable ConstantHoisting"))
static cl::opt< cl::boolOrDefault > EnableFastISelOption("fast-isel", cl::Hidden, cl::desc("Enable the \"fast\" instruction selector"))
static cl::opt< bool > DisableSSC("disable-ssc", cl::Hidden, cl::desc("Disable Stack Slot Coloring"))
static cl::opt< bool > DisableBranchFold("disable-branch-fold", cl::Hidden, cl::desc("Disable branch folding"))
#define DISABLE_PASS(Option, Name)
static RegisterRegAlloc defaultRegAlloc("default", "pick register allocator based on -O option", useDefaultRegisterAllocator)
static cl::opt< std::string > StopBeforeOpt(StringRef(StopBeforeOptName), cl::desc("Stop compilation before a specific pass"), cl::value_desc("pass-name"), cl::init(""), cl::Hidden)
static cl::opt< bool > DisableMachineCSE("disable-machine-cse", cl::Hidden, cl::desc("Disable Machine Common Subexpression Elimination"))
static cl::opt< bool > DisableLayoutFSProfileLoader("disable-layout-fsprofile-loader", cl::init(false), cl::Hidden, cl::desc("Disable MIRProfileLoader before BlockPlacement"))
static cl::opt< bool > MISchedPostRA("misched-postra", cl::Hidden, cl::desc("Run MachineScheduler post regalloc (independent of preRA sched)"))
static cl::opt< bool > DisableMergeICmps("disable-mergeicmps", cl::desc("Disable MergeICmps Pass"), cl::init(false), cl::Hidden)
static cl::opt< RunOutliner > EnableMachineOutliner("enable-machine-outliner", cl::desc("Enable the machine outliner"), cl::Hidden, cl::ValueOptional, cl::init(RunOutliner::TargetDefault), cl::values(clEnumValN(RunOutliner::AlwaysOutline, "always", "Run on all functions guaranteed to be beneficial"), clEnumValN(RunOutliner::NeverOutline, "never", "Disable all outlining"), clEnumValN(RunOutliner::AlwaysOutline, "", "")))
static cl::opt< bool > DisableCopyProp("disable-copyprop", cl::Hidden, cl::desc("Disable Copy Propagation pass"))
static cl::opt< cl::boolOrDefault > OptimizeRegAlloc("optimize-regalloc", cl::Hidden, cl::desc("Enable optimized register allocation compilation path."))
static cl::opt< bool > DisableLSR("disable-lsr", cl::Hidden, cl::desc("Disable Loop Strength Reduction Pass"))
static cl::opt< std::string > FSProfileFile("fs-profile-file", cl::init(""), cl::value_desc("filename"), cl::desc("Flow Sensitive profile file name."), cl::Hidden)
static cl::opt< cl::boolOrDefault > DebugifyCheckAndStripAll("debugify-check-and-strip-all-safe", cl::Hidden, cl::desc("Debugify MIR before, by checking and stripping the debug info after, " "each pass except those known to be unsafe when debug info is " "present"))
#define SET_OPTION(Option)
Target-Independent Code Generator Pass Configuration Options pass.
This pass exposes codegen information to IR-level passes.
This is the interface for a metadata-based TBAA.
Defines the virtual file system interface vfs::FileSystem.
static const char PassName[]
Definition: Any.h:28
This pass is required by interprocedural register allocation.
This is a fast-path instruction selection class that generates poor code and doesn't support illegal ...
Definition: FastISel.h:66
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:311
Discriminated union of Pass ID types.
AnalysisID getID() const
ImmutablePass class - This class is used to provide information that does not need to be run.
Definition: Pass.h:282
This class describes a target machine that is implemented with the LLVM target-independent code gener...
virtual bool isMachineVerifierClean() const
Returns true if the target is expected to pass all machine verifier checks.
virtual bool useIPRA() const
True if the target wants to use interprocedural register allocation by default.
virtual TargetPassConfig * createPassConfig(PassManagerBase &PM)
Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of ...
virtual std::pair< StringRef, bool > getPassNameFromLegacyName(StringRef)
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:56
ExceptionHandling getExceptionHandlingType() const
Definition: MCAsmInfo.h:781
DenseMap< AnalysisID, IdentifyingPassPtr > TargetPasses
SmallVector< InsertedPass, 4 > InsertedPasses
Store the pairs of <AnalysisID, AnalysisID> of which the second pass is inserted after each instance ...
PassInfo class - An instance of this class exists for every pass known by the system,...
Definition: PassInfo.h:30
const void * getTypeInfo() const
getTypeInfo - Return the id object for the pass... TODO : Rename
Definition: PassInfo.h:71
This class manages callbacks registration, as well as provides a way for PassInstrumentation to pass ...
void registerShouldRunOptionalPassCallback(CallableT C)
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
Definition: PassRegistry.h:37
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
const PassInfo * getPassInfo(const void *TI) const
getPassInfo - Look up a pass' corresponding PassInfo, indexed by the pass' type identifier (&MyPass::...
Pass interface - Implemented by all 'passes'.
Definition: Pass.h:94
static Pass * createPass(AnalysisID ID)
Definition: Pass.cpp:196
AnalysisID getPassID() const
getPassID - Return the PassID number that corresponds to this pass.
Definition: Pass.h:113
RegisterPassParser class - Handle the addition of new machine passes.
static void setDefault(FunctionPassCtor C)
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:225
reference emplace_back(ArgTypes &&... Args)
Definition: SmallVector.h:941
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1200
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
bool getAsInteger(unsigned Radix, T &Result) const
Parse the current string as an integer of the specified radix.
Definition: StringRef.h:474
constexpr bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:134
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:78
const Triple & getTargetTriple() const
void setFastISel(bool Enable)
CodeGenOpt::Level getOptLevel() const
Returns the optimization level: None, Less, Default, or Aggressive.
const MemoryBuffer * getBBSectionsFuncListBuf() const
Get the list of functions and basic block ids that need unique sections.
bool useEmulatedTLS() const
Returns true if this target uses emulated TLS.
virtual bool targetSchedulesPostRAScheduling() const
True if subtarget inserts the final scheduling pass on its own.
bool requiresStructuredCFG() const
void setGlobalISel(bool Enable)
TargetIRAnalysis getTargetIRAnalysis() const
Get a TargetIRAnalysis appropriate for the target.
TargetOptions Options
void setO0WantsFastISel(bool Enable)
llvm::BasicBlockSection getBBSectionsType() const
If basic blocks should be emitted into their own section, corresponding to -fbasic-block-sections.
const MCAsmInfo * getMCAsmInfo() const
Return target specific asm information.
unsigned EnableMachineOutliner
Enables the MachineOutliner pass.
GlobalISelAbortMode GlobalISelAbort
EnableGlobalISelAbort - Control abort behaviour when global instruction selection fails to lower/sele...
unsigned EnableCFIFixup
Enable the CFIFixup pass.
unsigned SupportsDefaultOutlining
Set if the target supports default outlining behaviour.
unsigned EnableMachineFunctionSplitter
Enables the MachineFunctionSplitter pass.
unsigned EnableIPRA
This flag enables InterProcedural Register Allocation (IPRA).
unsigned EnableGlobalISel
EnableGlobalISel - This flag enables global instruction selection.
Target-Independent Code Generator Pass Configuration Options.
bool usingDefaultRegAlloc() const
Return true if the default global register allocator is in use and has not be overriden on the comman...
bool requiresCodeGenSCCOrder() const
void addCheckDebugPass()
Add a pass to check synthesized debug info for MIR.
LLVMTargetMachine * TM
virtual void addPreLegalizeMachineIR()
This method may be implemented by targets that want to run passes immediately before legalization.
void addPrintPass(const std::string &Banner)
Add a pass to print the machine function if printing is enabled.
virtual void addPreEmitPass2()
Targets may add passes immediately before machine code is emitted in this callback.
virtual std::unique_ptr< CSEConfigBase > getCSEConfig() const
Returns the CSEConfig object to use for the current optimization level.
void printAndVerify(const std::string &Banner)
printAndVerify - Add a pass to dump then verify the machine function, if those steps are enabled.
static std::string getLimitedCodeGenPipelineReason(const char *Separator="/")
If hasLimitedCodeGenPipeline is true, this method returns a string with the name of the options,...
static bool hasLimitedCodeGenPipeline()
Returns true if one of the -start-after, -start-before, -stop-after or -stop-before options is set.
virtual void addCodeGenPrepare()
Add pass to prepare the LLVM IR for code generation.
void insertPass(AnalysisID TargetPassID, IdentifyingPassPtr InsertedPassID)
Insert InsertedPassID pass after TargetPassID pass.
void addMachinePostPasses(const std::string &Banner)
Add standard passes after a pass that has just been added.
virtual void addPreSched2()
This method may be implemented by targets that want to run passes after prolog-epilog insertion and b...
virtual bool isGISelCSEEnabled() const
Check whether continuous CSE should be enabled in GISel passes.
virtual bool addILPOpts()
Add passes that optimize instruction level parallelism for out-of-order targets.
virtual void addPostRegAlloc()
This method may be implemented by targets that want to run passes after register allocation pass pipe...
void addDebugifyPass()
Add a pass to add synthesized debug info to the MIR.
virtual bool addInstSelector()
addInstSelector - This method should install an instruction selector pass, which converts from LLVM c...
virtual bool addPreISel()
Methods with trivial inline returns are convenient points in the common codegen pass pipeline where t...
void setOpt(bool &Opt, bool Val)
virtual void addBlockPlacement()
Add standard basic block placement passes.
virtual FunctionPass * createRegAllocPass(bool Optimized)
addMachinePasses helper to create the target-selected or overriden regalloc pass.
virtual void addOptimizedRegAlloc()
addOptimizedRegAlloc - Add passes related to register allocation.
virtual bool addRegAssignAndRewriteFast()
Add core register allocator passes which do the actual register assignment and rewriting.
virtual void addPreEmitPass()
This pass may be implemented by targets that want to run passes immediately before machine code is em...
bool isGlobalISelAbortEnabled() const
Check whether or not GlobalISel should abort on error.
bool getOptimizeRegAlloc() const
Return true if the optimized regalloc pipeline is enabled.
bool isCustomizedRegAlloc()
Return true if register allocator is specified by -regalloc=override.
virtual void addPreRegBankSelect()
This method may be implemented by targets that want to run passes immediately before the register ban...
virtual bool reportDiagnosticWhenGlobalISelFallback() const
Check whether or not a diagnostic should be emitted when GlobalISel uses the fallback path.
virtual bool addPreRewrite()
addPreRewrite - Add passes to the optimized register allocation pipeline after register allocation is...
virtual bool addRegBankSelect()
This method should install a register bank selector pass, which assigns register banks to virtual reg...
CodeGenOpt::Level getOptLevel() const
void setRequiresCodeGenSCCOrder(bool Enable=true)
virtual void addMachineLateOptimization()
Add passes that optimize machine instructions after register allocation.
virtual void addMachinePasses()
Add the complete, standard set of LLVM CodeGen passes.
virtual void addIRPasses()
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
virtual void addPreGlobalInstructionSelect()
This method may be implemented by targets that want to run passes immediately before the (global) ins...
virtual void addFastRegAlloc()
addFastRegAlloc - Add the minimum set of target-independent passes that are required for fast registe...
virtual bool addLegalizeMachineIR()
This method should install a legalize pass, which converts the instruction sequence into one that can...
virtual void addMachineSSAOptimization()
addMachineSSAOptimization - Add standard passes that optimize machine instructions in SSA form.
void substitutePass(AnalysisID StandardID, IdentifyingPassPtr TargetID)
Allow the target to override a specific pass without overriding the pass pipeline.
virtual bool addRegAssignAndRewriteOptimized()
virtual bool addGlobalInstructionSelect()
This method should install a (global) instruction selector pass, which converts possibly generic inst...
virtual void addPreRegAlloc()
This method may be implemented by targets that want to run passes immediately before register allocat...
AnalysisID addPass(AnalysisID PassID)
Utilities for targets to add passes to the pass manager.
void addPassesToHandleExceptions()
Add passes to lower exception handling for the code generator.
void addStripDebugPass()
Add a pass to remove debug info from the MIR.
bool isPassSubstitutedOrOverridden(AnalysisID ID) const
Return true if the pass has been substituted by the target or overridden on the command line.
bool addCoreISelPasses()
Add the actual instruction selection passes.
virtual void addISelPrepare()
Add common passes that perform LLVM IR to IR transforms in preparation for instruction selection.
static bool willCompleteCodeGenPipeline()
Returns true if none of the -stop-before and -stop-after options is set.
void addMachinePrePasses(bool AllowDebugify=true)
Add standard passes before a pass that's about to be added.
virtual bool addGCPasses()
addGCPasses - Add late codegen passes that analyze code for garbage collection.
virtual bool addIRTranslator()
This method should install an IR translator pass, which converts from LLVM code to machine instructio...
void addVerifyPass(const std::string &Banner)
Add a pass to perform basic verification of the machine function if verification is enabled.
virtual FunctionPass * createTargetRegisterAllocator(bool Optimized)
createTargetRegisterAllocator - Create the register allocator pass for this target at the current opt...
virtual bool addPostFastRegAllocRewrite()
addPostFastRegAllocRewrite - Add passes to the optimized register allocation pipeline after fast regi...
IdentifyingPassPtr getPassSubstitution(AnalysisID StandardID) const
Return the pass substituted for StandardID by the target.
bool addISelPasses()
High level function that adds all passes necessary to go from llvm IR representation to the MI repres...
virtual void addPostRewrite()
Add passes to be run immediately after virtual registers are rewritten to physical registers.
bool isOSBinFormatMachO() const
Tests whether the environment is MachO.
Definition: Triple.h:688
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:81
PassManagerBase - An abstract interface to allow code to add passes to a pass manager without having ...
virtual void add(Pass *P)=0
Add a pass to the queue of passes to run.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Code generation optimization level.
Definition: CodeGen.h:57
@ ValueOptional
Definition: CommandLine.h:131
ValuesClass values(OptsTy... Options)
Helper to build a ValuesClass by forwarding a variable number of arguments as an initializer list to ...
Definition: CommandLine.h:703
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:445
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
FunctionPass * createFastRegisterAllocator()
FastRegisterAllocation Pass - This pass register allocates as fast as possible.
char & EarlyMachineLICMID
This pass performs loop invariant code motion on machine instructions.
char & GCMachineCodeAnalysisID
GCMachineCodeAnalysis - Target-independent pass to mark safe points in machine code.
ModulePass * createPreISelIntrinsicLoweringPass()
This pass lowers the @llvm.load.relative and @llvm.objc.
char & FEntryInserterID
This pass inserts FEntry calls.
FunctionPass * createUnreachableBlockEliminationPass()
createUnreachableBlockEliminationPass - The LLVM code generator does not work well with unreachable b...
FunctionPass * createSjLjEHPreparePass(const TargetMachine *TM)
createSjLjEHPreparePass - This pass adapts exception handling code to use the GCC-style builtin setjm...
FunctionPass * createTLSVariableHoistPass()
char & GCLoweringID
GCLowering Pass - Used by gc.root to perform its default lowering operations.
char & RegisterCoalescerID
RegisterCoalescer - This pass merges live ranges to eliminate copies.
FunctionPass * createGreedyRegisterAllocator()
Greedy register allocation pass - This pass implements a global register allocator for optimized buil...
FunctionPass * createConstantHoistingPass()
char & OptimizePHIsID
OptimizePHIs - This pass optimizes machine instruction PHIs to take advantage of opportunities create...
FunctionPass * createSafeStackPass()
This pass splits the stack into a safe stack and an unsafe stack to protect against stack-based overf...
Definition: SafeStack.cpp:939
char & EarlyTailDuplicateID
Duplicate blocks with unconditional branches into tails of their predecessors.
void registerCodeGenCallback(PassInstrumentationCallbacks &PIC, LLVMTargetMachine &)
char & MachineSinkingID
MachineSinking - This pass performs sinking on machine instructions.
@ SjLj
setjmp/longjmp based exceptions
@ None
No exception support.
AIX Exception Handling.
@ DwarfCFI
DWARF-like instruction based exceptions.
@ WinEH
Windows Exception Handling.
@ Wasm
WebAssembly Exception Handling.
FunctionPass * createSelectOptimizePass()
This pass converts conditional moves to conditional jumps when profitable.
FunctionPass * createWasmEHPass()
createWasmEHPass - This pass adapts exception handling code to use WebAssembly's exception handling s...
char & FixupStatepointCallerSavedID
The pass fixups statepoint machine instruction to replace usage of caller saved registers with stack ...
FunctionPass * createExpandVectorPredicationPass()
This pass expands the vector predication intrinsics into unpredicated instructions with selects or ju...
MachineFunctionPass * createBasicBlockSectionsPass()
createBasicBlockSections Pass - This pass assigns sections to machine basic blocks and is enabled wit...
MachineFunctionPass * createPrologEpilogInserterPass()
char & TailDuplicateID
TailDuplicate - Duplicate blocks with unconditional branches into tails of their predecessors.
ModulePass * createStripDebugMachineModulePass(bool OnlyDebugified)
Creates MIR Strip Debug pass.
char & ExpandPostRAPseudosID
ExpandPostRAPseudos - This pass expands pseudo instructions after register allocation.
char & PatchableFunctionID
This pass implements the "patchable-function" attribute.
FunctionPass * createScalarizeMaskedMemIntrinLegacyPass()
ModulePass * createLowerEmuTLSPass()
LowerEmuTLS - This pass generates __emutls_[vt].xyz variables for all TLS variables for the emulated ...
char & PostRASchedulerID
PostRAScheduler - This pass performs post register allocation scheduling.
FunctionPass * createStackProtectorPass()
createStackProtectorPass - This pass adds stack protectors to functions.
char & MachineSchedulerID
MachineScheduler - This pass schedules machine instructions.
char & PeepholeOptimizerID
PeepholeOptimizer - This pass performs peephole optimizations - like extension and comparison elimina...
char & PostMachineSchedulerID
PostMachineScheduler - This pass schedules machine instructions postRA.
char & LiveDebugValuesID
LiveDebugValues pass.
char & PrologEpilogCodeInserterID
PrologEpilogCodeInserter - This pass inserts prolog and epilog code, and eliminates abstract frame re...
FunctionPass * createExpandLargeFpConvertPass()
FunctionPass * createDwarfEHPass(CodeGenOpt::Level OptLevel)
createDwarfEHPass - This pass mulches exception handling code into a form adapted to code generation.
char & MachineLoopInfoID
MachineLoopInfo - This pass is a loop analysis pass.
cl::opt< bool > EnableFSDiscriminator
char & ShadowStackGCLoweringID
ShadowStackGCLowering - Implements the custom lowering mechanism used by the shadow stack GC.
MachineFunctionPass * createStackFrameLayoutAnalysisPass()
StackFramePrinter pass - This pass prints out the machine function's stack frame to the given stream ...
FunctionPass * createMIRAddFSDiscriminatorsPass(sampleprof::FSDiscriminatorPass P)
Add Flow Sensitive Discriminators.
char & MachineSanitizerBinaryMetadataID
char & ImplicitNullChecksID
ImplicitNullChecks - This pass folds null pointer checks into nearby memory operations.
void initializeAAResultsWrapperPassPass(PassRegistry &)
char & ShrinkWrapID
ShrinkWrap pass. Look for the best place to insert save and restore.
Definition: ShrinkWrap.cpp:278
char & MachineLateInstrsCleanupID
MachineLateInstrsCleanup - This pass removes redundant identical instructions after register allocati...
ImmutablePass * createScopedNoAliasAAWrapperPass()
ModulePass * createLowerGlobalDtorsLegacyPass()
FunctionPass * createLowerInvokePass()
Definition: LowerInvoke.cpp:85
FunctionPass * createRegUsageInfoCollector()
This pass is executed POST-RA to collect which physical registers are preserved by given machine func...
FunctionPass * createExpandMemCmpPass()
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
char & XRayInstrumentationID
This pass inserts the XRay instrumentation sleds if they are supported by the target platform.
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:145
char & StackMapLivenessID
StackMapLiveness - This pass analyses the register live-out set of stackmap/patchpoint intrinsics and...
char & FuncletLayoutID
This pass lays out funclets contiguously.
FunctionPass * createGCInfoPrinter(raw_ostream &OS)
Creates a pass to print GC metadata.
Definition: GCMetadata.cpp:89
char & RemoveRedundantDebugValuesID
RemoveRedundantDebugValues pass.
FunctionPass * createBasicAAWrapperPass()
char & DetectDeadLanesID
This pass adds dead/undef flags after analyzing subregister lanes.
char & StackColoringID
StackSlotColoring - This pass performs stack coloring and merging.
char & PostRAMachineSinkingID
This pass perform post-ra machine sink for COPY instructions.
FunctionPass * createRegAllocScoringPass()
When learning an eviction policy, extract score(reward) information, otherwise this does nothing.
ModulePass * createMachineOutlinerPass(bool RunOnAllFunctions=true)
This pass performs outlining on machine instructions directly before printing assembly.
const void * AnalysisID
Definition: Pass.h:50
char & StackSlotColoringID
StackSlotColoring - This pass performs stack slot coloring.
char & EarlyIfConverterID
EarlyIfConverter - This pass performs if-conversion on SSA form by inserting cmov instructions.
FunctionPass * createExpandLargeDivRemPass()
Pass * createMergeICmpsLegacyPass()
Definition: MergeICmps.cpp:955
char & ProcessImplicitDefsID
ProcessImpicitDefs pass - This pass removes IMPLICIT_DEFs.
ModulePass * createCheckDebugMachineModulePass()
Creates MIR Check Debug pass.
ImmutablePass * createTargetTransformInfoWrapperPass(TargetIRAnalysis TIRA)
Create an analysis pass wrapper around a TTI object.
ImmutablePass * createTypeBasedAAWrapperPass()
FunctionPass * createMIRProfileLoaderPass(std::string File, std::string RemappingFile, sampleprof::FSDiscriminatorPass P, IntrusiveRefCntPtr< vfs::FileSystem > FS)
Read Flow Sensitive Profile.
FunctionPass * createCFIFixup()
Creates CFI Fixup pass.
char & MachineCSEID
MachineCSE - This pass performs global CSE on machine instructions.
Definition: MachineCSE.cpp:162
FunctionPass * createVerifierPass(bool FatalErrors=true)
Definition: Verifier.cpp:6937
void initializeBasicAAWrapperPassPass(PassRegistry &)
MachineFunctionPass * createMachineFunctionPrinterPass(raw_ostream &OS, const std::string &Banner="")
MachineFunctionPrinter pass - This pass prints out the machine function to the given stream as a debu...
Pass * createLoopStrengthReducePass()
char & LiveVariablesID
LiveVariables pass - This pass computes the set of blocks in which each variable is life and sets mac...
FunctionPass * createExpandReductionsPass()
This pass expands the reduction intrinsics into sequences of shuffles.
MachineFunctionPass * createMachineFunctionSplitterPass()
createMachineFunctionSplitterPass - This pass splits machine functions using profile information.
void call_once(once_flag &flag, Function &&F, Args &&... ArgList)
Execute the function specified as a parameter once.
Definition: Threading.h:87
MachineFunctionPass * createResetMachineFunctionPass(bool EmitFallbackDiag, bool AbortOnFailedISel)
This pass resets a MachineFunction when it has the FailedISel property as if it was just created.
char & VirtRegRewriterID
VirtRegRewriter pass.
Definition: VirtRegMap.cpp:227
FunctionPass * createReplaceWithVeclibLegacyPass()
FunctionPass * createLowerConstantIntrinsicsPass()
ImmutablePass * createBasicBlockSectionsProfileReaderPass(const MemoryBuffer *Buf)
char & FinalizeISelID
This pass expands pseudo-instructions, reserves registers and adjusts machine frame information.
FunctionPass * createCodeGenPreparePass()
createCodeGenPreparePass - Transform the code to expose more pattern matching during instruction sele...
FunctionPass * createRegUsageInfoPropPass()
Return a MachineFunction pass that identifies call sites and propagates register usage information of...
FunctionPass * createPartiallyInlineLibCallsPass()
char & UnreachableMachineBlockElimID
UnreachableMachineBlockElimination - This pass removes unreachable machine basic blocks.
char & MachineBlockPlacementID
MachineBlockPlacement - This pass places basic blocks based on branch probabilities.
char & TwoAddressInstructionPassID
TwoAddressInstruction - This pass reduces two-address instructions to use two operands.
Pass * createCanonicalizeFreezeInLoopsPass()
char & LocalStackSlotAllocationID
LocalStackSlotAllocation - This pass assigns local frame indices to stack slots relative to one anoth...
char & BranchFolderPassID
BranchFolding - This pass performs machine code CFG based optimizations to delete branches to branche...
char & PHIEliminationID
PHIElimination - This pass eliminates machine instruction PHI nodes by inserting copy instructions.
ModulePass * createDebugifyMachineModulePass()
Creates MIR Debugify pass.
FunctionPass * createPrintFunctionPass(raw_ostream &OS, const std::string &Banner="")
Create and return a pass that prints functions to the specified raw_ostream as they are processed.
FunctionPass * createCallBrPass()
char & RenameIndependentSubregsID
This pass detects subregister lanes in a virtual register that are used independently of other lanes ...
char & MachineLICMID
This pass performs loop invariant code motion on machine instructions.
char & MachineBlockPlacementStatsID
MachineBlockPlacementStats - This pass collects statistics about the basic block placement using bran...
char & LiveIntervalsID
LiveIntervals - This analysis keeps track of the live ranges of virtual and physical registers.
char & MachineCopyPropagationID
MachineCopyPropagation - This pass performs copy propagation on machine instructions.
char & DeadMachineInstructionElimID
DeadMachineInstructionElim - This pass removes dead machine instructions.
void initializeCodeGen(PassRegistry &)
Initialize all passes linked into the CodeGen library.
Definition: CodeGen.cpp:20
FunctionPass * createMachineVerifierPass(const std::string &Banner)
createMachineVerifierPass - This pass verifies cenerated machine code instructions for correctness.
FunctionPass * createWinEHPass(bool DemoteCatchSwitchPHIOnly=false)
createWinEHPass - Prepares personality functions used by MSVC on Windows, in addition to the Itanium ...
CGPassBuilderOption getCGPassBuilderOption()
InsertedPass(AnalysisID TargetPassID, IdentifyingPassPtr InsertedPassID)
A utility class that uses RAII to save and restore the value of a variable.
The llvm::once_flag structure.
Definition: Threading.h:68