LLVM  15.0.0git
TargetPassConfig.cpp
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1 //===- TargetPassConfig.cpp - Target independent code generation passes ---===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines interfaces to access the target independent code
10 // generation passes provided by the LLVM backend.
11 //
12 //===---------------------------------------------------------------------===//
13 
15 #include "llvm/ADT/DenseMap.h"
16 #include "llvm/ADT/SmallVector.h"
17 #include "llvm/ADT/StringRef.h"
29 #include "llvm/CodeGen/Passes.h"
34 #include "llvm/IR/Verifier.h"
35 #include "llvm/InitializePasses.h"
36 #include "llvm/MC/MCAsmInfo.h"
38 #include "llvm/Pass.h"
39 #include "llvm/Support/CodeGen.h"
41 #include "llvm/Support/Compiler.h"
42 #include "llvm/Support/Debug.h"
46 #include "llvm/Support/Threading.h"
49 #include "llvm/Transforms/Scalar.h"
50 #include "llvm/Transforms/Utils.h"
51 #include <cassert>
52 #include <string>
53 
54 using namespace llvm;
55 
56 static cl::opt<bool>
57  EnableIPRA("enable-ipra", cl::init(false), cl::Hidden,
58  cl::desc("Enable interprocedural register allocation "
59  "to reduce load/store at procedure calls."));
60 static cl::opt<bool> DisablePostRASched("disable-post-ra", cl::Hidden,
61  cl::desc("Disable Post Regalloc Scheduler"));
62 static cl::opt<bool> DisableBranchFold("disable-branch-fold", cl::Hidden,
63  cl::desc("Disable branch folding"));
64 static cl::opt<bool> DisableTailDuplicate("disable-tail-duplicate", cl::Hidden,
65  cl::desc("Disable tail duplication"));
66 static cl::opt<bool> DisableEarlyTailDup("disable-early-taildup", cl::Hidden,
67  cl::desc("Disable pre-register allocation tail duplication"));
68 static cl::opt<bool> DisableBlockPlacement("disable-block-placement",
69  cl::Hidden, cl::desc("Disable probability-driven block placement"));
70 static cl::opt<bool> EnableBlockPlacementStats("enable-block-placement-stats",
71  cl::Hidden, cl::desc("Collect probability-driven block placement stats"));
72 static cl::opt<bool> DisableSSC("disable-ssc", cl::Hidden,
73  cl::desc("Disable Stack Slot Coloring"));
74 static cl::opt<bool> DisableMachineDCE("disable-machine-dce", cl::Hidden,
75  cl::desc("Disable Machine Dead Code Elimination"));
76 static cl::opt<bool> DisableEarlyIfConversion("disable-early-ifcvt", cl::Hidden,
77  cl::desc("Disable Early If-conversion"));
78 static cl::opt<bool> DisableMachineLICM("disable-machine-licm", cl::Hidden,
79  cl::desc("Disable Machine LICM"));
80 static cl::opt<bool> DisableMachineCSE("disable-machine-cse", cl::Hidden,
81  cl::desc("Disable Machine Common Subexpression Elimination"));
83  "optimize-regalloc", cl::Hidden,
84  cl::desc("Enable optimized register allocation compilation path."));
85 static cl::opt<bool> DisablePostRAMachineLICM("disable-postra-machine-licm",
86  cl::Hidden,
87  cl::desc("Disable Machine LICM"));
88 static cl::opt<bool> DisableMachineSink("disable-machine-sink", cl::Hidden,
89  cl::desc("Disable Machine Sinking"));
90 static cl::opt<bool> DisablePostRAMachineSink("disable-postra-machine-sink",
91  cl::Hidden,
92  cl::desc("Disable PostRA Machine Sinking"));
93 static cl::opt<bool> DisableLSR("disable-lsr", cl::Hidden,
94  cl::desc("Disable Loop Strength Reduction Pass"));
95 static cl::opt<bool> DisableConstantHoisting("disable-constant-hoisting",
96  cl::Hidden, cl::desc("Disable ConstantHoisting"));
97 static cl::opt<bool> DisableCGP("disable-cgp", cl::Hidden,
98  cl::desc("Disable Codegen Prepare"));
99 static cl::opt<bool> DisableCopyProp("disable-copyprop", cl::Hidden,
100  cl::desc("Disable Copy Propagation pass"));
101 static cl::opt<bool> DisablePartialLibcallInlining("disable-partial-libcall-inlining",
102  cl::Hidden, cl::desc("Disable Partial Libcall Inlining"));
104  "enable-implicit-null-checks",
105  cl::desc("Fold null checks into faulting memory operations"),
106  cl::init(false), cl::Hidden);
107 static cl::opt<bool> DisableMergeICmps("disable-mergeicmps",
108  cl::desc("Disable MergeICmps Pass"),
109  cl::init(false), cl::Hidden);
110 static cl::opt<bool> PrintLSR("print-lsr-output", cl::Hidden,
111  cl::desc("Print LLVM IR produced by the loop-reduce pass"));
112 static cl::opt<bool> PrintISelInput("print-isel-input", cl::Hidden,
113  cl::desc("Print LLVM IR input to isel pass"));
114 static cl::opt<bool> PrintGCInfo("print-gc", cl::Hidden,
115  cl::desc("Dump garbage collector data"));
117  VerifyMachineCode("verify-machineinstrs", cl::Hidden,
118  cl::desc("Verify generated machine code"));
120  DebugifyAndStripAll("debugify-and-strip-all-safe", cl::Hidden,
121  cl::desc("Debugify MIR before and Strip debug after "
122  "each pass except those known to be unsafe "
123  "when debug info is present"));
125  "debugify-check-and-strip-all-safe", cl::Hidden,
126  cl::desc(
127  "Debugify MIR before, by checking and stripping the debug info after, "
128  "each pass except those known to be unsafe when debug info is "
129  "present"));
130 // Enable or disable the MachineOutliner.
132  "enable-machine-outliner", cl::desc("Enable the machine outliner"),
135  "Run on all functions guaranteed to be beneficial"),
137  "Disable all outlining"),
138  // Sentinel value for unspecified option.
140 // Disable the pass to fix unwind information. Whether the pass is included in
141 // the pipeline is controlled via the target options, this option serves as
142 // manual override.
143 static cl::opt<bool> DisableCFIFixup("disable-cfi-fixup", cl::Hidden,
144  cl::desc("Disable the CFI fixup pass"));
145 // Enable or disable FastISel. Both options are needed, because
146 // FastISel is enabled by default with -fast, and we wish to be
147 // able to enable or disable fast-isel independently from -O0.
149 EnableFastISelOption("fast-isel", cl::Hidden,
150  cl::desc("Enable the \"fast\" instruction selector"));
151 
153  "global-isel", cl::Hidden,
154  cl::desc("Enable the \"global\" instruction selector"));
155 
156 // FIXME: remove this after switching to NPM or GlobalISel, whichever gets there
157 // first...
158 static cl::opt<bool>
159  PrintAfterISel("print-after-isel", cl::init(false), cl::Hidden,
160  cl::desc("Print machine instrs after ISel"));
161 
163  "global-isel-abort", cl::Hidden,
164  cl::desc("Enable abort calls when \"global\" instruction selection "
165  "fails to lower/select an instruction"),
166  cl::values(
167  clEnumValN(GlobalISelAbortMode::Disable, "0", "Disable the abort"),
168  clEnumValN(GlobalISelAbortMode::Enable, "1", "Enable the abort"),
170  "Disable the abort but emit a diagnostic on failure")));
171 
172 // An option that disables inserting FS-AFDO discriminators before emit.
173 // This is mainly for debugging and tuning purpose.
174 static cl::opt<bool>
175  FSNoFinalDiscrim("fs-no-final-discrim", cl::init(false), cl::Hidden,
176  cl::desc("Do not insert FS-AFDO discriminators before "
177  "emit."));
178 // Disable MIRProfileLoader before RegAlloc. This is for for debugging and
179 // tuning purpose.
181  "disable-ra-fsprofile-loader", cl::init(false), cl::Hidden,
182  cl::desc("Disable MIRProfileLoader before RegAlloc"));
183 // Disable MIRProfileLoader before BloackPlacement. This is for for debugging
184 // and tuning purpose.
186  "disable-layout-fsprofile-loader", cl::init(false), cl::Hidden,
187  cl::desc("Disable MIRProfileLoader before BlockPlacement"));
188 // Specify FSProfile file name.
190  FSProfileFile("fs-profile-file", cl::init(""), cl::value_desc("filename"),
191  cl::desc("Flow Sensitive profile file name."), cl::Hidden);
192 // Specify Remapping file for FSProfile.
194  "fs-remapping-file", cl::init(""), cl::value_desc("filename"),
195  cl::desc("Flow Sensitive profile remapping file name."), cl::Hidden);
196 
197 // Temporary option to allow experimenting with MachineScheduler as a post-RA
198 // scheduler. Targets can "properly" enable this with
199 // substitutePass(&PostRASchedulerID, &PostMachineSchedulerID).
200 // Targets can return true in targetSchedulesPostRAScheduling() and
201 // insert a PostRA scheduling pass wherever it wants.
203  "misched-postra", cl::Hidden,
204  cl::desc(
205  "Run MachineScheduler post regalloc (independent of preRA sched)"));
206 
207 // Experimental option to run live interval analysis early.
208 static cl::opt<bool> EarlyLiveIntervals("early-live-intervals", cl::Hidden,
209  cl::desc("Run live interval analysis earlier in the pipeline"));
210 
211 // Experimental option to use CFL-AA in codegen
213  "use-cfl-aa-in-codegen", cl::init(CFLAAType::None), cl::Hidden,
214  cl::desc("Enable the new, experimental CFL alias analysis in CodeGen"),
215  cl::values(clEnumValN(CFLAAType::None, "none", "Disable CFL-AA"),
217  "Enable unification-based CFL-AA"),
219  "Enable inclusion-based CFL-AA"),
220  clEnumValN(CFLAAType::Both, "both",
221  "Enable both variants of CFL-AA")));
222 
223 /// Option names for limiting the codegen pipeline.
224 /// Those are used in error reporting and we didn't want
225 /// to duplicate their names all over the place.
226 static const char StartAfterOptName[] = "start-after";
227 static const char StartBeforeOptName[] = "start-before";
228 static const char StopAfterOptName[] = "stop-after";
229 static const char StopBeforeOptName[] = "stop-before";
230 
233  cl::desc("Resume compilation after a specific pass"),
234  cl::value_desc("pass-name"), cl::init(""), cl::Hidden);
235 
238  cl::desc("Resume compilation before a specific pass"),
239  cl::value_desc("pass-name"), cl::init(""), cl::Hidden);
240 
243  cl::desc("Stop compilation after a specific pass"),
244  cl::value_desc("pass-name"), cl::init(""), cl::Hidden);
245 
248  cl::desc("Stop compilation before a specific pass"),
249  cl::value_desc("pass-name"), cl::init(""), cl::Hidden);
250 
251 /// Enable the machine function splitter pass.
253  "enable-split-machine-functions", cl::Hidden,
254  cl::desc("Split out cold blocks from machine functions based on profile "
255  "information."));
256 
257 /// Disable the expand reductions pass for testing.
259  "disable-expand-reductions", cl::init(false), cl::Hidden,
260  cl::desc("Disable the expand reduction intrinsics pass from running"));
261 
262 /// Disable the select optimization pass.
264  "disable-select-optimize", cl::init(true), cl::Hidden,
265  cl::desc("Disable the select-optimization pass from running"));
266 
267 /// Allow standard passes to be disabled by command line options. This supports
268 /// simple binary flags that either suppress the pass or do nothing.
269 /// i.e. -disable-mypass=false has no effect.
270 /// These should be converted to boolOrDefault in order to use applyOverride.
272  bool Override) {
273  if (Override)
274  return IdentifyingPassPtr();
275  return PassID;
276 }
277 
278 /// Allow standard passes to be disabled by the command line, regardless of who
279 /// is adding the pass.
280 ///
281 /// StandardID is the pass identified in the standard pass pipeline and provided
282 /// to addPass(). It may be a target-specific ID in the case that the target
283 /// directly adds its own pass, but in that case we harmlessly fall through.
284 ///
285 /// TargetID is the pass that the target has configured to override StandardID.
286 ///
287 /// StandardID may be a pseudo ID. In that case TargetID is the name of the real
288 /// pass to run. This allows multiple options to control a single pass depending
289 /// on where in the pipeline that pass is added.
291  IdentifyingPassPtr TargetID) {
292  if (StandardID == &PostRASchedulerID)
293  return applyDisable(TargetID, DisablePostRASched);
294 
295  if (StandardID == &BranchFolderPassID)
296  return applyDisable(TargetID, DisableBranchFold);
297 
298  if (StandardID == &TailDuplicateID)
299  return applyDisable(TargetID, DisableTailDuplicate);
300 
301  if (StandardID == &EarlyTailDuplicateID)
302  return applyDisable(TargetID, DisableEarlyTailDup);
303 
304  if (StandardID == &MachineBlockPlacementID)
305  return applyDisable(TargetID, DisableBlockPlacement);
306 
307  if (StandardID == &StackSlotColoringID)
308  return applyDisable(TargetID, DisableSSC);
309 
310  if (StandardID == &DeadMachineInstructionElimID)
311  return applyDisable(TargetID, DisableMachineDCE);
312 
313  if (StandardID == &EarlyIfConverterID)
314  return applyDisable(TargetID, DisableEarlyIfConversion);
315 
316  if (StandardID == &EarlyMachineLICMID)
317  return applyDisable(TargetID, DisableMachineLICM);
318 
319  if (StandardID == &MachineCSEID)
320  return applyDisable(TargetID, DisableMachineCSE);
321 
322  if (StandardID == &MachineLICMID)
323  return applyDisable(TargetID, DisablePostRAMachineLICM);
324 
325  if (StandardID == &MachineSinkingID)
326  return applyDisable(TargetID, DisableMachineSink);
327 
328  if (StandardID == &PostRAMachineSinkingID)
329  return applyDisable(TargetID, DisablePostRAMachineSink);
330 
331  if (StandardID == &MachineCopyPropagationID)
332  return applyDisable(TargetID, DisableCopyProp);
333 
334  return TargetID;
335 }
336 
337 // Find the FSProfile file name. The internal option takes the precedence
338 // before getting from TargetMachine.
339 static std::string getFSProfileFile(const TargetMachine *TM) {
340  if (!FSProfileFile.empty())
341  return FSProfileFile.getValue();
342  const Optional<PGOOptions> &PGOOpt = TM->getPGOOption();
343  if (PGOOpt == None || PGOOpt->Action != PGOOptions::SampleUse)
344  return std::string();
345  return PGOOpt->ProfileFile;
346 }
347 
348 // Find the Profile remapping file name. The internal option takes the
349 // precedence before getting from TargetMachine.
350 static std::string getFSRemappingFile(const TargetMachine *TM) {
351  if (!FSRemappingFile.empty())
352  return FSRemappingFile.getValue();
353  const Optional<PGOOptions> &PGOOpt = TM->getPGOOption();
354  if (PGOOpt == None || PGOOpt->Action != PGOOptions::SampleUse)
355  return std::string();
356  return PGOOpt->ProfileRemappingFile;
357 }
358 
359 //===---------------------------------------------------------------------===//
360 /// TargetPassConfig
361 //===---------------------------------------------------------------------===//
362 
363 INITIALIZE_PASS(TargetPassConfig, "targetpassconfig",
364  "Target Pass Configuration", false, false)
365 char TargetPassConfig::ID = 0;
366 
367 namespace {
368 
369 struct InsertedPass {
372 
373  InsertedPass(AnalysisID TargetPassID, IdentifyingPassPtr InsertedPassID)
374  : TargetPassID(TargetPassID), InsertedPassID(InsertedPassID) {}
375 
377  assert(InsertedPassID.isValid() && "Illegal Pass ID!");
378  if (InsertedPassID.isInstance())
379  return InsertedPassID.getInstance();
380  Pass *NP = Pass::createPass(InsertedPassID.getID());
381  assert(NP && "Pass ID not registered");
382  return NP;
383  }
384 };
385 
386 } // end anonymous namespace
387 
388 namespace llvm {
389 
391 
393 public:
394  // List of passes explicitly substituted by this target. Normally this is
395  // empty, but it is a convenient way to suppress or replace specific passes
396  // that are part of a standard pass pipeline without overridding the entire
397  // pipeline. This mechanism allows target options to inherit a standard pass's
398  // user interface. For example, a target may disable a standard pass by
399  // default by substituting a pass ID of zero, and the user may still enable
400  // that standard pass with an explicit command line option.
402 
403  /// Store the pairs of <AnalysisID, AnalysisID> of which the second pass
404  /// is inserted after each instance of the first one.
406 };
407 
408 } // end namespace llvm
409 
410 // Out of line virtual method.
412  delete Impl;
413 }
414 
416  if (PassName.empty())
417  return nullptr;
418 
420  const PassInfo *PI = PR.getPassInfo(PassName);
421  if (!PI)
423  Twine("\" pass is not registered."));
424  return PI;
425 }
426 
428  const PassInfo *PI = getPassInfo(PassName);
429  return PI ? PI->getTypeInfo() : nullptr;
430 }
431 
432 static std::pair<StringRef, unsigned>
434  StringRef Name, InstanceNumStr;
435  std::tie(Name, InstanceNumStr) = PassName.split(',');
436 
437  unsigned InstanceNum = 0;
438  if (!InstanceNumStr.empty() && InstanceNumStr.getAsInteger(10, InstanceNum))
439  report_fatal_error("invalid pass instance specifier " + PassName);
440 
441  return std::make_pair(Name, InstanceNum);
442 }
443 
444 void TargetPassConfig::setStartStopPasses() {
445  StringRef StartBeforeName;
446  std::tie(StartBeforeName, StartBeforeInstanceNum) =
448 
449  StringRef StartAfterName;
450  std::tie(StartAfterName, StartAfterInstanceNum) =
452 
453  StringRef StopBeforeName;
454  std::tie(StopBeforeName, StopBeforeInstanceNum)
456 
457  StringRef StopAfterName;
458  std::tie(StopAfterName, StopAfterInstanceNum)
460 
461  StartBefore = getPassIDFromName(StartBeforeName);
462  StartAfter = getPassIDFromName(StartAfterName);
463  StopBefore = getPassIDFromName(StopBeforeName);
464  StopAfter = getPassIDFromName(StopAfterName);
465  if (StartBefore && StartAfter)
467  Twine(StartAfterOptName) + Twine(" specified!"));
468  if (StopBefore && StopAfter)
470  Twine(StopAfterOptName) + Twine(" specified!"));
471  Started = (StartAfter == nullptr) && (StartBefore == nullptr);
472 }
473 
476 
477 #define SET_OPTION(Option) \
478  if (Option.getNumOccurrences()) \
479  Opt.Option = Option;
480 
487 
488 #define SET_BOOLEAN_OPTION(Option) Opt.Option = Option;
489 
505 
506  return Opt;
507 }
508 
510  LLVMTargetMachine &LLVMTM) {
511  StringRef StartBefore;
512  StringRef StartAfter;
513  StringRef StopBefore;
514  StringRef StopAfter;
515 
516  unsigned StartBeforeInstanceNum = 0;
517  unsigned StartAfterInstanceNum = 0;
518  unsigned StopBeforeInstanceNum = 0;
519  unsigned StopAfterInstanceNum = 0;
520 
521  std::tie(StartBefore, StartBeforeInstanceNum) =
523  std::tie(StartAfter, StartAfterInstanceNum) =
525  std::tie(StopBefore, StopBeforeInstanceNum) =
527  std::tie(StopAfter, StopAfterInstanceNum) =
529 
530  if (StartBefore.empty() && StartAfter.empty() && StopBefore.empty() &&
531  StopAfter.empty())
532  return;
533 
534  std::tie(StartBefore, std::ignore) =
535  LLVMTM.getPassNameFromLegacyName(StartBefore);
536  std::tie(StartAfter, std::ignore) =
537  LLVMTM.getPassNameFromLegacyName(StartAfter);
538  std::tie(StopBefore, std::ignore) =
539  LLVMTM.getPassNameFromLegacyName(StopBefore);
540  std::tie(StopAfter, std::ignore) =
541  LLVMTM.getPassNameFromLegacyName(StopAfter);
542  if (!StartBefore.empty() && !StartAfter.empty())
544  Twine(StartAfterOptName) + Twine(" specified!"));
545  if (!StopBefore.empty() && !StopAfter.empty())
547  Twine(StopAfterOptName) + Twine(" specified!"));
548 
550  [=, EnableCurrent = StartBefore.empty() && StartAfter.empty(),
551  EnableNext = Optional<bool>(), StartBeforeCount = 0u,
552  StartAfterCount = 0u, StopBeforeCount = 0u,
553  StopAfterCount = 0u](StringRef P, Any) mutable {
554  bool StartBeforePass = !StartBefore.empty() && P.contains(StartBefore);
555  bool StartAfterPass = !StartAfter.empty() && P.contains(StartAfter);
556  bool StopBeforePass = !StopBefore.empty() && P.contains(StopBefore);
557  bool StopAfterPass = !StopAfter.empty() && P.contains(StopAfter);
558 
559  // Implement -start-after/-stop-after
560  if (EnableNext) {
561  EnableCurrent = *EnableNext;
562  EnableNext.reset();
563  }
564 
565  // Using PIC.registerAfterPassCallback won't work because if this
566  // callback returns false, AfterPassCallback is also skipped.
567  if (StartAfterPass && StartAfterCount++ == StartAfterInstanceNum) {
568  assert(!EnableNext && "Error: assign to EnableNext more than once");
569  EnableNext = true;
570  }
571  if (StopAfterPass && StopAfterCount++ == StopAfterInstanceNum) {
572  assert(!EnableNext && "Error: assign to EnableNext more than once");
573  EnableNext = false;
574  }
575 
576  if (StartBeforePass && StartBeforeCount++ == StartBeforeInstanceNum)
577  EnableCurrent = true;
578  if (StopBeforePass && StopBeforeCount++ == StopBeforeInstanceNum)
579  EnableCurrent = false;
580  return EnableCurrent;
581  });
582 }
583 
585  LLVMTargetMachine &LLVMTM) {
586 
587  // Register a callback for disabling passes.
589 
590 #define DISABLE_PASS(Option, Name) \
591  if (Option && P.contains(#Name)) \
592  return false;
593  DISABLE_PASS(DisableBlockPlacement, MachineBlockPlacementPass)
594  DISABLE_PASS(DisableBranchFold, BranchFolderPass)
595  DISABLE_PASS(DisableCopyProp, MachineCopyPropagationPass)
596  DISABLE_PASS(DisableEarlyIfConversion, EarlyIfConverterPass)
597  DISABLE_PASS(DisableEarlyTailDup, EarlyTailDuplicatePass)
598  DISABLE_PASS(DisableMachineCSE, MachineCSEPass)
599  DISABLE_PASS(DisableMachineDCE, DeadMachineInstructionElimPass)
600  DISABLE_PASS(DisableMachineLICM, EarlyMachineLICMPass)
601  DISABLE_PASS(DisableMachineSink, MachineSinkingPass)
602  DISABLE_PASS(DisablePostRAMachineLICM, MachineLICMPass)
603  DISABLE_PASS(DisablePostRAMachineSink, PostRAMachineSinkingPass)
604  DISABLE_PASS(DisablePostRASched, PostRASchedulerPass)
605  DISABLE_PASS(DisableSSC, StackSlotColoringPass)
606  DISABLE_PASS(DisableTailDuplicate, TailDuplicatePass)
607 
608  return true;
609  });
610 
612 }
613 
614 // Out of line constructor provides default values for pass options and
615 // registers all common codegen passes.
616 TargetPassConfig::TargetPassConfig(LLVMTargetMachine &TM, PassManagerBase &pm)
617  : ImmutablePass(ID), PM(&pm), TM(&TM) {
618  Impl = new PassConfigImpl();
619 
620  // Register all target independent codegen passes to activate their PassIDs,
621  // including this pass itself.
623 
624  // Also register alias analysis passes required by codegen passes.
627 
630  else {
631  // If not explicitly specified, use target default.
633  }
634 
635  if (TM.Options.EnableIPRA)
637 
638  if (EnableGlobalISelAbort.getNumOccurrences())
640 
641  setStartStopPasses();
642 }
643 
645  return TM->getOptLevel();
646 }
647 
648 /// Insert InsertedPassID pass after TargetPassID.
650  IdentifyingPassPtr InsertedPassID) {
651  assert(((!InsertedPassID.isInstance() &&
652  TargetPassID != InsertedPassID.getID()) ||
653  (InsertedPassID.isInstance() &&
654  TargetPassID != InsertedPassID.getInstance()->getPassID())) &&
655  "Insert a pass after itself!");
656  Impl->InsertedPasses.emplace_back(TargetPassID, InsertedPassID);
657 }
658 
659 /// createPassConfig - Create a pass configuration object to be used by
660 /// addPassToEmitX methods for generating a pipeline of CodeGen passes.
661 ///
662 /// Targets may override this to extend TargetPassConfig.
664  return new TargetPassConfig(*this, PM);
665 }
666 
668  : ImmutablePass(ID) {
669  report_fatal_error("Trying to construct TargetPassConfig without a target "
670  "machine. Scheduling a CodeGen pass without a target "
671  "triple set?");
672 }
673 
675  return StopBeforeOpt.empty() && StopAfterOpt.empty();
676 }
677 
679  return !StartBeforeOpt.empty() || !StartAfterOpt.empty() ||
681 }
682 
683 std::string
686  return std::string();
687  std::string Res;
688  static cl::opt<std::string> *PassNames[] = {&StartAfterOpt, &StartBeforeOpt,
690  static const char *OptNames[] = {StartAfterOptName, StartBeforeOptName,
692  bool IsFirst = true;
693  for (int Idx = 0; Idx < 4; ++Idx)
694  if (!PassNames[Idx]->empty()) {
695  if (!IsFirst)
696  Res += Separator;
697  IsFirst = false;
698  Res += OptNames[Idx];
699  }
700  return Res;
701 }
702 
703 // Helper to verify the analysis is really immutable.
704 void TargetPassConfig::setOpt(bool &Opt, bool Val) {
705  assert(!Initialized && "PassConfig is immutable");
706  Opt = Val;
707 }
708 
710  IdentifyingPassPtr TargetID) {
711  Impl->TargetPasses[StandardID] = TargetID;
712 }
713 
716  I = Impl->TargetPasses.find(ID);
717  if (I == Impl->TargetPasses.end())
718  return ID;
719  return I->second;
720 }
721 
724  IdentifyingPassPtr FinalPtr = overridePass(ID, TargetID);
725  return !FinalPtr.isValid() || FinalPtr.isInstance() ||
726  FinalPtr.getID() != ID;
727 }
728 
729 /// Add a pass to the PassManager if that pass is supposed to be run. If the
730 /// Started/Stopped flags indicate either that the compilation should start at
731 /// a later pass or that it should stop after an earlier pass, then do not add
732 /// the pass. Finally, compare the current pass against the StartAfter
733 /// and StopAfter options and change the Started/Stopped flags accordingly.
735  assert(!Initialized && "PassConfig is immutable");
736 
737  // Cache the Pass ID here in case the pass manager finds this pass is
738  // redundant with ones already scheduled / available, and deletes it.
739  // Fundamentally, once we add the pass to the manager, we no longer own it
740  // and shouldn't reference it.
741  AnalysisID PassID = P->getPassID();
742 
743  if (StartBefore == PassID && StartBeforeCount++ == StartBeforeInstanceNum)
744  Started = true;
745  if (StopBefore == PassID && StopBeforeCount++ == StopBeforeInstanceNum)
746  Stopped = true;
747  if (Started && !Stopped) {
748  if (AddingMachinePasses) {
749  // Construct banner message before PM->add() as that may delete the pass.
750  std::string Banner =
751  std::string("After ") + std::string(P->getPassName());
753  PM->add(P);
754  addMachinePostPasses(Banner);
755  } else {
756  PM->add(P);
757  }
758 
759  // Add the passes after the pass P if there is any.
760  for (const auto &IP : Impl->InsertedPasses)
761  if (IP.TargetPassID == PassID)
762  addPass(IP.getInsertedPass());
763  } else {
764  delete P;
765  }
766 
767  if (StopAfter == PassID && StopAfterCount++ == StopAfterInstanceNum)
768  Stopped = true;
769 
770  if (StartAfter == PassID && StartAfterCount++ == StartAfterInstanceNum)
771  Started = true;
772  if (Stopped && !Started)
773  report_fatal_error("Cannot stop compilation after pass that is not run");
774 }
775 
776 /// Add a CodeGen pass at this point in the pipeline after checking for target
777 /// and command line overrides.
778 ///
779 /// addPass cannot return a pointer to the pass instance because is internal the
780 /// PassManager and the instance we create here may already be freed.
782  IdentifyingPassPtr TargetID = getPassSubstitution(PassID);
783  IdentifyingPassPtr FinalPtr = overridePass(PassID, TargetID);
784  if (!FinalPtr.isValid())
785  return nullptr;
786 
787  Pass *P;
788  if (FinalPtr.isInstance())
789  P = FinalPtr.getInstance();
790  else {
791  P = Pass::createPass(FinalPtr.getID());
792  if (!P)
793  llvm_unreachable("Pass ID not registered");
794  }
795  AnalysisID FinalID = P->getPassID();
796  addPass(P); // Ends the lifetime of P.
797 
798  return FinalID;
799 }
800 
801 void TargetPassConfig::printAndVerify(const std::string &Banner) {
802  addPrintPass(Banner);
803  addVerifyPass(Banner);
804 }
805 
806 void TargetPassConfig::addPrintPass(const std::string &Banner) {
807  if (PrintAfterISel)
808  PM->add(createMachineFunctionPrinterPass(dbgs(), Banner));
809 }
810 
811 void TargetPassConfig::addVerifyPass(const std::string &Banner) {
813 #ifdef EXPENSIVE_CHECKS
816 #endif
817  if (Verify)
818  PM->add(createMachineVerifierPass(Banner));
819 }
820 
823 }
824 
826  PM->add(createStripDebugMachineModulePass(/*OnlyDebugified=*/true));
827 }
828 
831 }
832 
833 void TargetPassConfig::addMachinePrePasses(bool AllowDebugify) {
834  if (AllowDebugify && DebugifyIsSafe &&
837  addDebugifyPass();
838 }
839 
840 void TargetPassConfig::addMachinePostPasses(const std::string &Banner) {
841  if (DebugifyIsSafe) {
845  } else if (DebugifyAndStripAll == cl::BOU_TRUE)
847  }
848  addVerifyPass(Banner);
849 }
850 
851 /// Add common target configurable passes that perform LLVM IR to IR transforms
852 /// following machine independent optimization.
854  // Before running any passes, run the verifier to determine if the input
855  // coming from the front-end and/or optimizer is valid.
856  if (!DisableVerify)
858 
859  if (getOptLevel() != CodeGenOpt::None) {
860  switch (UseCFLAA) {
863  break;
864  case CFLAAType::Andersen:
866  break;
867  case CFLAAType::Both:
870  break;
871  default:
872  break;
873  }
874 
875  // Basic AliasAnalysis support.
876  // Add TypeBasedAliasAnalysis before BasicAliasAnalysis so that
877  // BasicAliasAnalysis wins if they disagree. This is intended to help
878  // support "obvious" type-punning idioms.
882 
883  // Run loop strength reduction before anything else.
884  if (!DisableLSR) {
887  if (PrintLSR)
889  "\n\n*** Code after LSR ***\n"));
890  }
891 
892  // The MergeICmpsPass tries to create memcmp calls by grouping sequences of
893  // loads and compares. ExpandMemCmpPass then tries to expand those calls
894  // into optimally-sized loads and compares. The transforms are enabled by a
895  // target lowering hook.
896  if (!DisableMergeICmps)
899  }
900 
901  // Run GC lowering passes for builtin collectors
902  // TODO: add a pass insertion point here
906 
907  // For MachO, lower @llvm.global_dtors into @llvm_global_ctors with
908  // __cxa_atexit() calls to avoid emitting the deprecated __mod_term_func.
912 
913  // Make sure that no unreachable blocks are instruction selected.
915 
916  // Prepare expensive constants for SelectionDAG.
919 
920  if (getOptLevel() != CodeGenOpt::None)
922 
925 
926  // Expand vector predication intrinsics into standard IR instructions.
927  // This pass has to run before ScalarizeMaskedMemIntrin and ExpandReduction
928  // passes since it emits those kinds of intrinsics.
930 
931  // Add scalarization of target's unsupported masked memory intrinsics pass.
932  // the unsupported intrinsic will be replaced with a chain of basic blocks,
933  // that stores/loads element one-by-one if the appropriate mask bit is set.
935 
936  // Expand reduction intrinsics into shuffle sequences if the target wants to.
937  // Allow disabling it for testing purposes.
940 
941  if (getOptLevel() != CodeGenOpt::None)
943 
944  // Convert conditional moves to conditional jumps when profitable.
947 }
948 
949 /// Turn exception handling constructs into something the code generators can
950 /// handle.
952  const MCAsmInfo *MCAI = TM->getMCAsmInfo();
953  assert(MCAI && "No MCAsmInfo");
954  switch (MCAI->getExceptionHandlingType()) {
956  // SjLj piggy-backs on dwarf for this bit. The cleanups done apply to both
957  // Dwarf EH prepare needs to be run after SjLj prepare. Otherwise,
958  // catch info can get misplaced when a selector ends up more than one block
959  // removed from the parent invoke(s). This could happen when a landing
960  // pad is shared by multiple invokes and is also a target of a normal
961  // edge from elsewhere.
968  break;
970  // We support using both GCC-style and MSVC-style exceptions on Windows, so
971  // add both preparation passes. Each pass will only actually run if it
972  // recognizes the personality function.
975  break;
977  // Wasm EH uses Windows EH instructions, but it does not need to demote PHIs
978  // on catchpads and cleanuppads because it does not outline them into
979  // funclets. Catchswitch blocks are not lowered in SelectionDAG, so we
980  // should remove PHIs there.
981  addPass(createWinEHPass(/*DemoteCatchSwitchPHIOnly=*/false));
983  break;
986 
987  // The lower invoke pass may create unreachable code. Remove it.
989  break;
990  }
991 }
992 
993 /// Add pass to prepare the LLVM IR for code generation. This should be done
994 /// before exception handling preparation passes.
998 }
999 
1000 /// Add common passes that perform LLVM IR to IR transforms in preparation for
1001 /// instruction selection.
1003  addPreISel();
1004 
1005  // Force codegen to run according to the callgraph.
1007  addPass(new DummyCGSCCPass);
1008 
1009  // Add both the safe stack and the stack protection passes: each of them will
1010  // only protect functions that have corresponding attributes.
1013 
1014  if (PrintISelInput)
1016  dbgs(), "\n\n*** Final LLVM Code input to ISel ***\n"));
1017 
1018  // All passes which modify the LLVM IR are now complete; run the verifier
1019  // to ensure that the IR is valid.
1020  if (!DisableVerify)
1022 }
1023 
1025  // Enable FastISel with -fast-isel, but allow that to be overridden.
1027 
1028  // Determine an instruction selector.
1029  enum class SelectorType { SelectionDAG, FastISel, GlobalISel };
1030  SelectorType Selector;
1031 
1033  Selector = SelectorType::FastISel;
1034  else if (EnableGlobalISelOption == cl::BOU_TRUE ||
1037  Selector = SelectorType::GlobalISel;
1038  else if (TM->getOptLevel() == CodeGenOpt::None && TM->getO0WantsFastISel())
1039  Selector = SelectorType::FastISel;
1040  else
1041  Selector = SelectorType::SelectionDAG;
1042 
1043  // Set consistently TM->Options.EnableFastISel and EnableGlobalISel.
1044  if (Selector == SelectorType::FastISel) {
1045  TM->setFastISel(true);
1046  TM->setGlobalISel(false);
1047  } else if (Selector == SelectorType::GlobalISel) {
1048  TM->setFastISel(false);
1049  TM->setGlobalISel(true);
1050  }
1051 
1052  // FIXME: Injecting into the DAGISel pipeline seems to cause issues with
1053  // analyses needing to be re-run. This can result in being unable to
1054  // schedule passes (particularly with 'Function Alias Analysis
1055  // Results'). It's not entirely clear why but AFAICT this seems to be
1056  // due to one FunctionPassManager not being able to use analyses from a
1057  // previous one. As we're injecting a ModulePass we break the usual
1058  // pass manager into two. GlobalISel with the fallback path disabled
1059  // and -run-pass seem to be unaffected. The majority of GlobalISel
1060  // testing uses -run-pass so this probably isn't too bad.
1061  SaveAndRestore<bool> SavedDebugifyIsSafe(DebugifyIsSafe);
1062  if (Selector != SelectorType::GlobalISel || !isGlobalISelAbortEnabled())
1063  DebugifyIsSafe = false;
1064 
1065  // Add instruction selector passes.
1066  if (Selector == SelectorType::GlobalISel) {
1067  SaveAndRestore<bool> SavedAddingMachinePasses(AddingMachinePasses, true);
1068  if (addIRTranslator())
1069  return true;
1070 
1072 
1073  if (addLegalizeMachineIR())
1074  return true;
1075 
1076  // Before running the register bank selector, ask the target if it
1077  // wants to run some passes.
1079 
1080  if (addRegBankSelect())
1081  return true;
1082 
1084 
1086  return true;
1087 
1088  // Pass to reset the MachineFunction if the ISel failed.
1091 
1092  // Provide a fallback path when we do not want to abort on
1093  // not-yet-supported input.
1095  return true;
1096 
1097  } else if (addInstSelector())
1098  return true;
1099 
1100  // Expand pseudo-instructions emitted by ISel. Don't run the verifier before
1101  // FinalizeISel.
1103 
1104  // Print the instruction selected machine code...
1105  printAndVerify("After Instruction Selection");
1106 
1107  return false;
1108 }
1109 
1111  if (TM->useEmulatedTLS())
1113 
1116  addIRPasses();
1119  addISelPrepare();
1120 
1121  return addCoreISelPasses();
1122 }
1123 
1124 /// -regalloc=... command line option.
1125 static FunctionPass *useDefaultRegisterAllocator() { return nullptr; }
1129  cl::desc("Register allocator to use"));
1130 
1131 /// Add the complete set of target-independent postISel code generator passes.
1132 ///
1133 /// This can be read as the standard order of major LLVM CodeGen stages. Stages
1134 /// with nontrivial configuration or multiple passes are broken out below in
1135 /// add%Stage routines.
1136 ///
1137 /// Any TargetPassConfig::addXX routine may be overriden by the Target. The
1138 /// addPre/Post methods with empty header implementations allow injecting
1139 /// target-specific fixups just before or after major stages. Additionally,
1140 /// targets have the flexibility to change pass order within a stage by
1141 /// overriding default implementation of add%Stage routines below. Each
1142 /// technique has maintainability tradeoffs because alternate pass orders are
1143 /// not well supported. addPre/Post works better if the target pass is easily
1144 /// tied to a common pass. But if it has subtle dependencies on multiple passes,
1145 /// the target should override the stage instead.
1146 ///
1147 /// TODO: We could use a single addPre/Post(ID) hook to allow pass injection
1148 /// before/after any target-independent pass. But it's currently overkill.
1150  AddingMachinePasses = true;
1151 
1152  // Add passes that optimize machine instructions in SSA form.
1153  if (getOptLevel() != CodeGenOpt::None) {
1155  } else {
1156  // If the target requests it, assign local variables to stack slots relative
1157  // to one another and simplify frame index references where possible.
1159  }
1160 
1161  if (TM->Options.EnableIPRA)
1163 
1164  // Run pre-ra passes.
1165  addPreRegAlloc();
1166 
1167  // Debugifying the register allocator passes seems to provoke some
1168  // non-determinism that affects CodeGen and there doesn't seem to be a point
1169  // where it becomes safe again so stop debugifying here.
1170  DebugifyIsSafe = false;
1171 
1172  // Add a FSDiscriminator pass right before RA, so that we could get
1173  // more precise SampleFDO profile for RA.
1174  if (EnableFSDiscriminator) {
1177  const std::string ProfileFile = getFSProfileFile(TM);
1178  if (!ProfileFile.empty() && !DisableRAFSProfileLoader)
1179  addPass(
1182  }
1183 
1184  // Run register allocation and passes that are tightly coupled with it,
1185  // including phi elimination and scheduling.
1186  if (getOptimizeRegAlloc())
1188  else
1189  addFastRegAlloc();
1190 
1191  // Run post-ra passes.
1192  addPostRegAlloc();
1193 
1195 
1197 
1198  // Insert prolog/epilog code. Eliminate abstract frame index references...
1199  if (getOptLevel() != CodeGenOpt::None) {
1202  }
1203 
1204  // Prolog/Epilog inserter needs a TargetMachine to instantiate. But only
1205  // do so if it hasn't been disabled, substituted, or overridden.
1208 
1209  /// Add passes that optimize machine instructions after register allocation.
1210  if (getOptLevel() != CodeGenOpt::None)
1212 
1213  // Expand pseudo instructions before second scheduling pass.
1215 
1216  // Run pre-sched2 passes.
1217  addPreSched2();
1218 
1221 
1222  // Second pass scheduler.
1223  // Let Target optionally insert this pass by itself at some other
1224  // point.
1225  if (getOptLevel() != CodeGenOpt::None &&
1227  if (MISchedPostRA)
1229  else
1231  }
1232 
1233  // GC
1234  if (addGCPasses()) {
1235  if (PrintGCInfo)
1237  }
1238 
1239  // Basic block placement.
1240  if (getOptLevel() != CodeGenOpt::None)
1242 
1243  // Insert before XRay Instrumentation.
1245 
1248 
1250  // Add FS discriminators here so that all the instruction duplicates
1251  // in different BBs get their own discriminators. With this, we can "sum"
1252  // the SampleFDO counters instead of using MAX. This will improve the
1253  // SampleFDO profile quality.
1256 
1257  addPreEmitPass();
1258 
1259  if (TM->Options.EnableIPRA)
1260  // Collect register usage information and produce a register mask of
1261  // clobbered registers, to be used to optimize call sites.
1263 
1264  // FIXME: Some backends are incompatible with running the verifier after
1265  // addPreEmitPass. Maybe only pass "false" here for those targets?
1267 
1270 
1273  bool RunOnAllFunctions =
1275  bool AddOutliner =
1276  RunOnAllFunctions || TM->Options.SupportsDefaultOutlining;
1277  if (AddOutliner)
1278  addPass(createMachineOutlinerPass(RunOnAllFunctions));
1279  }
1280 
1281  // Machine function splitter uses the basic block sections feature. Both
1282  // cannot be enabled at the same time. Basic block sections takes precedence.
1283  // FIXME: In principle, BasicBlockSection::Labels and splitting can used
1284  // together. Update this check once we have addressed any issues.
1289  }
1294  }
1295 
1298 
1299  // Add passes that directly emit MI after all other MI passes.
1300  addPreEmitPass2();
1301 
1302  AddingMachinePasses = false;
1303 }
1304 
1305 /// Add passes that optimize machine instructions in SSA form.
1307  // Pre-ra tail duplication.
1309 
1310  // Optimize PHIs before DCE: removing dead PHI cycles may make more
1311  // instructions dead.
1313 
1314  // This pass merges large allocas. StackSlotColoring is a different pass
1315  // which merges spill slots.
1317 
1318  // If the target requests it, assign local variables to stack slots relative
1319  // to one another and simplify frame index references where possible.
1321 
1322  // With optimization, dead code should already be eliminated. However
1323  // there is one known exception: lowered code for arguments that are only
1324  // used by tail calls, where the tail calls reuse the incoming stack
1325  // arguments directly (see t11 in test/CodeGen/X86/sibcall.ll).
1327 
1328  // Allow targets to insert passes that improve instruction level parallelism,
1329  // like if-conversion. Such passes will typically need dominator trees and
1330  // loop info, just like LICM and CSE below.
1331  addILPOpts();
1332 
1335 
1337 
1339  // Clean-up the dead code that may have been generated by peephole
1340  // rewriting.
1342 }
1343 
1344 //===---------------------------------------------------------------------===//
1345 /// Register Allocation Pass Configuration
1346 //===---------------------------------------------------------------------===//
1347 
1349  switch (OptimizeRegAlloc) {
1350  case cl::BOU_UNSET: return getOptLevel() != CodeGenOpt::None;
1351  case cl::BOU_TRUE: return true;
1352  case cl::BOU_FALSE: return false;
1353  }
1354  llvm_unreachable("Invalid optimize-regalloc state");
1355 }
1356 
1357 /// A dummy default pass factory indicates whether the register allocator is
1358 /// overridden on the command line.
1360 
1361 static RegisterRegAlloc
1362 defaultRegAlloc("default",
1363  "pick register allocator based on -O option",
1365 
1369 }
1370 
1371 /// Instantiate the default register allocator pass for this target for either
1372 /// the optimized or unoptimized allocation path. This will be added to the pass
1373 /// manager by addFastRegAlloc in the unoptimized case or addOptimizedRegAlloc
1374 /// in the optimized case.
1375 ///
1376 /// A target that uses the standard regalloc pass order for fast or optimized
1377 /// allocation may still override this for per-target regalloc
1378 /// selection. But -regalloc=... always takes precedence.
1380  if (Optimized)
1382  else
1383  return createFastRegisterAllocator();
1384 }
1385 
1386 /// Find and instantiate the register allocation pass requested by this target
1387 /// at the current optimization level. Different register allocators are
1388 /// defined as separate passes because they may require different analysis.
1389 ///
1390 /// This helper ensures that the regalloc= option is always available,
1391 /// even for targets that override the default allocator.
1392 ///
1393 /// FIXME: When MachinePassRegistry register pass IDs instead of function ptrs,
1394 /// this can be folded into addPass.
1396  // Initialize the global default.
1399 
1401  if (Ctor != useDefaultRegisterAllocator)
1402  return Ctor();
1403 
1404  // With no -regalloc= override, ask the target for a regalloc pass.
1405  return createTargetRegisterAllocator(Optimized);
1406 }
1407 
1411  report_fatal_error("Must use fast (default) register allocator for unoptimized regalloc.");
1412 
1413  addPass(createRegAllocPass(false));
1414 
1415  // Allow targets to change the register assignments after
1416  // fast register allocation.
1418  return true;
1419 }
1420 
1422  // Add the selected register allocation pass.
1423  addPass(createRegAllocPass(true));
1424 
1425  // Allow targets to change the register assignments before rewriting.
1426  addPreRewrite();
1427 
1428  // Finally rewrite virtual registers.
1430 
1431  // Regalloc scoring for ML-driven eviction - noop except when learning a new
1432  // eviction policy.
1434  return true;
1435 }
1436 
1437 /// Return true if the default global register allocator is in use and
1438 /// has not be overriden on the command line with '-regalloc=...'
1440  return RegAlloc.getNumOccurrences() == 0;
1441 }
1442 
1443 /// Add the minimum set of target-independent passes that are required for
1444 /// register allocation. No coalescing or scheduling.
1448 
1450 }
1451 
1452 /// Add standard target-independent passes that are tightly coupled with
1453 /// optimized register allocation, including coalescing, machine instruction
1454 /// scheduling, and register allocation itself.
1457 
1459 
1460  // LiveVariables currently requires pure SSA form.
1461  //
1462  // FIXME: Once TwoAddressInstruction pass no longer uses kill flags,
1463  // LiveVariables can be removed completely, and LiveIntervals can be directly
1464  // computed. (We still either need to regenerate kill flags after regalloc, or
1465  // preferably fix the scavenger to not depend on them).
1466  // FIXME: UnreachableMachineBlockElim is a dependant pass of LiveVariables.
1467  // When LiveVariables is removed this has to be removed/moved either.
1468  // Explicit addition of UnreachableMachineBlockElim allows stopping before or
1469  // after it with -stop-before/-stop-after.
1472 
1473  // Edge splitting is smarter with machine loop info.
1476 
1477  // Eventually, we want to run LiveIntervals before PHI elimination.
1478  if (EarlyLiveIntervals)
1480 
1483 
1484  // The machine scheduler may accidentally create disconnected components
1485  // when moving subregister definitions around, avoid this by splitting them to
1486  // separate vregs before. Splitting can also improve reg. allocation quality.
1488 
1489  // PreRA instruction scheduling.
1491 
1493  // Perform stack slot coloring and post-ra machine LICM.
1495 
1496  // Allow targets to expand pseudo instructions depending on the choice of
1497  // registers before MachineCopyPropagation.
1498  addPostRewrite();
1499 
1500  // Copy propagate to forward register uses and try to eliminate COPYs that
1501  // were not coalesced.
1503 
1504  // Run post-ra machine LICM to hoist reloads / remats.
1505  //
1506  // FIXME: can this move into MachineLateOptimization?
1508  }
1509 }
1510 
1511 //===---------------------------------------------------------------------===//
1512 /// Post RegAlloc Pass Configuration
1513 //===---------------------------------------------------------------------===//
1514 
1515 /// Add passes that optimize machine instructions after register allocation.
1517  // Branch folding must be run after regalloc and prolog/epilog insertion.
1519 
1520  // Tail duplication.
1521  // Note that duplicating tail just increases code size and degrades
1522  // performance for targets that require Structured Control Flow.
1523  // In addition it can also make CFG irreducible. Thus we disable it.
1524  if (!TM->requiresStructuredCFG())
1526 
1527  // Copy propagation.
1529 }
1530 
1531 /// Add standard GC passes.
1534  return true;
1535 }
1536 
1537 /// Add standard basic block placement passes.
1539  if (EnableFSDiscriminator) {
1542  const std::string ProfileFile = getFSProfileFile(TM);
1543  if (!ProfileFile.empty() && !DisableLayoutFSProfileLoader)
1544  addPass(
1547  }
1549  // Run a separate pass to collect block placement statistics.
1552  }
1553 }
1554 
1555 //===---------------------------------------------------------------------===//
1556 /// GlobalISel Configuration
1557 //===---------------------------------------------------------------------===//
1560 }
1561 
1564 }
1565 
1567  return true;
1568 }
1569 
1570 std::unique_ptr<CSEConfigBase> TargetPassConfig::getCSEConfig() const {
1571  return std::make_unique<CSEConfigBase>();
1572 }
DisableCGP
static cl::opt< bool > DisableCGP("disable-cgp", cl::Hidden, cl::desc("Disable Codegen Prepare"))
DisableMachineSink
static cl::opt< bool > DisableMachineSink("disable-machine-sink", cl::Hidden, cl::desc("Disable Machine Sinking"))
llvm::TargetMachine::requiresStructuredCFG
bool requiresStructuredCFG() const
Definition: TargetMachine.h:216
llvm::TargetPassConfig::addPostRegAlloc
virtual void addPostRegAlloc()
This method may be implemented by targets that want to run passes after register allocation pass pipe...
Definition: TargetPassConfig.h:417
TypeBasedAliasAnalysis.h
llvm::TargetMachine::getOptLevel
CodeGenOpt::Level getOptLevel() const
Returns the optimization level: None, Less, Default, or Aggressive.
Definition: TargetMachine.cpp:186
llvm::TargetPassConfig::ID
static char ID
Definition: TargetPassConfig.h:148
EnableMachineOutliner
static cl::opt< RunOutliner > EnableMachineOutliner("enable-machine-outliner", cl::desc("Enable the machine outliner"), cl::Hidden, cl::ValueOptional, cl::init(RunOutliner::TargetDefault), cl::values(clEnumValN(RunOutliner::AlwaysOutline, "always", "Run on all functions guaranteed to be beneficial"), clEnumValN(RunOutliner::NeverOutline, "never", "Disable all outlining"), clEnumValN(RunOutliner::AlwaysOutline, "", "")))
llvm::createFastRegisterAllocator
FunctionPass * createFastRegisterAllocator()
FastRegisterAllocation Pass - This pass register allocates as fast as possible.
Definition: RegAllocFast.cpp:1579
llvm::createCheckDebugMachineModulePass
ModulePass * createCheckDebugMachineModulePass()
Creates MIR Check Debug pass.
Definition: MachineCheckDebugify.cpp:124
llvm::RegisterRegAllocBase< RegisterRegAlloc >::setDefault
static void setDefault(FunctionPassCtor C)
Definition: RegAllocRegistry.h:54
llvm::PassInfo::getTypeInfo
const void * getTypeInfo() const
getTypeInfo - Return the id object for the pass...
Definition: PassInfo.h:71
llvm::OptimizePHIsID
char & OptimizePHIsID
OptimizePHIs - This pass optimizes machine instruction PHIs to take advantage of opportunities create...
Definition: OptimizePHIs.cpp:68
llvm::createLowerInvokePass
FunctionPass * createLowerInvokePass()
Definition: LowerInvoke.cpp:85
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
llvm::createGreedyRegisterAllocator
FunctionPass * createGreedyRegisterAllocator()
Greedy register allocation pass - This pass implements a global register allocator for optimized buil...
Definition: RegAllocGreedy.cpp:179
llvm::TargetMachine::useEmulatedTLS
bool useEmulatedTLS() const
Returns true if this target uses emulated TLS.
Definition: TargetMachine.cpp:150
MCTargetOptions.h
llvm::createMachineFunctionSplitterPass
MachineFunctionPass * createMachineFunctionSplitterPass()
createMachineFunctionSplitterPass - This pass splits machine functions using profile information.
llvm::PeepholeOptimizerID
char & PeepholeOptimizerID
PeepholeOptimizer - This pass performs peephole optimizations - like extension and comparison elimina...
Definition: PeepholeOptimizer.cpp:443
DisableConstantHoisting
static cl::opt< bool > DisableConstantHoisting("disable-constant-hoisting", cl::Hidden, cl::desc("Disable ConstantHoisting"))
llvm::IdentifyingPassPtr::getInstance
Pass * getInstance() const
Definition: TargetPassConfig.h:73
llvm::createCFLAndersAAWrapperPass
ImmutablePass * createCFLAndersAAWrapperPass()
llvm::ImmutablePass
ImmutablePass class - This class is used to provide information that does not need to be run.
Definition: Pass.h:279
Scalar.h
llvm::ExceptionHandling::SjLj
@ SjLj
setjmp/longjmp based exceptions
llvm::TargetPassConfig::willCompleteCodeGenPipeline
static bool willCompleteCodeGenPipeline()
Returns true if none of the -stop-before and -stop-after options is set.
Definition: TargetPassConfig.cpp:674
MachinePassRegistry.h
llvm::TargetMachine::targetSchedulesPostRAScheduling
virtual bool targetSchedulesPostRAScheduling() const
True if subtarget inserts the final scheduling pass on its own.
Definition: TargetMachine.h:389
llvm::Pass::getPassID
AnalysisID getPassID() const
getPassID - Return the PassID number that corresponds to this pass.
Definition: Pass.h:110
StringRef.h
P
This currently compiles esp xmm0 movsd esp eax eax esp ret We should use not the dag combiner This is because dagcombine2 needs to be able to see through the X86ISD::Wrapper which DAGCombine can t really do The code for turning x load into a single vector load is target independent and should be moved to the dag combiner The code for turning x load into a vector load can only handle a direct load from a global or a direct load from the stack It should be generalized to handle any load from P
Definition: README-SSE.txt:411
llvm::cl::BOU_FALSE
@ BOU_FALSE
Definition: CommandLine.h:611
Pass.h
llvm::PHIEliminationID
char & PHIEliminationID
PHIElimination - This pass eliminates machine instruction PHI nodes by inserting copy instructions.
Definition: PHIElimination.cpp:128
INITIALIZE_PASS::InsertedPass::TargetPassID
AnalysisID TargetPassID
Definition: TargetPassConfig.cpp:370
CSEConfigBase.h
DisableSelectOptimize
static cl::opt< bool > DisableSelectOptimize("disable-select-optimize", cl::init(true), cl::Hidden, cl::desc("Disable the select-optimization pass from running"))
Disable the select optimization pass.
llvm::IdentifyingPassPtr::isInstance
bool isInstance() const
Definition: TargetPassConfig.h:66
llvm::MCAsmInfo
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:56
llvm::TargetPassConfig::addStripDebugPass
void addStripDebugPass()
Add a pass to remove debug info from the MIR.
Definition: TargetPassConfig.cpp:825
llvm::SmallVector< InsertedPass, 4 >
llvm::TargetMachine::getO0WantsFastISel
bool getO0WantsFastISel()
Definition: TargetMachine.h:244
FSNoFinalDiscrim
static cl::opt< bool > FSNoFinalDiscrim("fs-no-final-discrim", cl::init(false), cl::Hidden, cl::desc("Do not insert FS-AFDO discriminators before " "emit."))
llvm::initializeBasicAAWrapperPassPass
void initializeBasicAAWrapperPassPass(PassRegistry &)
EnableFastISelOption
static cl::opt< cl::boolOrDefault > EnableFastISelOption("fast-isel", cl::Hidden, cl::desc("Enable the \"fast\" instruction selector"))
ErrorHandling.h
llvm::TargetPassConfig::addPreLegalizeMachineIR
virtual void addPreLegalizeMachineIR()
This method may be implemented by targets that want to run passes immediately before legalization.
Definition: TargetPassConfig.h:249
EnableMachineFunctionSplitter
static cl::opt< bool > EnableMachineFunctionSplitter("enable-split-machine-functions", cl::Hidden, cl::desc("Split out cold blocks from machine functions based on profile " "information."))
Enable the machine function splitter pass.
llvm::LLVMTargetMachine::createPassConfig
virtual TargetPassConfig * createPassConfig(PassManagerBase &PM)
Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of ...
Definition: TargetPassConfig.cpp:663
DebugifyAndStripAll
static cl::opt< cl::boolOrDefault > DebugifyAndStripAll("debugify-and-strip-all-safe", cl::Hidden, cl::desc("Debugify MIR before and Strip debug after " "each pass except those known to be unsafe " "when debug info is present"))
llvm::cl::ValueOptional
@ ValueOptional
Definition: CommandLine.h:132
llvm::ExpandPostRAPseudosID
char & ExpandPostRAPseudosID
ExpandPostRAPseudos - This pass expands pseudo instructions after register allocation.
Definition: ExpandPostRAPseudos.cpp:57
llvm::TargetPassConfig::addPreRewrite
virtual bool addPreRewrite()
addPreRewrite - Add passes to the optimized register allocation pipeline after register allocation is...
Definition: TargetPassConfig.h:403
CGPassBuilderOption.h
llvm::TargetPassConfig::createRegAllocPass
virtual FunctionPass * createRegAllocPass(bool Optimized)
addMachinePasses helper to create the target-selected or overriden regalloc pass.
Definition: TargetPassConfig.cpp:1395
llvm::TargetPassConfig::addGCPasses
virtual bool addGCPasses()
addGCPasses - Add late codegen passes that analyze code for garbage collection.
Definition: TargetPassConfig.cpp:1532
DisableLayoutFSProfileLoader
static cl::opt< bool > DisableLayoutFSProfileLoader("disable-layout-fsprofile-loader", cl::init(false), cl::Hidden, cl::desc("Disable MIRProfileLoader before BlockPlacement"))
llvm::AnalysisID
const void * AnalysisID
Definition: Pass.h:47
llvm::TargetPassConfig::addPostRewrite
virtual void addPostRewrite()
Add passes to be run immediately after virtual registers are rewritten to physical registers.
Definition: TargetPassConfig.h:413
llvm::RunOutliner::TargetDefault
@ TargetDefault
llvm::TargetPassConfig::addPreSched2
virtual void addPreSched2()
This method may be implemented by targets that want to run passes after prolog-epilog insertion and b...
Definition: TargetPassConfig.h:424
llvm::cl::Hidden
@ Hidden
Definition: CommandLine.h:139
DisableTailDuplicate
static cl::opt< bool > DisableTailDuplicate("disable-tail-duplicate", cl::Hidden, cl::desc("Disable tail duplication"))
llvm::PassConfigImpl::InsertedPasses
SmallVector< InsertedPass, 4 > InsertedPasses
Store the pairs of <AnalysisID, AnalysisID> of which the second pass is inserted after each instance ...
Definition: TargetPassConfig.cpp:405
llvm::EnableFSDiscriminator
cl::opt< bool > EnableFSDiscriminator
Definition: TargetPassConfig.cpp:390
getPassNameAndInstanceNum
static std::pair< StringRef, unsigned > getPassNameAndInstanceNum(StringRef PassName)
Definition: TargetPassConfig.cpp:433
llvm::Pass::createPass
static Pass * createPass(AnalysisID ID)
Definition: Pass.cpp:194
llvm::createPrologEpilogInserterPass
MachineFunctionPass * createPrologEpilogInserterPass()
Definition: PrologEpilogInserter.cpp:149
Discriminator.h
llvm::DenseMapIterator
Definition: DenseMap.h:57
llvm::PassConfigImpl
Definition: TargetPassConfig.cpp:392
DisableBranchFold
static cl::opt< bool > DisableBranchFold("disable-branch-fold", cl::Hidden, cl::desc("Disable branch folding"))
DenseMap.h
llvm::createCFLSteensAAWrapperPass
ImmutablePass * createCFLSteensAAWrapperPass()
MISchedPostRA
static cl::opt< bool > MISchedPostRA("misched-postra", cl::Hidden, cl::desc("Run MachineScheduler post regalloc (independent of preRA sched)"))
llvm::ShadowStackGCLoweringID
char & ShadowStackGCLoweringID
ShadowStackGCLowering - Implements the custom lowering mechanism used by the shadow stack GC.
Definition: ShadowStackGCLowering.cpp:91
FSRemappingFile
static cl::opt< std::string > FSRemappingFile("fs-remapping-file", cl::init(""), cl::value_desc("filename"), cl::desc("Flow Sensitive profile remapping file name."), cl::Hidden)
llvm::LocalStackSlotAllocationID
char & LocalStackSlotAllocationID
LocalStackSlotAllocation - This pass assigns local frame indices to stack slots relative to one anoth...
Definition: LocalStackSlotAllocation.cpp:108
llvm::CFLAAType::Andersen
@ Andersen
llvm::createGCInfoPrinter
FunctionPass * createGCInfoPrinter(raw_ostream &OS)
Creates a pass to print GC metadata.
Definition: GCMetadata.cpp:89
PIC
PassInstrumentationCallbacks PIC
Definition: PassBuilderBindings.cpp:55
llvm::LLVMTargetMachine::isMachineVerifierClean
virtual bool isMachineVerifierClean() const
Returns true if the target is expected to pass all machine verifier checks.
Definition: TargetMachine.h:468
llvm::PassInfo
PassInfo class - An instance of this class exists for every pass known by the system,...
Definition: PassInfo.h:30
llvm::UseCFLAA
static cl::opt<::CFLAAType > UseCFLAA("use-cfl-aa", cl::init(::CFLAAType::None), cl::Hidden, cl::desc("Enable the new, experimental CFL alias analysis"), cl::values(clEnumValN(::CFLAAType::None, "none", "Disable CFL-AA"), clEnumValN(::CFLAAType::Steensgaard, "steens", "Enable unification-based CFL-AA"), clEnumValN(::CFLAAType::Andersen, "anders", "Enable inclusion-based CFL-AA"), clEnumValN(::CFLAAType::Both, "both", "Enable both variants of CFL-AA")))
DisableExpandReductions
static cl::opt< bool > DisableExpandReductions("disable-expand-reductions", cl::init(false), cl::Hidden, cl::desc("Disable the expand reduction intrinsics pass from running"))
Disable the expand reductions pass for testing.
llvm::createLoopStrengthReducePass
Pass * createLoopStrengthReducePass()
Definition: LoopStrengthReduce.cpp:6713
llvm::ExceptionHandling::ARM
@ ARM
ARM EHABI.
llvm::Optional
Definition: APInt.h:33
llvm::RunOutliner::NeverOutline
@ NeverOutline
llvm::IdentifyingPassPtr
Discriminated union of Pass ID types.
Definition: TargetPassConfig.h:53
llvm::createLowerGlobalDtorsLegacyPass
ModulePass * createLowerGlobalDtorsLegacyPass()
llvm::CFLAAType::Both
@ Both
getPassInfo
static const PassInfo * getPassInfo(StringRef PassName)
Definition: TargetPassConfig.cpp:415
INITIALIZE_PASS::InsertedPass
Definition: TargetPassConfig.cpp:369
INITIALIZE_PASS::InsertedPass::InsertedPassID
IdentifyingPassPtr InsertedPassID
Definition: TargetPassConfig.cpp:371
llvm::TargetPassConfig::addRegAssignAndRewriteFast
virtual bool addRegAssignAndRewriteFast()
Add core register allocator passes which do the actual register assignment and rewriting.
Definition: TargetPassConfig.cpp:1408
llvm::StackSlotColoringID
char & StackSlotColoringID
StackSlotColoring - This pass performs stack slot coloring.
Definition: StackSlotColoring.cpp:131
DebugifyCheckAndStripAll
static cl::opt< cl::boolOrDefault > DebugifyCheckAndStripAll("debugify-check-and-strip-all-safe", cl::Hidden, cl::desc("Debugify MIR before, by checking and stripping the debug info after, " "each pass except those known to be unsafe when debug info is " "present"))
llvm::MachineCopyPropagationID
char & MachineCopyPropagationID
MachineCopyPropagation - This pass performs copy propagation on machine instructions.
Definition: MachineCopyPropagation.cpp:354
FSProfileFile
static cl::opt< std::string > FSProfileFile("fs-profile-file", cl::init(""), cl::value_desc("filename"), cl::desc("Flow Sensitive profile file name."), cl::Hidden)
llvm::PGOOptions::SampleUse
@ SampleUse
Definition: PGOOptions.h:23
BasicAliasAnalysis.h
LegacyPassManager.h
llvm::TwoAddressInstructionPassID
char & TwoAddressInstructionPassID
TwoAddressInstruction - This pass reduces two-address instructions to use two operands.
Definition: TwoAddressInstructionPass.cpp:193
llvm::MachineLICMID
char & MachineLICMID
This pass performs loop invariant code motion on machine instructions.
Definition: MachineLICM.cpp:297
llvm::TargetOptions::EnableMachineFunctionSplitter
unsigned EnableMachineFunctionSplitter
Enables the MachineFunctionSplitter pass.
Definition: TargetOptions.h:306
llvm::BasicBlockSection::List
@ List
llvm::BasicBlockSection::None
@ None
llvm::createUnreachableBlockEliminationPass
FunctionPass * createUnreachableBlockEliminationPass()
createUnreachableBlockEliminationPass - The LLVM code generator does not work well with unreachable b...
llvm::RegisterRegAlloc
Definition: RegAllocRegistry.h:61
llvm::createBasicBlockSectionsProfileReaderPass
ImmutablePass * createBasicBlockSectionsProfileReaderPass(const MemoryBuffer *Buf)
Definition: BasicBlockSectionsProfileReader.cpp:142
llvm::TargetPassConfig::addPreRegBankSelect
virtual void addPreRegBankSelect()
This method may be implemented by targets that want to run passes immediately before the register ban...
Definition: TargetPassConfig.h:257
llvm::TargetPassConfig::isGISelCSEEnabled
virtual bool isGISelCSEEnabled() const
Check whether continuous CSE should be enabled in GISel passes.
Definition: TargetPassConfig.cpp:1566
llvm::createExpandMemCmpPass
FunctionPass * createExpandMemCmpPass()
Definition: ExpandMemCmp.cpp:920
PrintISelInput
static cl::opt< bool > PrintISelInput("print-isel-input", cl::Hidden, cl::desc("Print LLVM IR input to isel pass"))
llvm::ExceptionHandling::AIX
@ AIX
AIX Exception Handling.
Verify
ppc ctr loops PowerPC CTR Loops Verify
Definition: PPCCTRLoopsVerify.cpp:77
llvm::dbgs
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
DisablePostRAMachineSink
static cl::opt< bool > DisablePostRAMachineSink("disable-postra-machine-sink", cl::Hidden, cl::desc("Disable PostRA Machine Sinking"))
llvm::TargetPassConfig::addInstSelector
virtual bool addInstSelector()
addInstSelector - This method should install an instruction selector pass, which converts from LLVM c...
Definition: TargetPassConfig.h:239
CommandLine.h
llvm::LiveDebugValuesID
char & LiveDebugValuesID
LiveDebugValues pass.
Definition: LiveDebugValues.cpp:95
llvm::createLowerEmuTLSPass
ModulePass * createLowerEmuTLSPass()
LowerEmuTLS - This pass generates __emutls_[vt].xyz variables for all TLS variables for the emulated ...
llvm::createDwarfEHPass
FunctionPass * createDwarfEHPass(CodeGenOpt::Level OptLevel)
createDwarfEHPass - This pass mulches exception handling code into a form adapted to code generation.
Definition: DwarfEHPrepare.cpp:370
llvm::TargetPassConfig::TM
LLVMTargetMachine * TM
Definition: TargetPassConfig.h:122
llvm::registerCodeGenCallback
void registerCodeGenCallback(PassInstrumentationCallbacks &PIC, LLVMTargetMachine &)
Definition: TargetPassConfig.cpp:584
DisablePostRAMachineLICM
static cl::opt< bool > DisablePostRAMachineLICM("disable-postra-machine-licm", cl::Hidden, cl::desc("Disable Machine LICM"))
TargetMachine.h
llvm::PassRegistry::getPassRegistry
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
Definition: PassRegistry.cpp:31
llvm::SelectionDAG
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:220
llvm::TargetPassConfig::printAndVerify
void printAndVerify(const std::string &Banner)
printAndVerify - Add a pass to dump then verify the machine function, if those steps are enabled.
Definition: TargetPassConfig.cpp:801
llvm::PrologEpilogCodeInserterID
char & PrologEpilogCodeInserterID
PrologEpilogCodeInserter - This pass inserts prolog and epilog code, and eliminates abstract frame re...
Definition: PrologEpilogInserter.cpp:138
DisableCFIFixup
static cl::opt< bool > DisableCFIFixup("disable-cfi-fixup", cl::Hidden, cl::desc("Disable the CFI fixup pass"))
llvm::FEntryInserterID
char & FEntryInserterID
This pass inserts FEntry calls.
Definition: FEntryInserter.cpp:48
llvm::createConstantHoistingPass
FunctionPass * createConstantHoistingPass()
Definition: ConstantHoisting.cpp:139
EarlyLiveIntervals
static cl::opt< bool > EarlyLiveIntervals("early-live-intervals", cl::Hidden, cl::desc("Run live interval analysis earlier in the pipeline"))
llvm::TargetPassConfig::substitutePass
void substitutePass(AnalysisID StandardID, IdentifyingPassPtr TargetID)
Allow the target to override a specific pass without overriding the pass pipeline.
Definition: TargetPassConfig.cpp:709
llvm::IdentifyingPassPtr::isValid
bool isValid() const
Definition: TargetPassConfig.h:65
llvm::TargetPassConfig::addVerifyPass
void addVerifyPass(const std::string &Banner)
Add a pass to perform basic verification of the machine function if verification is enabled.
Definition: TargetPassConfig.cpp:811
StopBeforeOptName
static const char StopBeforeOptName[]
Definition: TargetPassConfig.cpp:229
llvm::createPreISelIntrinsicLoweringPass
ModulePass * createPreISelIntrinsicLoweringPass()
This pass lowers the @llvm.load.relative and @llvm.objc.
llvm::TargetPassConfig::hasLimitedCodeGenPipeline
static bool hasLimitedCodeGenPipeline()
Returns true if one of the -start-after, -start-before, -stop-after or -stop-before options is set.
Definition: TargetPassConfig.cpp:678
llvm::TargetOptions::EnableIPRA
unsigned EnableIPRA
This flag enables InterProcedural Register Allocation (IPRA).
Definition: TargetOptions.h:297
PrintGCInfo
static cl::opt< bool > PrintGCInfo("print-gc", cl::Hidden, cl::desc("Dump garbage collector data"))
llvm::FuncletLayoutID
char & FuncletLayoutID
This pass lays out funclets contiguously.
Definition: FuncletLayout.cpp:39
llvm::GCMachineCodeAnalysisID
char & GCMachineCodeAnalysisID
GCMachineCodeAnalysis - Target-independent pass to mark safe points in machine code.
Definition: GCRootLowering.cpp:238
llvm::TargetOptions::SupportsDefaultOutlining
unsigned SupportsDefaultOutlining
Set if the target supports default outlining behaviour.
Definition: TargetOptions.h:309
PassInstrumentation.h
INITIALIZE_PASS
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:37
initializeDefaultRegisterAllocatorOnce
static void initializeDefaultRegisterAllocatorOnce()
Definition: TargetPassConfig.cpp:1366
DisablePartialLibcallInlining
static cl::opt< bool > DisablePartialLibcallInlining("disable-partial-libcall-inlining", cl::Hidden, cl::desc("Disable Partial Libcall Inlining"))
llvm::createReplaceWithVeclibLegacyPass
FunctionPass * createReplaceWithVeclibLegacyPass()
Definition: ReplaceWithVeclib.cpp:251
IP
Definition: NVPTXLowerArgs.cpp:167
llvm::createResetMachineFunctionPass
MachineFunctionPass * createResetMachineFunctionPass(bool EmitFallbackDiag, bool AbortOnFailedISel)
This pass resets a MachineFunction when it has the FailedISel property as if it was just created.
DISABLE_PASS
#define DISABLE_PASS(Option, Name)
llvm::RegisterCoalescerID
char & RegisterCoalescerID
RegisterCoalescer - This pass merges live ranges to eliminate copies.
Definition: RegisterCoalescer.cpp:410
useDefaultRegisterAllocator
static FunctionPass * useDefaultRegisterAllocator()
-regalloc=... command line option.
Definition: TargetPassConfig.cpp:1125
llvm::EarlyIfConverterID
char & EarlyIfConverterID
EarlyIfConverter - This pass performs if-conversion on SSA form by inserting cmov instructions.
Definition: EarlyIfConversion.cpp:782
llvm::sampleprof::Pass2
@ Pass2
Definition: Discriminator.h:61
PrintLSR
static cl::opt< bool > PrintLSR("print-lsr-output", cl::Hidden, cl::desc("Print LLVM IR produced by the loop-reduce pass"))
llvm::Triple::isOSBinFormatMachO
bool isOSBinFormatMachO() const
Tests whether the environment is MachO.
Definition: Triple.h:669
llvm::createMIRProfileLoaderPass
FunctionPass * createMIRProfileLoaderPass(std::string File, std::string RemappingFile, sampleprof::FSDiscriminatorPass P)
Read Flow Sensitive Profile.
Definition: MIRSampleProfile.cpp:75
llvm::TargetPassConfig::isGlobalISelAbortEnabled
bool isGlobalISelAbortEnabled() const
Check whether or not GlobalISel should abort on error.
Definition: TargetPassConfig.cpp:1558
llvm::TargetPassConfig::getPassSubstitution
IdentifyingPassPtr getPassSubstitution(AnalysisID StandardID) const
Return the pass substituted for StandardID by the target.
Definition: TargetPassConfig.cpp:714
llvm::PassRegistry
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
Definition: PassRegistry.h:38
llvm::TargetPassConfig::addMachinePrePasses
void addMachinePrePasses(bool AllowDebugify=true)
Add standard passes before a pass that's about to be added.
Definition: TargetPassConfig.cpp:833
llvm::report_fatal_error
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:143
IRPrintingPasses.h
llvm::ExceptionHandling::Wasm
@ Wasm
WebAssembly Exception Handling.
llvm::cl::Option::getNumOccurrences
int getNumOccurrences() const
Definition: CommandLine.h:395
llvm::createRegAllocScoringPass
FunctionPass * createRegAllocScoringPass()
When learning an eviction policy, extract score(reward) information, otherwise this does nothing.
Definition: MLRegallocEvictAdvisor.cpp:103
StartAfterOpt
static cl::opt< std::string > StartAfterOpt(StringRef(StartAfterOptName), cl::desc("Resume compilation after a specific pass"), cl::value_desc("pass-name"), cl::init(""), cl::Hidden)
getFSProfileFile
static std::string getFSProfileFile(const TargetMachine *TM)
Definition: TargetPassConfig.cpp:339
llvm::StackMapLivenessID
char & StackMapLivenessID
StackMapLiveness - This pass analyses the register live-out set of stackmap/patchpoint intrinsics and...
Definition: StackMapLivenessAnalysis.cpp:86
llvm::CGPassBuilderOption
Definition: CGPassBuilderOption.h:29
llvm::PassInstrumentationCallbacks::registerShouldRunOptionalPassCallback
void registerShouldRunOptionalPassCallback(CallableT C)
Definition: PassInstrumentation.h:96
StopBeforeOpt
static cl::opt< std::string > StopBeforeOpt(StringRef(StopBeforeOptName), cl::desc("Stop compilation before a specific pass"), cl::value_desc("pass-name"), cl::init(""), cl::Hidden)
llvm::TargetPassConfig::addPostFastRegAllocRewrite
virtual bool addPostFastRegAllocRewrite()
addPostFastRegAllocRewrite - Add passes to the optimized register allocation pipeline after fast regi...
Definition: TargetPassConfig.h:409
CFLAndersAliasAnalysis.h
Utils.h
ScopedNoAliasAA.h
llvm::RegisterPassParser
RegisterPassParser class - Handle the addition of new machine passes.
Definition: MachinePassRegistry.h:135
llvm::StringRef::getAsInteger
std::enable_if_t< std::numeric_limits< T >::is_signed, bool > getAsInteger(unsigned Radix, T &Result) const
Parse the current string as an integer of the specified radix.
Definition: StringRef.h:514
llvm::None
const NoneType None
Definition: None.h:24
llvm::TargetPassConfig::setRequiresCodeGenSCCOrder
void setRequiresCodeGenSCCOrder(bool Enable=true)
Definition: TargetPassConfig.h:180
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::createMachineOutlinerPass
ModulePass * createMachineOutlinerPass(bool RunOnAllFunctions=true)
This pass performs outlining on machine instructions directly before printing assembly.
Definition: MachineOutliner.cpp:458
llvm::createCFIFixup
FunctionPass * createCFIFixup()
Creates CFI Fixup pass.
llvm::initializeCodeGen
void initializeCodeGen(PassRegistry &)
Initialize all passes linked into the CodeGen library.
Definition: CodeGen.cpp:21
DisableMergeICmps
static cl::opt< bool > DisableMergeICmps("disable-mergeicmps", cl::desc("Disable MergeICmps Pass"), cl::init(false), cl::Hidden)
llvm::createMachineFunctionPrinterPass
MachineFunctionPass * createMachineFunctionPrinterPass(raw_ostream &OS, const std::string &Banner="")
MachineFunctionPrinter pass - This pass prints out the machine function to the given stream as a debu...
llvm::legacy::PassManagerBase::add
virtual void add(Pass *P)=0
Add a pass to the queue of passes to run.
InitializeDefaultRegisterAllocatorFlag
static llvm::once_flag InitializeDefaultRegisterAllocatorFlag
A dummy default pass factory indicates whether the register allocator is overridden on the command li...
Definition: TargetPassConfig.cpp:1359
llvm::createCanonicalizeFreezeInLoopsPass
Pass * createCanonicalizeFreezeInLoopsPass()
Definition: CanonicalizeFreezeInLoops.cpp:244
StartAfterOptName
static const char StartAfterOptName[]
Option names for limiting the codegen pipeline.
Definition: TargetPassConfig.cpp:226
llvm::EarlyTailDuplicateID
char & EarlyTailDuplicateID
Duplicate blocks with unconditional branches into tails of their predecessors.
Definition: TailDuplication.cpp:77
DisableRAFSProfileLoader
static cl::opt< bool > DisableRAFSProfileLoader("disable-ra-fsprofile-loader", cl::init(false), cl::Hidden, cl::desc("Disable MIRProfileLoader before RegAlloc"))
llvm::createTargetTransformInfoWrapperPass
ImmutablePass * createTargetTransformInfoWrapperPass(TargetIRAnalysis TIRA)
Create an analysis pass wrapper around a TTI object.
Definition: TargetTransformInfo.cpp:1228
getPassIDFromName
static AnalysisID getPassIDFromName(StringRef PassName)
Definition: TargetPassConfig.cpp:427
Passes.h
llvm::VirtRegRewriterID
char & VirtRegRewriterID
VirtRegRewriter pass.
Definition: VirtRegMap.cpp:227
llvm::TargetPassConfig
Target-Independent Code Generator Pass Configuration Options.
Definition: TargetPassConfig.h:84
StartBeforeOpt
static cl::opt< std::string > StartBeforeOpt(StringRef(StartBeforeOptName), cl::desc("Resume compilation before a specific pass"), cl::value_desc("pass-name"), cl::init(""), cl::Hidden)
llvm::sampleprof::PassLast
@ PassLast
Definition: Discriminator.h:64
StartBeforeOptName
static const char StartBeforeOptName[]
Definition: TargetPassConfig.cpp:227
llvm::TargetPassConfig::usingDefaultRegAlloc
bool usingDefaultRegAlloc() const
Return true if the default global register allocator is in use and has not be overriden on the comman...
Definition: TargetPassConfig.cpp:1439
llvm::MachineLoopInfoID
char & MachineLoopInfoID
MachineLoopInfo - This pass is a loop analysis pass.
Definition: MachineLoopInfo.cpp:43
llvm::cl::opt< bool >
llvm::TargetOptions::EnableGlobalISel
unsigned EnableGlobalISel
EnableGlobalISel - This flag enables global instruction selection.
Definition: TargetOptions.h:235
llvm::TargetPassConfig::DisableVerify
bool DisableVerify
Definition: TargetPassConfig.h:128
llvm::TargetPassConfig::addMachinePasses
virtual void addMachinePasses()
Add the complete, standard set of LLVM CodeGen passes.
Definition: TargetPassConfig.cpp:1149
llvm::TargetPassConfig::isPassSubstitutedOrOverridden
bool isPassSubstitutedOrOverridden(AnalysisID ID) const
Return true if the pass has been substituted by the target or overridden on the command line.
Definition: TargetPassConfig.cpp:722
llvm::GCLoweringID
char & GCLoweringID
GCLowering Pass - Used by gc.root to perform its default lowering operations.
Definition: GCRootLowering.cpp:85
llvm::CFLAAType::None
@ None
registerPartialPipelineCallback
static void registerPartialPipelineCallback(PassInstrumentationCallbacks &PIC, LLVMTargetMachine &LLVMTM)
Definition: TargetPassConfig.cpp:509
Threading.h
llvm::TargetPassConfig::getLimitedCodeGenPipelineReason
static std::string getLimitedCodeGenPipelineReason(const char *Separator="/")
If hasLimitedCodeGenPipeline is true, this method returns a string with the name of the options,...
Definition: TargetPassConfig.cpp:684
llvm::TargetPassConfig::addRegBankSelect
virtual bool addRegBankSelect()
This method should install a register bank selector pass, which assigns register banks to virtual reg...
Definition: TargetPassConfig.h:262
llvm::TargetMachine::setO0WantsFastISel
void setO0WantsFastISel(bool Enable)
Definition: TargetMachine.h:245
llvm::cl::values
ValuesClass values(OptsTy... Options)
Helper to build a ValuesClass by forwarding a variable number of arguments as an initializer list to ...
Definition: CommandLine.h:685
llvm::cl::BOU_UNSET
@ BOU_UNSET
Definition: CommandLine.h:611
llvm::StackColoringID
char & StackColoringID
StackSlotColoring - This pass performs stack coloring and merging.
Definition: StackColoring.cpp:549
llvm::StringRef::empty
constexpr LLVM_NODISCARD bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:153
DisableEarlyTailDup
static cl::opt< bool > DisableEarlyTailDup("disable-early-taildup", cl::Hidden, cl::desc("Disable pre-register allocation tail duplication"))
SaveAndRestore.h
EnableGlobalISelOption
static cl::opt< cl::boolOrDefault > EnableGlobalISelOption("global-isel", cl::Hidden, cl::desc("Enable the \"global\" instruction selector"))
defaultRegAlloc
static RegisterRegAlloc defaultRegAlloc("default", "pick register allocator based on -O option", useDefaultRegisterAllocator)
llvm::RegisterRegAllocBase< RegisterRegAlloc >::FunctionPassCtor
FunctionPass *(*)() FunctionPassCtor
Definition: RegAllocRegistry.h:32
llvm::MachineSinkingID
char & MachineSinkingID
MachineSinking - This pass performs sinking on machine instructions.
Definition: MachineSink.cpp:260
llvm::DetectDeadLanesID
char & DetectDeadLanesID
This pass adds dead/undef flags after analyzing subregister lanes.
Definition: DetectDeadLanes.cpp:125
llvm::TargetPassConfig::addPreGlobalInstructionSelect
virtual void addPreGlobalInstructionSelect()
This method may be implemented by targets that want to run passes immediately before the (global) ins...
Definition: TargetPassConfig.h:266
applyDisable
static IdentifyingPassPtr applyDisable(IdentifyingPassPtr PassID, bool Override)
Allow standard passes to be disabled by command line options.
Definition: TargetPassConfig.cpp:271
llvm::DenseMap
Definition: DenseMap.h:716
llvm::PGOOptions::ProfileFile
std::string ProfileFile
Definition: PGOOptions.h:55
INITIALIZE_PASS::InsertedPass::getInsertedPass
Pass * getInsertedPass() const
Definition: TargetPassConfig.cpp:376
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::TargetPassConfig::addIRPasses
virtual void addIRPasses()
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
Definition: TargetPassConfig.cpp:853
EnableBlockPlacementStats
static cl::opt< bool > EnableBlockPlacementStats("enable-block-placement-stats", cl::Hidden, cl::desc("Collect probability-driven block placement stats"))
llvm::cl::init
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:432
llvm::TargetPassConfig::addOptimizedRegAlloc
virtual void addOptimizedRegAlloc()
addOptimizedRegAlloc - Add passes related to register allocation.
Definition: TargetPassConfig.cpp:1455
llvm::TargetPassConfig::addRegAssignAndRewriteOptimized
virtual bool addRegAssignAndRewriteOptimized()
Definition: TargetPassConfig.cpp:1421
llvm::createPartiallyInlineLibCallsPass
FunctionPass * createPartiallyInlineLibCallsPass()
Definition: PartiallyInlineLibCalls.cpp:215
llvm::createRegUsageInfoPropPass
FunctionPass * createRegUsageInfoPropPass()
Return a MachineFunction pass that identifies call sites and propagates register usage information of...
Definition: RegUsageInfoPropagate.cpp:152
llvm::createMachineVerifierPass
FunctionPass * createMachineVerifierPass(const std::string &Banner)
createMachineVerifierPass - This pass verifies cenerated machine code instructions for correctness.
llvm::LiveVariablesID
char & LiveVariablesID
LiveVariables pass - This pass computes the set of blocks in which each variable is life and sets mac...
Definition: LiveVariables.cpp:45
overridePass
static IdentifyingPassPtr overridePass(AnalysisID StandardID, IdentifyingPassPtr TargetID)
Allow standard passes to be disabled by the command line, regardless of who is adding the pass.
Definition: TargetPassConfig.cpp:290
TargetPassConfig.h
MachineFunctionPass.h
llvm::TargetPassConfig::addPreEmitPass2
virtual void addPreEmitPass2()
Targets may add passes immediately before machine code is emitted in this callback.
Definition: TargetPassConfig.h:443
llvm::TargetMachine::getTargetIRAnalysis
TargetIRAnalysis getTargetIRAnalysis() const
Get a TargetIRAnalysis appropriate for the target.
Definition: TargetMachine.cpp:219
llvm::MachineCSEID
char & MachineCSEID
MachineCSE - This pass performs global CSE on machine instructions.
Definition: MachineCSE.cpp:157
llvm::FinalizeISelID
char & FinalizeISelID
This pass expands pseudo-instructions, reserves registers and adjusts machine frame information.
Definition: FinalizeISel.cpp:42
llvm::TargetMachine::Options
TargetOptions Options
Definition: TargetMachine.h:118
llvm::TargetPassConfig::addCodeGenPrepare
virtual void addCodeGenPrepare()
Add pass to prepare the LLVM IR for code generation.
Definition: TargetPassConfig.cpp:995
llvm::TargetPassConfig::getOptimizeRegAlloc
bool getOptimizeRegAlloc() const
Return true if the optimized regalloc pipeline is enabled.
Definition: TargetPassConfig.cpp:1348
llvm::createExpandReductionsPass
FunctionPass * createExpandReductionsPass()
This pass expands the experimental reduction intrinsics into sequences of shuffles.
Definition: ExpandReductions.cpp:200
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::TargetMachine
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:77
llvm::DummyCGSCCPass
This pass is required by interprocedural register allocation.
Definition: CallGraphSCCPass.h:122
DisableEarlyIfConversion
static cl::opt< bool > DisableEarlyIfConversion("disable-early-ifcvt", cl::Hidden, cl::desc("Disable Early If-conversion"))
llvm::TargetPassConfig::addCheckDebugPass
void addCheckDebugPass()
Add a pass to check synthesized debug info for MIR.
Definition: TargetPassConfig.cpp:829
llvm::createExpandVectorPredicationPass
FunctionPass * createExpandVectorPredicationPass()
This pass expands the vector predication intrinsics into unpredicated instructions with selects or ju...
Definition: ExpandVectorPredication.cpp:601
EnableGlobalISelAbort
static cl::opt< GlobalISelAbortMode > EnableGlobalISelAbort("global-isel-abort", cl::Hidden, cl::desc("Enable abort calls when \"global\" instruction selection " "fails to lower/select an instruction"), cl::values(clEnumValN(GlobalISelAbortMode::Disable, "0", "Disable the abort"), clEnumValN(GlobalISelAbortMode::Enable, "1", "Enable the abort"), clEnumValN(GlobalISelAbortMode::DisableWithDiag, "2", "Disable the abort but emit a diagnostic on failure")))
getFSRemappingFile
static std::string getFSRemappingFile(const TargetMachine *TM)
Definition: TargetPassConfig.cpp:350
llvm::createTypeBasedAAWrapperPass
ImmutablePass * createTypeBasedAAWrapperPass()
llvm::ProcessImplicitDefsID
char & ProcessImplicitDefsID
ProcessImpicitDefs pass - This pass removes IMPLICIT_DEFs.
Definition: ProcessImplicitDefs.cpp:58
llvm::FastISel
This is a fast-path instruction selection class that generates poor code and doesn't support illegal ...
Definition: FastISel.h:65
llvm::RegisterRegAllocBase< RegisterRegAlloc >::getDefault
static FunctionPassCtor getDefault()
Definition: RegAllocRegistry.h:52
llvm::TargetPassConfig::addIRTranslator
virtual bool addIRTranslator()
This method should install an IR translator pass, which converts from LLVM code to machine instructio...
Definition: TargetPassConfig.h:245
llvm::PatchableFunctionID
char & PatchableFunctionID
This pass implements the "patchable-function" attribute.
Definition: PatchableFunction.cpp:96
llvm::MachineBlockPlacementStatsID
char & MachineBlockPlacementStatsID
MachineBlockPlacementStats - This pass collects statistics about the basic block placement using bran...
Definition: MachineBlockPlacement.cpp:3649
llvm::CFLAAType::Steensgaard
@ Steensgaard
llvm::CodeGenOpt::None
@ None
Definition: CodeGen.h:53
llvm::TargetPassConfig::addISelPasses
bool addISelPasses()
High level function that adds all passes necessary to go from llvm IR representation to the MI repres...
Definition: TargetPassConfig.cpp:1110
llvm::createSjLjEHPreparePass
FunctionPass * createSjLjEHPreparePass(const TargetMachine *TM)
createSjLjEHPreparePass - This pass adapts exception handling code to use the GCC-style builtin setjm...
llvm::TargetMachine::getMCAsmInfo
const MCAsmInfo * getMCAsmInfo() const
Return target specific asm information.
Definition: TargetMachine.h:205
llvm::TargetPassConfig::addPass
AnalysisID addPass(AnalysisID PassID)
Utilities for targets to add passes to the pass manager.
Definition: TargetPassConfig.cpp:781
llvm::initializeAAResultsWrapperPassPass
void initializeAAResultsWrapperPassPass(PassRegistry &)
MCAsmInfo.h
llvm::XRayInstrumentationID
char & XRayInstrumentationID
This pass inserts the XRay instrumentation sleds if they are supported by the target platform.
Definition: XRayInstrumentation.cpp:264
llvm::UnreachableMachineBlockElimID
char & UnreachableMachineBlockElimID
UnreachableMachineBlockElimination - This pass removes unreachable machine basic blocks.
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
SET_OPTION
#define SET_OPTION(Option)
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
if
if(llvm_vc STREQUAL "") set(fake_version_inc "$
Definition: CMakeLists.txt:14
llvm::createStripDebugMachineModulePass
ModulePass * createStripDebugMachineModulePass(bool OnlyDebugified)
Creates MIR Strip Debug pass.
Definition: MachineStripDebug.cpp:106
llvm::BranchFolderPassID
char & BranchFolderPassID
BranchFolding - This pass performs machine code CFG based optimizations to delete branches to branche...
Definition: BranchFolding.cpp:118
Compiler.h
llvm::MachineBlockPlacementID
char & MachineBlockPlacementID
MachineBlockPlacement - This pass places basic blocks based on branch probabilities.
Definition: MachineBlockPlacement.cpp:610
clEnumValN
#define clEnumValN(ENUMVAL, FLAGNAME, DESC)
Definition: CommandLine.h:660
llvm::ShrinkWrapID
char & ShrinkWrapID
ShrinkWrap pass. Look for the best place to insert save and restore.
Definition: ShrinkWrap.cpp:250
llvm::createWinEHPass
FunctionPass * createWinEHPass(bool DemoteCatchSwitchPHIOnly=false)
createWinEHPass - Prepares personality functions used by MSVC on Windows, in addition to the Itanium ...
llvm::RunOutliner::AlwaysOutline
@ AlwaysOutline
llvm::TargetPassConfig::reportDiagnosticWhenGlobalISelFallback
virtual bool reportDiagnosticWhenGlobalISelFallback() const
Check whether or not a diagnostic should be emitted when GlobalISel uses the fallback path.
Definition: TargetPassConfig.cpp:1562
llvm::SaveAndRestore
A utility class that uses RAII to save and restore the value of a variable.
Definition: SaveAndRestore.h:21
llvm::TargetPassConfig::addDebugifyPass
void addDebugifyPass()
Add a pass to add synthesized debug info to the MIR.
Definition: TargetPassConfig.cpp:821
llvm::createDebugifyMachineModulePass
ModulePass * createDebugifyMachineModulePass()
Creates MIR Debugify pass.
Definition: MachineDebugify.cpp:197
DisableLSR
static cl::opt< bool > DisableLSR("disable-lsr", cl::Hidden, cl::desc("Disable Loop Strength Reduction Pass"))
llvm::GlobalISelAbortMode::DisableWithDiag
@ DisableWithDiag
llvm::once_flag
std::once_flag once_flag
Definition: Threading.h:57
OptimizeRegAlloc
static cl::opt< cl::boolOrDefault > OptimizeRegAlloc("optimize-regalloc", cl::Hidden, cl::desc("Enable optimized register allocation compilation path."))
llvm::getCGPassBuilderOption
CGPassBuilderOption getCGPassBuilderOption()
Definition: TargetPassConfig.cpp:474
adjust::pm
static void pm(uint64_t &Value)
Adjusts a program memory address.
Definition: AVRAsmBackend.cpp:192
llvm::CodeGenOpt::Level
Level
Definition: CodeGen.h:52
CallGraphSCCPass.h
llvm::createVerifierPass
FunctionPass * createVerifierPass(bool FatalErrors=true)
Definition: Verifier.cpp:6573
llvm::TargetMachine::setFastISel
void setFastISel(bool Enable)
Definition: TargetMachine.h:243
llvm::TargetPassConfig::addPreRegAlloc
virtual void addPreRegAlloc()
This method may be implemented by targets that want to run passes immediately before register allocat...
Definition: TargetPassConfig.h:377
LLVM_FALLTHROUGH
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:280
INITIALIZE_PASS::InsertedPass::InsertedPass
InsertedPass(AnalysisID TargetPassID, IdentifyingPassPtr InsertedPassID)
Definition: TargetPassConfig.cpp:373
llvm::PGOOptions::Action
PGOAction Action
Definition: PGOOptions.h:58
llvm::RenameIndependentSubregsID
char & RenameIndependentSubregsID
This pass detects subregister lanes in a virtual register that are used independently of other lanes ...
Definition: RenameIndependentSubregs.cpp:113
DisableMachineCSE
static cl::opt< bool > DisableMachineCSE("disable-machine-cse", cl::Hidden, cl::desc("Disable Machine Common Subexpression Elimination"))
llvm::createTLSVariableHoistPass
FunctionPass * createTLSVariableHoistPass()
Definition: TLSVariableHoist.cpp:84
llvm::FixupStatepointCallerSavedID
char & FixupStatepointCallerSavedID
The pass fixups statepoint machine instruction to replace usage of caller saved registers with stack ...
Definition: FixupStatepointCallerSaved.cpp:84
llvm::PassConfigImpl::TargetPasses
DenseMap< AnalysisID, IdentifyingPassPtr > TargetPasses
Definition: TargetPassConfig.cpp:401
llvm::TargetPassConfig::getCSEConfig
virtual std::unique_ptr< CSEConfigBase > getCSEConfig() const
Returns the CSEConfig object to use for the current optimization level.
Definition: TargetPassConfig.cpp:1570
llvm::createBasicAAWrapperPass
FunctionPass * createBasicAAWrapperPass()
Definition: BasicAliasAnalysis.cpp:1888
llvm::createRegUsageInfoCollector
FunctionPass * createRegUsageInfoCollector()
This pass is executed POST-RA to collect which physical registers are preserved by given machine func...
Definition: RegUsageInfoCollector.cpp:75
llvm::createMIRAddFSDiscriminatorsPass
FunctionPass * createMIRAddFSDiscriminatorsPass(sampleprof::FSDiscriminatorPass P)
Add Flow Sensitive Discriminators.
llvm::Twine
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:83
llvm::Any
Definition: Any.h:28
Verifier.h
llvm::empty
constexpr bool empty(const T &RangeOrContainer)
Test whether RangeOrContainer is empty. Similar to C++17 std::empty.
Definition: STLExtras.h:268
llvm::TargetPassConfig::requiresCodeGenSCCOrder
bool requiresCodeGenSCCOrder() const
Definition: TargetPassConfig.h:179
llvm::GraphProgram::Name
Name
Definition: GraphWriter.h:50
llvm::call_once
void call_once(once_flag &flag, Function &&F, Args &&... ArgList)
Execute the function specified as a parameter once.
Definition: Threading.h:87
llvm::TargetOptions::LowerGlobalDtorsViaCxaAtExit
unsigned LowerGlobalDtorsViaCxaAtExit
Use __cxa_atexit to register global destructors; determines how llvm.global_dtors is lowered.
Definition: TargetOptions.h:252
llvm::createSelectOptimizePass
FunctionPass * createSelectOptimizePass()
This pass converts conditional moves to conditional jumps when profitable.
Definition: SelectOptimize.cpp:229
llvm::TargetPassConfig::Impl
PassConfigImpl * Impl
Definition: TargetPassConfig.h:123
llvm::TargetPassConfig::addMachineSSAOptimization
virtual void addMachineSSAOptimization()
addMachineSSAOptimization - Add standard passes that optimize machine instructions in SSA form.
Definition: TargetPassConfig.cpp:1306
BasicBlockSectionsProfileReader.h
llvm::createScalarizeMaskedMemIntrinLegacyPass
FunctionPass * createScalarizeMaskedMemIntrinLegacyPass()
Definition: ScalarizeMaskedMemIntrin.cpp:86
llvm::TargetOptions::GlobalISelAbort
GlobalISelAbortMode GlobalISelAbort
EnableGlobalISelAbort - Control abort behaviour when global instruction selection fails to lower/sele...
Definition: TargetOptions.h:239
llvm::createScopedNoAliasAAWrapperPass
ImmutablePass * createScopedNoAliasAAWrapperPass()
llvm::createWasmEHPass
FunctionPass * createWasmEHPass()
createWasmEHPass - This pass adapts exception handling code to use WebAssembly's exception handling s...
Definition: WasmEHPrepare.cpp:134
llvm::TargetPassConfig::addLegalizeMachineIR
virtual bool addLegalizeMachineIR()
This method should install a legalize pass, which converts the instruction sequence into one that can...
Definition: TargetPassConfig.h:253
llvm::ExceptionHandling::WinEH
@ WinEH
Windows Exception Handling.
llvm::TargetPassConfig::addMachinePostPasses
void addMachinePostPasses(const std::string &Banner)
Add standard passes after a pass that has just been added.
Definition: TargetPassConfig.cpp:840
llvm::TailDuplicateID
char & TailDuplicateID
TailDuplicate - Duplicate blocks with unconditional branches into tails of their predecessors.
Definition: TailDuplication.cpp:76
llvm::LLVMTargetMachine
This class describes a target machine that is implemented with the LLVM target-independent code gener...
Definition: TargetMachine.h:411
llvm::IdentifyingPassPtr::getID
AnalysisID getID() const
Definition: TargetPassConfig.h:68
llvm::cl::value_desc
Definition: CommandLine.h:414
llvm::TargetMachine::setGlobalISel
void setGlobalISel(bool Enable)
Definition: TargetMachine.h:246
llvm::DeadMachineInstructionElimID
char & DeadMachineInstructionElimID
DeadMachineInstructionElim - This pass removes dead machine instructions.
Definition: DeadMachineInstructionElim.cpp:56
llvm::TargetOptions::EnableMachineOutliner
unsigned EnableMachineOutliner
Enables the MachineOutliner pass.
Definition: TargetOptions.h:303
DisableSSC
static cl::opt< bool > DisableSSC("disable-ssc", cl::Hidden, cl::desc("Disable Stack Slot Coloring"))
llvm::TargetPassConfig::addBlockPlacement
virtual void addBlockPlacement()
Add standard basic block placement passes.
Definition: TargetPassConfig.cpp:1538
llvm::ExceptionHandling::None
@ None
No exception support.
llvm::TargetMachine::getBBSectionsFuncListBuf
const MemoryBuffer * getBBSectionsFuncListBuf() const
Get the list of functions and basic block ids that need unique sections.
Definition: TargetMachine.h:302
llvm::MachineSchedulerID
char & MachineSchedulerID
MachineScheduler - This pass schedules machine instructions.
Definition: MachineScheduler.cpp:213
CodeGen.h
llvm::sampleprof::Pass1
@ Pass1
Definition: Discriminator.h:60
llvm::MCAsmInfo::getExceptionHandlingType
ExceptionHandling getExceptionHandlingType() const
Definition: MCAsmInfo.h:777
DisableMachineDCE
static cl::opt< bool > DisableMachineDCE("disable-machine-dce", cl::Hidden, cl::desc("Disable Machine Dead Code Elimination"))
llvm::TargetPassConfig::createTargetRegisterAllocator
virtual FunctionPass * createTargetRegisterAllocator(bool Optimized)
createTargetRegisterAllocator - Create the register allocator pass for this target at the current opt...
Definition: TargetPassConfig.cpp:1379
llvm::cl::BOU_TRUE
@ BOU_TRUE
Definition: CommandLine.h:611
llvm::GlobalISelAbortMode::Enable
@ Enable
llvm::Pass
Pass interface - Implemented by all 'passes'.
Definition: Pass.h:91
llvm::TargetPassConfig::addISelPrepare
virtual void addISelPrepare()
Add common passes that perform LLVM IR to IR transforms in preparation for instruction selection.
Definition: TargetPassConfig.cpp:1002
llvm::TargetPassConfig::addGlobalInstructionSelect
virtual bool addGlobalInstructionSelect()
This method should install a (global) instruction selector pass, which converts possibly generic inst...
Definition: TargetPassConfig.h:272
llvm::PostRASchedulerID
char & PostRASchedulerID
PostRAScheduler - This pass performs post register allocation scheduling.
Definition: PostRASchedulerList.cpp:197
SmallVector.h
llvm::createLowerConstantIntrinsicsPass
FunctionPass * createLowerConstantIntrinsicsPass()
Definition: LowerConstantIntrinsics.cpp:203
llvm::PassInstrumentationCallbacks
This class manages callbacks registration, as well as provides a way for PassInstrumentation to pass ...
Definition: PassInstrumentation.h:66
llvm::LLVMTargetMachine::getPassNameFromLegacyName
virtual std::pair< StringRef, bool > getPassNameFromLegacyName(StringRef)
Definition: TargetMachine.h:451
llvm::TargetMachine::getTargetTriple
const Triple & getTargetTriple() const
Definition: TargetMachine.h:126
llvm::PGOOptions::ProfileRemappingFile
std::string ProfileRemappingFile
Definition: PGOOptions.h:57
DisableMachineLICM
static cl::opt< bool > DisableMachineLICM("disable-machine-licm", cl::Hidden, cl::desc("Disable Machine LICM"))
RegAlloc
static cl::opt< RegisterRegAlloc::FunctionPassCtor, false, RegisterPassParser< RegisterRegAlloc > > RegAlloc("regalloc", cl::Hidden, cl::init(&useDefaultRegisterAllocator), cl::desc("Register allocator to use"))
TargetTransformInfo.h
llvm::TargetPassConfig::addPreISel
virtual bool addPreISel()
Methods with trivial inline returns are convenient points in the common codegen pass pipeline where t...
Definition: TargetPassConfig.h:357
llvm::legacy::PassManagerBase
PassManagerBase - An abstract interface to allow code to add passes to a pass manager without having ...
Definition: LegacyPassManager.h:39
llvm::TargetPassConfig::addPassesToHandleExceptions
void addPassesToHandleExceptions()
Add passes to lower exception handling for the code generator.
Definition: TargetPassConfig.cpp:951
llvm::GlobalISelAbortMode::Disable
@ Disable
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::FunctionPass
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:308
EnableImplicitNullChecks
static cl::opt< bool > EnableImplicitNullChecks("enable-implicit-null-checks", cl::desc("Fold null checks into faulting memory operations"), cl::init(false), cl::Hidden)
llvm::ImplicitNullChecksID
char & ImplicitNullChecksID
ImplicitNullChecks - This pass folds null pointer checks into nearby memory operations.
Definition: ImplicitNullChecks.cpp:816
llvm::EarlyMachineLICMID
char & EarlyMachineLICMID
This pass performs loop invariant code motion on machine instructions.
Definition: MachineLICM.cpp:298
llvm::TargetPassConfig::TargetPassConfig
TargetPassConfig()
Definition: TargetPassConfig.cpp:667
llvm::PostMachineSchedulerID
char & PostMachineSchedulerID
PostMachineScheduler - This pass schedules machine instructions postRA.
Definition: MachineScheduler.cpp:244
llvm::PostRAMachineSinkingID
char & PostRAMachineSinkingID
This pass perform post-ra machine sink for COPY instructions.
Definition: MachineSink.cpp:1622
llvm::RemoveRedundantDebugValuesID
char & RemoveRedundantDebugValuesID
RemoveRedundantDebugValues pass.
Definition: RemoveRedundantDebugValues.cpp:61
llvm::cl::desc
Definition: CommandLine.h:405
llvm::PassRegistry::getPassInfo
const PassInfo * getPassInfo(const void *TI) const
getPassInfo - Look up a pass' corresponding PassInfo, indexed by the pass' type identifier (&MyPass::...
Definition: PassRegistry.cpp:41
llvm::TargetPassConfig::addPreEmitPass
virtual void addPreEmitPass()
This pass may be implemented by targets that want to run passes immediately before machine code is em...
Definition: TargetPassConfig.h:436
VerifyMachineCode
static cl::opt< cl::boolOrDefault > VerifyMachineCode("verify-machineinstrs", cl::Hidden, cl::desc("Verify generated machine code"))
llvm::TargetPassConfig::insertPass
void insertPass(AnalysisID TargetPassID, IdentifyingPassPtr InsertedPassID)
Insert InsertedPassID pass after TargetPassID pass.
Definition: TargetPassConfig.cpp:649
llvm::createSafeStackPass
FunctionPass * createSafeStackPass()
This pass splits the stack into a safe stack and an unsafe stack to protect against stack-based overf...
Definition: SafeStack.cpp:938
llvm::TargetPassConfig::Initialized
bool Initialized
Definition: TargetPassConfig.h:124
llvm::TargetPassConfig::addFastRegAlloc
virtual void addFastRegAlloc()
addFastRegAlloc - Add the minimum set of target-independent passes that are required for fast registe...
Definition: TargetPassConfig.cpp:1445
llvm::TargetOptions::EnableCFIFixup
unsigned EnableCFIFixup
Enable the CFIFixup pass.
Definition: TargetOptions.h:361
llvm::TargetPassConfig::addCoreISelPasses
bool addCoreISelPasses()
Add the actual instruction selection passes.
Definition: TargetPassConfig.cpp:1024
SET_BOOLEAN_OPTION
#define SET_BOOLEAN_OPTION(Option)
llvm::LiveIntervalsID
char & LiveIntervalsID
LiveIntervals - This analysis keeps track of the live ranges of virtual and physical registers.
Definition: LiveIntervals.cpp:62
EnableIPRA
static cl::opt< bool > EnableIPRA("enable-ipra", cl::init(false), cl::Hidden, cl::desc("Enable interprocedural register allocation " "to reduce load/store at procedure calls."))
InitializePasses.h
llvm::LLVMTargetMachine::useIPRA
virtual bool useIPRA() const
True if the target wants to use interprocedural register allocation by default.
Definition: TargetMachine.h:490
llvm::createBasicBlockSectionsPass
MachineFunctionPass * createBasicBlockSectionsPass()
createBasicBlockSections Pass - This pass assigns sections to machine basic blocks and is enabled wit...
Definition: BasicBlockSections.cpp:392
llvm::TargetPassConfig::addPrintPass
void addPrintPass(const std::string &Banner)
Add a pass to print the machine function if printing is enabled.
Definition: TargetPassConfig.cpp:806
llvm::ExceptionHandling::DwarfCFI
@ DwarfCFI
DWARF-like instruction based exceptions.
StopAfterOptName
static const char StopAfterOptName[]
Definition: TargetPassConfig.cpp:228
Debug.h
llvm::TargetPassConfig::addILPOpts
virtual bool addILPOpts()
Add passes that optimize instruction level parallelism for out-of-order targets.
Definition: TargetPassConfig.h:371
llvm::TargetPassConfig::getOptLevel
CodeGenOpt::Level getOptLevel() const
Definition: TargetPassConfig.cpp:644
PassName
static const char PassName[]
Definition: X86LowerAMXIntrinsics.cpp:671
CFLSteensAliasAnalysis.h
llvm::TargetPassConfig::setOpt
void setOpt(bool &Opt, bool Val)
Definition: TargetPassConfig.cpp:704
llvm::createCodeGenPreparePass
FunctionPass * createCodeGenPreparePass()
createCodeGenPreparePass - Transform the code to expose more pattern matching during instruction sele...
Definition: CodeGenPrepare.cpp:465
RegAllocRegistry.h
StopAfterOpt
static cl::opt< std::string > StopAfterOpt(StringRef(StopAfterOptName), cl::desc("Stop compilation after a specific pass"), cl::value_desc("pass-name"), cl::init(""), cl::Hidden)
llvm::TargetPassConfig::~TargetPassConfig
~TargetPassConfig() override
Definition: TargetPassConfig.cpp:411
llvm::TargetMachine::getBBSectionsType
llvm::BasicBlockSection getBBSectionsType() const
If basic blocks should be emitted into their own section, corresponding to -fbasic-block-sections.
Definition: TargetMachine.h:297
llvm::createStackProtectorPass
FunctionPass * createStackProtectorPass()
createStackProtectorPass - This pass adds stack protectors to functions.
Definition: StackProtector.cpp:75
llvm::TargetPassConfig::addMachineLateOptimization
virtual void addMachineLateOptimization()
Add passes that optimize machine instructions after register allocation.
Definition: TargetPassConfig.cpp:1516
llvm::SmallVectorImpl::emplace_back
reference emplace_back(ArgTypes &&... Args)
Definition: SmallVector.h:927
llvm::createPrintFunctionPass
FunctionPass * createPrintFunctionPass(raw_ostream &OS, const std::string &Banner="")
Create and return a pass that prints functions to the specified raw_ostream as they are processed.
Definition: IRPrintingPasses.cpp:130
PrintAfterISel
static cl::opt< bool > PrintAfterISel("print-after-isel", cl::init(false), cl::Hidden, cl::desc("Print machine instrs after ISel"))
llvm::createMergeICmpsLegacyPass
Pass * createMergeICmpsLegacyPass()
Definition: MergeICmps.cpp:901
DisablePostRASched
static cl::opt< bool > DisablePostRASched("disable-post-ra", cl::Hidden, cl::desc("Disable Post Regalloc Scheduler"))
DisableCopyProp
static cl::opt< bool > DisableCopyProp("disable-copyprop", cl::Hidden, cl::desc("Disable Copy Propagation pass"))
DisableBlockPlacement
static cl::opt< bool > DisableBlockPlacement("disable-block-placement", cl::Hidden, cl::desc("Disable probability-driven block placement"))