LLVM 17.0.0git
TargetPassConfig.cpp
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1//===- TargetPassConfig.cpp - Target independent code generation passes ---===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines interfaces to access the target independent code
10// generation passes provided by the LLVM backend.
11//
12//===---------------------------------------------------------------------===//
13
15#include "llvm/ADT/DenseMap.h"
17#include "llvm/ADT/StringRef.h"
27#include "llvm/CodeGen/Passes.h"
32#include "llvm/IR/Verifier.h"
34#include "llvm/MC/MCAsmInfo.h"
36#include "llvm/Pass.h"
40#include "llvm/Support/Debug.h"
50#include <cassert>
51#include <optional>
52#include <string>
53
54using namespace llvm;
55
56static cl::opt<bool>
57 EnableIPRA("enable-ipra", cl::init(false), cl::Hidden,
58 cl::desc("Enable interprocedural register allocation "
59 "to reduce load/store at procedure calls."));
61 cl::desc("Disable Post Regalloc Scheduler"));
62static cl::opt<bool> DisableBranchFold("disable-branch-fold", cl::Hidden,
63 cl::desc("Disable branch folding"));
64static cl::opt<bool> DisableTailDuplicate("disable-tail-duplicate", cl::Hidden,
65 cl::desc("Disable tail duplication"));
66static cl::opt<bool> DisableEarlyTailDup("disable-early-taildup", cl::Hidden,
67 cl::desc("Disable pre-register allocation tail duplication"));
68static cl::opt<bool> DisableBlockPlacement("disable-block-placement",
69 cl::Hidden, cl::desc("Disable probability-driven block placement"));
70static cl::opt<bool> EnableBlockPlacementStats("enable-block-placement-stats",
71 cl::Hidden, cl::desc("Collect probability-driven block placement stats"));
72static cl::opt<bool> DisableSSC("disable-ssc", cl::Hidden,
73 cl::desc("Disable Stack Slot Coloring"));
74static cl::opt<bool> DisableMachineDCE("disable-machine-dce", cl::Hidden,
75 cl::desc("Disable Machine Dead Code Elimination"));
77 cl::desc("Disable Early If-conversion"));
78static cl::opt<bool> DisableMachineLICM("disable-machine-licm", cl::Hidden,
79 cl::desc("Disable Machine LICM"));
80static cl::opt<bool> DisableMachineCSE("disable-machine-cse", cl::Hidden,
81 cl::desc("Disable Machine Common Subexpression Elimination"));
83 "optimize-regalloc", cl::Hidden,
84 cl::desc("Enable optimized register allocation compilation path."));
85static cl::opt<bool> DisablePostRAMachineLICM("disable-postra-machine-licm",
87 cl::desc("Disable Machine LICM"));
88static cl::opt<bool> DisableMachineSink("disable-machine-sink", cl::Hidden,
89 cl::desc("Disable Machine Sinking"));
90static cl::opt<bool> DisablePostRAMachineSink("disable-postra-machine-sink",
92 cl::desc("Disable PostRA Machine Sinking"));
93static cl::opt<bool> DisableLSR("disable-lsr", cl::Hidden,
94 cl::desc("Disable Loop Strength Reduction Pass"));
95static cl::opt<bool> DisableConstantHoisting("disable-constant-hoisting",
96 cl::Hidden, cl::desc("Disable ConstantHoisting"));
97static cl::opt<bool> DisableCGP("disable-cgp", cl::Hidden,
98 cl::desc("Disable Codegen Prepare"));
99static cl::opt<bool> DisableCopyProp("disable-copyprop", cl::Hidden,
100 cl::desc("Disable Copy Propagation pass"));
101static cl::opt<bool> DisablePartialLibcallInlining("disable-partial-libcall-inlining",
102 cl::Hidden, cl::desc("Disable Partial Libcall Inlining"));
104 "enable-implicit-null-checks",
105 cl::desc("Fold null checks into faulting memory operations"),
106 cl::init(false), cl::Hidden);
107static cl::opt<bool> DisableMergeICmps("disable-mergeicmps",
108 cl::desc("Disable MergeICmps Pass"),
109 cl::init(false), cl::Hidden);
110static cl::opt<bool> PrintLSR("print-lsr-output", cl::Hidden,
111 cl::desc("Print LLVM IR produced by the loop-reduce pass"));
112static cl::opt<bool> PrintISelInput("print-isel-input", cl::Hidden,
113 cl::desc("Print LLVM IR input to isel pass"));
115 cl::desc("Dump garbage collector data"));
117 VerifyMachineCode("verify-machineinstrs", cl::Hidden,
118 cl::desc("Verify generated machine code"));
120 DebugifyAndStripAll("debugify-and-strip-all-safe", cl::Hidden,
121 cl::desc("Debugify MIR before and Strip debug after "
122 "each pass except those known to be unsafe "
123 "when debug info is present"));
125 "debugify-check-and-strip-all-safe", cl::Hidden,
126 cl::desc(
127 "Debugify MIR before, by checking and stripping the debug info after, "
128 "each pass except those known to be unsafe when debug info is "
129 "present"));
130// Enable or disable the MachineOutliner.
132 "enable-machine-outliner", cl::desc("Enable the machine outliner"),
133 cl::Hidden, cl::ValueOptional, cl::init(RunOutliner::TargetDefault),
134 cl::values(clEnumValN(RunOutliner::AlwaysOutline, "always",
135 "Run on all functions guaranteed to be beneficial"),
136 clEnumValN(RunOutliner::NeverOutline, "never",
137 "Disable all outlining"),
138 // Sentinel value for unspecified option.
139 clEnumValN(RunOutliner::AlwaysOutline, "", "")));
140// Disable the pass to fix unwind information. Whether the pass is included in
141// the pipeline is controlled via the target options, this option serves as
142// manual override.
143static cl::opt<bool> DisableCFIFixup("disable-cfi-fixup", cl::Hidden,
144 cl::desc("Disable the CFI fixup pass"));
145// Enable or disable FastISel. Both options are needed, because
146// FastISel is enabled by default with -fast, and we wish to be
147// able to enable or disable fast-isel independently from -O0.
150 cl::desc("Enable the \"fast\" instruction selector"));
151
153 "global-isel", cl::Hidden,
154 cl::desc("Enable the \"global\" instruction selector"));
155
156// FIXME: remove this after switching to NPM or GlobalISel, whichever gets there
157// first...
158static cl::opt<bool>
159 PrintAfterISel("print-after-isel", cl::init(false), cl::Hidden,
160 cl::desc("Print machine instrs after ISel"));
161
163 "global-isel-abort", cl::Hidden,
164 cl::desc("Enable abort calls when \"global\" instruction selection "
165 "fails to lower/select an instruction"),
167 clEnumValN(GlobalISelAbortMode::Disable, "0", "Disable the abort"),
168 clEnumValN(GlobalISelAbortMode::Enable, "1", "Enable the abort"),
169 clEnumValN(GlobalISelAbortMode::DisableWithDiag, "2",
170 "Disable the abort but emit a diagnostic on failure")));
171
172// An option that disables inserting FS-AFDO discriminators before emit.
173// This is mainly for debugging and tuning purpose.
174static cl::opt<bool>
175 FSNoFinalDiscrim("fs-no-final-discrim", cl::init(false), cl::Hidden,
176 cl::desc("Do not insert FS-AFDO discriminators before "
177 "emit."));
178// Disable MIRProfileLoader before RegAlloc. This is for for debugging and
179// tuning purpose.
181 "disable-ra-fsprofile-loader", cl::init(false), cl::Hidden,
182 cl::desc("Disable MIRProfileLoader before RegAlloc"));
183// Disable MIRProfileLoader before BloackPlacement. This is for for debugging
184// and tuning purpose.
186 "disable-layout-fsprofile-loader", cl::init(false), cl::Hidden,
187 cl::desc("Disable MIRProfileLoader before BlockPlacement"));
188// Specify FSProfile file name.
190 FSProfileFile("fs-profile-file", cl::init(""), cl::value_desc("filename"),
191 cl::desc("Flow Sensitive profile file name."), cl::Hidden);
192// Specify Remapping file for FSProfile.
194 "fs-remapping-file", cl::init(""), cl::value_desc("filename"),
195 cl::desc("Flow Sensitive profile remapping file name."), cl::Hidden);
196
197// Temporary option to allow experimenting with MachineScheduler as a post-RA
198// scheduler. Targets can "properly" enable this with
199// substitutePass(&PostRASchedulerID, &PostMachineSchedulerID).
200// Targets can return true in targetSchedulesPostRAScheduling() and
201// insert a PostRA scheduling pass wherever it wants.
203 "misched-postra", cl::Hidden,
204 cl::desc(
205 "Run MachineScheduler post regalloc (independent of preRA sched)"));
206
207// Experimental option to run live interval analysis early.
208static cl::opt<bool> EarlyLiveIntervals("early-live-intervals", cl::Hidden,
209 cl::desc("Run live interval analysis earlier in the pipeline"));
210
211/// Option names for limiting the codegen pipeline.
212/// Those are used in error reporting and we didn't want
213/// to duplicate their names all over the place.
214static const char StartAfterOptName[] = "start-after";
215static const char StartBeforeOptName[] = "start-before";
216static const char StopAfterOptName[] = "stop-after";
217static const char StopBeforeOptName[] = "stop-before";
218
221 cl::desc("Resume compilation after a specific pass"),
222 cl::value_desc("pass-name"), cl::init(""), cl::Hidden);
223
226 cl::desc("Resume compilation before a specific pass"),
227 cl::value_desc("pass-name"), cl::init(""), cl::Hidden);
228
231 cl::desc("Stop compilation after a specific pass"),
232 cl::value_desc("pass-name"), cl::init(""), cl::Hidden);
233
236 cl::desc("Stop compilation before a specific pass"),
237 cl::value_desc("pass-name"), cl::init(""), cl::Hidden);
238
239/// Enable the machine function splitter pass.
241 "enable-split-machine-functions", cl::Hidden,
242 cl::desc("Split out cold blocks from machine functions based on profile "
243 "information."));
244
245/// Disable the expand reductions pass for testing.
247 "disable-expand-reductions", cl::init(false), cl::Hidden,
248 cl::desc("Disable the expand reduction intrinsics pass from running"));
249
250/// Disable the select optimization pass.
252 "disable-select-optimize", cl::init(true), cl::Hidden,
253 cl::desc("Disable the select-optimization pass from running"));
254
255/// Allow standard passes to be disabled by command line options. This supports
256/// simple binary flags that either suppress the pass or do nothing.
257/// i.e. -disable-mypass=false has no effect.
258/// These should be converted to boolOrDefault in order to use applyOverride.
260 bool Override) {
261 if (Override)
262 return IdentifyingPassPtr();
263 return PassID;
264}
265
266/// Allow standard passes to be disabled by the command line, regardless of who
267/// is adding the pass.
268///
269/// StandardID is the pass identified in the standard pass pipeline and provided
270/// to addPass(). It may be a target-specific ID in the case that the target
271/// directly adds its own pass, but in that case we harmlessly fall through.
272///
273/// TargetID is the pass that the target has configured to override StandardID.
274///
275/// StandardID may be a pseudo ID. In that case TargetID is the name of the real
276/// pass to run. This allows multiple options to control a single pass depending
277/// on where in the pipeline that pass is added.
279 IdentifyingPassPtr TargetID) {
280 if (StandardID == &PostRASchedulerID)
281 return applyDisable(TargetID, DisablePostRASched);
282
283 if (StandardID == &BranchFolderPassID)
284 return applyDisable(TargetID, DisableBranchFold);
285
286 if (StandardID == &TailDuplicateID)
287 return applyDisable(TargetID, DisableTailDuplicate);
288
289 if (StandardID == &EarlyTailDuplicateID)
290 return applyDisable(TargetID, DisableEarlyTailDup);
291
292 if (StandardID == &MachineBlockPlacementID)
293 return applyDisable(TargetID, DisableBlockPlacement);
294
295 if (StandardID == &StackSlotColoringID)
296 return applyDisable(TargetID, DisableSSC);
297
298 if (StandardID == &DeadMachineInstructionElimID)
299 return applyDisable(TargetID, DisableMachineDCE);
300
301 if (StandardID == &EarlyIfConverterID)
302 return applyDisable(TargetID, DisableEarlyIfConversion);
303
304 if (StandardID == &EarlyMachineLICMID)
305 return applyDisable(TargetID, DisableMachineLICM);
306
307 if (StandardID == &MachineCSEID)
308 return applyDisable(TargetID, DisableMachineCSE);
309
310 if (StandardID == &MachineLICMID)
311 return applyDisable(TargetID, DisablePostRAMachineLICM);
312
313 if (StandardID == &MachineSinkingID)
314 return applyDisable(TargetID, DisableMachineSink);
315
316 if (StandardID == &PostRAMachineSinkingID)
317 return applyDisable(TargetID, DisablePostRAMachineSink);
318
319 if (StandardID == &MachineCopyPropagationID)
320 return applyDisable(TargetID, DisableCopyProp);
321
322 return TargetID;
323}
324
325// Find the FSProfile file name. The internal option takes the precedence
326// before getting from TargetMachine.
327static std::string getFSProfileFile(const TargetMachine *TM) {
328 if (!FSProfileFile.empty())
329 return FSProfileFile.getValue();
330 const std::optional<PGOOptions> &PGOOpt = TM->getPGOOption();
331 if (PGOOpt == std::nullopt || PGOOpt->Action != PGOOptions::SampleUse)
332 return std::string();
333 return PGOOpt->ProfileFile;
334}
335
336// Find the Profile remapping file name. The internal option takes the
337// precedence before getting from TargetMachine.
338static std::string getFSRemappingFile(const TargetMachine *TM) {
339 if (!FSRemappingFile.empty())
340 return FSRemappingFile.getValue();
341 const std::optional<PGOOptions> &PGOOpt = TM->getPGOOption();
342 if (PGOOpt == std::nullopt || PGOOpt->Action != PGOOptions::SampleUse)
343 return std::string();
344 return PGOOpt->ProfileRemappingFile;
345}
346
347//===---------------------------------------------------------------------===//
348/// TargetPassConfig
349//===---------------------------------------------------------------------===//
350
351INITIALIZE_PASS(TargetPassConfig, "targetpassconfig",
352 "Target Pass Configuration", false, false)
354
355namespace {
356
360
361 InsertedPass(AnalysisID TargetPassID, IdentifyingPassPtr InsertedPassID)
362 : TargetPassID(TargetPassID), InsertedPassID(InsertedPassID) {}
363
365 assert(InsertedPassID.isValid() && "Illegal Pass ID!");
366 if (InsertedPassID.isInstance())
367 return InsertedPassID.getInstance();
368 Pass *NP = Pass::createPass(InsertedPassID.getID());
369 assert(NP && "Pass ID not registered");
370 return NP;
371 }
372};
373
374} // end anonymous namespace
375
376namespace llvm {
377
379
381public:
382 // List of passes explicitly substituted by this target. Normally this is
383 // empty, but it is a convenient way to suppress or replace specific passes
384 // that are part of a standard pass pipeline without overridding the entire
385 // pipeline. This mechanism allows target options to inherit a standard pass's
386 // user interface. For example, a target may disable a standard pass by
387 // default by substituting a pass ID of zero, and the user may still enable
388 // that standard pass with an explicit command line option.
390
391 /// Store the pairs of <AnalysisID, AnalysisID> of which the second pass
392 /// is inserted after each instance of the first one.
394};
395
396} // end namespace llvm
397
398// Out of line virtual method.
400 delete Impl;
401}
402
404 if (PassName.empty())
405 return nullptr;
406
408 const PassInfo *PI = PR.getPassInfo(PassName);
409 if (!PI)
411 Twine("\" pass is not registered."));
412 return PI;
413}
414
416 const PassInfo *PI = getPassInfo(PassName);
417 return PI ? PI->getTypeInfo() : nullptr;
418}
419
420static std::pair<StringRef, unsigned>
422 StringRef Name, InstanceNumStr;
423 std::tie(Name, InstanceNumStr) = PassName.split(',');
424
425 unsigned InstanceNum = 0;
426 if (!InstanceNumStr.empty() && InstanceNumStr.getAsInteger(10, InstanceNum))
427 report_fatal_error("invalid pass instance specifier " + PassName);
428
429 return std::make_pair(Name, InstanceNum);
430}
431
432void TargetPassConfig::setStartStopPasses() {
433 StringRef StartBeforeName;
434 std::tie(StartBeforeName, StartBeforeInstanceNum) =
436
437 StringRef StartAfterName;
438 std::tie(StartAfterName, StartAfterInstanceNum) =
440
441 StringRef StopBeforeName;
442 std::tie(StopBeforeName, StopBeforeInstanceNum)
444
445 StringRef StopAfterName;
446 std::tie(StopAfterName, StopAfterInstanceNum)
448
449 StartBefore = getPassIDFromName(StartBeforeName);
450 StartAfter = getPassIDFromName(StartAfterName);
451 StopBefore = getPassIDFromName(StopBeforeName);
452 StopAfter = getPassIDFromName(StopAfterName);
453 if (StartBefore && StartAfter)
455 Twine(StartAfterOptName) + Twine(" specified!"));
456 if (StopBefore && StopAfter)
458 Twine(StopAfterOptName) + Twine(" specified!"));
459 Started = (StartAfter == nullptr) && (StartBefore == nullptr);
460}
461
464
465#define SET_OPTION(Option) \
466 if (Option.getNumOccurrences()) \
467 Opt.Option = Option;
468
475
476#define SET_BOOLEAN_OPTION(Option) Opt.Option = Option;
477
492
493 return Opt;
494}
495
497 LLVMTargetMachine &LLVMTM) {
498 StringRef StartBefore;
499 StringRef StartAfter;
500 StringRef StopBefore;
501 StringRef StopAfter;
502
503 unsigned StartBeforeInstanceNum = 0;
504 unsigned StartAfterInstanceNum = 0;
505 unsigned StopBeforeInstanceNum = 0;
506 unsigned StopAfterInstanceNum = 0;
507
508 std::tie(StartBefore, StartBeforeInstanceNum) =
510 std::tie(StartAfter, StartAfterInstanceNum) =
512 std::tie(StopBefore, StopBeforeInstanceNum) =
514 std::tie(StopAfter, StopAfterInstanceNum) =
516
517 if (StartBefore.empty() && StartAfter.empty() && StopBefore.empty() &&
518 StopAfter.empty())
519 return;
520
521 std::tie(StartBefore, std::ignore) =
522 LLVMTM.getPassNameFromLegacyName(StartBefore);
523 std::tie(StartAfter, std::ignore) =
524 LLVMTM.getPassNameFromLegacyName(StartAfter);
525 std::tie(StopBefore, std::ignore) =
526 LLVMTM.getPassNameFromLegacyName(StopBefore);
527 std::tie(StopAfter, std::ignore) =
528 LLVMTM.getPassNameFromLegacyName(StopAfter);
529 if (!StartBefore.empty() && !StartAfter.empty())
531 Twine(StartAfterOptName) + Twine(" specified!"));
532 if (!StopBefore.empty() && !StopAfter.empty())
534 Twine(StopAfterOptName) + Twine(" specified!"));
535
537 [=, EnableCurrent = StartBefore.empty() && StartAfter.empty(),
538 EnableNext = std::optional<bool>(), StartBeforeCount = 0u,
539 StartAfterCount = 0u, StopBeforeCount = 0u,
540 StopAfterCount = 0u](StringRef P, Any) mutable {
541 bool StartBeforePass = !StartBefore.empty() && P.contains(StartBefore);
542 bool StartAfterPass = !StartAfter.empty() && P.contains(StartAfter);
543 bool StopBeforePass = !StopBefore.empty() && P.contains(StopBefore);
544 bool StopAfterPass = !StopAfter.empty() && P.contains(StopAfter);
545
546 // Implement -start-after/-stop-after
547 if (EnableNext) {
548 EnableCurrent = *EnableNext;
549 EnableNext.reset();
550 }
551
552 // Using PIC.registerAfterPassCallback won't work because if this
553 // callback returns false, AfterPassCallback is also skipped.
554 if (StartAfterPass && StartAfterCount++ == StartAfterInstanceNum) {
555 assert(!EnableNext && "Error: assign to EnableNext more than once");
556 EnableNext = true;
557 }
558 if (StopAfterPass && StopAfterCount++ == StopAfterInstanceNum) {
559 assert(!EnableNext && "Error: assign to EnableNext more than once");
560 EnableNext = false;
561 }
562
563 if (StartBeforePass && StartBeforeCount++ == StartBeforeInstanceNum)
564 EnableCurrent = true;
565 if (StopBeforePass && StopBeforeCount++ == StopBeforeInstanceNum)
566 EnableCurrent = false;
567 return EnableCurrent;
568 });
569}
570
572 LLVMTargetMachine &LLVMTM) {
573
574 // Register a callback for disabling passes.
576
577#define DISABLE_PASS(Option, Name) \
578 if (Option && P.contains(#Name)) \
579 return false;
580 DISABLE_PASS(DisableBlockPlacement, MachineBlockPlacementPass)
581 DISABLE_PASS(DisableBranchFold, BranchFolderPass)
582 DISABLE_PASS(DisableCopyProp, MachineCopyPropagationPass)
583 DISABLE_PASS(DisableEarlyIfConversion, EarlyIfConverterPass)
584 DISABLE_PASS(DisableEarlyTailDup, EarlyTailDuplicatePass)
585 DISABLE_PASS(DisableMachineCSE, MachineCSEPass)
586 DISABLE_PASS(DisableMachineDCE, DeadMachineInstructionElimPass)
587 DISABLE_PASS(DisableMachineLICM, EarlyMachineLICMPass)
588 DISABLE_PASS(DisableMachineSink, MachineSinkingPass)
589 DISABLE_PASS(DisablePostRAMachineLICM, MachineLICMPass)
590 DISABLE_PASS(DisablePostRAMachineSink, PostRAMachineSinkingPass)
591 DISABLE_PASS(DisablePostRASched, PostRASchedulerPass)
592 DISABLE_PASS(DisableSSC, StackSlotColoringPass)
593 DISABLE_PASS(DisableTailDuplicate, TailDuplicatePass)
594
595 return true;
596 });
597
599}
600
601// Out of line constructor provides default values for pass options and
602// registers all common codegen passes.
604 : ImmutablePass(ID), PM(&pm), TM(&TM) {
605 Impl = new PassConfigImpl();
606
607 // Register all target independent codegen passes to activate their PassIDs,
608 // including this pass itself.
610
611 // Also register alias analysis passes required by codegen passes.
614
617 else {
618 // If not explicitly specified, use target default.
620 }
621
624
625 if (EnableGlobalISelAbort.getNumOccurrences())
627
628 setStartStopPasses();
629}
630
632 return TM->getOptLevel();
633}
634
635/// Insert InsertedPassID pass after TargetPassID.
637 IdentifyingPassPtr InsertedPassID) {
638 assert(((!InsertedPassID.isInstance() &&
639 TargetPassID != InsertedPassID.getID()) ||
640 (InsertedPassID.isInstance() &&
641 TargetPassID != InsertedPassID.getInstance()->getPassID())) &&
642 "Insert a pass after itself!");
643 Impl->InsertedPasses.emplace_back(TargetPassID, InsertedPassID);
644}
645
646/// createPassConfig - Create a pass configuration object to be used by
647/// addPassToEmitX methods for generating a pipeline of CodeGen passes.
648///
649/// Targets may override this to extend TargetPassConfig.
651 return new TargetPassConfig(*this, PM);
652}
653
655 : ImmutablePass(ID) {
656 report_fatal_error("Trying to construct TargetPassConfig without a target "
657 "machine. Scheduling a CodeGen pass without a target "
658 "triple set?");
659}
660
662 return StopBeforeOpt.empty() && StopAfterOpt.empty();
663}
664
666 return !StartBeforeOpt.empty() || !StartAfterOpt.empty() ||
668}
669
670std::string
673 return std::string();
674 std::string Res;
675 static cl::opt<std::string> *PassNames[] = {&StartAfterOpt, &StartBeforeOpt,
677 static const char *OptNames[] = {StartAfterOptName, StartBeforeOptName,
679 bool IsFirst = true;
680 for (int Idx = 0; Idx < 4; ++Idx)
681 if (!PassNames[Idx]->empty()) {
682 if (!IsFirst)
683 Res += Separator;
684 IsFirst = false;
685 Res += OptNames[Idx];
686 }
687 return Res;
688}
689
690// Helper to verify the analysis is really immutable.
691void TargetPassConfig::setOpt(bool &Opt, bool Val) {
692 assert(!Initialized && "PassConfig is immutable");
693 Opt = Val;
694}
695
697 IdentifyingPassPtr TargetID) {
698 Impl->TargetPasses[StandardID] = TargetID;
699}
700
703 I = Impl->TargetPasses.find(ID);
704 if (I == Impl->TargetPasses.end())
705 return ID;
706 return I->second;
707}
708
711 IdentifyingPassPtr FinalPtr = overridePass(ID, TargetID);
712 return !FinalPtr.isValid() || FinalPtr.isInstance() ||
713 FinalPtr.getID() != ID;
714}
715
716/// Add a pass to the PassManager if that pass is supposed to be run. If the
717/// Started/Stopped flags indicate either that the compilation should start at
718/// a later pass or that it should stop after an earlier pass, then do not add
719/// the pass. Finally, compare the current pass against the StartAfter
720/// and StopAfter options and change the Started/Stopped flags accordingly.
722 assert(!Initialized && "PassConfig is immutable");
723
724 // Cache the Pass ID here in case the pass manager finds this pass is
725 // redundant with ones already scheduled / available, and deletes it.
726 // Fundamentally, once we add the pass to the manager, we no longer own it
727 // and shouldn't reference it.
728 AnalysisID PassID = P->getPassID();
729
730 if (StartBefore == PassID && StartBeforeCount++ == StartBeforeInstanceNum)
731 Started = true;
732 if (StopBefore == PassID && StopBeforeCount++ == StopBeforeInstanceNum)
733 Stopped = true;
734 if (Started && !Stopped) {
735 if (AddingMachinePasses) {
736 // Construct banner message before PM->add() as that may delete the pass.
737 std::string Banner =
738 std::string("After ") + std::string(P->getPassName());
740 PM->add(P);
741 addMachinePostPasses(Banner);
742 } else {
743 PM->add(P);
744 }
745
746 // Add the passes after the pass P if there is any.
747 for (const auto &IP : Impl->InsertedPasses)
748 if (IP.TargetPassID == PassID)
749 addPass(IP.getInsertedPass());
750 } else {
751 delete P;
752 }
753
754 if (StopAfter == PassID && StopAfterCount++ == StopAfterInstanceNum)
755 Stopped = true;
756
757 if (StartAfter == PassID && StartAfterCount++ == StartAfterInstanceNum)
758 Started = true;
759 if (Stopped && !Started)
760 report_fatal_error("Cannot stop compilation after pass that is not run");
761}
762
763/// Add a CodeGen pass at this point in the pipeline after checking for target
764/// and command line overrides.
765///
766/// addPass cannot return a pointer to the pass instance because is internal the
767/// PassManager and the instance we create here may already be freed.
769 IdentifyingPassPtr TargetID = getPassSubstitution(PassID);
770 IdentifyingPassPtr FinalPtr = overridePass(PassID, TargetID);
771 if (!FinalPtr.isValid())
772 return nullptr;
773
774 Pass *P;
775 if (FinalPtr.isInstance())
776 P = FinalPtr.getInstance();
777 else {
778 P = Pass::createPass(FinalPtr.getID());
779 if (!P)
780 llvm_unreachable("Pass ID not registered");
781 }
782 AnalysisID FinalID = P->getPassID();
783 addPass(P); // Ends the lifetime of P.
784
785 return FinalID;
786}
787
788void TargetPassConfig::printAndVerify(const std::string &Banner) {
789 addPrintPass(Banner);
790 addVerifyPass(Banner);
791}
792
793void TargetPassConfig::addPrintPass(const std::string &Banner) {
794 if (PrintAfterISel)
796}
797
798void TargetPassConfig::addVerifyPass(const std::string &Banner) {
800#ifdef EXPENSIVE_CHECKS
803#endif
804 if (Verify)
805 PM->add(createMachineVerifierPass(Banner));
806}
807
810}
811
813 PM->add(createStripDebugMachineModulePass(/*OnlyDebugified=*/true));
814}
815
818}
819
821 if (AllowDebugify && DebugifyIsSafe &&
825}
826
827void TargetPassConfig::addMachinePostPasses(const std::string &Banner) {
828 if (DebugifyIsSafe) {
832 } else if (DebugifyAndStripAll == cl::BOU_TRUE)
834 }
835 addVerifyPass(Banner);
836}
837
838/// Add common target configurable passes that perform LLVM IR to IR transforms
839/// following machine independent optimization.
841 // Before running any passes, run the verifier to determine if the input
842 // coming from the front-end and/or optimizer is valid.
843 if (!DisableVerify)
845
846 if (getOptLevel() != CodeGenOpt::None) {
847 // Basic AliasAnalysis support.
848 // Add TypeBasedAliasAnalysis before BasicAliasAnalysis so that
849 // BasicAliasAnalysis wins if they disagree. This is intended to help
850 // support "obvious" type-punning idioms.
854
855 // Run loop strength reduction before anything else.
856 if (!DisableLSR) {
859 if (PrintLSR)
861 "\n\n*** Code after LSR ***\n"));
862 }
863
864 // The MergeICmpsPass tries to create memcmp calls by grouping sequences of
865 // loads and compares. ExpandMemCmpPass then tries to expand those calls
866 // into optimally-sized loads and compares. The transforms are enabled by a
867 // target lowering hook.
871 }
872
873 // Run GC lowering passes for builtin collectors
874 // TODO: add a pass insertion point here
878
879 // For MachO, lower @llvm.global_dtors into @llvm.global_ctors with
880 // __cxa_atexit() calls to avoid emitting the deprecated __mod_term_func.
884
885 // Make sure that no unreachable blocks are instruction selected.
887
888 // Prepare expensive constants for SelectionDAG.
891
894
897
898 // Expand vector predication intrinsics into standard IR instructions.
899 // This pass has to run before ScalarizeMaskedMemIntrin and ExpandReduction
900 // passes since it emits those kinds of intrinsics.
902
903 // Add scalarization of target's unsupported masked memory intrinsics pass.
904 // the unsupported intrinsic will be replaced with a chain of basic blocks,
905 // that stores/loads element one-by-one if the appropriate mask bit is set.
907
908 // Expand reduction intrinsics into shuffle sequences if the target wants to.
909 // Allow disabling it for testing purposes.
912
915
916 // Convert conditional moves to conditional jumps when profitable.
919}
920
921/// Turn exception handling constructs into something the code generators can
922/// handle.
924 const MCAsmInfo *MCAI = TM->getMCAsmInfo();
925 assert(MCAI && "No MCAsmInfo");
926 switch (MCAI->getExceptionHandlingType()) {
928 // SjLj piggy-backs on dwarf for this bit. The cleanups done apply to both
929 // Dwarf EH prepare needs to be run after SjLj prepare. Otherwise,
930 // catch info can get misplaced when a selector ends up more than one block
931 // removed from the parent invoke(s). This could happen when a landing
932 // pad is shared by multiple invokes and is also a target of a normal
933 // edge from elsewhere.
935 [[fallthrough]];
940 break;
942 // We support using both GCC-style and MSVC-style exceptions on Windows, so
943 // add both preparation passes. Each pass will only actually run if it
944 // recognizes the personality function.
947 break;
949 // Wasm EH uses Windows EH instructions, but it does not need to demote PHIs
950 // on catchpads and cleanuppads because it does not outline them into
951 // funclets. Catchswitch blocks are not lowered in SelectionDAG, so we
952 // should remove PHIs there.
953 addPass(createWinEHPass(/*DemoteCatchSwitchPHIOnly=*/false));
955 break;
958
959 // The lower invoke pass may create unreachable code. Remove it.
961 break;
962 }
963}
964
965/// Add pass to prepare the LLVM IR for code generation. This should be done
966/// before exception handling preparation passes.
970}
971
972/// Add common passes that perform LLVM IR to IR transforms in preparation for
973/// instruction selection.
975 addPreISel();
976
977 // Force codegen to run according to the callgraph.
980
981 // Add both the safe stack and the stack protection passes: each of them will
982 // only protect functions that have corresponding attributes.
985
986 if (PrintISelInput)
988 dbgs(), "\n\n*** Final LLVM Code input to ISel ***\n"));
989
990 // All passes which modify the LLVM IR are now complete; run the verifier
991 // to ensure that the IR is valid.
992 if (!DisableVerify)
994}
995
997 // Enable FastISel with -fast-isel, but allow that to be overridden.
999
1000 // Determine an instruction selector.
1001 enum class SelectorType { SelectionDAG, FastISel, GlobalISel };
1002 SelectorType Selector;
1003
1005 Selector = SelectorType::FastISel;
1009 Selector = SelectorType::GlobalISel;
1011 Selector = SelectorType::FastISel;
1012 else
1013 Selector = SelectorType::SelectionDAG;
1014
1015 // Set consistently TM->Options.EnableFastISel and EnableGlobalISel.
1016 if (Selector == SelectorType::FastISel) {
1017 TM->setFastISel(true);
1018 TM->setGlobalISel(false);
1019 } else if (Selector == SelectorType::GlobalISel) {
1020 TM->setFastISel(false);
1021 TM->setGlobalISel(true);
1022 }
1023
1024 // FIXME: Injecting into the DAGISel pipeline seems to cause issues with
1025 // analyses needing to be re-run. This can result in being unable to
1026 // schedule passes (particularly with 'Function Alias Analysis
1027 // Results'). It's not entirely clear why but AFAICT this seems to be
1028 // due to one FunctionPassManager not being able to use analyses from a
1029 // previous one. As we're injecting a ModulePass we break the usual
1030 // pass manager into two. GlobalISel with the fallback path disabled
1031 // and -run-pass seem to be unaffected. The majority of GlobalISel
1032 // testing uses -run-pass so this probably isn't too bad.
1033 SaveAndRestore SavedDebugifyIsSafe(DebugifyIsSafe);
1034 if (Selector != SelectorType::GlobalISel || !isGlobalISelAbortEnabled())
1035 DebugifyIsSafe = false;
1036
1037 // Add instruction selector passes.
1038 if (Selector == SelectorType::GlobalISel) {
1039 SaveAndRestore SavedAddingMachinePasses(AddingMachinePasses, true);
1040 if (addIRTranslator())
1041 return true;
1042
1044
1046 return true;
1047
1048 // Before running the register bank selector, ask the target if it
1049 // wants to run some passes.
1051
1052 if (addRegBankSelect())
1053 return true;
1054
1056
1058 return true;
1059
1060 // Pass to reset the MachineFunction if the ISel failed.
1063
1064 // Provide a fallback path when we do not want to abort on
1065 // not-yet-supported input.
1067 return true;
1068
1069 } else if (addInstSelector())
1070 return true;
1071
1072 // Expand pseudo-instructions emitted by ISel. Don't run the verifier before
1073 // FinalizeISel.
1075
1076 // Print the instruction selected machine code...
1077 printAndVerify("After Instruction Selection");
1078
1079 return false;
1080}
1081
1083 if (TM->useEmulatedTLS())
1085
1090 addIRPasses();
1094
1095 return addCoreISelPasses();
1096}
1097
1098/// -regalloc=... command line option.
1099static FunctionPass *useDefaultRegisterAllocator() { return nullptr; }
1103 cl::desc("Register allocator to use"));
1104
1105/// Add the complete set of target-independent postISel code generator passes.
1106///
1107/// This can be read as the standard order of major LLVM CodeGen stages. Stages
1108/// with nontrivial configuration or multiple passes are broken out below in
1109/// add%Stage routines.
1110///
1111/// Any TargetPassConfig::addXX routine may be overriden by the Target. The
1112/// addPre/Post methods with empty header implementations allow injecting
1113/// target-specific fixups just before or after major stages. Additionally,
1114/// targets have the flexibility to change pass order within a stage by
1115/// overriding default implementation of add%Stage routines below. Each
1116/// technique has maintainability tradeoffs because alternate pass orders are
1117/// not well supported. addPre/Post works better if the target pass is easily
1118/// tied to a common pass. But if it has subtle dependencies on multiple passes,
1119/// the target should override the stage instead.
1120///
1121/// TODO: We could use a single addPre/Post(ID) hook to allow pass injection
1122/// before/after any target-independent pass. But it's currently overkill.
1124 AddingMachinePasses = true;
1125
1126 // Add passes that optimize machine instructions in SSA form.
1127 if (getOptLevel() != CodeGenOpt::None) {
1129 } else {
1130 // If the target requests it, assign local variables to stack slots relative
1131 // to one another and simplify frame index references where possible.
1133 }
1134
1135 if (TM->Options.EnableIPRA)
1137
1138 // Run pre-ra passes.
1140
1141 // Debugifying the register allocator passes seems to provoke some
1142 // non-determinism that affects CodeGen and there doesn't seem to be a point
1143 // where it becomes safe again so stop debugifying here.
1144 DebugifyIsSafe = false;
1145
1146 // Add a FSDiscriminator pass right before RA, so that we could get
1147 // more precise SampleFDO profile for RA.
1151 const std::string ProfileFile = getFSProfileFile(TM);
1152 if (!ProfileFile.empty() && !DisableRAFSProfileLoader)
1155 nullptr));
1156 }
1157
1158 // Run register allocation and passes that are tightly coupled with it,
1159 // including phi elimination and scheduling.
1160 if (getOptimizeRegAlloc())
1162 else
1164
1165 // Run post-ra passes.
1167
1169
1171
1172 // Insert prolog/epilog code. Eliminate abstract frame index references...
1173 if (getOptLevel() != CodeGenOpt::None) {
1176 }
1177
1178 // Prolog/Epilog inserter needs a TargetMachine to instantiate. But only
1179 // do so if it hasn't been disabled, substituted, or overridden.
1182
1183 /// Add passes that optimize machine instructions after register allocation.
1186
1187 // Expand pseudo instructions before second scheduling pass.
1189
1190 // Run pre-sched2 passes.
1191 addPreSched2();
1192
1195
1196 // Second pass scheduler.
1197 // Let Target optionally insert this pass by itself at some other
1198 // point.
1199 if (getOptLevel() != CodeGenOpt::None &&
1201 if (MISchedPostRA)
1203 else
1205 }
1206
1207 // GC
1208 if (addGCPasses()) {
1209 if (PrintGCInfo)
1211 }
1212
1213 // Basic block placement.
1216
1217 // Insert before XRay Instrumentation.
1219
1222
1224 // Add FS discriminators here so that all the instruction duplicates
1225 // in different BBs get their own discriminators. With this, we can "sum"
1226 // the SampleFDO counters instead of using MAX. This will improve the
1227 // SampleFDO profile quality.
1230
1232
1233 if (TM->Options.EnableIPRA)
1234 // Collect register usage information and produce a register mask of
1235 // clobbered registers, to be used to optimize call sites.
1237
1238 // FIXME: Some backends are incompatible with running the verifier after
1239 // addPreEmitPass. Maybe only pass "false" here for those targets?
1241
1245
1248 bool RunOnAllFunctions =
1250 bool AddOutliner =
1251 RunOnAllFunctions || TM->Options.SupportsDefaultOutlining;
1252 if (AddOutliner)
1253 addPass(createMachineOutlinerPass(RunOnAllFunctions));
1254 }
1255
1256 // Machine function splitter uses the basic block sections feature. Both
1257 // cannot be enabled at the same time. Basic block sections takes precedence.
1258 // FIXME: In principle, BasicBlockSection::Labels and splitting can used
1259 // together. Update this check once we have addressed any issues.
1264 }
1269 }
1270
1273
1275
1276 // Add passes that directly emit MI after all other MI passes.
1278
1279 AddingMachinePasses = false;
1280}
1281
1282/// Add passes that optimize machine instructions in SSA form.
1284 // Pre-ra tail duplication.
1286
1287 // Optimize PHIs before DCE: removing dead PHI cycles may make more
1288 // instructions dead.
1290
1291 // This pass merges large allocas. StackSlotColoring is a different pass
1292 // which merges spill slots.
1294
1295 // If the target requests it, assign local variables to stack slots relative
1296 // to one another and simplify frame index references where possible.
1298
1299 // With optimization, dead code should already be eliminated. However
1300 // there is one known exception: lowered code for arguments that are only
1301 // used by tail calls, where the tail calls reuse the incoming stack
1302 // arguments directly (see t11 in test/CodeGen/X86/sibcall.ll).
1304
1305 // Allow targets to insert passes that improve instruction level parallelism,
1306 // like if-conversion. Such passes will typically need dominator trees and
1307 // loop info, just like LICM and CSE below.
1308 addILPOpts();
1309
1312
1314
1316 // Clean-up the dead code that may have been generated by peephole
1317 // rewriting.
1319}
1320
1321//===---------------------------------------------------------------------===//
1322/// Register Allocation Pass Configuration
1323//===---------------------------------------------------------------------===//
1324
1326 switch (OptimizeRegAlloc) {
1327 case cl::BOU_UNSET: return getOptLevel() != CodeGenOpt::None;
1328 case cl::BOU_TRUE: return true;
1329 case cl::BOU_FALSE: return false;
1330 }
1331 llvm_unreachable("Invalid optimize-regalloc state");
1332}
1333
1334/// A dummy default pass factory indicates whether the register allocator is
1335/// overridden on the command line.
1337
1338static RegisterRegAlloc
1340 "pick register allocator based on -O option",
1342
1346}
1347
1348/// Instantiate the default register allocator pass for this target for either
1349/// the optimized or unoptimized allocation path. This will be added to the pass
1350/// manager by addFastRegAlloc in the unoptimized case or addOptimizedRegAlloc
1351/// in the optimized case.
1352///
1353/// A target that uses the standard regalloc pass order for fast or optimized
1354/// allocation may still override this for per-target regalloc
1355/// selection. But -regalloc=... always takes precedence.
1357 if (Optimized)
1359 else
1361}
1362
1363/// Find and instantiate the register allocation pass requested by this target
1364/// at the current optimization level. Different register allocators are
1365/// defined as separate passes because they may require different analysis.
1366///
1367/// This helper ensures that the regalloc= option is always available,
1368/// even for targets that override the default allocator.
1369///
1370/// FIXME: When MachinePassRegistry register pass IDs instead of function ptrs,
1371/// this can be folded into addPass.
1373 // Initialize the global default.
1376
1378 if (Ctor != useDefaultRegisterAllocator)
1379 return Ctor();
1380
1381 // With no -regalloc= override, ask the target for a regalloc pass.
1382 return createTargetRegisterAllocator(Optimized);
1383}
1384
1386 return RegAlloc !=
1388}
1389
1393 report_fatal_error("Must use fast (default) register allocator for unoptimized regalloc.");
1394
1396
1397 // Allow targets to change the register assignments after
1398 // fast register allocation.
1400 return true;
1401}
1402
1404 // Add the selected register allocation pass.
1406
1407 // Allow targets to change the register assignments before rewriting.
1408 addPreRewrite();
1409
1410 // Finally rewrite virtual registers.
1412
1413 // Regalloc scoring for ML-driven eviction - noop except when learning a new
1414 // eviction policy.
1416 return true;
1417}
1418
1419/// Return true if the default global register allocator is in use and
1420/// has not be overriden on the command line with '-regalloc=...'
1422 return RegAlloc.getNumOccurrences() == 0;
1423}
1424
1425/// Add the minimum set of target-independent passes that are required for
1426/// register allocation. No coalescing or scheduling.
1430
1432}
1433
1434/// Add standard target-independent passes that are tightly coupled with
1435/// optimized register allocation, including coalescing, machine instruction
1436/// scheduling, and register allocation itself.
1439
1441
1442 // LiveVariables currently requires pure SSA form.
1443 //
1444 // FIXME: Once TwoAddressInstruction pass no longer uses kill flags,
1445 // LiveVariables can be removed completely, and LiveIntervals can be directly
1446 // computed. (We still either need to regenerate kill flags after regalloc, or
1447 // preferably fix the scavenger to not depend on them).
1448 // FIXME: UnreachableMachineBlockElim is a dependant pass of LiveVariables.
1449 // When LiveVariables is removed this has to be removed/moved either.
1450 // Explicit addition of UnreachableMachineBlockElim allows stopping before or
1451 // after it with -stop-before/-stop-after.
1454
1455 // Edge splitting is smarter with machine loop info.
1458
1459 // Eventually, we want to run LiveIntervals before PHI elimination.
1462
1465
1466 // The machine scheduler may accidentally create disconnected components
1467 // when moving subregister definitions around, avoid this by splitting them to
1468 // separate vregs before. Splitting can also improve reg. allocation quality.
1470
1471 // PreRA instruction scheduling.
1473
1475 // Perform stack slot coloring and post-ra machine LICM.
1477
1478 // Allow targets to expand pseudo instructions depending on the choice of
1479 // registers before MachineCopyPropagation.
1481
1482 // Copy propagate to forward register uses and try to eliminate COPYs that
1483 // were not coalesced.
1485
1486 // Run post-ra machine LICM to hoist reloads / remats.
1487 //
1488 // FIXME: can this move into MachineLateOptimization?
1490 }
1491}
1492
1493//===---------------------------------------------------------------------===//
1494/// Post RegAlloc Pass Configuration
1495//===---------------------------------------------------------------------===//
1496
1497/// Add passes that optimize machine instructions after register allocation.
1499 // Cleanup of redundant immediate/address loads.
1501
1502 // Branch folding must be run after regalloc and prolog/epilog insertion.
1504
1505 // Tail duplication.
1506 // Note that duplicating tail just increases code size and degrades
1507 // performance for targets that require Structured Control Flow.
1508 // In addition it can also make CFG irreducible. Thus we disable it.
1509 if (!TM->requiresStructuredCFG())
1511
1512 // Copy propagation.
1514}
1515
1516/// Add standard GC passes.
1519 return true;
1520}
1521
1522/// Add standard basic block placement passes.
1527 const std::string ProfileFile = getFSProfileFile(TM);
1528 if (!ProfileFile.empty() && !DisableLayoutFSProfileLoader)
1531 nullptr));
1532 }
1534 // Run a separate pass to collect block placement statistics.
1537 }
1538}
1539
1540//===---------------------------------------------------------------------===//
1541/// GlobalISel Configuration
1542//===---------------------------------------------------------------------===//
1545}
1546
1549}
1550
1552 return true;
1553}
1554
1555std::unique_ptr<CSEConfigBase> TargetPassConfig::getCSEConfig() const {
1556 return std::make_unique<CSEConfigBase>();
1557}
This is the interface for LLVM's primary stateless and local alias analysis.
#define clEnumValN(ENUMVAL, FLAGNAME, DESC)
Definition: CommandLine.h:678
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
This file defines the DenseMap class.
std::string Name
This file contains an interface for creating legacy passes to print out IR in various granularities.
#define I(x, y, z)
Definition: MD5.cpp:58
#define P(N)
ppc ctr loops PowerPC CTR Loops Verify
if(VerifyEach)
const char LLVMTargetMachineRef TM
PassInstrumentationCallbacks PIC
This file defines the Pass Instrumentation classes that provide instrumentation points into the pass ...
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:38
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file provides utility classes that use RAII to save and restore values.
This is the interface for a metadata-based scoped no-alias analysis.
This file defines the SmallVector class.
static const char StopAfterOptName[]
static cl::opt< bool > DisableExpandReductions("disable-expand-reductions", cl::init(false), cl::Hidden, cl::desc("Disable the expand reduction intrinsics pass from running"))
Disable the expand reductions pass for testing.
static cl::opt< bool > EnableImplicitNullChecks("enable-implicit-null-checks", cl::desc("Fold null checks into faulting memory operations"), cl::init(false), cl::Hidden)
static cl::opt< bool > DisableMachineSink("disable-machine-sink", cl::Hidden, cl::desc("Disable Machine Sinking"))
static cl::opt< cl::boolOrDefault > DebugifyAndStripAll("debugify-and-strip-all-safe", cl::Hidden, cl::desc("Debugify MIR before and Strip debug after " "each pass except those known to be unsafe " "when debug info is present"))
static llvm::once_flag InitializeDefaultRegisterAllocatorFlag
A dummy default pass factory indicates whether the register allocator is overridden on the command li...
static cl::opt< RegisterRegAlloc::FunctionPassCtor, false, RegisterPassParser< RegisterRegAlloc > > RegAlloc("regalloc", cl::Hidden, cl::init(&useDefaultRegisterAllocator), cl::desc("Register allocator to use"))
static cl::opt< bool > PrintISelInput("print-isel-input", cl::Hidden, cl::desc("Print LLVM IR input to isel pass"))
static FunctionPass * useDefaultRegisterAllocator()
-regalloc=... command line option.
static cl::opt< bool > DisablePostRASched("disable-post-ra", cl::Hidden, cl::desc("Disable Post Regalloc Scheduler"))
static cl::opt< bool > EnableBlockPlacementStats("enable-block-placement-stats", cl::Hidden, cl::desc("Collect probability-driven block placement stats"))
static cl::opt< bool > DisableMachineDCE("disable-machine-dce", cl::Hidden, cl::desc("Disable Machine Dead Code Elimination"))
static void registerPartialPipelineCallback(PassInstrumentationCallbacks &PIC, LLVMTargetMachine &LLVMTM)
static std::string getFSRemappingFile(const TargetMachine *TM)
static const char StopBeforeOptName[]
static AnalysisID getPassIDFromName(StringRef PassName)
static cl::opt< bool > DisableEarlyIfConversion("disable-early-ifcvt", cl::Hidden, cl::desc("Disable Early If-conversion"))
static cl::opt< bool > EnableMachineFunctionSplitter("enable-split-machine-functions", cl::Hidden, cl::desc("Split out cold blocks from machine functions based on profile " "information."))
Enable the machine function splitter pass.
static IdentifyingPassPtr overridePass(AnalysisID StandardID, IdentifyingPassPtr TargetID)
Allow standard passes to be disabled by the command line, regardless of who is adding the pass.
static cl::opt< bool > PrintGCInfo("print-gc", cl::Hidden, cl::desc("Dump garbage collector data"))
static std::pair< StringRef, unsigned > getPassNameAndInstanceNum(StringRef PassName)
static cl::opt< bool > PrintAfterISel("print-after-isel", cl::init(false), cl::Hidden, cl::desc("Print machine instrs after ISel"))
static cl::opt< cl::boolOrDefault > VerifyMachineCode("verify-machineinstrs", cl::Hidden, cl::desc("Verify generated machine code"))
static cl::opt< bool > DisablePartialLibcallInlining("disable-partial-libcall-inlining", cl::Hidden, cl::desc("Disable Partial Libcall Inlining"))
#define SET_BOOLEAN_OPTION(Option)
static cl::opt< std::string > StartAfterOpt(StringRef(StartAfterOptName), cl::desc("Resume compilation after a specific pass"), cl::value_desc("pass-name"), cl::init(""), cl::Hidden)
static cl::opt< bool > DisableBlockPlacement("disable-block-placement", cl::Hidden, cl::desc("Disable probability-driven block placement"))
static cl::opt< bool > DisableRAFSProfileLoader("disable-ra-fsprofile-loader", cl::init(false), cl::Hidden, cl::desc("Disable MIRProfileLoader before RegAlloc"))
static cl::opt< std::string > StopAfterOpt(StringRef(StopAfterOptName), cl::desc("Stop compilation after a specific pass"), cl::value_desc("pass-name"), cl::init(""), cl::Hidden)
static void initializeDefaultRegisterAllocatorOnce()
static cl::opt< bool > PrintLSR("print-lsr-output", cl::Hidden, cl::desc("Print LLVM IR produced by the loop-reduce pass"))
static cl::opt< bool > DisableSelectOptimize("disable-select-optimize", cl::init(true), cl::Hidden, cl::desc("Disable the select-optimization pass from running"))
Disable the select optimization pass.
static cl::opt< std::string > FSRemappingFile("fs-remapping-file", cl::init(""), cl::value_desc("filename"), cl::desc("Flow Sensitive profile remapping file name."), cl::Hidden)
static cl::opt< bool > DisableCFIFixup("disable-cfi-fixup", cl::Hidden, cl::desc("Disable the CFI fixup pass"))
static cl::opt< bool > FSNoFinalDiscrim("fs-no-final-discrim", cl::init(false), cl::Hidden, cl::desc("Do not insert FS-AFDO discriminators before " "emit."))
static cl::opt< bool > DisablePostRAMachineLICM("disable-postra-machine-licm", cl::Hidden, cl::desc("Disable Machine LICM"))
static const char StartBeforeOptName[]
static const PassInfo * getPassInfo(StringRef PassName)
static cl::opt< bool > EarlyLiveIntervals("early-live-intervals", cl::Hidden, cl::desc("Run live interval analysis earlier in the pipeline"))
static cl::opt< bool > DisableMachineLICM("disable-machine-licm", cl::Hidden, cl::desc("Disable Machine LICM"))
static cl::opt< cl::boolOrDefault > EnableGlobalISelOption("global-isel", cl::Hidden, cl::desc("Enable the \"global\" instruction selector"))
static cl::opt< bool > DisableTailDuplicate("disable-tail-duplicate", cl::Hidden, cl::desc("Disable tail duplication"))
static cl::opt< bool > DisablePostRAMachineSink("disable-postra-machine-sink", cl::Hidden, cl::desc("Disable PostRA Machine Sinking"))
static const char StartAfterOptName[]
Option names for limiting the codegen pipeline.
static cl::opt< bool > EnableIPRA("enable-ipra", cl::init(false), cl::Hidden, cl::desc("Enable interprocedural register allocation " "to reduce load/store at procedure calls."))
static cl::opt< bool > DisableCGP("disable-cgp", cl::Hidden, cl::desc("Disable Codegen Prepare"))
static std::string getFSProfileFile(const TargetMachine *TM)
static cl::opt< std::string > StartBeforeOpt(StringRef(StartBeforeOptName), cl::desc("Resume compilation before a specific pass"), cl::value_desc("pass-name"), cl::init(""), cl::Hidden)
static IdentifyingPassPtr applyDisable(IdentifyingPassPtr PassID, bool Override)
Allow standard passes to be disabled by command line options.
static cl::opt< GlobalISelAbortMode > EnableGlobalISelAbort("global-isel-abort", cl::Hidden, cl::desc("Enable abort calls when \"global\" instruction selection " "fails to lower/select an instruction"), cl::values(clEnumValN(GlobalISelAbortMode::Disable, "0", "Disable the abort"), clEnumValN(GlobalISelAbortMode::Enable, "1", "Enable the abort"), clEnumValN(GlobalISelAbortMode::DisableWithDiag, "2", "Disable the abort but emit a diagnostic on failure")))
static cl::opt< bool > DisableEarlyTailDup("disable-early-taildup", cl::Hidden, cl::desc("Disable pre-register allocation tail duplication"))
static cl::opt< bool > DisableConstantHoisting("disable-constant-hoisting", cl::Hidden, cl::desc("Disable ConstantHoisting"))
static cl::opt< cl::boolOrDefault > EnableFastISelOption("fast-isel", cl::Hidden, cl::desc("Enable the \"fast\" instruction selector"))
static cl::opt< bool > DisableSSC("disable-ssc", cl::Hidden, cl::desc("Disable Stack Slot Coloring"))
static cl::opt< bool > DisableBranchFold("disable-branch-fold", cl::Hidden, cl::desc("Disable branch folding"))
#define DISABLE_PASS(Option, Name)
static RegisterRegAlloc defaultRegAlloc("default", "pick register allocator based on -O option", useDefaultRegisterAllocator)
static cl::opt< std::string > StopBeforeOpt(StringRef(StopBeforeOptName), cl::desc("Stop compilation before a specific pass"), cl::value_desc("pass-name"), cl::init(""), cl::Hidden)
static cl::opt< bool > DisableMachineCSE("disable-machine-cse", cl::Hidden, cl::desc("Disable Machine Common Subexpression Elimination"))
static cl::opt< bool > DisableLayoutFSProfileLoader("disable-layout-fsprofile-loader", cl::init(false), cl::Hidden, cl::desc("Disable MIRProfileLoader before BlockPlacement"))
static cl::opt< bool > MISchedPostRA("misched-postra", cl::Hidden, cl::desc("Run MachineScheduler post regalloc (independent of preRA sched)"))
static cl::opt< bool > DisableMergeICmps("disable-mergeicmps", cl::desc("Disable MergeICmps Pass"), cl::init(false), cl::Hidden)
static cl::opt< RunOutliner > EnableMachineOutliner("enable-machine-outliner", cl::desc("Enable the machine outliner"), cl::Hidden, cl::ValueOptional, cl::init(RunOutliner::TargetDefault), cl::values(clEnumValN(RunOutliner::AlwaysOutline, "always", "Run on all functions guaranteed to be beneficial"), clEnumValN(RunOutliner::NeverOutline, "never", "Disable all outlining"), clEnumValN(RunOutliner::AlwaysOutline, "", "")))
static cl::opt< bool > DisableCopyProp("disable-copyprop", cl::Hidden, cl::desc("Disable Copy Propagation pass"))
static cl::opt< cl::boolOrDefault > OptimizeRegAlloc("optimize-regalloc", cl::Hidden, cl::desc("Enable optimized register allocation compilation path."))
static cl::opt< bool > DisableLSR("disable-lsr", cl::Hidden, cl::desc("Disable Loop Strength Reduction Pass"))
static cl::opt< std::string > FSProfileFile("fs-profile-file", cl::init(""), cl::value_desc("filename"), cl::desc("Flow Sensitive profile file name."), cl::Hidden)
static cl::opt< cl::boolOrDefault > DebugifyCheckAndStripAll("debugify-check-and-strip-all-safe", cl::Hidden, cl::desc("Debugify MIR before, by checking and stripping the debug info after, " "each pass except those known to be unsafe when debug info is " "present"))
#define SET_OPTION(Option)
Target-Independent Code Generator Pass Configuration Options pass.
This pass exposes codegen information to IR-level passes.
This is the interface for a metadata-based TBAA.
Defines the virtual file system interface vfs::FileSystem.
static const char PassName[]
Definition: Any.h:28
This pass is required by interprocedural register allocation.
This is a fast-path instruction selection class that generates poor code and doesn't support illegal ...
Definition: FastISel.h:66
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:308
Discriminated union of Pass ID types.
AnalysisID getID() const
ImmutablePass class - This class is used to provide information that does not need to be run.
Definition: Pass.h:279
This class describes a target machine that is implemented with the LLVM target-independent code gener...
virtual bool isMachineVerifierClean() const
Returns true if the target is expected to pass all machine verifier checks.
virtual bool useIPRA() const
True if the target wants to use interprocedural register allocation by default.
virtual TargetPassConfig * createPassConfig(PassManagerBase &PM)
Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of ...
virtual std::pair< StringRef, bool > getPassNameFromLegacyName(StringRef)
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:56
ExceptionHandling getExceptionHandlingType() const
Definition: MCAsmInfo.h:781
DenseMap< AnalysisID, IdentifyingPassPtr > TargetPasses
SmallVector< InsertedPass, 4 > InsertedPasses
Store the pairs of <AnalysisID, AnalysisID> of which the second pass is inserted after each instance ...
PassInfo class - An instance of this class exists for every pass known by the system,...
Definition: PassInfo.h:30
const void * getTypeInfo() const
getTypeInfo - Return the id object for the pass... TODO : Rename
Definition: PassInfo.h:71
This class manages callbacks registration, as well as provides a way for PassInstrumentation to pass ...
void registerShouldRunOptionalPassCallback(CallableT C)
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
Definition: PassRegistry.h:38
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
const PassInfo * getPassInfo(const void *TI) const
getPassInfo - Look up a pass' corresponding PassInfo, indexed by the pass' type identifier (&MyPass::...
Pass interface - Implemented by all 'passes'.
Definition: Pass.h:91
static Pass * createPass(AnalysisID ID)
Definition: Pass.cpp:196
AnalysisID getPassID() const
getPassID - Return the PassID number that corresponds to this pass.
Definition: Pass.h:110
RegisterPassParser class - Handle the addition of new machine passes.
static void setDefault(FunctionPassCtor C)
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:221
reference emplace_back(ArgTypes &&... Args)
Definition: SmallVector.h:941
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1200
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
bool getAsInteger(unsigned Radix, T &Result) const
Parse the current string as an integer of the specified radix.
Definition: StringRef.h:469
constexpr bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:134
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:78
const Triple & getTargetTriple() const
void setFastISel(bool Enable)
CodeGenOpt::Level getOptLevel() const
Returns the optimization level: None, Less, Default, or Aggressive.
const MemoryBuffer * getBBSectionsFuncListBuf() const
Get the list of functions and basic block ids that need unique sections.
bool useEmulatedTLS() const
Returns true if this target uses emulated TLS.
virtual bool targetSchedulesPostRAScheduling() const
True if subtarget inserts the final scheduling pass on its own.
bool requiresStructuredCFG() const
void setGlobalISel(bool Enable)
TargetIRAnalysis getTargetIRAnalysis() const
Get a TargetIRAnalysis appropriate for the target.
TargetOptions Options
void setO0WantsFastISel(bool Enable)
llvm::BasicBlockSection getBBSectionsType() const
If basic blocks should be emitted into their own section, corresponding to -fbasic-block-sections.
const MCAsmInfo * getMCAsmInfo() const
Return target specific asm information.
unsigned EnableMachineOutliner
Enables the MachineOutliner pass.
GlobalISelAbortMode GlobalISelAbort
EnableGlobalISelAbort - Control abort behaviour when global instruction selection fails to lower/sele...
unsigned EnableCFIFixup
Enable the CFIFixup pass.
unsigned SupportsDefaultOutlining
Set if the target supports default outlining behaviour.
unsigned LowerGlobalDtorsViaCxaAtExit
Use __cxa_atexit to register global destructors; determines how llvm.global_dtors is lowered.
unsigned EnableMachineFunctionSplitter
Enables the MachineFunctionSplitter pass.
unsigned EnableIPRA
This flag enables InterProcedural Register Allocation (IPRA).
unsigned EnableGlobalISel
EnableGlobalISel - This flag enables global instruction selection.
Target-Independent Code Generator Pass Configuration Options.
bool usingDefaultRegAlloc() const
Return true if the default global register allocator is in use and has not be overriden on the comman...
bool requiresCodeGenSCCOrder() const
void addCheckDebugPass()
Add a pass to check synthesized debug info for MIR.
LLVMTargetMachine * TM
virtual void addPreLegalizeMachineIR()
This method may be implemented by targets that want to run passes immediately before legalization.
void addPrintPass(const std::string &Banner)
Add a pass to print the machine function if printing is enabled.
virtual void addPreEmitPass2()
Targets may add passes immediately before machine code is emitted in this callback.
virtual std::unique_ptr< CSEConfigBase > getCSEConfig() const
Returns the CSEConfig object to use for the current optimization level.
void printAndVerify(const std::string &Banner)
printAndVerify - Add a pass to dump then verify the machine function, if those steps are enabled.
static std::string getLimitedCodeGenPipelineReason(const char *Separator="/")
If hasLimitedCodeGenPipeline is true, this method returns a string with the name of the options,...
static bool hasLimitedCodeGenPipeline()
Returns true if one of the -start-after, -start-before, -stop-after or -stop-before options is set.
virtual void addCodeGenPrepare()
Add pass to prepare the LLVM IR for code generation.
void insertPass(AnalysisID TargetPassID, IdentifyingPassPtr InsertedPassID)
Insert InsertedPassID pass after TargetPassID pass.
void addMachinePostPasses(const std::string &Banner)
Add standard passes after a pass that has just been added.
virtual void addPreSched2()
This method may be implemented by targets that want to run passes after prolog-epilog insertion and b...
virtual bool isGISelCSEEnabled() const
Check whether continuous CSE should be enabled in GISel passes.
virtual bool addILPOpts()
Add passes that optimize instruction level parallelism for out-of-order targets.
virtual void addPostRegAlloc()
This method may be implemented by targets that want to run passes after register allocation pass pipe...
void addDebugifyPass()
Add a pass to add synthesized debug info to the MIR.
virtual bool addInstSelector()
addInstSelector - This method should install an instruction selector pass, which converts from LLVM c...
virtual bool addPreISel()
Methods with trivial inline returns are convenient points in the common codegen pass pipeline where t...
void setOpt(bool &Opt, bool Val)
virtual void addBlockPlacement()
Add standard basic block placement passes.
virtual FunctionPass * createRegAllocPass(bool Optimized)
addMachinePasses helper to create the target-selected or overriden regalloc pass.
virtual void addOptimizedRegAlloc()
addOptimizedRegAlloc - Add passes related to register allocation.
virtual bool addRegAssignAndRewriteFast()
Add core register allocator passes which do the actual register assignment and rewriting.
virtual void addPreEmitPass()
This pass may be implemented by targets that want to run passes immediately before machine code is em...
bool isGlobalISelAbortEnabled() const
Check whether or not GlobalISel should abort on error.
bool getOptimizeRegAlloc() const
Return true if the optimized regalloc pipeline is enabled.
bool isCustomizedRegAlloc()
Return true if register allocator is specified by -regalloc=override.
virtual void addPreRegBankSelect()
This method may be implemented by targets that want to run passes immediately before the register ban...
virtual bool reportDiagnosticWhenGlobalISelFallback() const
Check whether or not a diagnostic should be emitted when GlobalISel uses the fallback path.
virtual bool addPreRewrite()
addPreRewrite - Add passes to the optimized register allocation pipeline after register allocation is...
virtual bool addRegBankSelect()
This method should install a register bank selector pass, which assigns register banks to virtual reg...
CodeGenOpt::Level getOptLevel() const
void setRequiresCodeGenSCCOrder(bool Enable=true)
virtual void addMachineLateOptimization()
Add passes that optimize machine instructions after register allocation.
virtual void addMachinePasses()
Add the complete, standard set of LLVM CodeGen passes.
virtual void addIRPasses()
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
virtual void addPreGlobalInstructionSelect()
This method may be implemented by targets that want to run passes immediately before the (global) ins...
virtual void addFastRegAlloc()
addFastRegAlloc - Add the minimum set of target-independent passes that are required for fast registe...
virtual bool addLegalizeMachineIR()
This method should install a legalize pass, which converts the instruction sequence into one that can...
virtual void addMachineSSAOptimization()
addMachineSSAOptimization - Add standard passes that optimize machine instructions in SSA form.
void substitutePass(AnalysisID StandardID, IdentifyingPassPtr TargetID)
Allow the target to override a specific pass without overriding the pass pipeline.
virtual bool addRegAssignAndRewriteOptimized()
virtual bool addGlobalInstructionSelect()
This method should install a (global) instruction selector pass, which converts possibly generic inst...
virtual void addPreRegAlloc()
This method may be implemented by targets that want to run passes immediately before register allocat...
AnalysisID addPass(AnalysisID PassID)
Utilities for targets to add passes to the pass manager.
void addPassesToHandleExceptions()
Add passes to lower exception handling for the code generator.
void addStripDebugPass()
Add a pass to remove debug info from the MIR.
bool isPassSubstitutedOrOverridden(AnalysisID ID) const
Return true if the pass has been substituted by the target or overridden on the command line.
bool addCoreISelPasses()
Add the actual instruction selection passes.
virtual void addISelPrepare()
Add common passes that perform LLVM IR to IR transforms in preparation for instruction selection.
static bool willCompleteCodeGenPipeline()
Returns true if none of the -stop-before and -stop-after options is set.
void addMachinePrePasses(bool AllowDebugify=true)
Add standard passes before a pass that's about to be added.
virtual bool addGCPasses()
addGCPasses - Add late codegen passes that analyze code for garbage collection.
virtual bool addIRTranslator()
This method should install an IR translator pass, which converts from LLVM code to machine instructio...
void addVerifyPass(const std::string &Banner)
Add a pass to perform basic verification of the machine function if verification is enabled.
virtual FunctionPass * createTargetRegisterAllocator(bool Optimized)
createTargetRegisterAllocator - Create the register allocator pass for this target at the current opt...
virtual bool addPostFastRegAllocRewrite()
addPostFastRegAllocRewrite - Add passes to the optimized register allocation pipeline after fast regi...
IdentifyingPassPtr getPassSubstitution(AnalysisID StandardID) const
Return the pass substituted for StandardID by the target.
bool addISelPasses()
High level function that adds all passes necessary to go from llvm IR representation to the MI repres...
virtual void addPostRewrite()
Add passes to be run immediately after virtual registers are rewritten to physical registers.
bool isOSBinFormatMachO() const
Tests whether the environment is MachO.
Definition: Triple.h:687
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:81
int getNumOccurrences() const
Definition: CommandLine.h:401
PassManagerBase - An abstract interface to allow code to add passes to a pass manager without having ...
virtual void add(Pass *P)=0
Add a pass to the queue of passes to run.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Level
Code generation optimization level.
Definition: CodeGen.h:57
@ ValueOptional
Definition: CommandLine.h:131
ValuesClass values(OptsTy... Options)
Helper to build a ValuesClass by forwarding a variable number of arguments as an initializer list to ...
Definition: CommandLine.h:703
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:445
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
FunctionPass * createFastRegisterAllocator()
FastRegisterAllocation Pass - This pass register allocates as fast as possible.
char & EarlyMachineLICMID
This pass performs loop invariant code motion on machine instructions.
char & GCMachineCodeAnalysisID
GCMachineCodeAnalysis - Target-independent pass to mark safe points in machine code.
ModulePass * createPreISelIntrinsicLoweringPass()
This pass lowers the @llvm.load.relative and @llvm.objc.
char & FEntryInserterID
This pass inserts FEntry calls.
FunctionPass * createUnreachableBlockEliminationPass()
createUnreachableBlockEliminationPass - The LLVM code generator does not work well with unreachable b...
FunctionPass * createSjLjEHPreparePass(const TargetMachine *TM)
createSjLjEHPreparePass - This pass adapts exception handling code to use the GCC-style builtin setjm...
FunctionPass * createTLSVariableHoistPass()
char & GCLoweringID
GCLowering Pass - Used by gc.root to perform its default lowering operations.
char & RegisterCoalescerID
RegisterCoalescer - This pass merges live ranges to eliminate copies.
FunctionPass * createGreedyRegisterAllocator()
Greedy register allocation pass - This pass implements a global register allocator for optimized buil...
FunctionPass * createConstantHoistingPass()
char & OptimizePHIsID
OptimizePHIs - This pass optimizes machine instruction PHIs to take advantage of opportunities create...
FunctionPass * createSafeStackPass()
This pass splits the stack into a safe stack and an unsafe stack to protect against stack-based overf...
Definition: SafeStack.cpp:939
char & EarlyTailDuplicateID
Duplicate blocks with unconditional branches into tails of their predecessors.
void registerCodeGenCallback(PassInstrumentationCallbacks &PIC, LLVMTargetMachine &)
char & MachineSinkingID
MachineSinking - This pass performs sinking on machine instructions.
@ SjLj
setjmp/longjmp based exceptions
@ None
No exception support.
@ AIX
AIX Exception Handling.
@ DwarfCFI
DWARF-like instruction based exceptions.
@ WinEH
Windows Exception Handling.
@ Wasm
WebAssembly Exception Handling.
FunctionPass * createSelectOptimizePass()
This pass converts conditional moves to conditional jumps when profitable.
FunctionPass * createWasmEHPass()
createWasmEHPass - This pass adapts exception handling code to use WebAssembly's exception handling s...
char & FixupStatepointCallerSavedID
The pass fixups statepoint machine instruction to replace usage of caller saved registers with stack ...
FunctionPass * createExpandVectorPredicationPass()
This pass expands the vector predication intrinsics into unpredicated instructions with selects or ju...
MachineFunctionPass * createBasicBlockSectionsPass()
createBasicBlockSections Pass - This pass assigns sections to machine basic blocks and is enabled wit...
MachineFunctionPass * createPrologEpilogInserterPass()
char & TailDuplicateID
TailDuplicate - Duplicate blocks with unconditional branches into tails of their predecessors.
ModulePass * createStripDebugMachineModulePass(bool OnlyDebugified)
Creates MIR Strip Debug pass.
char & ExpandPostRAPseudosID
ExpandPostRAPseudos - This pass expands pseudo instructions after register allocation.
char & PatchableFunctionID
This pass implements the "patchable-function" attribute.
FunctionPass * createScalarizeMaskedMemIntrinLegacyPass()
ModulePass * createLowerEmuTLSPass()
LowerEmuTLS - This pass generates __emutls_[vt].xyz variables for all TLS variables for the emulated ...
char & PostRASchedulerID
PostRAScheduler - This pass performs post register allocation scheduling.
FunctionPass * createStackProtectorPass()
createStackProtectorPass - This pass adds stack protectors to functions.
char & MachineSchedulerID
MachineScheduler - This pass schedules machine instructions.
char & PeepholeOptimizerID
PeepholeOptimizer - This pass performs peephole optimizations - like extension and comparison elimina...
char & PostMachineSchedulerID
PostMachineScheduler - This pass schedules machine instructions postRA.
char & LiveDebugValuesID
LiveDebugValues pass.
char & PrologEpilogCodeInserterID
PrologEpilogCodeInserter - This pass inserts prolog and epilog code, and eliminates abstract frame re...
FunctionPass * createExpandLargeFpConvertPass()
FunctionPass * createDwarfEHPass(CodeGenOpt::Level OptLevel)
createDwarfEHPass - This pass mulches exception handling code into a form adapted to code generation.
char & MachineLoopInfoID
MachineLoopInfo - This pass is a loop analysis pass.
cl::opt< bool > EnableFSDiscriminator
char & ShadowStackGCLoweringID
ShadowStackGCLowering - Implements the custom lowering mechanism used by the shadow stack GC.
MachineFunctionPass * createStackFrameLayoutAnalysisPass()
StackFramePrinter pass - This pass prints out the machine function's stack frame to the given stream ...
FunctionPass * createMIRAddFSDiscriminatorsPass(sampleprof::FSDiscriminatorPass P)
Add Flow Sensitive Discriminators.
char & MachineSanitizerBinaryMetadataID
char & ImplicitNullChecksID
ImplicitNullChecks - This pass folds null pointer checks into nearby memory operations.
void initializeAAResultsWrapperPassPass(PassRegistry &)
char & ShrinkWrapID
ShrinkWrap pass. Look for the best place to insert save and restore.
Definition: ShrinkWrap.cpp:250
char & MachineLateInstrsCleanupID
MachineLateInstrsCleanup - This pass removes redundant identical instructions after register allocati...
ImmutablePass * createScopedNoAliasAAWrapperPass()
ModulePass * createLowerGlobalDtorsLegacyPass()
FunctionPass * createLowerInvokePass()
Definition: LowerInvoke.cpp:85
FunctionPass * createRegUsageInfoCollector()
This pass is executed POST-RA to collect which physical registers are preserved by given machine func...
FunctionPass * createExpandMemCmpPass()
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
char & XRayInstrumentationID
This pass inserts the XRay instrumentation sleds if they are supported by the target platform.
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:145
char & StackMapLivenessID
StackMapLiveness - This pass analyses the register live-out set of stackmap/patchpoint intrinsics and...
char & FuncletLayoutID
This pass lays out funclets contiguously.
FunctionPass * createGCInfoPrinter(raw_ostream &OS)
Creates a pass to print GC metadata.
Definition: GCMetadata.cpp:89
char & RemoveRedundantDebugValuesID
RemoveRedundantDebugValues pass.
FunctionPass * createBasicAAWrapperPass()
char & DetectDeadLanesID
This pass adds dead/undef flags after analyzing subregister lanes.
char & StackColoringID
StackSlotColoring - This pass performs stack coloring and merging.
char & PostRAMachineSinkingID
This pass perform post-ra machine sink for COPY instructions.
FunctionPass * createRegAllocScoringPass()
When learning an eviction policy, extract score(reward) information, otherwise this does nothing.
ModulePass * createMachineOutlinerPass(bool RunOnAllFunctions=true)
This pass performs outlining on machine instructions directly before printing assembly.
const void * AnalysisID
Definition: Pass.h:47
char & StackSlotColoringID
StackSlotColoring - This pass performs stack slot coloring.
char & EarlyIfConverterID
EarlyIfConverter - This pass performs if-conversion on SSA form by inserting cmov instructions.
FunctionPass * createExpandLargeDivRemPass()
Pass * createMergeICmpsLegacyPass()
Definition: MergeICmps.cpp:910
char & ProcessImplicitDefsID
ProcessImpicitDefs pass - This pass removes IMPLICIT_DEFs.
ModulePass * createCheckDebugMachineModulePass()
Creates MIR Check Debug pass.
ImmutablePass * createTargetTransformInfoWrapperPass(TargetIRAnalysis TIRA)
Create an analysis pass wrapper around a TTI object.
ImmutablePass * createTypeBasedAAWrapperPass()
FunctionPass * createMIRProfileLoaderPass(std::string File, std::string RemappingFile, sampleprof::FSDiscriminatorPass P, IntrusiveRefCntPtr< vfs::FileSystem > FS)
Read Flow Sensitive Profile.
FunctionPass * createCFIFixup()
Creates CFI Fixup pass.
char & MachineCSEID
MachineCSE - This pass performs global CSE on machine instructions.
Definition: MachineCSE.cpp:162
FunctionPass * createVerifierPass(bool FatalErrors=true)
Definition: Verifier.cpp:6851
void initializeBasicAAWrapperPassPass(PassRegistry &)
MachineFunctionPass * createMachineFunctionPrinterPass(raw_ostream &OS, const std::string &Banner="")
MachineFunctionPrinter pass - This pass prints out the machine function to the given stream as a debu...
Pass * createLoopStrengthReducePass()
char & LiveVariablesID
LiveVariables pass - This pass computes the set of blocks in which each variable is life and sets mac...
FunctionPass * createExpandReductionsPass()
This pass expands the experimental reduction intrinsics into sequences of shuffles.
MachineFunctionPass * createMachineFunctionSplitterPass()
createMachineFunctionSplitterPass - This pass splits machine functions using profile information.
void call_once(once_flag &flag, Function &&F, Args &&... ArgList)
Execute the function specified as a parameter once.
Definition: Threading.h:87
MachineFunctionPass * createResetMachineFunctionPass(bool EmitFallbackDiag, bool AbortOnFailedISel)
This pass resets a MachineFunction when it has the FailedISel property as if it was just created.
char & VirtRegRewriterID
VirtRegRewriter pass.
Definition: VirtRegMap.cpp:227
FunctionPass * createReplaceWithVeclibLegacyPass()
FunctionPass * createLowerConstantIntrinsicsPass()
ImmutablePass * createBasicBlockSectionsProfileReaderPass(const MemoryBuffer *Buf)
char & FinalizeISelID
This pass expands pseudo-instructions, reserves registers and adjusts machine frame information.
FunctionPass * createCodeGenPreparePass()
createCodeGenPreparePass - Transform the code to expose more pattern matching during instruction sele...
FunctionPass * createRegUsageInfoPropPass()
Return a MachineFunction pass that identifies call sites and propagates register usage information of...
FunctionPass * createPartiallyInlineLibCallsPass()
char & UnreachableMachineBlockElimID
UnreachableMachineBlockElimination - This pass removes unreachable machine basic blocks.
char & MachineBlockPlacementID
MachineBlockPlacement - This pass places basic blocks based on branch probabilities.
char & TwoAddressInstructionPassID
TwoAddressInstruction - This pass reduces two-address instructions to use two operands.
Pass * createCanonicalizeFreezeInLoopsPass()
char & LocalStackSlotAllocationID
LocalStackSlotAllocation - This pass assigns local frame indices to stack slots relative to one anoth...
char & BranchFolderPassID
BranchFolding - This pass performs machine code CFG based optimizations to delete branches to branche...
char & PHIEliminationID
PHIElimination - This pass eliminates machine instruction PHI nodes by inserting copy instructions.
ModulePass * createDebugifyMachineModulePass()
Creates MIR Debugify pass.
FunctionPass * createPrintFunctionPass(raw_ostream &OS, const std::string &Banner="")
Create and return a pass that prints functions to the specified raw_ostream as they are processed.
char & RenameIndependentSubregsID
This pass detects subregister lanes in a virtual register that are used independently of other lanes ...
char & MachineLICMID
This pass performs loop invariant code motion on machine instructions.
char & MachineBlockPlacementStatsID
MachineBlockPlacementStats - This pass collects statistics about the basic block placement using bran...
char & LiveIntervalsID
LiveIntervals - This analysis keeps track of the live ranges of virtual and physical registers.
char & MachineCopyPropagationID
MachineCopyPropagation - This pass performs copy propagation on machine instructions.
char & DeadMachineInstructionElimID
DeadMachineInstructionElim - This pass removes dead machine instructions.
void initializeCodeGen(PassRegistry &)
Initialize all passes linked into the CodeGen library.
Definition: CodeGen.cpp:21
FunctionPass * createMachineVerifierPass(const std::string &Banner)
createMachineVerifierPass - This pass verifies cenerated machine code instructions for correctness.
FunctionPass * createWinEHPass(bool DemoteCatchSwitchPHIOnly=false)
createWinEHPass - Prepares personality functions used by MSVC on Windows, in addition to the Itanium ...
CGPassBuilderOption getCGPassBuilderOption()
InsertedPass(AnalysisID TargetPassID, IdentifyingPassPtr InsertedPassID)
A utility class that uses RAII to save and restore the value of a variable.
The llvm::once_flag structure.
Definition: Threading.h:68