LLVM  13.0.0git
TargetPassConfig.cpp
Go to the documentation of this file.
1 //===- TargetPassConfig.cpp - Target independent code generation passes ---===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines interfaces to access the target independent code
10 // generation passes provided by the LLVM backend.
11 //
12 //===---------------------------------------------------------------------===//
13 
15 #include "llvm/ADT/DenseMap.h"
16 #include "llvm/ADT/SmallVector.h"
17 #include "llvm/ADT/StringRef.h"
28 #include "llvm/CodeGen/Passes.h"
33 #include "llvm/IR/Verifier.h"
34 #include "llvm/InitializePasses.h"
35 #include "llvm/MC/MCAsmInfo.h"
37 #include "llvm/Pass.h"
38 #include "llvm/Support/CodeGen.h"
40 #include "llvm/Support/Compiler.h"
41 #include "llvm/Support/Debug.h"
44 #include "llvm/Support/Threading.h"
47 #include "llvm/Transforms/Scalar.h"
48 #include "llvm/Transforms/Utils.h"
50 #include <cassert>
51 #include <string>
52 
53 using namespace llvm;
54 
55 static cl::opt<bool>
56  EnableIPRA("enable-ipra", cl::init(false), cl::Hidden,
57  cl::desc("Enable interprocedural register allocation "
58  "to reduce load/store at procedure calls."));
59 static cl::opt<bool> DisablePostRASched("disable-post-ra", cl::Hidden,
60  cl::desc("Disable Post Regalloc Scheduler"));
61 static cl::opt<bool> DisableBranchFold("disable-branch-fold", cl::Hidden,
62  cl::desc("Disable branch folding"));
63 static cl::opt<bool> DisableTailDuplicate("disable-tail-duplicate", cl::Hidden,
64  cl::desc("Disable tail duplication"));
65 static cl::opt<bool> DisableEarlyTailDup("disable-early-taildup", cl::Hidden,
66  cl::desc("Disable pre-register allocation tail duplication"));
67 static cl::opt<bool> DisableBlockPlacement("disable-block-placement",
68  cl::Hidden, cl::desc("Disable probability-driven block placement"));
69 static cl::opt<bool> EnableBlockPlacementStats("enable-block-placement-stats",
70  cl::Hidden, cl::desc("Collect probability-driven block placement stats"));
71 static cl::opt<bool> DisableSSC("disable-ssc", cl::Hidden,
72  cl::desc("Disable Stack Slot Coloring"));
73 static cl::opt<bool> DisableMachineDCE("disable-machine-dce", cl::Hidden,
74  cl::desc("Disable Machine Dead Code Elimination"));
75 static cl::opt<bool> DisableEarlyIfConversion("disable-early-ifcvt", cl::Hidden,
76  cl::desc("Disable Early If-conversion"));
77 static cl::opt<bool> DisableMachineLICM("disable-machine-licm", cl::Hidden,
78  cl::desc("Disable Machine LICM"));
79 static cl::opt<bool> DisableMachineCSE("disable-machine-cse", cl::Hidden,
80  cl::desc("Disable Machine Common Subexpression Elimination"));
82  "optimize-regalloc", cl::Hidden,
83  cl::desc("Enable optimized register allocation compilation path."));
84 static cl::opt<bool> DisablePostRAMachineLICM("disable-postra-machine-licm",
85  cl::Hidden,
86  cl::desc("Disable Machine LICM"));
87 static cl::opt<bool> DisableMachineSink("disable-machine-sink", cl::Hidden,
88  cl::desc("Disable Machine Sinking"));
89 static cl::opt<bool> DisablePostRAMachineSink("disable-postra-machine-sink",
90  cl::Hidden,
91  cl::desc("Disable PostRA Machine Sinking"));
92 static cl::opt<bool> DisableLSR("disable-lsr", cl::Hidden,
93  cl::desc("Disable Loop Strength Reduction Pass"));
94 static cl::opt<bool> DisableConstantHoisting("disable-constant-hoisting",
95  cl::Hidden, cl::desc("Disable ConstantHoisting"));
96 static cl::opt<bool> DisableCGP("disable-cgp", cl::Hidden,
97  cl::desc("Disable Codegen Prepare"));
98 static cl::opt<bool> DisableCopyProp("disable-copyprop", cl::Hidden,
99  cl::desc("Disable Copy Propagation pass"));
100 static cl::opt<bool> DisablePartialLibcallInlining("disable-partial-libcall-inlining",
101  cl::Hidden, cl::desc("Disable Partial Libcall Inlining"));
103  "enable-implicit-null-checks",
104  cl::desc("Fold null checks into faulting memory operations"),
105  cl::init(false), cl::Hidden);
106 static cl::opt<bool> DisableMergeICmps("disable-mergeicmps",
107  cl::desc("Disable MergeICmps Pass"),
108  cl::init(false), cl::Hidden);
109 static cl::opt<bool> PrintLSR("print-lsr-output", cl::Hidden,
110  cl::desc("Print LLVM IR produced by the loop-reduce pass"));
111 static cl::opt<bool> PrintISelInput("print-isel-input", cl::Hidden,
112  cl::desc("Print LLVM IR input to isel pass"));
113 static cl::opt<bool> PrintGCInfo("print-gc", cl::Hidden,
114  cl::desc("Dump garbage collector data"));
116  VerifyMachineCode("verify-machineinstrs", cl::Hidden,
117  cl::desc("Verify generated machine code"),
120  "debugify-and-strip-all-safe", cl::Hidden,
121  cl::desc(
122  "Debugify MIR before and Strip debug after "
123  "each pass except those known to be unsafe when debug info is present"),
126  "debugify-check-and-strip-all-safe", cl::Hidden,
127  cl::desc(
128  "Debugify MIR before, by checking and stripping the debug info after, "
129  "each pass except those known to be unsafe when debug info is present"),
131 // Enable or disable the MachineOutliner.
133  "enable-machine-outliner", cl::desc("Enable the machine outliner"),
136  "Run on all functions guaranteed to be beneficial"),
138  "Disable all outlining"),
139  // Sentinel value for unspecified option.
141 // Enable or disable FastISel. Both options are needed, because
142 // FastISel is enabled by default with -fast, and we wish to be
143 // able to enable or disable fast-isel independently from -O0.
145 EnableFastISelOption("fast-isel", cl::Hidden,
146  cl::desc("Enable the \"fast\" instruction selector"));
147 
149  "global-isel", cl::Hidden,
150  cl::desc("Enable the \"global\" instruction selector"));
151 
152 // FIXME: remove this after switching to NPM or GlobalISel, whichever gets there
153 // first...
154 static cl::opt<bool>
155  PrintAfterISel("print-after-isel", cl::init(false), cl::Hidden,
156  cl::desc("Print machine instrs after ISel"));
157 
159  "global-isel-abort", cl::Hidden,
160  cl::desc("Enable abort calls when \"global\" instruction selection "
161  "fails to lower/select an instruction"),
162  cl::values(
163  clEnumValN(GlobalISelAbortMode::Disable, "0", "Disable the abort"),
164  clEnumValN(GlobalISelAbortMode::Enable, "1", "Enable the abort"),
166  "Disable the abort but emit a diagnostic on failure")));
167 
168 // Temporary option to allow experimenting with MachineScheduler as a post-RA
169 // scheduler. Targets can "properly" enable this with
170 // substitutePass(&PostRASchedulerID, &PostMachineSchedulerID).
171 // Targets can return true in targetSchedulesPostRAScheduling() and
172 // insert a PostRA scheduling pass wherever it wants.
174  "misched-postra", cl::Hidden,
175  cl::desc(
176  "Run MachineScheduler post regalloc (independent of preRA sched)"));
177 
178 // Experimental option to run live interval analysis early.
179 static cl::opt<bool> EarlyLiveIntervals("early-live-intervals", cl::Hidden,
180  cl::desc("Run live interval analysis earlier in the pipeline"));
181 
182 // Experimental option to use CFL-AA in codegen
184  "use-cfl-aa-in-codegen", cl::init(CFLAAType::None), cl::Hidden,
185  cl::desc("Enable the new, experimental CFL alias analysis in CodeGen"),
186  cl::values(clEnumValN(CFLAAType::None, "none", "Disable CFL-AA"),
188  "Enable unification-based CFL-AA"),
190  "Enable inclusion-based CFL-AA"),
191  clEnumValN(CFLAAType::Both, "both",
192  "Enable both variants of CFL-AA")));
193 
194 /// Option names for limiting the codegen pipeline.
195 /// Those are used in error reporting and we didn't want
196 /// to duplicate their names all over the place.
197 static const char StartAfterOptName[] = "start-after";
198 static const char StartBeforeOptName[] = "start-before";
199 static const char StopAfterOptName[] = "stop-after";
200 static const char StopBeforeOptName[] = "stop-before";
201 
204  cl::desc("Resume compilation after a specific pass"),
205  cl::value_desc("pass-name"), cl::init(""), cl::Hidden);
206 
209  cl::desc("Resume compilation before a specific pass"),
210  cl::value_desc("pass-name"), cl::init(""), cl::Hidden);
211 
214  cl::desc("Stop compilation after a specific pass"),
215  cl::value_desc("pass-name"), cl::init(""), cl::Hidden);
216 
219  cl::desc("Stop compilation before a specific pass"),
220  cl::value_desc("pass-name"), cl::init(""), cl::Hidden);
221 
222 /// Enable the machine function splitter pass.
224  "enable-split-machine-functions", cl::Hidden,
225  cl::desc("Split out cold blocks from machine functions based on profile "
226  "information."));
227 
228 /// Disable the expand reductions pass for testing.
230  "disable-expand-reductions", cl::init(false), cl::Hidden,
231  cl::desc("Disable the expand reduction intrinsics pass from running"));
232 
233 /// Allow standard passes to be disabled by command line options. This supports
234 /// simple binary flags that either suppress the pass or do nothing.
235 /// i.e. -disable-mypass=false has no effect.
236 /// These should be converted to boolOrDefault in order to use applyOverride.
238  bool Override) {
239  if (Override)
240  return IdentifyingPassPtr();
241  return PassID;
242 }
243 
244 /// Allow standard passes to be disabled by the command line, regardless of who
245 /// is adding the pass.
246 ///
247 /// StandardID is the pass identified in the standard pass pipeline and provided
248 /// to addPass(). It may be a target-specific ID in the case that the target
249 /// directly adds its own pass, but in that case we harmlessly fall through.
250 ///
251 /// TargetID is the pass that the target has configured to override StandardID.
252 ///
253 /// StandardID may be a pseudo ID. In that case TargetID is the name of the real
254 /// pass to run. This allows multiple options to control a single pass depending
255 /// on where in the pipeline that pass is added.
257  IdentifyingPassPtr TargetID) {
258  if (StandardID == &PostRASchedulerID)
259  return applyDisable(TargetID, DisablePostRASched);
260 
261  if (StandardID == &BranchFolderPassID)
262  return applyDisable(TargetID, DisableBranchFold);
263 
264  if (StandardID == &TailDuplicateID)
265  return applyDisable(TargetID, DisableTailDuplicate);
266 
267  if (StandardID == &EarlyTailDuplicateID)
268  return applyDisable(TargetID, DisableEarlyTailDup);
269 
270  if (StandardID == &MachineBlockPlacementID)
271  return applyDisable(TargetID, DisableBlockPlacement);
272 
273  if (StandardID == &StackSlotColoringID)
274  return applyDisable(TargetID, DisableSSC);
275 
276  if (StandardID == &DeadMachineInstructionElimID)
277  return applyDisable(TargetID, DisableMachineDCE);
278 
279  if (StandardID == &EarlyIfConverterID)
280  return applyDisable(TargetID, DisableEarlyIfConversion);
281 
282  if (StandardID == &EarlyMachineLICMID)
283  return applyDisable(TargetID, DisableMachineLICM);
284 
285  if (StandardID == &MachineCSEID)
286  return applyDisable(TargetID, DisableMachineCSE);
287 
288  if (StandardID == &MachineLICMID)
289  return applyDisable(TargetID, DisablePostRAMachineLICM);
290 
291  if (StandardID == &MachineSinkingID)
292  return applyDisable(TargetID, DisableMachineSink);
293 
294  if (StandardID == &PostRAMachineSinkingID)
295  return applyDisable(TargetID, DisablePostRAMachineSink);
296 
297  if (StandardID == &MachineCopyPropagationID)
298  return applyDisable(TargetID, DisableCopyProp);
299 
300  return TargetID;
301 }
302 
303 //===---------------------------------------------------------------------===//
304 /// TargetPassConfig
305 //===---------------------------------------------------------------------===//
306 
307 INITIALIZE_PASS(TargetPassConfig, "targetpassconfig",
308  "Target Pass Configuration", false, false)
309 char TargetPassConfig::ID = 0;
310 
311 namespace {
312 
313 struct InsertedPass {
317 
318  InsertedPass(AnalysisID TargetPassID, IdentifyingPassPtr InsertedPassID,
319  bool VerifyAfter)
320  : TargetPassID(TargetPassID), InsertedPassID(InsertedPassID),
321  VerifyAfter(VerifyAfter) {}
322 
324  assert(InsertedPassID.isValid() && "Illegal Pass ID!");
325  if (InsertedPassID.isInstance())
326  return InsertedPassID.getInstance();
327  Pass *NP = Pass::createPass(InsertedPassID.getID());
328  assert(NP && "Pass ID not registered");
329  return NP;
330  }
331 };
332 
333 } // end anonymous namespace
334 
335 namespace llvm {
336 
338 public:
339  // List of passes explicitly substituted by this target. Normally this is
340  // empty, but it is a convenient way to suppress or replace specific passes
341  // that are part of a standard pass pipeline without overridding the entire
342  // pipeline. This mechanism allows target options to inherit a standard pass's
343  // user interface. For example, a target may disable a standard pass by
344  // default by substituting a pass ID of zero, and the user may still enable
345  // that standard pass with an explicit command line option.
347 
348  /// Store the pairs of <AnalysisID, AnalysisID> of which the second pass
349  /// is inserted after each instance of the first one.
351 };
352 
353 } // end namespace llvm
354 
355 // Out of line virtual method.
357  delete Impl;
358 }
359 
361  if (PassName.empty())
362  return nullptr;
363 
365  const PassInfo *PI = PR.getPassInfo(PassName);
366  if (!PI)
368  Twine("\" pass is not registered."));
369  return PI;
370 }
371 
373  const PassInfo *PI = getPassInfo(PassName);
374  return PI ? PI->getTypeInfo() : nullptr;
375 }
376 
377 static std::pair<StringRef, unsigned>
379  StringRef Name, InstanceNumStr;
380  std::tie(Name, InstanceNumStr) = PassName.split(',');
381 
382  unsigned InstanceNum = 0;
383  if (!InstanceNumStr.empty() && InstanceNumStr.getAsInteger(10, InstanceNum))
384  report_fatal_error("invalid pass instance specifier " + PassName);
385 
386  return std::make_pair(Name, InstanceNum);
387 }
388 
389 void TargetPassConfig::setStartStopPasses() {
390  StringRef StartBeforeName;
391  std::tie(StartBeforeName, StartBeforeInstanceNum) =
393 
394  StringRef StartAfterName;
395  std::tie(StartAfterName, StartAfterInstanceNum) =
397 
398  StringRef StopBeforeName;
399  std::tie(StopBeforeName, StopBeforeInstanceNum)
401 
402  StringRef StopAfterName;
403  std::tie(StopAfterName, StopAfterInstanceNum)
405 
406  StartBefore = getPassIDFromName(StartBeforeName);
407  StartAfter = getPassIDFromName(StartAfterName);
408  StopBefore = getPassIDFromName(StopBeforeName);
409  StopAfter = getPassIDFromName(StopAfterName);
410  if (StartBefore && StartAfter)
412  Twine(StartAfterOptName) + Twine(" specified!"));
413  if (StopBefore && StopAfter)
415  Twine(StopAfterOptName) + Twine(" specified!"));
416  Started = (StartAfter == nullptr) && (StartBefore == nullptr);
417 }
418 
421 
422 #define SET_OPTION(Option) \
423  if (Option.getNumOccurrences()) \
424  Opt.Option = Option;
425 
432 
433 #define SET_BOOLEAN_OPTION(Option) Opt.Option = Option;
434 
449 
450  return Opt;
451 }
452 
454  LLVMTargetMachine &LLVMTM) {
455  StringRef StartBefore;
456  StringRef StartAfter;
457  StringRef StopBefore;
458  StringRef StopAfter;
459 
460  unsigned StartBeforeInstanceNum = 0;
461  unsigned StartAfterInstanceNum = 0;
462  unsigned StopBeforeInstanceNum = 0;
463  unsigned StopAfterInstanceNum = 0;
464 
465  std::tie(StartBefore, StartBeforeInstanceNum) =
467  std::tie(StartAfter, StartAfterInstanceNum) =
469  std::tie(StopBefore, StopBeforeInstanceNum) =
471  std::tie(StopAfter, StopAfterInstanceNum) =
473 
474  if (StartBefore.empty() && StartAfter.empty() && StopBefore.empty() &&
475  StopAfter.empty())
476  return;
477 
478  std::tie(StartBefore, std::ignore) =
479  LLVMTM.getPassNameFromLegacyName(StartBefore);
480  std::tie(StartAfter, std::ignore) =
481  LLVMTM.getPassNameFromLegacyName(StartAfter);
482  std::tie(StopBefore, std::ignore) =
483  LLVMTM.getPassNameFromLegacyName(StopBefore);
484  std::tie(StopAfter, std::ignore) =
485  LLVMTM.getPassNameFromLegacyName(StopAfter);
486  if (!StartBefore.empty() && !StartAfter.empty())
488  Twine(StartAfterOptName) + Twine(" specified!"));
489  if (!StopBefore.empty() && !StopAfter.empty())
491  Twine(StopAfterOptName) + Twine(" specified!"));
492 
494  [=, EnableCurrent = StartBefore.empty() && StartAfter.empty(),
495  EnableNext = Optional<bool>(), StartBeforeCount = 0u,
496  StartAfterCount = 0u, StopBeforeCount = 0u,
497  StopAfterCount = 0u](StringRef P, Any) mutable {
498  bool StartBeforePass = !StartBefore.empty() && P.contains(StartBefore);
499  bool StartAfterPass = !StartAfter.empty() && P.contains(StartAfter);
500  bool StopBeforePass = !StopBefore.empty() && P.contains(StopBefore);
501  bool StopAfterPass = !StopAfter.empty() && P.contains(StopAfter);
502 
503  // Implement -start-after/-stop-after
504  if (EnableNext) {
505  EnableCurrent = *EnableNext;
506  EnableNext.reset();
507  }
508 
509  // Using PIC.registerAfterPassCallback won't work because if this
510  // callback returns false, AfterPassCallback is also skipped.
511  if (StartAfterPass && StartAfterCount++ == StartAfterInstanceNum) {
512  assert(!EnableNext && "Error: assign to EnableNext more than once");
513  EnableNext = true;
514  }
515  if (StopAfterPass && StopAfterCount++ == StopAfterInstanceNum) {
516  assert(!EnableNext && "Error: assign to EnableNext more than once");
517  EnableNext = false;
518  }
519 
520  if (StartBeforePass && StartBeforeCount++ == StartBeforeInstanceNum)
521  EnableCurrent = true;
522  if (StopBeforePass && StopBeforeCount++ == StopBeforeInstanceNum)
523  EnableCurrent = false;
524  return EnableCurrent;
525  });
526 }
527 
529  LLVMTargetMachine &LLVMTM) {
530 
531  // Register a callback for disabling passes.
533 
534 #define DISABLE_PASS(Option, Name) \
535  if (Option && P.contains(#Name)) \
536  return false;
537  DISABLE_PASS(DisableBlockPlacement, MachineBlockPlacementPass)
538  DISABLE_PASS(DisableBranchFold, BranchFolderPass)
539  DISABLE_PASS(DisableCopyProp, MachineCopyPropagationPass)
540  DISABLE_PASS(DisableEarlyIfConversion, EarlyIfConverterPass)
541  DISABLE_PASS(DisableEarlyTailDup, EarlyTailDuplicatePass)
542  DISABLE_PASS(DisableMachineCSE, MachineCSEPass)
543  DISABLE_PASS(DisableMachineDCE, DeadMachineInstructionElimPass)
544  DISABLE_PASS(DisableMachineLICM, EarlyMachineLICMPass)
545  DISABLE_PASS(DisableMachineSink, MachineSinkingPass)
546  DISABLE_PASS(DisablePostRAMachineLICM, MachineLICMPass)
547  DISABLE_PASS(DisablePostRAMachineSink, PostRAMachineSinkingPass)
548  DISABLE_PASS(DisablePostRASched, PostRASchedulerPass)
549  DISABLE_PASS(DisableSSC, StackSlotColoringPass)
550  DISABLE_PASS(DisableTailDuplicate, TailDuplicatePass)
551 
552  return true;
553  });
554 
555  registerPartialPipelineCallback(PIC, LLVMTM);
556 }
557 
558 // Out of line constructor provides default values for pass options and
559 // registers all common codegen passes.
560 TargetPassConfig::TargetPassConfig(LLVMTargetMachine &TM, PassManagerBase &pm)
561  : ImmutablePass(ID), PM(&pm), TM(&TM) {
562  Impl = new PassConfigImpl();
563 
564  // Register all target independent codegen passes to activate their PassIDs,
565  // including this pass itself.
567 
568  // Also register alias analysis passes required by codegen passes.
571 
574  else {
575  // If not explicitly specified, use target default.
577  }
578 
579  if (TM.Options.EnableIPRA)
581 
582  if (EnableGlobalISelAbort.getNumOccurrences())
584 
585  setStartStopPasses();
586 }
587 
589  return TM->getOptLevel();
590 }
591 
592 /// Insert InsertedPassID pass after TargetPassID.
594  IdentifyingPassPtr InsertedPassID,
595  bool VerifyAfter) {
596  assert(((!InsertedPassID.isInstance() &&
597  TargetPassID != InsertedPassID.getID()) ||
598  (InsertedPassID.isInstance() &&
599  TargetPassID != InsertedPassID.getInstance()->getPassID())) &&
600  "Insert a pass after itself!");
601  Impl->InsertedPasses.emplace_back(TargetPassID, InsertedPassID, VerifyAfter);
602 }
603 
604 /// createPassConfig - Create a pass configuration object to be used by
605 /// addPassToEmitX methods for generating a pipeline of CodeGen passes.
606 ///
607 /// Targets may override this to extend TargetPassConfig.
609  return new TargetPassConfig(*this, PM);
610 }
611 
613  : ImmutablePass(ID) {
614  report_fatal_error("Trying to construct TargetPassConfig without a target "
615  "machine. Scheduling a CodeGen pass without a target "
616  "triple set?");
617 }
618 
620  return StopBeforeOpt.empty() && StopAfterOpt.empty();
621 }
622 
624  return !StartBeforeOpt.empty() || !StartAfterOpt.empty() ||
626 }
627 
628 std::string
631  return std::string();
632  std::string Res;
633  static cl::opt<std::string> *PassNames[] = {&StartAfterOpt, &StartBeforeOpt,
635  static const char *OptNames[] = {StartAfterOptName, StartBeforeOptName,
637  bool IsFirst = true;
638  for (int Idx = 0; Idx < 4; ++Idx)
639  if (!PassNames[Idx]->empty()) {
640  if (!IsFirst)
641  Res += Separator;
642  IsFirst = false;
643  Res += OptNames[Idx];
644  }
645  return Res;
646 }
647 
648 // Helper to verify the analysis is really immutable.
649 void TargetPassConfig::setOpt(bool &Opt, bool Val) {
650  assert(!Initialized && "PassConfig is immutable");
651  Opt = Val;
652 }
653 
655  IdentifyingPassPtr TargetID) {
656  Impl->TargetPasses[StandardID] = TargetID;
657 }
658 
661  I = Impl->TargetPasses.find(ID);
662  if (I == Impl->TargetPasses.end())
663  return ID;
664  return I->second;
665 }
666 
669  IdentifyingPassPtr FinalPtr = overridePass(ID, TargetID);
670  return !FinalPtr.isValid() || FinalPtr.isInstance() ||
671  FinalPtr.getID() != ID;
672 }
673 
674 /// Add a pass to the PassManager if that pass is supposed to be run. If the
675 /// Started/Stopped flags indicate either that the compilation should start at
676 /// a later pass or that it should stop after an earlier pass, then do not add
677 /// the pass. Finally, compare the current pass against the StartAfter
678 /// and StopAfter options and change the Started/Stopped flags accordingly.
679 void TargetPassConfig::addPass(Pass *P, bool verifyAfter) {
680  assert(!Initialized && "PassConfig is immutable");
681 
682  // Cache the Pass ID here in case the pass manager finds this pass is
683  // redundant with ones already scheduled / available, and deletes it.
684  // Fundamentally, once we add the pass to the manager, we no longer own it
685  // and shouldn't reference it.
686  AnalysisID PassID = P->getPassID();
687 
688  if (StartBefore == PassID && StartBeforeCount++ == StartBeforeInstanceNum)
689  Started = true;
690  if (StopBefore == PassID && StopBeforeCount++ == StopBeforeInstanceNum)
691  Stopped = true;
692  if (Started && !Stopped) {
693  if (AddingMachinePasses)
695  std::string Banner;
696  // Construct banner message before PM->add() as that may delete the pass.
697  if (AddingMachinePasses && verifyAfter)
698  Banner = std::string("After ") + std::string(P->getPassName());
699  PM->add(P);
700  if (AddingMachinePasses)
701  addMachinePostPasses(Banner, /*AllowVerify*/ verifyAfter);
702 
703  // Add the passes after the pass P if there is any.
704  for (const auto &IP : Impl->InsertedPasses) {
705  if (IP.TargetPassID == PassID)
706  addPass(IP.getInsertedPass(), IP.VerifyAfter);
707  }
708  } else {
709  delete P;
710  }
711 
712  if (StopAfter == PassID && StopAfterCount++ == StopAfterInstanceNum)
713  Stopped = true;
714 
715  if (StartAfter == PassID && StartAfterCount++ == StartAfterInstanceNum)
716  Started = true;
717  if (Stopped && !Started)
718  report_fatal_error("Cannot stop compilation after pass that is not run");
719 }
720 
721 /// Add a CodeGen pass at this point in the pipeline after checking for target
722 /// and command line overrides.
723 ///
724 /// addPass cannot return a pointer to the pass instance because is internal the
725 /// PassManager and the instance we create here may already be freed.
727  IdentifyingPassPtr TargetID = getPassSubstitution(PassID);
728  IdentifyingPassPtr FinalPtr = overridePass(PassID, TargetID);
729  if (!FinalPtr.isValid())
730  return nullptr;
731 
732  Pass *P;
733  if (FinalPtr.isInstance())
734  P = FinalPtr.getInstance();
735  else {
736  P = Pass::createPass(FinalPtr.getID());
737  if (!P)
738  llvm_unreachable("Pass ID not registered");
739  }
740  AnalysisID FinalID = P->getPassID();
741  addPass(P, verifyAfter); // Ends the lifetime of P.
742 
743  return FinalID;
744 }
745 
746 void TargetPassConfig::printAndVerify(const std::string &Banner) {
747  addPrintPass(Banner);
748  addVerifyPass(Banner);
749 }
750 
751 void TargetPassConfig::addPrintPass(const std::string &Banner) {
752  if (PrintAfterISel)
753  PM->add(createMachineFunctionPrinterPass(dbgs(), Banner));
754 }
755 
756 void TargetPassConfig::addVerifyPass(const std::string &Banner) {
758 #ifdef EXPENSIVE_CHECKS
761 #endif
762  if (Verify)
763  PM->add(createMachineVerifierPass(Banner));
764 }
765 
768 }
769 
771  PM->add(createStripDebugMachineModulePass(/*OnlyDebugified=*/true));
772 }
773 
776 }
777 
778 void TargetPassConfig::addMachinePrePasses(bool AllowDebugify) {
779  if (AllowDebugify && DebugifyIsSafe &&
782  addDebugifyPass();
783 }
784 
785 void TargetPassConfig::addMachinePostPasses(const std::string &Banner,
786  bool AllowVerify, bool AllowStrip) {
787  if (DebugifyIsSafe) {
791  } else if (DebugifyAndStripAll == cl::BOU_TRUE)
793  }
794  if (AllowVerify)
795  addVerifyPass(Banner);
796 }
797 
798 /// Add common target configurable passes that perform LLVM IR to IR transforms
799 /// following machine independent optimization.
801  // Before running any passes, run the verifier to determine if the input
802  // coming from the front-end and/or optimizer is valid.
803  if (!DisableVerify)
805 
806  if (getOptLevel() != CodeGenOpt::None) {
807  switch (UseCFLAA) {
810  break;
811  case CFLAAType::Andersen:
813  break;
814  case CFLAAType::Both:
817  break;
818  default:
819  break;
820  }
821 
822  // Basic AliasAnalysis support.
823  // Add TypeBasedAliasAnalysis before BasicAliasAnalysis so that
824  // BasicAliasAnalysis wins if they disagree. This is intended to help
825  // support "obvious" type-punning idioms.
829 
830  // Run loop strength reduction before anything else.
831  if (!DisableLSR) {
834  if (PrintLSR)
836  "\n\n*** Code after LSR ***\n"));
837  }
838 
839  // The MergeICmpsPass tries to create memcmp calls by grouping sequences of
840  // loads and compares. ExpandMemCmpPass then tries to expand those calls
841  // into optimally-sized loads and compares. The transforms are enabled by a
842  // target lowering hook.
843  if (!DisableMergeICmps)
846  }
847 
848  // Run GC lowering passes for builtin collectors
849  // TODO: add a pass insertion point here
853 
854  // Make sure that no unreachable blocks are instruction selected.
856 
857  // Prepare expensive constants for SelectionDAG.
860 
861  if (getOptLevel() != CodeGenOpt::None)
863 
866 
867  // Expand vector predication intrinsics into standard IR instructions.
868  // This pass has to run before ScalarizeMaskedMemIntrin and ExpandReduction
869  // passes since it emits those kinds of intrinsics.
871 
872  // Add scalarization of target's unsupported masked memory intrinsics pass.
873  // the unsupported intrinsic will be replaced with a chain of basic blocks,
874  // that stores/loads element one-by-one if the appropriate mask bit is set.
876 
877  // Expand reduction intrinsics into shuffle sequences if the target wants to.
878  // Allow disabling it for testing purposes.
881 }
882 
883 /// Turn exception handling constructs into something the code generators can
884 /// handle.
886  const MCAsmInfo *MCAI = TM->getMCAsmInfo();
887  assert(MCAI && "No MCAsmInfo");
888  switch (MCAI->getExceptionHandlingType()) {
890  // SjLj piggy-backs on dwarf for this bit. The cleanups done apply to both
891  // Dwarf EH prepare needs to be run after SjLj prepare. Otherwise,
892  // catch info can get misplaced when a selector ends up more than one block
893  // removed from the parent invoke(s). This could happen when a landing
894  // pad is shared by multiple invokes and is also a target of a normal
895  // edge from elsewhere.
902  break;
904  // We support using both GCC-style and MSVC-style exceptions on Windows, so
905  // add both preparation passes. Each pass will only actually run if it
906  // recognizes the personality function.
909  break;
911  // Wasm EH uses Windows EH instructions, but it does not need to demote PHIs
912  // on catchpads and cleanuppads because it does not outline them into
913  // funclets. Catchswitch blocks are not lowered in SelectionDAG, so we
914  // should remove PHIs there.
915  addPass(createWinEHPass(/*DemoteCatchSwitchPHIOnly=*/false));
917  break;
920 
921  // The lower invoke pass may create unreachable code. Remove it.
923  break;
924  }
925 }
926 
927 /// Add pass to prepare the LLVM IR for code generation. This should be done
928 /// before exception handling preparation passes.
933 }
934 
935 /// Add common passes that perform LLVM IR to IR transforms in preparation for
936 /// instruction selection.
938  addPreISel();
939 
940  // Force codegen to run according to the callgraph.
942  addPass(new DummyCGSCCPass);
943 
944  // Add both the safe stack and the stack protection passes: each of them will
945  // only protect functions that have corresponding attributes.
948 
949  if (PrintISelInput)
951  dbgs(), "\n\n*** Final LLVM Code input to ISel ***\n"));
952 
953  // All passes which modify the LLVM IR are now complete; run the verifier
954  // to ensure that the IR is valid.
955  if (!DisableVerify)
957 }
958 
960  // Enable FastISel with -fast-isel, but allow that to be overridden.
962 
963  // Determine an instruction selector.
964  enum class SelectorType { SelectionDAG, FastISel, GlobalISel };
965  SelectorType Selector;
966 
968  Selector = SelectorType::FastISel;
969  else if (EnableGlobalISelOption == cl::BOU_TRUE ||
972  Selector = SelectorType::GlobalISel;
973  else if (TM->getOptLevel() == CodeGenOpt::None && TM->getO0WantsFastISel())
974  Selector = SelectorType::FastISel;
975  else
976  Selector = SelectorType::SelectionDAG;
977 
978  // Set consistently TM->Options.EnableFastISel and EnableGlobalISel.
979  if (Selector == SelectorType::FastISel) {
980  TM->setFastISel(true);
981  TM->setGlobalISel(false);
982  } else if (Selector == SelectorType::GlobalISel) {
983  TM->setFastISel(false);
984  TM->setGlobalISel(true);
985  }
986 
987  // FIXME: Injecting into the DAGISel pipeline seems to cause issues with
988  // analyses needing to be re-run. This can result in being unable to
989  // schedule passes (particularly with 'Function Alias Analysis
990  // Results'). It's not entirely clear why but AFAICT this seems to be
991  // due to one FunctionPassManager not being able to use analyses from a
992  // previous one. As we're injecting a ModulePass we break the usual
993  // pass manager into two. GlobalISel with the fallback path disabled
994  // and -run-pass seem to be unaffected. The majority of GlobalISel
995  // testing uses -run-pass so this probably isn't too bad.
996  SaveAndRestore<bool> SavedDebugifyIsSafe(DebugifyIsSafe);
997  if (Selector != SelectorType::GlobalISel || !isGlobalISelAbortEnabled())
998  DebugifyIsSafe = false;
999 
1000  // Add instruction selector passes.
1001  if (Selector == SelectorType::GlobalISel) {
1002  SaveAndRestore<bool> SavedAddingMachinePasses(AddingMachinePasses, true);
1003  if (addIRTranslator())
1004  return true;
1005 
1007 
1008  if (addLegalizeMachineIR())
1009  return true;
1010 
1011  // Before running the register bank selector, ask the target if it
1012  // wants to run some passes.
1014 
1015  if (addRegBankSelect())
1016  return true;
1017 
1019 
1021  return true;
1022 
1023  // Pass to reset the MachineFunction if the ISel failed.
1026 
1027  // Provide a fallback path when we do not want to abort on
1028  // not-yet-supported input.
1030  return true;
1031 
1032  } else if (addInstSelector())
1033  return true;
1034 
1035  // Expand pseudo-instructions emitted by ISel. Don't run the verifier before
1036  // FinalizeISel.
1038 
1039  // Print the instruction selected machine code...
1040  printAndVerify("After Instruction Selection");
1041 
1042  return false;
1043 }
1044 
1046  if (TM->useEmulatedTLS())
1048 
1051  addIRPasses();
1054  addISelPrepare();
1055 
1056  return addCoreISelPasses();
1057 }
1058 
1059 /// -regalloc=... command line option.
1060 static FunctionPass *useDefaultRegisterAllocator() { return nullptr; }
1064  cl::desc("Register allocator to use"));
1065 
1066 /// Add the complete set of target-independent postISel code generator passes.
1067 ///
1068 /// This can be read as the standard order of major LLVM CodeGen stages. Stages
1069 /// with nontrivial configuration or multiple passes are broken out below in
1070 /// add%Stage routines.
1071 ///
1072 /// Any TargetPassConfig::addXX routine may be overriden by the Target. The
1073 /// addPre/Post methods with empty header implementations allow injecting
1074 /// target-specific fixups just before or after major stages. Additionally,
1075 /// targets have the flexibility to change pass order within a stage by
1076 /// overriding default implementation of add%Stage routines below. Each
1077 /// technique has maintainability tradeoffs because alternate pass orders are
1078 /// not well supported. addPre/Post works better if the target pass is easily
1079 /// tied to a common pass. But if it has subtle dependencies on multiple passes,
1080 /// the target should override the stage instead.
1081 ///
1082 /// TODO: We could use a single addPre/Post(ID) hook to allow pass injection
1083 /// before/after any target-independent pass. But it's currently overkill.
1085  AddingMachinePasses = true;
1086 
1087  // Add passes that optimize machine instructions in SSA form.
1088  if (getOptLevel() != CodeGenOpt::None) {
1090  } else {
1091  // If the target requests it, assign local variables to stack slots relative
1092  // to one another and simplify frame index references where possible.
1094  }
1095 
1096  if (TM->Options.EnableIPRA)
1098 
1099  // Run pre-ra passes.
1100  addPreRegAlloc();
1101 
1102  // Debugifying the register allocator passes seems to provoke some
1103  // non-determinism that affects CodeGen and there doesn't seem to be a point
1104  // where it becomes safe again so stop debugifying here.
1105  DebugifyIsSafe = false;
1106 
1107  // Run register allocation and passes that are tightly coupled with it,
1108  // including phi elimination and scheduling.
1109  if (getOptimizeRegAlloc())
1111  else
1112  addFastRegAlloc();
1113 
1114  // Run post-ra passes.
1115  addPostRegAlloc();
1116 
1118 
1119  // Insert prolog/epilog code. Eliminate abstract frame index references...
1120  if (getOptLevel() != CodeGenOpt::None) {
1123  }
1124 
1125  // Prolog/Epilog inserter needs a TargetMachine to instantiate. But only
1126  // do so if it hasn't been disabled, substituted, or overridden.
1129 
1130  /// Add passes that optimize machine instructions after register allocation.
1131  if (getOptLevel() != CodeGenOpt::None)
1133 
1134  // Expand pseudo instructions before second scheduling pass.
1136 
1137  // Run pre-sched2 passes.
1138  addPreSched2();
1139 
1142 
1143  // Second pass scheduler.
1144  // Let Target optionally insert this pass by itself at some other
1145  // point.
1146  if (getOptLevel() != CodeGenOpt::None &&
1148  if (MISchedPostRA)
1150  else
1152  }
1153 
1154  // GC
1155  if (addGCPasses()) {
1156  if (PrintGCInfo)
1157  addPass(createGCInfoPrinter(dbgs()), false);
1158  }
1159 
1160  // Basic block placement.
1161  if (getOptLevel() != CodeGenOpt::None)
1163 
1164  // Insert before XRay Instrumentation.
1166 
1169 
1170  addPreEmitPass();
1171 
1172  if (TM->Options.EnableIPRA)
1173  // Collect register usage information and produce a register mask of
1174  // clobbered registers, to be used to optimize call sites.
1176 
1177  // FIXME: Some backends are incompatible with running the verifier after
1178  // addPreEmitPass. Maybe only pass "false" here for those targets?
1179  addPass(&FuncletLayoutID, false);
1180 
1181  addPass(&StackMapLivenessID, false);
1182  addPass(&LiveDebugValuesID, false);
1183 
1186  bool RunOnAllFunctions =
1188  bool AddOutliner =
1189  RunOnAllFunctions || TM->Options.SupportsDefaultOutlining;
1190  if (AddOutliner)
1191  addPass(createMachineOutlinerPass(RunOnAllFunctions));
1192  }
1193 
1194  // Machine function splitter uses the basic block sections feature. Both
1195  // cannot be enabled at the same time. Basic block sections takes precedence.
1196  // FIXME: In principle, BasicBlockSection::Labels and splitting can used
1197  // together. Update this check once we have addressed any issues.
1203  }
1204 
1205  // Add passes that directly emit MI after all other MI passes.
1206  addPreEmitPass2();
1207 
1208  // Insert pseudo probe annotation for callsite profiling
1211 
1212  AddingMachinePasses = false;
1213 }
1214 
1215 /// Add passes that optimize machine instructions in SSA form.
1217  // Pre-ra tail duplication.
1219 
1220  // Optimize PHIs before DCE: removing dead PHI cycles may make more
1221  // instructions dead.
1223 
1224  // This pass merges large allocas. StackSlotColoring is a different pass
1225  // which merges spill slots.
1227 
1228  // If the target requests it, assign local variables to stack slots relative
1229  // to one another and simplify frame index references where possible.
1231 
1232  // With optimization, dead code should already be eliminated. However
1233  // there is one known exception: lowered code for arguments that are only
1234  // used by tail calls, where the tail calls reuse the incoming stack
1235  // arguments directly (see t11 in test/CodeGen/X86/sibcall.ll).
1237 
1238  // Allow targets to insert passes that improve instruction level parallelism,
1239  // like if-conversion. Such passes will typically need dominator trees and
1240  // loop info, just like LICM and CSE below.
1241  addILPOpts();
1242 
1245 
1247 
1249  // Clean-up the dead code that may have been generated by peephole
1250  // rewriting.
1252 }
1253 
1254 //===---------------------------------------------------------------------===//
1255 /// Register Allocation Pass Configuration
1256 //===---------------------------------------------------------------------===//
1257 
1259  switch (OptimizeRegAlloc) {
1260  case cl::BOU_UNSET: return getOptLevel() != CodeGenOpt::None;
1261  case cl::BOU_TRUE: return true;
1262  case cl::BOU_FALSE: return false;
1263  }
1264  llvm_unreachable("Invalid optimize-regalloc state");
1265 }
1266 
1267 /// A dummy default pass factory indicates whether the register allocator is
1268 /// overridden on the command line.
1270 
1271 static RegisterRegAlloc
1272 defaultRegAlloc("default",
1273  "pick register allocator based on -O option",
1275 
1279 }
1280 
1281 /// Instantiate the default register allocator pass for this target for either
1282 /// the optimized or unoptimized allocation path. This will be added to the pass
1283 /// manager by addFastRegAlloc in the unoptimized case or addOptimizedRegAlloc
1284 /// in the optimized case.
1285 ///
1286 /// A target that uses the standard regalloc pass order for fast or optimized
1287 /// allocation may still override this for per-target regalloc
1288 /// selection. But -regalloc=... always takes precedence.
1290  if (Optimized)
1292  else
1293  return createFastRegisterAllocator();
1294 }
1295 
1296 /// Find and instantiate the register allocation pass requested by this target
1297 /// at the current optimization level. Different register allocators are
1298 /// defined as separate passes because they may require different analysis.
1299 ///
1300 /// This helper ensures that the regalloc= option is always available,
1301 /// even for targets that override the default allocator.
1302 ///
1303 /// FIXME: When MachinePassRegistry register pass IDs instead of function ptrs,
1304 /// this can be folded into addPass.
1306  // Initialize the global default.
1309 
1311  if (Ctor != useDefaultRegisterAllocator)
1312  return Ctor();
1313 
1314  // With no -regalloc= override, ask the target for a regalloc pass.
1315  return createTargetRegisterAllocator(Optimized);
1316 }
1317 
1321  report_fatal_error("Must use fast (default) register allocator for unoptimized regalloc.");
1322 
1323  addPass(createRegAllocPass(false));
1324 
1325  // Allow targets to change the register assignments after
1326  // fast register allocation.
1328  return true;
1329 }
1330 
1332  // Add the selected register allocation pass.
1333  addPass(createRegAllocPass(true));
1334 
1335  // Allow targets to change the register assignments before rewriting.
1336  addPreRewrite();
1337 
1338  // Finally rewrite virtual registers.
1340 
1341  return true;
1342 }
1343 
1344 /// Return true if the default global register allocator is in use and
1345 /// has not be overriden on the command line with '-regalloc=...'
1347  return RegAlloc.getNumOccurrences() == 0;
1348 }
1349 
1350 /// Add the minimum set of target-independent passes that are required for
1351 /// register allocation. No coalescing or scheduling.
1353  addPass(&PHIEliminationID, false);
1355 
1357 }
1358 
1359 /// Add standard target-independent passes that are tightly coupled with
1360 /// optimized register allocation, including coalescing, machine instruction
1361 /// scheduling, and register allocation itself.
1363  addPass(&DetectDeadLanesID, false);
1364 
1365  addPass(&ProcessImplicitDefsID, false);
1366 
1367  // LiveVariables currently requires pure SSA form.
1368  //
1369  // FIXME: Once TwoAddressInstruction pass no longer uses kill flags,
1370  // LiveVariables can be removed completely, and LiveIntervals can be directly
1371  // computed. (We still either need to regenerate kill flags after regalloc, or
1372  // preferably fix the scavenger to not depend on them).
1373  // FIXME: UnreachableMachineBlockElim is a dependant pass of LiveVariables.
1374  // When LiveVariables is removed this has to be removed/moved either.
1375  // Explicit addition of UnreachableMachineBlockElim allows stopping before or
1376  // after it with -stop-before/-stop-after.
1378  addPass(&LiveVariablesID, false);
1379 
1380  // Edge splitting is smarter with machine loop info.
1381  addPass(&MachineLoopInfoID, false);
1382  addPass(&PHIEliminationID, false);
1383 
1384  // Eventually, we want to run LiveIntervals before PHI elimination.
1385  if (EarlyLiveIntervals)
1386  addPass(&LiveIntervalsID, false);
1387 
1390 
1391  // The machine scheduler may accidentally create disconnected components
1392  // when moving subregister definitions around, avoid this by splitting them to
1393  // separate vregs before. Splitting can also improve reg. allocation quality.
1395 
1396  // PreRA instruction scheduling.
1398 
1400  // Perform stack slot coloring and post-ra machine LICM.
1401  //
1402  // FIXME: Re-enable coloring with register when it's capable of adding
1403  // kill markers.
1405 
1406  // Allow targets to expand pseudo instructions depending on the choice of
1407  // registers before MachineCopyPropagation.
1408  addPostRewrite();
1409 
1410  // Copy propagate to forward register uses and try to eliminate COPYs that
1411  // were not coalesced.
1413 
1414  // Run post-ra machine LICM to hoist reloads / remats.
1415  //
1416  // FIXME: can this move into MachineLateOptimization?
1418  }
1419 }
1420 
1421 //===---------------------------------------------------------------------===//
1422 /// Post RegAlloc Pass Configuration
1423 //===---------------------------------------------------------------------===//
1424 
1425 /// Add passes that optimize machine instructions after register allocation.
1427  // Branch folding must be run after regalloc and prolog/epilog insertion.
1429 
1430  // Tail duplication.
1431  // Note that duplicating tail just increases code size and degrades
1432  // performance for targets that require Structured Control Flow.
1433  // In addition it can also make CFG irreducible. Thus we disable it.
1434  if (!TM->requiresStructuredCFG())
1436 
1437  // Copy propagation.
1439 }
1440 
1441 /// Add standard GC passes.
1444  return true;
1445 }
1446 
1447 /// Add standard basic block placement passes.
1450  // Run a separate pass to collect block placement statistics.
1453  }
1454 }
1455 
1456 //===---------------------------------------------------------------------===//
1457 /// GlobalISel Configuration
1458 //===---------------------------------------------------------------------===//
1461 }
1462 
1465 }
1466 
1468  return true;
1469 }
1470 
1471 std::unique_ptr<CSEConfigBase> TargetPassConfig::getCSEConfig() const {
1472  return std::make_unique<CSEConfigBase>();
1473 }
DisableCGP
static cl::opt< bool > DisableCGP("disable-cgp", cl::Hidden, cl::desc("Disable Codegen Prepare"))
DisableMachineSink
static cl::opt< bool > DisableMachineSink("disable-machine-sink", cl::Hidden, cl::desc("Disable Machine Sinking"))
llvm::TargetMachine::requiresStructuredCFG
bool requiresStructuredCFG() const
Definition: TargetMachine.h:213
llvm::TargetPassConfig::addPostRegAlloc
virtual void addPostRegAlloc()
This method may be implemented by targets that want to run passes after register allocation pass pipe...
Definition: TargetPassConfig.h:419
TypeBasedAliasAnalysis.h
SymbolRewriter.h
llvm::TargetMachine::getOptLevel
CodeGenOpt::Level getOptLevel() const
Returns the optimization level: None, Less, Default, or Aggressive.
Definition: TargetMachine.cpp:198
llvm::TargetPassConfig::ID
static char ID
Definition: TargetPassConfig.h:148
EnableMachineOutliner
static cl::opt< RunOutliner > EnableMachineOutliner("enable-machine-outliner", cl::desc("Enable the machine outliner"), cl::Hidden, cl::ValueOptional, cl::init(RunOutliner::TargetDefault), cl::values(clEnumValN(RunOutliner::AlwaysOutline, "always", "Run on all functions guaranteed to be beneficial"), clEnumValN(RunOutliner::NeverOutline, "never", "Disable all outlining"), clEnumValN(RunOutliner::AlwaysOutline, "", "")))
llvm::createFastRegisterAllocator
FunctionPass * createFastRegisterAllocator()
FastRegisterAllocation Pass - This pass register allocates as fast as possible.
Definition: RegAllocFast.cpp:1553
llvm::createCheckDebugMachineModulePass
ModulePass * createCheckDebugMachineModulePass()
Creates MIR Check Debug pass.
Definition: MachineCheckDebugify.cpp:124
llvm::RegisterRegAllocBase< RegisterRegAlloc >::setDefault
static void setDefault(FunctionPassCtor C)
Definition: RegAllocRegistry.h:53
DebugifyAndStripAll
static cl::opt< cl::boolOrDefault > DebugifyAndStripAll("debugify-and-strip-all-safe", cl::Hidden, cl::desc("Debugify MIR before and Strip debug after " "each pass except those known to be unsafe when debug info is present"), cl::ZeroOrMore)
llvm::PassInfo::getTypeInfo
const void * getTypeInfo() const
getTypeInfo - Return the id object for the pass...
Definition: PassInfo.h:71
llvm::OptimizePHIsID
char & OptimizePHIsID
OptimizePHIs - This pass optimizes machine instruction PHIs to take advantage of opportunities create...
Definition: OptimizePHIs.cpp:69
llvm::createLowerInvokePass
FunctionPass * createLowerInvokePass()
Definition: LowerInvoke.cpp:87
llvm
Definition: AllocatorList.h:23
llvm::createGreedyRegisterAllocator
FunctionPass * createGreedyRegisterAllocator()
Greedy register allocation pass - This pass implements a global register allocator for optimized buil...
Definition: RegAllocGreedy.cpp:635
llvm::StringRef::empty
LLVM_NODISCARD bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:156
llvm::SystemZISD::TM
@ TM
Definition: SystemZISelLowering.h:65
llvm::TargetMachine::useEmulatedTLS
bool useEmulatedTLS() const
Returns true if this target uses emulated TLS.
Definition: TargetMachine.cpp:162
MCTargetOptions.h
llvm::createMachineFunctionSplitterPass
MachineFunctionPass * createMachineFunctionSplitterPass()
createMachineFunctionSplitterPass - This pass splits machine functions using profile information.
llvm::PeepholeOptimizerID
char & PeepholeOptimizerID
PeepholeOptimizer - This pass performs peephole optimizations - like extension and comparison elimina...
Definition: PeepholeOptimizer.cpp:443
DisableConstantHoisting
static cl::opt< bool > DisableConstantHoisting("disable-constant-hoisting", cl::Hidden, cl::desc("Disable ConstantHoisting"))
llvm::IdentifyingPassPtr::getInstance
Pass * getInstance() const
Definition: TargetPassConfig.h:73
llvm::createCFLAndersAAWrapperPass
ImmutablePass * createCFLAndersAAWrapperPass()
llvm::ImmutablePass
ImmutablePass class - This class is used to provide information that does not need to be run.
Definition: Pass.h:269
Scalar.h
llvm::ExceptionHandling::SjLj
@ SjLj
setjmp/longjmp based exceptions
llvm::TargetPassConfig::willCompleteCodeGenPipeline
static bool willCompleteCodeGenPipeline()
Returns true if none of the -stop-before and -stop-after options is set.
Definition: TargetPassConfig.cpp:619
MachinePassRegistry.h
llvm::TargetMachine::targetSchedulesPostRAScheduling
virtual bool targetSchedulesPostRAScheduling() const
True if subtarget inserts the final scheduling pass on its own.
Definition: TargetMachine.h:369
llvm::Pass::getPassID
AnalysisID getPassID() const
getPassID - Return the PassID number that corresponds to this pass.
Definition: Pass.h:110
StringRef.h
P
This currently compiles esp xmm0 movsd esp eax eax esp ret We should use not the dag combiner This is because dagcombine2 needs to be able to see through the X86ISD::Wrapper which DAGCombine can t really do The code for turning x load into a single vector load is target independent and should be moved to the dag combiner The code for turning x load into a vector load can only handle a direct load from a global or a direct load from the stack It should be generalized to handle any load from P
Definition: README-SSE.txt:411
llvm::cl::BOU_FALSE
@ BOU_FALSE
Definition: CommandLine.h:625
Pass.h
llvm::PHIEliminationID
char & PHIEliminationID
PHIElimination - This pass eliminates machine instruction PHI nodes by inserting copy instructions.
Definition: PHIElimination.cpp:129
INITIALIZE_PASS::InsertedPass::TargetPassID
AnalysisID TargetPassID
Definition: TargetPassConfig.cpp:314
CSEConfigBase.h
llvm::IdentifyingPassPtr::isInstance
bool isInstance() const
Definition: TargetPassConfig.h:66
llvm::MCAsmInfo
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:56
llvm::TargetPassConfig::addStripDebugPass
void addStripDebugPass()
Add a pass to remove debug info from the MIR.
Definition: TargetPassConfig.cpp:770
llvm::SmallVector< InsertedPass, 4 >
llvm::TargetMachine::getO0WantsFastISel
bool getO0WantsFastISel()
Definition: TargetMachine.h:241
llvm::initializeBasicAAWrapperPassPass
void initializeBasicAAWrapperPassPass(PassRegistry &)
EnableFastISelOption
static cl::opt< cl::boolOrDefault > EnableFastISelOption("fast-isel", cl::Hidden, cl::desc("Enable the \"fast\" instruction selector"))
ErrorHandling.h
llvm::TargetPassConfig::addPreLegalizeMachineIR
virtual void addPreLegalizeMachineIR()
This method may be implemented by targets that want to run passes immediately before legalization.
Definition: TargetPassConfig.h:250
EnableMachineFunctionSplitter
static cl::opt< bool > EnableMachineFunctionSplitter("enable-split-machine-functions", cl::Hidden, cl::desc("Split out cold blocks from machine functions based on profile " "information."))
Enable the machine function splitter pass.
llvm::LLVMTargetMachine::createPassConfig
virtual TargetPassConfig * createPassConfig(PassManagerBase &PM)
Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of ...
Definition: TargetPassConfig.cpp:608
llvm::cl::ValueOptional
@ ValueOptional
Definition: CommandLine.h:136
llvm::ExpandPostRAPseudosID
char & ExpandPostRAPseudosID
ExpandPostRAPseudos - This pass expands pseudo instructions after register allocation.
Definition: ExpandPostRAPseudos.cpp:59
llvm::TargetPassConfig::addPreRewrite
virtual bool addPreRewrite()
addPreRewrite - Add passes to the optimized register allocation pipeline after register allocation is...
Definition: TargetPassConfig.h:405
CGPassBuilderOption.h
llvm::TargetPassConfig::createRegAllocPass
virtual FunctionPass * createRegAllocPass(bool Optimized)
addMachinePasses helper to create the target-selected or overriden regalloc pass.
Definition: TargetPassConfig.cpp:1305
llvm::TargetPassConfig::addGCPasses
virtual bool addGCPasses()
addGCPasses - Add late codegen passes that analyze code for garbage collection.
Definition: TargetPassConfig.cpp:1442
llvm::AnalysisID
const void * AnalysisID
Definition: Pass.h:47
llvm::TargetPassConfig::addPostRewrite
virtual void addPostRewrite()
Add passes to be run immediately after virtual registers are rewritten to physical registers.
Definition: TargetPassConfig.h:415
llvm::RunOutliner::TargetDefault
@ TargetDefault
llvm::TargetPassConfig::addPreSched2
virtual void addPreSched2()
This method may be implemented by targets that want to run passes after prolog-epilog insertion and b...
Definition: TargetPassConfig.h:426
llvm::cl::Hidden
@ Hidden
Definition: CommandLine.h:143
DisableTailDuplicate
static cl::opt< bool > DisableTailDuplicate("disable-tail-duplicate", cl::Hidden, cl::desc("Disable tail duplication"))
llvm::PassConfigImpl::InsertedPasses
SmallVector< InsertedPass, 4 > InsertedPasses
Store the pairs of <AnalysisID, AnalysisID> of which the second pass is inserted after each instance ...
Definition: TargetPassConfig.cpp:350
getPassNameAndInstanceNum
static std::pair< StringRef, unsigned > getPassNameAndInstanceNum(StringRef PassName)
Definition: TargetPassConfig.cpp:378
llvm::Pass::createPass
static Pass * createPass(AnalysisID ID)
Definition: Pass.cpp:184
llvm::createPrologEpilogInserterPass
MachineFunctionPass * createPrologEpilogInserterPass()
Definition: PrologEpilogInserter.cpp:155
llvm::DenseMapIterator
Definition: DenseMap.h:56
llvm::PassConfigImpl
Definition: TargetPassConfig.cpp:337
DisableBranchFold
static cl::opt< bool > DisableBranchFold("disable-branch-fold", cl::Hidden, cl::desc("Disable branch folding"))
DenseMap.h
INITIALIZE_PASS::InsertedPass::VerifyAfter
bool VerifyAfter
Definition: TargetPassConfig.cpp:316
llvm::createCFLSteensAAWrapperPass
ImmutablePass * createCFLSteensAAWrapperPass()
MISchedPostRA
static cl::opt< bool > MISchedPostRA("misched-postra", cl::Hidden, cl::desc("Run MachineScheduler post regalloc (independent of preRA sched)"))
llvm::LocalStackSlotAllocationID
char & LocalStackSlotAllocationID
LocalStackSlotAllocation - This pass assigns local frame indices to stack slots relative to one anoth...
Definition: LocalStackSlotAllocation.cpp:109
llvm::CFLAAType::Andersen
@ Andersen
llvm::createGCInfoPrinter
FunctionPass * createGCInfoPrinter(raw_ostream &OS)
Creates a pass to print GC metadata.
Definition: GCMetadata.cpp:92
llvm::LLVMTargetMachine::isMachineVerifierClean
virtual bool isMachineVerifierClean() const
Returns true if the target is expected to pass all machine verifier checks.
Definition: TargetMachine.h:442
llvm::PassInfo
PassInfo class - An instance of this class exists for every pass known by the system,...
Definition: PassInfo.h:30
llvm::UseCFLAA
static cl::opt<::CFLAAType > UseCFLAA("use-cfl-aa", cl::init(::CFLAAType::None), cl::Hidden, cl::desc("Enable the new, experimental CFL alias analysis"), cl::values(clEnumValN(::CFLAAType::None, "none", "Disable CFL-AA"), clEnumValN(::CFLAAType::Steensgaard, "steens", "Enable unification-based CFL-AA"), clEnumValN(::CFLAAType::Andersen, "anders", "Enable inclusion-based CFL-AA"), clEnumValN(::CFLAAType::Both, "both", "Enable both variants of CFL-AA")))
DisableExpandReductions
static cl::opt< bool > DisableExpandReductions("disable-expand-reductions", cl::init(false), cl::Hidden, cl::desc("Disable the expand reduction intrinsics pass from running"))
Disable the expand reductions pass for testing.
llvm::createLoopStrengthReducePass
Pass * createLoopStrengthReducePass()
Definition: LoopStrengthReduce.cpp:6006
llvm::ExceptionHandling::ARM
@ ARM
ARM EHABI.
llvm::Optional< bool >
llvm::RunOutliner::NeverOutline
@ NeverOutline
llvm::IdentifyingPassPtr
Discriminated union of Pass ID types.
Definition: TargetPassConfig.h:53
llvm::CFLAAType::Both
@ Both
getPassInfo
static const PassInfo * getPassInfo(StringRef PassName)
Definition: TargetPassConfig.cpp:360
INITIALIZE_PASS::InsertedPass
Definition: TargetPassConfig.cpp:313
INITIALIZE_PASS::InsertedPass::InsertedPassID
IdentifyingPassPtr InsertedPassID
Definition: TargetPassConfig.cpp:315
llvm::TargetPassConfig::addRegAssignAndRewriteFast
virtual bool addRegAssignAndRewriteFast()
Add core register allocator passes which do the actual register assignment and rewriting.
Definition: TargetPassConfig.cpp:1318
llvm::StackSlotColoringID
char & StackSlotColoringID
StackSlotColoring - This pass performs stack slot coloring.
Definition: StackSlotColoring.cpp:132
llvm::MachineCopyPropagationID
char & MachineCopyPropagationID
MachineCopyPropagation - This pass performs copy propagation on machine instructions.
Definition: MachineCopyPropagation.cpp:308
BasicAliasAnalysis.h
LegacyPassManager.h
llvm::TwoAddressInstructionPassID
char & TwoAddressInstructionPassID
TwoAddressInstruction - This pass reduces two-address instructions to use two operands.
Definition: TwoAddressInstructionPass.cpp:192
llvm::MachineLICMID
char & MachineLICMID
This pass performs loop invariant code motion on machine instructions.
Definition: MachineLICM.cpp:294
llvm::TargetOptions::EnableMachineFunctionSplitter
unsigned EnableMachineFunctionSplitter
Enables the MachineFunctionSplitter pass.
Definition: TargetOptions.h:287
llvm::BasicBlockSection::None
@ None
llvm::createUnreachableBlockEliminationPass
FunctionPass * createUnreachableBlockEliminationPass()
createUnreachableBlockEliminationPass - The LLVM code generator does not work well with unreachable b...
llvm::RegisterRegAlloc
Definition: RegAllocRegistry.h:60
llvm::TargetPassConfig::addPreRegBankSelect
virtual void addPreRegBankSelect()
This method may be implemented by targets that want to run passes immediately before the register ban...
Definition: TargetPassConfig.h:258
llvm::TargetPassConfig::isGISelCSEEnabled
virtual bool isGISelCSEEnabled() const
Check whether continuous CSE should be enabled in GISel passes.
Definition: TargetPassConfig.cpp:1467
llvm::createRewriteSymbolsPass
ModulePass * createRewriteSymbolsPass()
llvm::createExpandMemCmpPass
FunctionPass * createExpandMemCmpPass()
Definition: ExpandMemCmp.cpp:917
PrintISelInput
static cl::opt< bool > PrintISelInput("print-isel-input", cl::Hidden, cl::desc("Print LLVM IR input to isel pass"))
llvm::ExceptionHandling::AIX
@ AIX
AIX Exception Handling.
llvm::dbgs
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
DisablePostRAMachineSink
static cl::opt< bool > DisablePostRAMachineSink("disable-postra-machine-sink", cl::Hidden, cl::desc("Disable PostRA Machine Sinking"))
llvm::TargetPassConfig::addInstSelector
virtual bool addInstSelector()
addInstSelector - This method should install an instruction selector pass, which converts from LLVM c...
Definition: TargetPassConfig.h:240
CommandLine.h
llvm::LiveDebugValuesID
char & LiveDebugValuesID
LiveDebugValues pass.
Definition: LiveDebugValues.cpp:69
llvm::createLowerEmuTLSPass
ModulePass * createLowerEmuTLSPass()
LowerEmuTLS - This pass generates __emutls_[vt].xyz variables for all TLS variables for the emulated ...
llvm::createDwarfEHPass
FunctionPass * createDwarfEHPass(CodeGenOpt::Level OptLevel)
createDwarfEHPass - This pass mulches exception handling code into a form adapted to code generation.
Definition: DwarfEHPrepare.cpp:325
llvm::TargetPassConfig::TM
LLVMTargetMachine * TM
Definition: TargetPassConfig.h:122
llvm::registerCodeGenCallback
void registerCodeGenCallback(PassInstrumentationCallbacks &PIC, LLVMTargetMachine &)
Definition: TargetPassConfig.cpp:528
DisablePostRAMachineLICM
static cl::opt< bool > DisablePostRAMachineLICM("disable-postra-machine-licm", cl::Hidden, cl::desc("Disable Machine LICM"))
TargetMachine.h
llvm::PassRegistry::getPassRegistry
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
Definition: PassRegistry.cpp:31
llvm::SelectionDAG
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:216
llvm::TargetPassConfig::printAndVerify
void printAndVerify(const std::string &Banner)
printAndVerify - Add a pass to dump then verify the machine function, if those steps are enabled.
Definition: TargetPassConfig.cpp:746
llvm::PrologEpilogCodeInserterID
char & PrologEpilogCodeInserterID
PrologEpilogCodeInserter - This pass inserts prolog and epilog code, and eliminates abstract frame re...
Definition: PrologEpilogInserter.cpp:139
llvm::FEntryInserterID
char & FEntryInserterID
This pass inserts FEntry calls.
Definition: FEntryInserter.cpp:51
llvm::createConstantHoistingPass
FunctionPass * createConstantHoistingPass()
Definition: ConstantHoisting.cpp:138
EarlyLiveIntervals
static cl::opt< bool > EarlyLiveIntervals("early-live-intervals", cl::Hidden, cl::desc("Run live interval analysis earlier in the pipeline"))
llvm::TargetPassConfig::substitutePass
void substitutePass(AnalysisID StandardID, IdentifyingPassPtr TargetID)
Allow the target to override a specific pass without overriding the pass pipeline.
Definition: TargetPassConfig.cpp:654
llvm::IdentifyingPassPtr::isValid
bool isValid() const
Definition: TargetPassConfig.h:65
llvm::TargetPassConfig::addVerifyPass
void addVerifyPass(const std::string &Banner)
Add a pass to perform basic verification of the machine function if verification is enabled.
Definition: TargetPassConfig.cpp:756
StopBeforeOptName
static const char StopBeforeOptName[]
Definition: TargetPassConfig.cpp:200
llvm::createPreISelIntrinsicLoweringPass
ModulePass * createPreISelIntrinsicLoweringPass()
This pass lowers the @llvm.load.relative and @llvm.objc.
llvm::TargetPassConfig::hasLimitedCodeGenPipeline
static bool hasLimitedCodeGenPipeline()
Returns true if one of the -start-after, -start-before, -stop-after or -stop-before options is set.
Definition: TargetPassConfig.cpp:623
llvm::TargetOptions::EnableIPRA
unsigned EnableIPRA
This flag enables InterProcedural Register Allocation (IPRA).
Definition: TargetOptions.h:278
PrintGCInfo
static cl::opt< bool > PrintGCInfo("print-gc", cl::Hidden, cl::desc("Dump garbage collector data"))
llvm::FuncletLayoutID
char & FuncletLayoutID
This pass lays out funclets contiguously.
Definition: FuncletLayout.cpp:39
llvm::GCMachineCodeAnalysisID
char & GCMachineCodeAnalysisID
GCMachineCodeAnalysis - Target-independent pass to mark safe points in machine code.
Definition: GCRootLowering.cpp:240
llvm::TargetOptions::SupportsDefaultOutlining
unsigned SupportsDefaultOutlining
Set if the target supports default outlining behaviour.
Definition: TargetOptions.h:290
PassInstrumentation.h
INITIALIZE_PASS
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:37
initializeDefaultRegisterAllocatorOnce
static void initializeDefaultRegisterAllocatorOnce()
Definition: TargetPassConfig.cpp:1276
DisablePartialLibcallInlining
static cl::opt< bool > DisablePartialLibcallInlining("disable-partial-libcall-inlining", cl::Hidden, cl::desc("Disable Partial Libcall Inlining"))
llvm::createReplaceWithVeclibLegacyPass
FunctionPass * createReplaceWithVeclibLegacyPass()
Definition: ReplaceWithVeclib.cpp:254
IP
Definition: NVPTXLowerArgs.cpp:166
llvm::createResetMachineFunctionPass
MachineFunctionPass * createResetMachineFunctionPass(bool EmitFallbackDiag, bool AbortOnFailedISel)
This pass resets a MachineFunction when it has the FailedISel property as if it was just created.
DISABLE_PASS
#define DISABLE_PASS(Option, Name)
llvm::RegisterCoalescerID
char & RegisterCoalescerID
RegisterCoalescer - This pass merges live ranges to eliminate copies.
Definition: RegisterCoalescer.cpp:391
useDefaultRegisterAllocator
static FunctionPass * useDefaultRegisterAllocator()
-regalloc=... command line option.
Definition: TargetPassConfig.cpp:1060
llvm::EarlyIfConverterID
char & EarlyIfConverterID
EarlyIfConverter - This pass performs if-conversion on SSA form by inserting cmov instructions.
Definition: EarlyIfConversion.cpp:784
PrintLSR
static cl::opt< bool > PrintLSR("print-lsr-output", cl::Hidden, cl::desc("Print LLVM IR produced by the loop-reduce pass"))
llvm::TargetPassConfig::isGlobalISelAbortEnabled
bool isGlobalISelAbortEnabled() const
Check whether or not GlobalISel should abort on error.
Definition: TargetPassConfig.cpp:1459
llvm::TargetPassConfig::getPassSubstitution
IdentifyingPassPtr getPassSubstitution(AnalysisID StandardID) const
Return the pass substituted for StandardID by the target.
Definition: TargetPassConfig.cpp:659
llvm::PassRegistry
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
Definition: PassRegistry.h:38
llvm::TargetPassConfig::addMachinePrePasses
void addMachinePrePasses(bool AllowDebugify=true)
Add standard passes before a pass that's about to be added.
Definition: TargetPassConfig.cpp:778
llvm::report_fatal_error
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:140
IRPrintingPasses.h
llvm::ExceptionHandling::Wasm
@ Wasm
WebAssembly Exception Handling.
llvm::cl::Option::getNumOccurrences
int getNumOccurrences() const
Definition: CommandLine.h:404
StartAfterOpt
static cl::opt< std::string > StartAfterOpt(StringRef(StartAfterOptName), cl::desc("Resume compilation after a specific pass"), cl::value_desc("pass-name"), cl::init(""), cl::Hidden)
llvm::StackMapLivenessID
char & StackMapLivenessID
StackMapLiveness - This pass analyses the register live-out set of stackmap/patchpoint intrinsics and...
Definition: StackMapLivenessAnalysis.cpp:86
llvm::CGPassBuilderOption
Definition: CGPassBuilderOption.h:30
llvm::createShadowStackGCLoweringPass
FunctionPass * createShadowStackGCLoweringPass()
ShadowStackGCLowering - Implements the custom lowering mechanism used by the shadow stack GC.
Definition: ShadowStackGCLowering.cpp:100
llvm::PassInstrumentationCallbacks::registerShouldRunOptionalPassCallback
void registerShouldRunOptionalPassCallback(CallableT C)
Definition: PassInstrumentation.h:95
StopBeforeOpt
static cl::opt< std::string > StopBeforeOpt(StringRef(StopBeforeOptName), cl::desc("Stop compilation before a specific pass"), cl::value_desc("pass-name"), cl::init(""), cl::Hidden)
llvm::TargetPassConfig::addPostFastRegAllocRewrite
virtual bool addPostFastRegAllocRewrite()
addPostFastRegAllocRewrite - Add passes to the optimized register allocation pipeline after fast regi...
Definition: TargetPassConfig.h:411
CFLAndersAliasAnalysis.h
Utils.h
ScopedNoAliasAA.h
llvm::RegisterPassParser
RegisterPassParser class - Handle the addition of new machine passes.
Definition: MachinePassRegistry.h:135
llvm::StringRef::getAsInteger
std::enable_if_t< std::numeric_limits< T >::is_signed, bool > getAsInteger(unsigned Radix, T &Result) const
Parse the current string as an integer of the specified radix.
Definition: StringRef.h:511
llvm::TargetPassConfig::setRequiresCodeGenSCCOrder
void setRequiresCodeGenSCCOrder(bool Enable=true)
Definition: TargetPassConfig.h:180
llvm::createMachineOutlinerPass
ModulePass * createMachineOutlinerPass(bool RunOnAllFunctions=true)
This pass performs outlining on machine instructions directly before printing assembly.
Definition: MachineOutliner.cpp:443
llvm::initializeCodeGen
void initializeCodeGen(PassRegistry &)
Initialize all passes linked into the CodeGen library.
Definition: CodeGen.cpp:21
DisableMergeICmps
static cl::opt< bool > DisableMergeICmps("disable-mergeicmps", cl::desc("Disable MergeICmps Pass"), cl::init(false), cl::Hidden)
llvm::createMachineFunctionPrinterPass
MachineFunctionPass * createMachineFunctionPrinterPass(raw_ostream &OS, const std::string &Banner="")
MachineFunctionPrinter pass - This pass prints out the machine function to the given stream as a debu...
llvm::legacy::PassManagerBase::add
virtual void add(Pass *P)=0
Add a pass to the queue of passes to run.
InitializeDefaultRegisterAllocatorFlag
static llvm::once_flag InitializeDefaultRegisterAllocatorFlag
A dummy default pass factory indicates whether the register allocator is overridden on the command li...
Definition: TargetPassConfig.cpp:1269
llvm::createCanonicalizeFreezeInLoopsPass
Pass * createCanonicalizeFreezeInLoopsPass()
Definition: CanonicalizeFreezeInLoops.cpp:246
StartAfterOptName
static const char StartAfterOptName[]
Option names for limiting the codegen pipeline.
Definition: TargetPassConfig.cpp:197
llvm::EarlyTailDuplicateID
char & EarlyTailDuplicateID
Duplicate blocks with unconditional branches into tails of their predecessors.
Definition: TailDuplication.cpp:77
llvm::createTargetTransformInfoWrapperPass
ImmutablePass * createTargetTransformInfoWrapperPass(TargetIRAnalysis TIRA)
Create an analysis pass wrapper around a TTI object.
Definition: TargetTransformInfo.cpp:1445
llvm::cl::ZeroOrMore
@ ZeroOrMore
Definition: CommandLine.h:120
getPassIDFromName
static AnalysisID getPassIDFromName(StringRef PassName)
Definition: TargetPassConfig.cpp:372
Passes.h
llvm::VirtRegRewriterID
char & VirtRegRewriterID
VirtRegRewriter pass.
Definition: VirtRegMap.cpp:219
llvm::TargetPassConfig
Target-Independent Code Generator Pass Configuration Options.
Definition: TargetPassConfig.h:84
StartBeforeOpt
static cl::opt< std::string > StartBeforeOpt(StringRef(StartBeforeOptName), cl::desc("Resume compilation before a specific pass"), cl::value_desc("pass-name"), cl::init(""), cl::Hidden)
StartBeforeOptName
static const char StartBeforeOptName[]
Definition: TargetPassConfig.cpp:198
llvm::TargetPassConfig::usingDefaultRegAlloc
bool usingDefaultRegAlloc() const
Return true if the default global register allocator is in use and has not be overriden on the comman...
Definition: TargetPassConfig.cpp:1346
llvm::MachineLoopInfoID
char & MachineLoopInfoID
MachineLoopInfo - This pass is a loop analysis pass.
Definition: MachineLoopInfo.cpp:43
llvm::cl::opt< bool >
llvm::TargetOptions::EnableGlobalISel
unsigned EnableGlobalISel
EnableGlobalISel - This flag enables global instruction selection.
Definition: TargetOptions.h:225
llvm::TargetPassConfig::DisableVerify
bool DisableVerify
Definition: TargetPassConfig.h:128
llvm::TargetPassConfig::addMachinePasses
virtual void addMachinePasses()
Add the complete, standard set of LLVM CodeGen passes.
Definition: TargetPassConfig.cpp:1084
llvm::TargetPassConfig::isPassSubstitutedOrOverridden
bool isPassSubstitutedOrOverridden(AnalysisID ID) const
Return true if the pass has been substituted by the target or overridden on the command line.
Definition: TargetPassConfig.cpp:667
llvm::TargetOptions::PseudoProbeForProfiling
unsigned PseudoProbeForProfiling
Emit pseudo probes into the binary for sample profiling.
Definition: TargetOptions.h:318
llvm::CFLAAType::None
@ None
registerPartialPipelineCallback
static void registerPartialPipelineCallback(PassInstrumentationCallbacks &PIC, LLVMTargetMachine &LLVMTM)
Definition: TargetPassConfig.cpp:453
Verify
ppc ctr loops PowerPC CTR Loops Verify
Definition: PPCCTRLoops.cpp:77
Threading.h
llvm::TargetPassConfig::getLimitedCodeGenPipelineReason
static std::string getLimitedCodeGenPipelineReason(const char *Separator="/")
If hasLimitedCodeGenPipeline is true, this method returns a string with the name of the options,...
Definition: TargetPassConfig.cpp:629
llvm::TargetPassConfig::addRegBankSelect
virtual bool addRegBankSelect()
This method should install a register bank selector pass, which assigns register banks to virtual reg...
Definition: TargetPassConfig.h:263
llvm::TargetMachine::setO0WantsFastISel
void setO0WantsFastISel(bool Enable)
Definition: TargetMachine.h:242
llvm::cl::values
ValuesClass values(OptsTy... Options)
Helper to build a ValuesClass by forwarding a variable number of arguments as an initializer list to ...
Definition: CommandLine.h:699
llvm::cl::BOU_UNSET
@ BOU_UNSET
Definition: CommandLine.h:625
llvm::StackColoringID
char & StackColoringID
StackSlotColoring - This pass performs stack coloring and merging.
Definition: StackColoring.cpp:551
llvm::TargetMachine::getTargetIRAnalysis
TargetIRAnalysis getTargetIRAnalysis()
Get a TargetIRAnalysis appropriate for the target.
Definition: TargetMachine.cpp:230
DisableEarlyTailDup
static cl::opt< bool > DisableEarlyTailDup("disable-early-taildup", cl::Hidden, cl::desc("Disable pre-register allocation tail duplication"))
SaveAndRestore.h
EnableGlobalISelOption
static cl::opt< cl::boolOrDefault > EnableGlobalISelOption("global-isel", cl::Hidden, cl::desc("Enable the \"global\" instruction selector"))
defaultRegAlloc
static RegisterRegAlloc defaultRegAlloc("default", "pick register allocator based on -O option", useDefaultRegisterAllocator)
llvm::RegisterRegAllocBase< RegisterRegAlloc >::FunctionPassCtor
FunctionPass *(*)() FunctionPassCtor
Definition: RegAllocRegistry.h:31
llvm::MachineSinkingID
char & MachineSinkingID
MachineSinking - This pass performs sinking on machine instructions.
Definition: MachineSink.cpp:256
llvm::DetectDeadLanesID
char & DetectDeadLanesID
This pass adds dead/undef flags after analyzing subregister lanes.
Definition: DetectDeadLanes.cpp:128
llvm::TargetPassConfig::addPreGlobalInstructionSelect
virtual void addPreGlobalInstructionSelect()
This method may be implemented by targets that want to run passes immediately before the (global) ins...
Definition: TargetPassConfig.h:267
applyDisable
static IdentifyingPassPtr applyDisable(IdentifyingPassPtr PassID, bool Override)
Allow standard passes to be disabled by command line options.
Definition: TargetPassConfig.cpp:237
llvm::DenseMap
Definition: DenseMap.h:714
INITIALIZE_PASS::InsertedPass::getInsertedPass
Pass * getInsertedPass() const
Definition: TargetPassConfig.cpp:323
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::TargetPassConfig::addIRPasses
virtual void addIRPasses()
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
Definition: TargetPassConfig.cpp:800
EnableBlockPlacementStats
static cl::opt< bool > EnableBlockPlacementStats("enable-block-placement-stats", cl::Hidden, cl::desc("Collect probability-driven block placement stats"))
llvm::cl::init
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:443
llvm::TargetPassConfig::addOptimizedRegAlloc
virtual void addOptimizedRegAlloc()
addOptimizedRegAlloc - Add passes related to register allocation.
Definition: TargetPassConfig.cpp:1362
llvm::TargetPassConfig::addRegAssignAndRewriteOptimized
virtual bool addRegAssignAndRewriteOptimized()
Definition: TargetPassConfig.cpp:1331
llvm::createPartiallyInlineLibCallsPass
FunctionPass * createPartiallyInlineLibCallsPass()
Definition: PartiallyInlineLibCalls.cpp:211
llvm::createRegUsageInfoPropPass
FunctionPass * createRegUsageInfoPropPass()
Return a MachineFunction pass that identifies call sites and propagates register usage information of...
Definition: RegUsageInfoPropagate.cpp:155
llvm::createMachineVerifierPass
FunctionPass * createMachineVerifierPass(const std::string &Banner)
createMachineVerifierPass - This pass verifies cenerated machine code instructions for correctness.
llvm::LiveVariablesID
char & LiveVariablesID
LiveVariables pass - This pass computes the set of blocks in which each variable is life and sets mac...
Definition: LiveVariables.cpp:45
overridePass
static IdentifyingPassPtr overridePass(AnalysisID StandardID, IdentifyingPassPtr TargetID)
Allow standard passes to be disabled by the command line, regardless of who is adding the pass.
Definition: TargetPassConfig.cpp:256
TargetPassConfig.h
MachineFunctionPass.h
llvm::TargetPassConfig::addPreEmitPass2
virtual void addPreEmitPass2()
Targets may add passes immediately before machine code is emitted in this callback.
Definition: TargetPassConfig.h:445
llvm::MachineCSEID
char & MachineCSEID
MachineCSE - This pass performs global CSE on machine instructions.
Definition: MachineCSE.cpp:153
llvm::FinalizeISelID
char & FinalizeISelID
This pass expands pseudo-instructions, reserves registers and adjusts machine frame information.
Definition: FinalizeISel.cpp:44
llvm::TargetMachine::Options
TargetOptions Options
Definition: TargetMachine.h:115
llvm::TargetPassConfig::addCodeGenPrepare
virtual void addCodeGenPrepare()
Add pass to prepare the LLVM IR for code generation.
Definition: TargetPassConfig.cpp:929
llvm::TargetPassConfig::getOptimizeRegAlloc
bool getOptimizeRegAlloc() const
Return true if the optimized regalloc pipeline is enabled.
Definition: TargetPassConfig.cpp:1258
llvm::createExpandReductionsPass
FunctionPass * createExpandReductionsPass()
This pass expands the experimental reduction intrinsics into sequences of shuffles.
Definition: ExpandReductions.cpp:202
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::DummyCGSCCPass
This pass is required by interprocedural register allocation.
Definition: CallGraphSCCPass.h:122
DisableEarlyIfConversion
static cl::opt< bool > DisableEarlyIfConversion("disable-early-ifcvt", cl::Hidden, cl::desc("Disable Early If-conversion"))
llvm::createGCLoweringPass
FunctionPass * createGCLoweringPass()
GCLowering Pass - Used by gc.root to perform its default lowering operations.
llvm::TargetPassConfig::addCheckDebugPass
void addCheckDebugPass()
Add a pass to check synthesized debug info for MIR.
Definition: TargetPassConfig.cpp:774
llvm::createExpandVectorPredicationPass
FunctionPass * createExpandVectorPredicationPass()
This pass expands the vector predication intrinsics into unpredicated instructions with selects or ju...
Definition: ExpandVectorPredication.cpp:456
EnableGlobalISelAbort
static cl::opt< GlobalISelAbortMode > EnableGlobalISelAbort("global-isel-abort", cl::Hidden, cl::desc("Enable abort calls when \"global\" instruction selection " "fails to lower/select an instruction"), cl::values(clEnumValN(GlobalISelAbortMode::Disable, "0", "Disable the abort"), clEnumValN(GlobalISelAbortMode::Enable, "1", "Enable the abort"), clEnumValN(GlobalISelAbortMode::DisableWithDiag, "2", "Disable the abort but emit a diagnostic on failure")))
llvm::createTypeBasedAAWrapperPass
ImmutablePass * createTypeBasedAAWrapperPass()
llvm::ProcessImplicitDefsID
char & ProcessImplicitDefsID
ProcessImpicitDefs pass - This pass removes IMPLICIT_DEFs.
Definition: ProcessImplicitDefs.cpp:52
llvm::FastISel
This is a fast-path instruction selection class that generates poor code and doesn't support illegal ...
Definition: FastISel.h:65
llvm::RegisterRegAllocBase< RegisterRegAlloc >::getDefault
static FunctionPassCtor getDefault()
Definition: RegAllocRegistry.h:51
llvm::TargetPassConfig::addIRTranslator
virtual bool addIRTranslator()
This method should install an IR translator pass, which converts from LLVM code to machine instructio...
Definition: TargetPassConfig.h:246
llvm::PatchableFunctionID
char & PatchableFunctionID
This pass implements the "patchable-function" attribute.
Definition: PatchableFunction.cpp:96
llvm::MachineBlockPlacementStatsID
char & MachineBlockPlacementStatsID
MachineBlockPlacementStats - This pass collects statistics about the basic block placement using bran...
Definition: MachineBlockPlacement.cpp:3456
llvm::CFLAAType::Steensgaard
@ Steensgaard
llvm::CodeGenOpt::None
@ None
Definition: CodeGen.h:53
llvm::TargetPassConfig::addISelPasses
bool addISelPasses()
High level function that adds all passes necessary to go from llvm IR representation to the MI repres...
Definition: TargetPassConfig.cpp:1045
llvm::createSjLjEHPreparePass
FunctionPass * createSjLjEHPreparePass(const TargetMachine *TM)
createSjLjEHPreparePass - This pass adapts exception handling code to use the GCC-style builtin setjm...
llvm::TargetMachine::getMCAsmInfo
const MCAsmInfo * getMCAsmInfo() const
Return target specific asm information.
Definition: TargetMachine.h:202
llvm::initializeAAResultsWrapperPassPass
void initializeAAResultsWrapperPassPass(PassRegistry &)
INITIALIZE_PASS::InsertedPass::InsertedPass
InsertedPass(AnalysisID TargetPassID, IdentifyingPassPtr InsertedPassID, bool VerifyAfter)
Definition: TargetPassConfig.cpp:318
MCAsmInfo.h
llvm::XRayInstrumentationID
char & XRayInstrumentationID
This pass inserts the XRay instrumentation sleds if they are supported by the target platform.
Definition: XRayInstrumentation.cpp:263
llvm::UnreachableMachineBlockElimID
char & UnreachableMachineBlockElimID
UnreachableMachineBlockElimination - This pass removes unreachable machine basic blocks.
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:57
SET_OPTION
#define SET_OPTION(Option)
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:136
if
if(llvm_vc STREQUAL "") set(fake_version_inc "$
Definition: CMakeLists.txt:14
llvm::createStripDebugMachineModulePass
ModulePass * createStripDebugMachineModulePass(bool OnlyDebugified)
Creates MIR Strip Debug pass.
Definition: MachineStripDebug.cpp:109
llvm::BranchFolderPassID
char & BranchFolderPassID
BranchFolding - This pass performs machine code CFG based optimizations to delete branches to branche...
Definition: BranchFolding.cpp:114
Compiler.h
llvm::MachineBlockPlacementID
char & MachineBlockPlacementID
MachineBlockPlacement - This pass places basic blocks based on branch probabilities.
Definition: MachineBlockPlacement.cpp:590
clEnumValN
#define clEnumValN(ENUMVAL, FLAGNAME, DESC)
Definition: CommandLine.h:674
llvm::ShrinkWrapID
char & ShrinkWrapID
ShrinkWrap pass. Look for the best place to insert save and restore.
Definition: ShrinkWrap.cpp:250
llvm::createWinEHPass
FunctionPass * createWinEHPass(bool DemoteCatchSwitchPHIOnly=false)
createWinEHPass - Prepares personality functions used by MSVC on Windows, in addition to the Itanium ...
llvm::RunOutliner::AlwaysOutline
@ AlwaysOutline
llvm::TargetPassConfig::reportDiagnosticWhenGlobalISelFallback
virtual bool reportDiagnosticWhenGlobalISelFallback() const
Check whether or not a diagnostic should be emitted when GlobalISel uses the fallback path.
Definition: TargetPassConfig.cpp:1463
llvm::SaveAndRestore
A utility class that uses RAII to save and restore the value of a variable.
Definition: SaveAndRestore.h:21
llvm::TargetPassConfig::addDebugifyPass
void addDebugifyPass()
Add a pass to add synthesized debug info to the MIR.
Definition: TargetPassConfig.cpp:766
llvm::createDebugifyMachineModulePass
ModulePass * createDebugifyMachineModulePass()
Creates MIR Debugify pass.
Definition: MachineDebugify.cpp:200
DisableLSR
static cl::opt< bool > DisableLSR("disable-lsr", cl::Hidden, cl::desc("Disable Loop Strength Reduction Pass"))
llvm::GlobalISelAbortMode::DisableWithDiag
@ DisableWithDiag
llvm::once_flag
std::once_flag once_flag
Definition: Threading.h:89
OptimizeRegAlloc
static cl::opt< cl::boolOrDefault > OptimizeRegAlloc("optimize-regalloc", cl::Hidden, cl::desc("Enable optimized register allocation compilation path."))
llvm::getCGPassBuilderOption
CGPassBuilderOption getCGPassBuilderOption()
Definition: TargetPassConfig.cpp:419
adjust::pm
static void pm(uint64_t &Value)
Adjusts a program memory address.
Definition: AVRAsmBackend.cpp:192
llvm::CodeGenOpt::Level
Level
Definition: CodeGen.h:52
CallGraphSCCPass.h
llvm::createVerifierPass
FunctionPass * createVerifierPass(bool FatalErrors=true)
Definition: Verifier.cpp:6173
llvm::TargetMachine::setFastISel
void setFastISel(bool Enable)
Definition: TargetMachine.h:240
llvm::TargetPassConfig::addPreRegAlloc
virtual void addPreRegAlloc()
This method may be implemented by targets that want to run passes immediately before register allocat...
Definition: TargetPassConfig.h:379
LLVM_FALLTHROUGH
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:281
llvm::RenameIndependentSubregsID
char & RenameIndependentSubregsID
This pass detects subregister lanes in a virtual register that are used independently of other lanes ...
Definition: RenameIndependentSubregs.cpp:113
DisableMachineCSE
static cl::opt< bool > DisableMachineCSE("disable-machine-cse", cl::Hidden, cl::desc("Disable Machine Common Subexpression Elimination"))
llvm::FixupStatepointCallerSavedID
char & FixupStatepointCallerSavedID
The pass fixups statepoint machine instruction to replace usage of caller saved registers with stack ...
Definition: FixupStatepointCallerSaved.cpp:88
llvm::PassConfigImpl::TargetPasses
DenseMap< AnalysisID, IdentifyingPassPtr > TargetPasses
Definition: TargetPassConfig.cpp:346
llvm::TargetPassConfig::getCSEConfig
virtual std::unique_ptr< CSEConfigBase > getCSEConfig() const
Returns the CSEConfig object to use for the current optimization level.
Definition: TargetPassConfig.cpp:1471
llvm::createBasicAAWrapperPass
FunctionPass * createBasicAAWrapperPass()
Definition: BasicAliasAnalysis.cpp:1799
llvm::createRegUsageInfoCollector
FunctionPass * createRegUsageInfoCollector()
This pass is executed POST-RA to collect which physical registers are preserved by given machine func...
Definition: RegUsageInfoCollector.cpp:76
llvm::Twine
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:80
llvm::TargetPassConfig::addPass
AnalysisID addPass(AnalysisID PassID, bool verifyAfter=true)
Utilities for targets to add passes to the pass manager.
Definition: TargetPassConfig.cpp:726
llvm::Any
Definition: Any.h:26
Verifier.h
llvm::empty
constexpr bool empty(const T &RangeOrContainer)
Test whether RangeOrContainer is empty. Similar to C++17 std::empty.
Definition: STLExtras.h:254
llvm::TargetPassConfig::requiresCodeGenSCCOrder
bool requiresCodeGenSCCOrder() const
Definition: TargetPassConfig.h:179
llvm::GraphProgram::Name
Name
Definition: GraphWriter.h:52
llvm::call_once
void call_once(once_flag &flag, Function &&F, Args &&... ArgList)
Execute the function specified as a parameter once.
Definition: Threading.h:119
llvm::TargetPassConfig::Impl
PassConfigImpl * Impl
Definition: TargetPassConfig.h:123
llvm::TargetPassConfig::addMachineSSAOptimization
virtual void addMachineSSAOptimization()
addMachineSSAOptimization - Add standard passes that optimize machine instructions in SSA form.
Definition: TargetPassConfig.cpp:1216
llvm::createBasicBlockSectionsPass
MachineFunctionPass * createBasicBlockSectionsPass(const MemoryBuffer *Buf)
createBasicBlockSections Pass - This pass assigns sections to machine basic blocks and is enabled wit...
Definition: BasicBlockSections.cpp:519
llvm::createScalarizeMaskedMemIntrinLegacyPass
FunctionPass * createScalarizeMaskedMemIntrinLegacyPass()
Definition: ScalarizeMaskedMemIntrin.cpp:89
llvm::TargetOptions::GlobalISelAbort
GlobalISelAbortMode GlobalISelAbort
EnableGlobalISelAbort - Control abort behaviour when global instruction selection fails to lower/sele...
Definition: TargetOptions.h:229
llvm::createScopedNoAliasAAWrapperPass
ImmutablePass * createScopedNoAliasAAWrapperPass()
llvm::createWasmEHPass
FunctionPass * createWasmEHPass()
createWasmEHPass - This pass adapts exception handling code to use WebAssembly's exception handling s...
Definition: WasmEHPrepare.cpp:144
VerifyMachineCode
static cl::opt< cl::boolOrDefault > VerifyMachineCode("verify-machineinstrs", cl::Hidden, cl::desc("Verify generated machine code"), cl::ZeroOrMore)
llvm::TargetPassConfig::addLegalizeMachineIR
virtual bool addLegalizeMachineIR()
This method should install a legalize pass, which converts the instruction sequence into one that can...
Definition: TargetPassConfig.h:254
llvm::createPseudoProbeInserter
FunctionPass * createPseudoProbeInserter()
This pass inserts pseudo probe annotation for callsite profiling.
Definition: PseudoProbeInserter.cpp:173
llvm::ExceptionHandling::WinEH
@ WinEH
Windows Exception Handling.
llvm::TailDuplicateID
char & TailDuplicateID
TailDuplicate - Duplicate blocks with unconditional branches into tails of their predecessors.
Definition: TailDuplication.cpp:76
llvm::LLVMTargetMachine
This class describes a target machine that is implemented with the LLVM target-independent code gener...
Definition: TargetMachine.h:385
llvm::IdentifyingPassPtr::getID
AnalysisID getID() const
Definition: TargetPassConfig.h:68
llvm::cl::value_desc
Definition: CommandLine.h:424
llvm::TargetMachine::setGlobalISel
void setGlobalISel(bool Enable)
Definition: TargetMachine.h:243
llvm::DeadMachineInstructionElimID
char & DeadMachineInstructionElimID
DeadMachineInstructionElim - This pass removes dead machine instructions.
Definition: DeadMachineInstructionElim.cpp:57
llvm::TargetOptions::EnableMachineOutliner
unsigned EnableMachineOutliner
Enables the MachineOutliner pass.
Definition: TargetOptions.h:284
DisableSSC
static cl::opt< bool > DisableSSC("disable-ssc", cl::Hidden, cl::desc("Disable Stack Slot Coloring"))
llvm::TargetPassConfig::addBlockPlacement
virtual void addBlockPlacement()
Add standard basic block placement passes.
Definition: TargetPassConfig.cpp:1448
llvm::ExceptionHandling::None
@ None
No exception support.
llvm::TargetMachine::getBBSectionsFuncListBuf
const MemoryBuffer * getBBSectionsFuncListBuf() const
Get the list of functions and basic block ids that need unique sections.
Definition: TargetMachine.h:297
llvm::MachineSchedulerID
char & MachineSchedulerID
MachineScheduler - This pass schedules machine instructions.
Definition: MachineScheduler.cpp:210
CodeGen.h
llvm::MCAsmInfo::getExceptionHandlingType
ExceptionHandling getExceptionHandlingType() const
Definition: MCAsmInfo.h:737
DisableMachineDCE
static cl::opt< bool > DisableMachineDCE("disable-machine-dce", cl::Hidden, cl::desc("Disable Machine Dead Code Elimination"))
llvm::TargetPassConfig::createTargetRegisterAllocator
virtual FunctionPass * createTargetRegisterAllocator(bool Optimized)
createTargetRegisterAllocator - Create the register allocator pass for this target at the current opt...
Definition: TargetPassConfig.cpp:1289
llvm::cl::BOU_TRUE
@ BOU_TRUE
Definition: CommandLine.h:625
llvm::GlobalISelAbortMode::Enable
@ Enable
llvm::Pass
Pass interface - Implemented by all 'passes'.
Definition: Pass.h:91
llvm::TargetPassConfig::addISelPrepare
virtual void addISelPrepare()
Add common passes that perform LLVM IR to IR transforms in preparation for instruction selection.
Definition: TargetPassConfig.cpp:937
llvm::TargetPassConfig::addGlobalInstructionSelect
virtual bool addGlobalInstructionSelect()
This method should install a (global) instruction selector pass, which converts possibly generic inst...
Definition: TargetPassConfig.h:273
llvm::PostRASchedulerID
char & PostRASchedulerID
PostRAScheduler - This pass performs post register allocation scheduling.
Definition: PostRASchedulerList.cpp:199
SmallVector.h
llvm::createLowerConstantIntrinsicsPass
FunctionPass * createLowerConstantIntrinsicsPass()
Definition: LowerConstantIntrinsics.cpp:198
llvm::PassInstrumentationCallbacks
This class manages callbacks registration, as well as provides a way for PassInstrumentation to pass ...
Definition: PassInstrumentation.h:65
llvm::LLVMTargetMachine::getPassNameFromLegacyName
virtual std::pair< StringRef, bool > getPassNameFromLegacyName(StringRef)
Definition: TargetMachine.h:425
DisableMachineLICM
static cl::opt< bool > DisableMachineLICM("disable-machine-licm", cl::Hidden, cl::desc("Disable Machine LICM"))
RegAlloc
static cl::opt< RegisterRegAlloc::FunctionPassCtor, false, RegisterPassParser< RegisterRegAlloc > > RegAlloc("regalloc", cl::Hidden, cl::init(&useDefaultRegisterAllocator), cl::desc("Register allocator to use"))
TargetTransformInfo.h
llvm::TargetPassConfig::addPreISel
virtual bool addPreISel()
Methods with trivial inline returns are convenient points in the common codegen pass pipeline where t...
Definition: TargetPassConfig.h:359
llvm::legacy::PassManagerBase
PassManagerBase - An abstract interface to allow code to add passes to a pass manager without having ...
Definition: LegacyPassManager.h:39
llvm::TargetPassConfig::addPassesToHandleExceptions
void addPassesToHandleExceptions()
Add passes to lower exception handling for the code generator.
Definition: TargetPassConfig.cpp:885
llvm::GlobalISelAbortMode::Disable
@ Disable
DebugifyCheckAndStripAll
static cl::opt< cl::boolOrDefault > DebugifyCheckAndStripAll("debugify-check-and-strip-all-safe", cl::Hidden, cl::desc("Debugify MIR before, by checking and stripping the debug info after, " "each pass except those known to be unsafe when debug info is present"), cl::ZeroOrMore)
llvm::FunctionPass
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:298
EnableImplicitNullChecks
static cl::opt< bool > EnableImplicitNullChecks("enable-implicit-null-checks", cl::desc("Fold null checks into faulting memory operations"), cl::init(false), cl::Hidden)
llvm::ImplicitNullChecksID
char & ImplicitNullChecksID
ImplicitNullChecks - This pass folds null pointer checks into nearby memory operations.
Definition: ImplicitNullChecks.cpp:816
llvm::EarlyMachineLICMID
char & EarlyMachineLICMID
This pass performs loop invariant code motion on machine instructions.
Definition: MachineLICM.cpp:295
llvm::TargetPassConfig::TargetPassConfig
TargetPassConfig()
Definition: TargetPassConfig.cpp:612
llvm::PostMachineSchedulerID
char & PostMachineSchedulerID
PostMachineScheduler - This pass schedules machine instructions postRA.
Definition: MachineScheduler.cpp:241
llvm::PostRAMachineSinkingID
char & PostRAMachineSinkingID
This pass perform post-ra machine sink for COPY instructions.
Definition: MachineSink.cpp:1561
llvm::cl::desc
Definition: CommandLine.h:414
llvm::PassRegistry::getPassInfo
const PassInfo * getPassInfo(const void *TI) const
getPassInfo - Look up a pass' corresponding PassInfo, indexed by the pass' type identifier (&MyPass::...
Definition: PassRegistry.cpp:41
llvm::TargetPassConfig::addPreEmitPass
virtual void addPreEmitPass()
This pass may be implemented by targets that want to run passes immediately before machine code is em...
Definition: TargetPassConfig.h:438
llvm::createSafeStackPass
FunctionPass * createSafeStackPass()
This pass splits the stack into a safe stack and an unsafe stack to protect against stack-based overf...
Definition: SafeStack.cpp:940
llvm::TargetPassConfig::Initialized
bool Initialized
Definition: TargetPassConfig.h:124
llvm::TargetPassConfig::addFastRegAlloc
virtual void addFastRegAlloc()
addFastRegAlloc - Add the minimum set of target-independent passes that are required for fast registe...
Definition: TargetPassConfig.cpp:1352
llvm::TargetPassConfig::addCoreISelPasses
bool addCoreISelPasses()
Add the actual instruction selection passes.
Definition: TargetPassConfig.cpp:959
SET_BOOLEAN_OPTION
#define SET_BOOLEAN_OPTION(Option)
llvm::LiveIntervalsID
char & LiveIntervalsID
LiveIntervals - This analysis keeps track of the live ranges of virtual and physical registers.
Definition: LiveIntervals.cpp:64
EnableIPRA
static cl::opt< bool > EnableIPRA("enable-ipra", cl::init(false), cl::Hidden, cl::desc("Enable interprocedural register allocation " "to reduce load/store at procedure calls."))
InitializePasses.h
llvm::LLVMTargetMachine::useIPRA
virtual bool useIPRA() const
True if the target wants to use interprocedural register allocation by default.
Definition: TargetMachine.h:464
llvm::TargetPassConfig::insertPass
void insertPass(AnalysisID TargetPassID, IdentifyingPassPtr InsertedPassID, bool VerifyAfter=true)
Insert InsertedPassID pass after TargetPassID pass.
Definition: TargetPassConfig.cpp:593
llvm::TargetPassConfig::addPrintPass
void addPrintPass(const std::string &Banner)
Add a pass to print the machine function if printing is enabled.
Definition: TargetPassConfig.cpp:751
llvm::ExceptionHandling::DwarfCFI
@ DwarfCFI
DWARF-like instruction based exceptions.
StopAfterOptName
static const char StopAfterOptName[]
Definition: TargetPassConfig.cpp:199
Debug.h
llvm::TargetPassConfig::addMachinePostPasses
void addMachinePostPasses(const std::string &Banner, bool AllowVerify=true, bool AllowStrip=true)
Add standard passes after a pass that has just been added.
Definition: TargetPassConfig.cpp:785
llvm::TargetPassConfig::addILPOpts
virtual bool addILPOpts()
Add passes that optimize instruction level parallelism for out-of-order targets.
Definition: TargetPassConfig.h:373
llvm::TargetPassConfig::getOptLevel
CodeGenOpt::Level getOptLevel() const
Definition: TargetPassConfig.cpp:588
PassName
static const char PassName[]
Definition: X86LowerAMXIntrinsics.cpp:669
CFLSteensAliasAnalysis.h
llvm::TargetPassConfig::setOpt
void setOpt(bool &Opt, bool Val)
Definition: TargetPassConfig.cpp:649
llvm::createCodeGenPreparePass
FunctionPass * createCodeGenPreparePass()
createCodeGenPreparePass - Transform the code to expose more pattern matching during instruction sele...
Definition: CodeGenPrepare.cpp:453
RegAllocRegistry.h
StopAfterOpt
static cl::opt< std::string > StopAfterOpt(StringRef(StopAfterOptName), cl::desc("Stop compilation after a specific pass"), cl::value_desc("pass-name"), cl::init(""), cl::Hidden)
llvm::TargetPassConfig::~TargetPassConfig
~TargetPassConfig() override
Definition: TargetPassConfig.cpp:356
llvm::TargetMachine::getBBSectionsType
llvm::BasicBlockSection getBBSectionsType() const
If basic blocks should be emitted into their own section, corresponding to -fbasic-block-sections.
Definition: TargetMachine.h:292
llvm::createStackProtectorPass
FunctionPass * createStackProtectorPass()
createStackProtectorPass - This pass adds stack protectors to functions.
Definition: StackProtector.cpp:77
llvm::TargetPassConfig::addMachineLateOptimization
virtual void addMachineLateOptimization()
Add passes that optimize machine instructions after register allocation.
Definition: TargetPassConfig.cpp:1426
llvm::SmallVectorImpl::emplace_back
reference emplace_back(ArgTypes &&... Args)
Definition: SmallVector.h:908
llvm::createPrintFunctionPass
FunctionPass * createPrintFunctionPass(raw_ostream &OS, const std::string &Banner="")
Create and return a pass that prints functions to the specified raw_ostream as they are processed.
Definition: IRPrintingPasses.cpp:130
llvm::Intrinsic::ID
unsigned ID
Definition: TargetTransformInfo.h:38
PrintAfterISel
static cl::opt< bool > PrintAfterISel("print-after-isel", cl::init(false), cl::Hidden, cl::desc("Print machine instrs after ISel"))
llvm::createMergeICmpsLegacyPass
Pass * createMergeICmpsLegacyPass()
Definition: MergeICmps.cpp:930
DisablePostRASched
static cl::opt< bool > DisablePostRASched("disable-post-ra", cl::Hidden, cl::desc("Disable Post Regalloc Scheduler"))
DisableCopyProp
static cl::opt< bool > DisableCopyProp("disable-copyprop", cl::Hidden, cl::desc("Disable Copy Propagation pass"))
DisableBlockPlacement
static cl::opt< bool > DisableBlockPlacement("disable-block-placement", cl::Hidden, cl::desc("Disable probability-driven block placement"))