Classes
struct	CPUInfo
struct	FeatureName

Enumerations
enum	CPUKind : unsigned { XTENSA_CPU , XTENSA_CPU }
enum	XtensaFeatureKind : uint64_t { XF_INVALID = 0 , XF_NONE = 1 , XF_FP = 1 << 1 , XF_WINDOWED = 1 << 2 , XF_BOOLEAN = 1 << 3 , XF_DENSITY = 1 << 4 , XF_LOOP = 1 << 5 , XF_SEXT = 1 << 6 , XF_NSA = 1 << 7 , XF_CLAMPS = 1 << 8 , XF_MINMAX = 1 << 9 , XF_MAC16 = 1 << 10 , XF_MUL32 = 1 << 11 , XF_MUL32HIGH = 1 << 12 , XF_DIV32 = 1 << 13 , XF_MUL16 = 1 << 14 , XF_DFPACCEL = 1 << 15 , XF_S32C1I = 1 << 16 , XF_THREADPTR = 1 << 17 , XF_EXTENDEDL32R = 1 << 18 , XF_DATACACHE = 1 << 19 , XF_DEBUG = 1 << 20 , XF_EXCEPTION = 1 << 21 , XF_HIGHPRIINTERRUPTS = 1 << 22 , XF_HIGHPRIINTERRUPTSLEVEL3 = 1 << 23 , XF_HIGHPRIINTERRUPTSLEVEL4 = 1 << 24 , XF_HIGHPRIINTERRUPTSLEVEL5 = 1 << 25 , XF_HIGHPRIINTERRUPTSLEVEL6 = 1 << 26 , XF_HIGHPRIINTERRUPTSLEVEL7 = 1 << 27 , XF_COPROCESSOR = 1 << 28 , XF_INTERRUPT = 1 << 29 , XF_RVECTOR = 1 << 30 , XF_TIMERS1 = 1ULL << 31 , XF_TIMERS2 = 1ULL << 32 , XF_TIMERS3 = 1ULL << 33 , XF_PRID = 1ULL << 34 , XF_REGPROTECT = 1ULL << 35 , XF_MISCSR = 1ULL << 36 }
enum	FixupKind { fixup_xtensa_branch_6 = FirstTargetFixupKind , fixup_xtensa_branch_8 , fixup_xtensa_branch_12 , fixup_xtensa_jump_18 , fixup_xtensa_call_18 , fixup_xtensa_l32r_16 , fixup_xtensa_loop_8 , fixup_xtensa_invalid , LastTargetFixupKind , NumTargetFixupKinds = LastTargetFixupKind - FirstTargetFixupKind }
enum	Specifier { S_None , S_TPOFF }
enum	RegisterAccessType { REGISTER_WRITE = 1 , REGISTER_READ = 2 , REGISTER_EXCHANGE = 3 }

Functions
CPUKind	parseCPUKind (StringRef CPU)
StringRef	getBaseName (StringRef CPU)
void	getCPUFeatures (StringRef CPU, SmallVectorImpl< StringRef > &Features)
void	fillValidCPUList (SmallVectorImpl< StringRef > &Values)
uint8_t	parseSpecifier (StringRef name)
StringRef	getSpecifierName (uint8_t S)
bool	isValidAddrOffset (int Scale, int64_t OffsetVal)
bool	isValidAddrOffsetForOpcode (unsigned Opcode, int64_t Offset)
bool	checkRegister (MCRegister RegNo, const FeatureBitset &FeatureBits, RegisterAccessType RA)
MCRegister	getUserRegister (unsigned Code, const MCRegisterInfo &MRI)
StringRef	getAliasName (StringRef CPU)
void	getCPUFeatures (StringRef CPU, std::vector< StringRef > &Features)
void	fillValidCPUList (std::vector< StringRef > &Values)

Variables
const FeatureName	XtensaFeatureNames []
constexpr CPUInfo	XtensaCPUInfo []

Enumeration Type Documentation

◆ CPUKind

enum llvm::Xtensa::CPUKind : unsigned

Enumerator
XTENSA_CPU
XTENSA_CPU

Definition at line 25 of file XtensaTargetParser.h.

◆ FixupKind

enum llvm::Xtensa::FixupKind

Enumerator
fixup_xtensa_branch_6
fixup_xtensa_branch_8
fixup_xtensa_branch_12
fixup_xtensa_jump_18
fixup_xtensa_call_18
fixup_xtensa_l32r_16
fixup_xtensa_loop_8
fixup_xtensa_invalid
LastTargetFixupKind
NumTargetFixupKinds

Definition at line 18 of file XtensaFixupKinds.h.

◆ RegisterAccessType

enum llvm::Xtensa::RegisterAccessType

Enumerator
REGISTER_WRITE
REGISTER_READ
REGISTER_EXCHANGE

Definition at line 58 of file XtensaMCTargetDesc.h.

◆ Specifier

enum llvm::Xtensa::Specifier

Enumerator
S_None
S_TPOFF

Definition at line 34 of file XtensaMCAsmInfo.h.

◆ XtensaFeatureKind

enum llvm::Xtensa::XtensaFeatureKind : uint64_t

Enumerator
XF_INVALID
XF_NONE
XF_FP
XF_WINDOWED
XF_BOOLEAN
XF_DENSITY
XF_LOOP
XF_SEXT
XF_NSA
XF_CLAMPS
XF_MINMAX
XF_MAC16
XF_MUL32
XF_MUL32HIGH
XF_DIV32
XF_MUL16
XF_DFPACCEL
XF_S32C1I
XF_THREADPTR
XF_EXTENDEDL32R
XF_DATACACHE
XF_DEBUG
XF_EXCEPTION
XF_HIGHPRIINTERRUPTS
XF_HIGHPRIINTERRUPTSLEVEL3
XF_HIGHPRIINTERRUPTSLEVEL4
XF_HIGHPRIINTERRUPTSLEVEL5
XF_HIGHPRIINTERRUPTSLEVEL6
XF_HIGHPRIINTERRUPTSLEVEL7
XF_COPROCESSOR
XF_INTERRUPT
XF_RVECTOR
XF_TIMERS1
XF_TIMERS2
XF_TIMERS3
XF_PRID
XF_REGPROTECT
XF_MISCSR

Definition at line 30 of file XtensaTargetParser.h.

Function Documentation

◆ checkRegister()

bool llvm::Xtensa::checkRegister	(	MCRegister	RegNo,
		const FeatureBitset &	FeatureBits,
		RegisterAccessType	RA )

Definition at line 78 of file XtensaMCTargetDesc.cpp.

References LLVM_FALLTHROUGH, REGISTER_EXCHANGE, REGISTER_READ, and REGISTER_WRITE.

Referenced by DecodeSRRegisterClass(), and DecodeURRegisterClass().

◆ fillValidCPUList() [1/2]

void llvm::Xtensa::fillValidCPUList ( SmallVectorImpl< StringRef > & Values )

◆ fillValidCPUList() [2/2]

void llvm::Xtensa::fillValidCPUList ( std::vector< StringRef > & Values )

Definition at line 81 of file XtensaTargetParser.cpp.

References llvm::CallingConv::C, getAliasName(), and XtensaCPUInfo.

◆ getAliasName()

StringRef llvm::Xtensa::getAliasName ( StringRef CPU )

Definition at line 51 of file XtensaTargetParser.cpp.

References llvm::StringSwitch< T, R >::Default().

Referenced by fillValidCPUList().

◆ getBaseName()

StringRef llvm::Xtensa::getBaseName ( StringRef CPU )

Definition at line 44 of file XtensaTargetParser.cpp.

References llvm::StringSwitch< T, R >::Default().

Referenced by getCPUFeatures(), and parseCPUKind().

◆ getCPUFeatures() [1/2]

void llvm::Xtensa::getCPUFeatures	(	StringRef	CPU,
		SmallVectorImpl< StringRef > &	Features )

◆ getCPUFeatures() [2/2]

void llvm::Xtensa::getCPUFeatures	(	StringRef	CPU,
		std::vector< StringRef > &	Features )

Definition at line 67 of file XtensaTargetParser.cpp.

References assert(), F, llvm::find_if(), getBaseName(), I, llvm::Xtensa::CPUInfo::Name, XtensaCPUInfo, and XtensaFeatureNames.

◆ getSpecifierName()

StringRef llvm::Xtensa::getSpecifierName ( uint8_t S )

Definition at line 47 of file XtensaMCAsmInfo.cpp.

References llvm_unreachable.

Referenced by llvm::XtensaMCAsmInfo::printSpecifierExpr().

◆ getUserRegister()

MCRegister llvm::Xtensa::getUserRegister	(	unsigned	Code,
		const MCRegisterInfo &	MRI )

Definition at line 214 of file XtensaMCTargetDesc.cpp.

References MRI.

Referenced by DecodeURRegisterClass().

◆ isValidAddrOffset()

bool llvm::Xtensa::isValidAddrOffset	(	int	Scale,
		int64_t	OffsetVal )

Definition at line 35 of file XtensaMCTargetDesc.cpp.

Referenced by isValidAddrOffsetForOpcode().

◆ isValidAddrOffsetForOpcode()

bool llvm::Xtensa::isValidAddrOffsetForOpcode	(	unsigned	Opcode,
		int64_t	Offset )

Definition at line 54 of file XtensaMCTargetDesc.cpp.

References isValidAddrOffset(), and llvm::Offset.

Referenced by llvm::XtensaRegisterInfo::eliminateFrameIndex().

◆ parseCPUKind()

CPUKind llvm::Xtensa::parseCPUKind ( StringRef CPU )

Definition at line 58 of file XtensaTargetParser.cpp.

References llvm::StringSwitch< T, R >::Default(), and getBaseName().

◆ parseSpecifier()

uint8_t llvm::Xtensa::parseSpecifier ( StringRef name )

Definition at line 45 of file XtensaMCAsmInfo.cpp.

References name.

Variable Documentation

◆ XtensaCPUInfo

CPUInfo llvm::Xtensa::XtensaCPUInfo[]

constexpr

Initial value:

= {
#define XTENSA_CPU(ENUM, NAME, FEATURES)                             
 
}

Definition at line 39 of file XtensaTargetParser.cpp.

Referenced by fillValidCPUList(), and getCPUFeatures().

◆ XtensaFeatureNames

const FeatureName llvm::Xtensa::XtensaFeatureNames[]