LLVM  10.0.0svn
RISCVRegisterInfo.cpp
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1 //===-- RISCVRegisterInfo.cpp - RISCV Register Information ------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the RISCV implementation of the TargetRegisterInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "RISCVRegisterInfo.h"
14 #include "RISCV.h"
15 #include "RISCVSubtarget.h"
23 
24 #define GET_REGINFO_TARGET_DESC
25 #include "RISCVGenRegisterInfo.inc"
26 
27 using namespace llvm;
28 
30  : RISCVGenRegisterInfo(RISCV::X1, /*DwarfFlavour*/0, /*EHFlavor*/0,
31  /*PC*/0, HwMode) {}
32 
33 const MCPhysReg *
35  auto &Subtarget = MF->getSubtarget<RISCVSubtarget>();
36  if (MF->getFunction().hasFnAttribute("interrupt")) {
37  if (Subtarget.hasStdExtD())
38  return CSR_XLEN_F64_Interrupt_SaveList;
39  if (Subtarget.hasStdExtF())
40  return CSR_XLEN_F32_Interrupt_SaveList;
41  return CSR_Interrupt_SaveList;
42  }
43 
44  switch (Subtarget.getTargetABI()) {
45  default:
46  llvm_unreachable("Unrecognized ABI");
48  case RISCVABI::ABI_LP64:
49  return CSR_ILP32_LP64_SaveList;
52  return CSR_ILP32F_LP64F_SaveList;
55  return CSR_ILP32D_LP64D_SaveList;
56  }
57 }
58 
60  const TargetFrameLowering *TFI = getFrameLowering(MF);
61  BitVector Reserved(getNumRegs());
62 
63  // Use markSuperRegs to ensure any register aliases are also reserved
64  markSuperRegs(Reserved, RISCV::X0); // zero
65  markSuperRegs(Reserved, RISCV::X1); // ra
66  markSuperRegs(Reserved, RISCV::X2); // sp
67  markSuperRegs(Reserved, RISCV::X3); // gp
68  markSuperRegs(Reserved, RISCV::X4); // tp
69  if (TFI->hasFP(MF))
70  markSuperRegs(Reserved, RISCV::X8); // fp
71  assert(checkAllSuperRegsMarked(Reserved));
72  return Reserved;
73 }
74 
75 bool RISCVRegisterInfo::isConstantPhysReg(unsigned PhysReg) const {
76  return PhysReg == RISCV::X0;
77 }
78 
80  return CSR_NoRegs_RegMask;
81 }
82 
84  int SPAdj, unsigned FIOperandNum,
85  RegScavenger *RS) const {
86  assert(SPAdj == 0 && "Unexpected non-zero SPAdj value");
87 
88  MachineInstr &MI = *II;
89  MachineFunction &MF = *MI.getParent()->getParent();
91  const RISCVInstrInfo *TII = MF.getSubtarget<RISCVSubtarget>().getInstrInfo();
92  DebugLoc DL = MI.getDebugLoc();
93 
94  int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
95  unsigned FrameReg;
96  int Offset =
97  getFrameLowering(MF)->getFrameIndexReference(MF, FrameIndex, FrameReg) +
98  MI.getOperand(FIOperandNum + 1).getImm();
99 
100  if (!isInt<32>(Offset)) {
102  "Frame offsets outside of the signed 32-bit range not supported");
103  }
104 
105  MachineBasicBlock &MBB = *MI.getParent();
106  bool FrameRegIsKill = false;
107 
108  if (!isInt<12>(Offset)) {
109  assert(isInt<32>(Offset) && "Int32 expected");
110  // The offset won't fit in an immediate, so use a scratch register instead
111  // Modify Offset and FrameReg appropriately
112  Register ScratchReg = MRI.createVirtualRegister(&RISCV::GPRRegClass);
113  TII->movImm(MBB, II, DL, ScratchReg, Offset);
114  BuildMI(MBB, II, DL, TII->get(RISCV::ADD), ScratchReg)
115  .addReg(FrameReg)
116  .addReg(ScratchReg, RegState::Kill);
117  Offset = 0;
118  FrameReg = ScratchReg;
119  FrameRegIsKill = true;
120  }
121 
122  MI.getOperand(FIOperandNum)
123  .ChangeToRegister(FrameReg, false, false, FrameRegIsKill);
124  MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
125 }
126 
128  const TargetFrameLowering *TFI = getFrameLowering(MF);
129  return TFI->hasFP(MF) ? RISCV::X8 : RISCV::X2;
130 }
131 
132 const uint32_t *
134  CallingConv::ID /*CC*/) const {
135  auto &Subtarget = MF.getSubtarget<RISCVSubtarget>();
136  if (MF.getFunction().hasFnAttribute("interrupt")) {
137  if (Subtarget.hasStdExtD())
138  return CSR_XLEN_F64_Interrupt_RegMask;
139  if (Subtarget.hasStdExtF())
140  return CSR_XLEN_F32_Interrupt_RegMask;
141  return CSR_Interrupt_RegMask;
142  }
143 
144  switch (Subtarget.getTargetABI()) {
145  default:
146  llvm_unreachable("Unrecognized ABI");
147  case RISCVABI::ABI_ILP32:
148  case RISCVABI::ABI_LP64:
149  return CSR_ILP32_LP64_RegMask;
151  case RISCVABI::ABI_LP64F:
152  return CSR_ILP32F_LP64F_RegMask;
154  case RISCVABI::ABI_LP64D:
155  return CSR_ILP32D_LP64D_RegMask;
156  }
157 }
void movImm(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, Register DstReg, uint64_t Val, MachineInstr::MIFlag Flag=MachineInstr::NoFlags) const
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:139
This class represents lattice values for constants.
Definition: AllocatorList.h:23
Register getFrameRegister(const MachineFunction &MF) const override
const uint32_t * getNoPreservedMask() const override
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:385
BitVector getReservedRegs(const MachineFunction &MF) const override
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.h:323
A debug info location.
Definition: DebugLoc.h:33
bool isConstantPhysReg(unsigned PhysReg) const override
RISCVRegisterInfo(unsigned HwMode)
const HexagonInstrInfo * TII
virtual bool hasFP(const MachineFunction &MF) const =0
hasFP - Return true if the specified function should have a dedicated frame pointer register...
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:200
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const override
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
Definition: MCRegister.h:19
void ChangeToImmediate(int64_t ImmVal)
ChangeToImmediate - Replace this operand with a new immediate operand of the specified value...
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
This file declares the machine register scavenger class.
unsigned const MachineRegisterInfo * MRI
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
constexpr bool isInt< 32 >(int64_t x)
Definition: MathExtras.h:308
Information about stack frame layout on the target.
int64_t getImm() const
const Function & getFunction() const
Return the LLVM function that this machine code represents.
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:256
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
Definition: MachineInstr.h:64
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
void ChangeToRegister(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isDebug=false)
ChangeToRegister - Replace this operand with a new register operand of the specified value...
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
IRTranslator LLVM IR MI
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:416
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Wrapper class representing virtual and physical registers.
Definition: Register.h:19