AArch64PostLegalizerCombiner.cpp File Reference

Post-legalization combines on generic MachineInstrs. More...

#include "AArch64TargetMachine.h"
#include "llvm/CodeGen/GlobalISel/CSEInfo.h"
#include "llvm/CodeGen/GlobalISel/Combiner.h"
#include "llvm/CodeGen/GlobalISel/CombinerHelper.h"
#include "llvm/CodeGen/GlobalISel/CombinerInfo.h"
#include "llvm/CodeGen/GlobalISel/GISelChangeObserver.h"
#include "llvm/CodeGen/GlobalISel/GISelKnownBits.h"
#include "llvm/CodeGen/GlobalISel/GenericMachineInstrs.h"
#include "llvm/CodeGen/GlobalISel/MIPatternMatch.h"
#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
#include "llvm/CodeGen/GlobalISel/Utils.h"
#include "llvm/CodeGen/MachineDominators.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/TargetOpcodes.h"
#include "llvm/CodeGen/TargetPassConfig.h"
#include "llvm/Support/Debug.h"
#include "AArch64GenPostLegalizeGICombiner.inc"

Include dependency graph for AArch64PostLegalizerCombiner.cpp:

Go to the source code of this file.

Namespaces
namespace	llvm
	This is an optimization pass for GlobalISel generic memory operations.

Macros
#define	DEBUG_TYPE   "aarch64-postlegalizer-combiner"
#define	AARCH64POSTLEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_DEPS
#define	AARCH64POSTLEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_H
#define	AARCH64POSTLEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_CPP

Functions
bool	matchExtractVecEltPairwiseAdd (MachineInstr &MI, MachineRegisterInfo &MRI, std::tuple< unsigned, LLT, Register > &MatchInfo)
	This combine tries do what performExtractVectorEltCombine does in SDAG.
bool	applyExtractVecEltPairwiseAdd (MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B, std::tuple< unsigned, LLT, Register > &MatchInfo)
static bool	isSignExtended (Register R, MachineRegisterInfo &MRI)
static bool	isZeroExtended (Register R, MachineRegisterInfo &MRI)
bool	matchAArch64MulConstCombine (MachineInstr &MI, MachineRegisterInfo &MRI, std::function< void(MachineIRBuilder &B, Register DstReg)> &ApplyFn)
bool	applyAArch64MulConstCombine (MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B, std::function< void(MachineIRBuilder &B, Register DstReg)> &ApplyFn)
bool	matchFoldMergeToZext (MachineInstr &MI, MachineRegisterInfo &MRI)
	Try to fold a G_MERGE_VALUES of 2 s32 sources, where the second source is a zero, into a G_ZEXT of the first.
void	applyFoldMergeToZext (MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B, GISelChangeObserver &Observer)
static bool	matchMutateAnyExtToZExt (MachineInstr &MI, MachineRegisterInfo &MRI)
static void	applyMutateAnyExtToZExt (MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B, GISelChangeObserver &Observer)
static bool	matchSplitStoreZero128 (MachineInstr &MI, MachineRegisterInfo &MRI)
	Match a 128b store of zero and split it into two 64 bit stores, for size/performance reasons.
static void	applySplitStoreZero128 (MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B, GISelChangeObserver &Observer)
	INITIALIZE_PASS_BEGIN (AArch64PostLegalizerCombiner, DEBUG_TYPE, "Combine AArch64 MachineInstrs after legalization", false, false) INITIALIZE_PASS_END(AArch64PostLegalizerCombiner
FunctionPass *	llvm::createAArch64PostLegalizerCombiner (bool IsOptNone)

Variables
	DEBUG_TYPE
Combine AArch64 MachineInstrs after	legalization
Combine AArch64 MachineInstrs after	false

Detailed Description

Post-legalization combines on generic MachineInstrs.

The combines here must preserve instruction legality.

Lowering combines (e.g. pseudo matching) should be handled by AArch64PostLegalizerLowering.

Combines which don't rely on instruction legality should go in the AArch64PreLegalizerCombiner.

Definition in file AArch64PostLegalizerCombiner.cpp.

Macro Definition Documentation

AARCH64POSTLEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_CPP

#define AARCH64POSTLEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_CPP

Definition at line 372 of file AArch64PostLegalizerCombiner.cpp.

AARCH64POSTLEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_DEPS

#define AARCH64POSTLEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_DEPS

Definition at line 332 of file AArch64PostLegalizerCombiner.cpp.

AARCH64POSTLEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_H

#define AARCH64POSTLEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_H

Definition at line 337 of file AArch64PostLegalizerCombiner.cpp.

DEBUG_TYPE

#define DEBUG_TYPE   "aarch64-postlegalizer-combiner"

Definition at line 40 of file AArch64PostLegalizerCombiner.cpp.

Function Documentation

applyAArch64MulConstCombine()

bool applyAArch64MulConstCombine	(	MachineInstr &	MI,
		MachineRegisterInfo &	MRI,
		MachineIRBuilder &	B,
		std::function< void(MachineIRBuilder &B, Register DstReg)> &	ApplyFn
	)

Definition at line 237 of file AArch64PostLegalizerCombiner.cpp.

References B, and MI.

applyExtractVecEltPairwiseAdd()

bool applyExtractVecEltPairwiseAdd	(	MachineInstr &	MI,
		MachineRegisterInfo &	MRI,
		MachineIRBuilder &	B,
		std::tuple< unsigned, LLT, Register > &	MatchInfo
	)

Definition at line 96 of file AArch64PostLegalizerCombiner.cpp.

References assert(), B, getReg(), MI, and llvm::LLT::scalar().

applyFoldMergeToZext()

void applyFoldMergeToZext	(	MachineInstr &	MI,
		MachineRegisterInfo &	MRI,
		MachineIRBuilder &	B,
		GISelChangeObserver &	Observer
	)

Definition at line 256 of file AArch64PostLegalizerCombiner.cpp.

References B, llvm::GISelChangeObserver::changedInstr(), llvm::GISelChangeObserver::changingInstr(), and MI.

applyMutateAnyExtToZExt()

static void applyMutateAnyExtToZExt ( MachineInstr &  MI, MachineRegisterInfo &  MRI, MachineIRBuilder &  B, GISelChangeObserver &  Observer  )

static

Definition at line 286 of file AArch64PostLegalizerCombiner.cpp.

References B, llvm::GISelChangeObserver::changedInstr(), llvm::GISelChangeObserver::changingInstr(), and MI.

applySplitStoreZero128()

static void applySplitStoreZero128 ( MachineInstr &  MI, MachineRegisterInfo &  MRI, MachineIRBuilder &  B, GISelChangeObserver &  Observer  )

static

Definition at line 312 of file AArch64PostLegalizerCombiner.cpp.

References assert(), B, MI, MRI, and llvm::LLT::scalar().

INITIALIZE_PASS_BEGIN()

INITIALIZE_PASS_BEGIN	(	AArch64PostLegalizerCombiner	,
		DEBUG_TYPE	,
		"Combine AArch64 MachineInstrs after legalization"	,
		false	,
		false
	)

isSignExtended()

static bool isSignExtended ( Register  R, MachineRegisterInfo &  MRI  )

static

Definition at line 113 of file AArch64PostLegalizerCombiner.cpp.

References MRI.

Referenced by matchAArch64MulConstCombine().

isZeroExtended()

static bool isZeroExtended ( Register  R, MachineRegisterInfo &  MRI  )

static

Definition at line 119 of file AArch64PostLegalizerCombiner.cpp.

References MRI.

Referenced by matchAArch64MulConstCombine().

matchAArch64MulConstCombine()

bool matchAArch64MulConstCombine	(	MachineInstr &	MI,
		MachineRegisterInfo &	MRI,
		std::function< void(MachineIRBuilder &B, Register DstReg)> &	ApplyFn
	)

Definition at line 124 of file AArch64PostLegalizerCombiner.cpp.

References llvm::APInt::ashr(), assert(), B, llvm::APInt::countr_zero(), llvm::getIConstantVRegValWithLookThrough(), llvm::LLT::getSizeInBits(), llvm::APInt::isNonNegative(), llvm::APInt::isPowerOf2(), isSignExtended(), isZeroExtended(), LHS, llvm::APInt::logBase2(), MI, MRI, RHS, llvm::LLT::scalar(), and UseMI.

matchExtractVecEltPairwiseAdd()

bool matchExtractVecEltPairwiseAdd	(	MachineInstr &	MI,
		MachineRegisterInfo &	MRI,
		std::tuple< unsigned, LLT, Register > &	MatchInfo
	)

This combine tries do what performExtractVectorEltCombine does in SDAG.

Rewrite for pairwise fadd pattern (s32 (g_extract_vector_elt (g_fadd (vXs32 Other) (g_vector_shuffle (vXs32 Other) undef <1,X,...> )) 0)) -> (s32 (g_fadd (g_extract_vector_elt (vXs32 Other) 0) (g_extract_vector_elt (vXs32 Other) 1))

Definition at line 53 of file AArch64PostLegalizerCombiner.cpp.

References llvm::getIConstantVRegValWithLookThrough(), llvm::getOpcodeDef(), llvm::LLT::getSizeInBits(), MI, MRI, Other, and llvm::Shuffle.

matchFoldMergeToZext()

bool matchFoldMergeToZext	(	MachineInstr &	MI,
		MachineRegisterInfo &	MRI
	)

Try to fold a G_MERGE_VALUES of 2 s32 sources, where the second source is a zero, into a G_ZEXT of the first.

Definition at line 248 of file AArch64PostLegalizerCombiner.cpp.

References llvm::MIPatternMatch::m_SpecificICst(), Merge, MI, llvm::MIPatternMatch::mi_match(), MRI, and llvm::LLT::scalar().

matchMutateAnyExtToZExt()

static bool matchMutateAnyExtToZExt ( MachineInstr &  MI, MachineRegisterInfo &  MRI  )

static

Returns

True if a G_ANYEXT instruction MI should be mutated to a G_ZEXT instruction.

Definition at line 269 of file AArch64PostLegalizerCombiner.cpp.

References assert(), llvm::MIPatternMatch::m_any_of(), llvm::MIPatternMatch::m_GFCmp(), llvm::MIPatternMatch::m_GICmp(), llvm::MIPatternMatch::m_Pred(), llvm::MIPatternMatch::m_Reg(), MI, llvm::MIPatternMatch::mi_match(), and MRI.

matchSplitStoreZero128()

static bool matchSplitStoreZero128 ( MachineInstr &  MI, MachineRegisterInfo &  MRI  )

static

Match a 128b store of zero and split it into two 64 bit stores, for size/performance reasons.

Definition at line 296 of file AArch64PostLegalizerCombiner.cpp.

References llvm::LLT::getSizeInBits(), llvm::isConstantOrConstantSplatVector(), llvm::LLT::isVector(), MI, and MRI.

Variable Documentation

DEBUG_TYPE

DEBUG_TYPE

Definition at line 443 of file AArch64PostLegalizerCombiner.cpp.

false

Combine AArch64 MachineInstrs after false

Definition at line 444 of file AArch64PostLegalizerCombiner.cpp.

legalization

Combine AArch64 MachineInstrs after legalization

Definition at line 444 of file AArch64PostLegalizerCombiner.cpp.