LLVM 18.0.0git
GenericMachineInstrs.h
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1//===- llvm/CodeGen/GlobalISel/GenericMachineInstrs.h -----------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8/// \file
9/// Declares convenience wrapper classes for interpreting MachineInstr instances
10/// as specific generic operations.
11///
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_CODEGEN_GLOBALISEL_GENERICMACHINEINSTRS_H
15#define LLVM_CODEGEN_GLOBALISEL_GENERICMACHINEINSTRS_H
16
22
23namespace llvm {
24
25/// A base class for all GenericMachineInstrs.
27public:
29
30 /// Access the Idx'th operand as a register and return it.
31 /// This assumes that the Idx'th operand is a Register type.
32 Register getReg(unsigned Idx) const { return getOperand(Idx).getReg(); }
33
34 static bool classof(const MachineInstr *MI) {
35 return isPreISelGenericOpcode(MI->getOpcode());
36 }
37};
38
39/// Provides common memory operand functionality.
41public:
42 /// Get the MachineMemOperand on this instruction.
44
45 /// Returns true if the attached MachineMemOperand has the atomic flag set.
46 bool isAtomic() const { return getMMO().isAtomic(); }
47 /// Returns true if the attached MachineMemOpeand as the volatile flag set.
48 bool isVolatile() const { return getMMO().isVolatile(); }
49 /// Returns true if the memory operation is neither atomic or volatile.
50 bool isSimple() const { return !isAtomic() && !isVolatile(); }
51 /// Returns true if this memory operation doesn't have any ordering
52 /// constraints other than normal aliasing. Volatile and (ordered) atomic
53 /// memory operations can't be reordered.
54 bool isUnordered() const { return getMMO().isUnordered(); }
55
56 /// Returns the size in bytes of the memory access.
57 uint64_t getMemSize() const { return getMMO().getSize();
58 } /// Returns the size in bits of the memory access.
60
61 static bool classof(const MachineInstr *MI) {
62 return GenericMachineInstr::classof(MI) && MI->hasOneMemOperand();
63 }
64};
65
66/// Represents any type of generic load or store.
67/// G_LOAD, G_STORE, G_ZEXTLOAD, G_SEXTLOAD.
68class GLoadStore : public GMemOperation {
69public:
70 /// Get the source register of the pointer value.
71 Register getPointerReg() const { return getOperand(1).getReg(); }
72
73 static bool classof(const MachineInstr *MI) {
74 switch (MI->getOpcode()) {
75 case TargetOpcode::G_LOAD:
76 case TargetOpcode::G_STORE:
77 case TargetOpcode::G_ZEXTLOAD:
78 case TargetOpcode::G_SEXTLOAD:
79 return true;
80 default:
81 return false;
82 }
83 }
84};
85
86/// Represents indexed loads. These are different enough from regular loads
87/// that they get their own class. Including them in GAnyLoad would probably
88/// make a footgun for someone.
90public:
91 /// Get the definition register of the loaded value.
92 Register getDstReg() const { return getOperand(0).getReg(); }
93 /// Get the def register of the writeback value.
94 Register getWritebackReg() const { return getOperand(1).getReg(); }
95 /// Get the base register of the pointer value.
96 Register getBaseReg() const { return getOperand(2).getReg(); }
97 /// Get the offset register of the pointer value.
98 Register getOffsetReg() const { return getOperand(3).getReg(); }
99
100 bool isPre() const { return getOperand(5).getImm() == 1; }
101 bool isPost() const { return !isPre(); }
102
103 static bool classof(const MachineInstr *MI) {
104 return MI->getOpcode() == TargetOpcode::G_INDEXED_LOAD;
105 }
106};
107
108/// Represents a G_INDEX_ZEXTLOAD/G_INDEXED_SEXTLOAD.
110public:
111 static bool classof(const MachineInstr *MI) {
112 return MI->getOpcode() == TargetOpcode::G_INDEXED_SEXTLOAD ||
113 MI->getOpcode() == TargetOpcode::G_INDEXED_ZEXTLOAD;
114 }
115};
116
117/// Represents a G_ZEXTLOAD.
119public:
120 static bool classof(const MachineInstr *MI) {
121 return MI->getOpcode() == TargetOpcode::G_INDEXED_ZEXTLOAD;
122 }
123};
124
125/// Represents a G_SEXTLOAD.
127public:
128 static bool classof(const MachineInstr *MI) {
129 return MI->getOpcode() == TargetOpcode::G_INDEXED_SEXTLOAD;
130 }
131};
132
133/// Represents indexed stores.
135public:
136 /// Get the def register of the writeback value.
137 Register getWritebackReg() const { return getOperand(0).getReg(); }
138 /// Get the stored value register.
139 Register getValueReg() const { return getOperand(1).getReg(); }
140 /// Get the base register of the pointer value.
141 Register getBaseReg() const { return getOperand(2).getReg(); }
142 /// Get the offset register of the pointer value.
143 Register getOffsetReg() const { return getOperand(3).getReg(); }
144
145 bool isPre() const { return getOperand(4).getImm() == 1; }
146 bool isPost() const { return !isPre(); }
147
148 static bool classof(const MachineInstr *MI) {
149 return MI->getOpcode() == TargetOpcode::G_INDEXED_STORE;
150 }
151};
152
153/// Represents any generic load, including sign/zero extending variants.
154class GAnyLoad : public GLoadStore {
155public:
156 /// Get the definition register of the loaded value.
157 Register getDstReg() const { return getOperand(0).getReg(); }
158
159 static bool classof(const MachineInstr *MI) {
160 switch (MI->getOpcode()) {
161 case TargetOpcode::G_LOAD:
162 case TargetOpcode::G_ZEXTLOAD:
163 case TargetOpcode::G_SEXTLOAD:
164 return true;
165 default:
166 return false;
167 }
168 }
169};
170
171/// Represents a G_LOAD.
172class GLoad : public GAnyLoad {
173public:
174 static bool classof(const MachineInstr *MI) {
175 return MI->getOpcode() == TargetOpcode::G_LOAD;
176 }
177};
178
179/// Represents either a G_SEXTLOAD or G_ZEXTLOAD.
180class GExtLoad : public GAnyLoad {
181public:
182 static bool classof(const MachineInstr *MI) {
183 return MI->getOpcode() == TargetOpcode::G_SEXTLOAD ||
184 MI->getOpcode() == TargetOpcode::G_ZEXTLOAD;
185 }
186};
187
188/// Represents a G_SEXTLOAD.
189class GSExtLoad : public GExtLoad {
190public:
191 static bool classof(const MachineInstr *MI) {
192 return MI->getOpcode() == TargetOpcode::G_SEXTLOAD;
193 }
194};
195
196/// Represents a G_ZEXTLOAD.
197class GZExtLoad : public GExtLoad {
198public:
199 static bool classof(const MachineInstr *MI) {
200 return MI->getOpcode() == TargetOpcode::G_ZEXTLOAD;
201 }
202};
203
204/// Represents a G_STORE.
205class GStore : public GLoadStore {
206public:
207 /// Get the stored value register.
208 Register getValueReg() const { return getOperand(0).getReg(); }
209
210 static bool classof(const MachineInstr *MI) {
211 return MI->getOpcode() == TargetOpcode::G_STORE;
212 }
213};
214
215/// Represents a G_UNMERGE_VALUES.
217public:
218 /// Returns the number of def registers.
219 unsigned getNumDefs() const { return getNumOperands() - 1; }
220 /// Get the unmerge source register.
222
223 static bool classof(const MachineInstr *MI) {
224 return MI->getOpcode() == TargetOpcode::G_UNMERGE_VALUES;
225 }
226};
227
228/// Represents G_BUILD_VECTOR, G_CONCAT_VECTORS or G_MERGE_VALUES.
229/// All these have the common property of generating a single value from
230/// multiple sources.
232public:
233 /// Returns the number of source registers.
234 unsigned getNumSources() const { return getNumOperands() - 1; }
235 /// Returns the I'th source register.
236 Register getSourceReg(unsigned I) const { return getReg(I + 1); }
237
238 static bool classof(const MachineInstr *MI) {
239 switch (MI->getOpcode()) {
240 case TargetOpcode::G_MERGE_VALUES:
241 case TargetOpcode::G_CONCAT_VECTORS:
242 case TargetOpcode::G_BUILD_VECTOR:
243 return true;
244 default:
245 return false;
246 }
247 }
248};
249
250/// Represents a G_MERGE_VALUES.
251class GMerge : public GMergeLikeInstr {
252public:
253 static bool classof(const MachineInstr *MI) {
254 return MI->getOpcode() == TargetOpcode::G_MERGE_VALUES;
255 }
256};
257
258/// Represents a G_CONCAT_VECTORS.
260public:
261 static bool classof(const MachineInstr *MI) {
262 return MI->getOpcode() == TargetOpcode::G_CONCAT_VECTORS;
263 }
264};
265
266/// Represents a G_BUILD_VECTOR.
268public:
269 static bool classof(const MachineInstr *MI) {
270 return MI->getOpcode() == TargetOpcode::G_BUILD_VECTOR;
271 }
272};
273
274/// Represents a G_PTR_ADD.
276public:
277 Register getBaseReg() const { return getReg(1); }
278 Register getOffsetReg() const { return getReg(2); }
279
280 static bool classof(const MachineInstr *MI) {
281 return MI->getOpcode() == TargetOpcode::G_PTR_ADD;
282 }
283};
284
285/// Represents a G_IMPLICIT_DEF.
287public:
288 static bool classof(const MachineInstr *MI) {
289 return MI->getOpcode() == TargetOpcode::G_IMPLICIT_DEF;
290 }
291};
292
293/// Represents a G_SELECT.
295public:
296 Register getCondReg() const { return getReg(1); }
297 Register getTrueReg() const { return getReg(2); }
298 Register getFalseReg() const { return getReg(3); }
299
300 static bool classof(const MachineInstr *MI) {
301 return MI->getOpcode() == TargetOpcode::G_SELECT;
302 }
303};
304
305/// Represent a G_ICMP or G_FCMP.
307public:
309 return static_cast<CmpInst::Predicate>(getOperand(1).getPredicate());
310 }
311 Register getLHSReg() const { return getReg(2); }
312 Register getRHSReg() const { return getReg(3); }
313
314 static bool classof(const MachineInstr *MI) {
315 return MI->getOpcode() == TargetOpcode::G_ICMP ||
316 MI->getOpcode() == TargetOpcode::G_FCMP;
317 }
318};
319
320/// Represent a G_ICMP.
321class GICmp : public GAnyCmp {
322public:
323 static bool classof(const MachineInstr *MI) {
324 return MI->getOpcode() == TargetOpcode::G_ICMP;
325 }
326};
327
328/// Represent a G_FCMP.
329class GFCmp : public GAnyCmp {
330public:
331 static bool classof(const MachineInstr *MI) {
332 return MI->getOpcode() == TargetOpcode::G_FCMP;
333 }
334};
335
336/// Represents overflowing binary operations.
337/// Only carry-out:
338/// G_UADDO, G_SADDO, G_USUBO, G_SSUBO, G_UMULO, G_SMULO
339/// Carry-in and carry-out:
340/// G_UADDE, G_SADDE, G_USUBE, G_SSUBE
342public:
343 Register getDstReg() const { return getReg(0); }
344 Register getCarryOutReg() const { return getReg(1); }
347
348 static bool classof(const MachineInstr *MI) {
349 switch (MI->getOpcode()) {
350 case TargetOpcode::G_UADDO:
351 case TargetOpcode::G_SADDO:
352 case TargetOpcode::G_USUBO:
353 case TargetOpcode::G_SSUBO:
354 case TargetOpcode::G_UADDE:
355 case TargetOpcode::G_SADDE:
356 case TargetOpcode::G_USUBE:
357 case TargetOpcode::G_SSUBE:
358 case TargetOpcode::G_UMULO:
359 case TargetOpcode::G_SMULO:
360 return true;
361 default:
362 return false;
363 }
364 }
365};
366
367/// Represents overflowing add/sub operations.
368/// Only carry-out:
369/// G_UADDO, G_SADDO, G_USUBO, G_SSUBO
370/// Carry-in and carry-out:
371/// G_UADDE, G_SADDE, G_USUBE, G_SSUBE
373public:
374 bool isAdd() const {
375 switch (getOpcode()) {
376 case TargetOpcode::G_UADDO:
377 case TargetOpcode::G_SADDO:
378 case TargetOpcode::G_UADDE:
379 case TargetOpcode::G_SADDE:
380 return true;
381 default:
382 return false;
383 }
384 }
385 bool isSub() const { return !isAdd(); }
386
387 bool isSigned() const {
388 switch (getOpcode()) {
389 case TargetOpcode::G_SADDO:
390 case TargetOpcode::G_SSUBO:
391 case TargetOpcode::G_SADDE:
392 case TargetOpcode::G_SSUBE:
393 return true;
394 default:
395 return false;
396 }
397 }
398 bool isUnsigned() const { return !isSigned(); }
399
400 static bool classof(const MachineInstr *MI) {
401 switch (MI->getOpcode()) {
402 case TargetOpcode::G_UADDO:
403 case TargetOpcode::G_SADDO:
404 case TargetOpcode::G_USUBO:
405 case TargetOpcode::G_SSUBO:
406 case TargetOpcode::G_UADDE:
407 case TargetOpcode::G_SADDE:
408 case TargetOpcode::G_USUBE:
409 case TargetOpcode::G_SSUBE:
410 return true;
411 default:
412 return false;
413 }
414 }
415};
416
417/// Represents overflowing add/sub operations that also consume a carry-in.
418/// G_UADDE, G_SADDE, G_USUBE, G_SSUBE
420public:
421 Register getCarryInReg() const { return getReg(4); }
422
423 static bool classof(const MachineInstr *MI) {
424 switch (MI->getOpcode()) {
425 case TargetOpcode::G_UADDE:
426 case TargetOpcode::G_SADDE:
427 case TargetOpcode::G_USUBE:
428 case TargetOpcode::G_SSUBE:
429 return true;
430 default:
431 return false;
432 }
433 }
434};
435
436/// Represents a call to an intrinsic.
437class GIntrinsic final : public GenericMachineInstr {
438public:
441 }
442
443 bool is(Intrinsic::ID ID) const { return getIntrinsicID() == ID; }
444
445 bool hasSideEffects() const {
446 switch (getOpcode()) {
447 case TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS:
448 case TargetOpcode::G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS:
449 return true;
450 default:
451 return false;
452 }
453 }
454
455 bool isConvergent() const {
456 switch (getOpcode()) {
457 case TargetOpcode::G_INTRINSIC_CONVERGENT:
458 case TargetOpcode::G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS:
459 return true;
460 default:
461 return false;
462 }
463 }
464
465 static bool classof(const MachineInstr *MI) {
466 switch (MI->getOpcode()) {
467 case TargetOpcode::G_INTRINSIC:
468 case TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS:
469 case TargetOpcode::G_INTRINSIC_CONVERGENT:
470 case TargetOpcode::G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS:
471 return true;
472 default:
473 return false;
474 }
475 }
476};
477
478// Represents a (non-sequential) vector reduction operation.
480public:
481 static bool classof(const MachineInstr *MI) {
482 switch (MI->getOpcode()) {
483 case TargetOpcode::G_VECREDUCE_FADD:
484 case TargetOpcode::G_VECREDUCE_FMUL:
485 case TargetOpcode::G_VECREDUCE_FMAX:
486 case TargetOpcode::G_VECREDUCE_FMIN:
487 case TargetOpcode::G_VECREDUCE_FMAXIMUM:
488 case TargetOpcode::G_VECREDUCE_FMINIMUM:
489 case TargetOpcode::G_VECREDUCE_ADD:
490 case TargetOpcode::G_VECREDUCE_MUL:
491 case TargetOpcode::G_VECREDUCE_AND:
492 case TargetOpcode::G_VECREDUCE_OR:
493 case TargetOpcode::G_VECREDUCE_XOR:
494 case TargetOpcode::G_VECREDUCE_SMAX:
495 case TargetOpcode::G_VECREDUCE_SMIN:
496 case TargetOpcode::G_VECREDUCE_UMAX:
497 case TargetOpcode::G_VECREDUCE_UMIN:
498 return true;
499 default:
500 return false;
501 }
502 }
503
504 /// Get the opcode for the equivalent scalar operation for this reduction.
505 /// E.g. for G_VECREDUCE_FADD, this returns G_FADD.
507 unsigned ScalarOpc;
508 switch (getOpcode()) {
509 case TargetOpcode::G_VECREDUCE_FADD:
510 ScalarOpc = TargetOpcode::G_FADD;
511 break;
512 case TargetOpcode::G_VECREDUCE_FMUL:
513 ScalarOpc = TargetOpcode::G_FMUL;
514 break;
515 case TargetOpcode::G_VECREDUCE_FMAX:
516 ScalarOpc = TargetOpcode::G_FMAXNUM;
517 break;
518 case TargetOpcode::G_VECREDUCE_FMIN:
519 ScalarOpc = TargetOpcode::G_FMINNUM;
520 break;
521 case TargetOpcode::G_VECREDUCE_FMAXIMUM:
522 ScalarOpc = TargetOpcode::G_FMAXIMUM;
523 break;
524 case TargetOpcode::G_VECREDUCE_FMINIMUM:
525 ScalarOpc = TargetOpcode::G_FMINIMUM;
526 break;
527 case TargetOpcode::G_VECREDUCE_ADD:
528 ScalarOpc = TargetOpcode::G_ADD;
529 break;
530 case TargetOpcode::G_VECREDUCE_MUL:
531 ScalarOpc = TargetOpcode::G_MUL;
532 break;
533 case TargetOpcode::G_VECREDUCE_AND:
534 ScalarOpc = TargetOpcode::G_AND;
535 break;
536 case TargetOpcode::G_VECREDUCE_OR:
537 ScalarOpc = TargetOpcode::G_OR;
538 break;
539 case TargetOpcode::G_VECREDUCE_XOR:
540 ScalarOpc = TargetOpcode::G_XOR;
541 break;
542 case TargetOpcode::G_VECREDUCE_SMAX:
543 ScalarOpc = TargetOpcode::G_SMAX;
544 break;
545 case TargetOpcode::G_VECREDUCE_SMIN:
546 ScalarOpc = TargetOpcode::G_SMIN;
547 break;
548 case TargetOpcode::G_VECREDUCE_UMAX:
549 ScalarOpc = TargetOpcode::G_UMAX;
550 break;
551 case TargetOpcode::G_VECREDUCE_UMIN:
552 ScalarOpc = TargetOpcode::G_UMIN;
553 break;
554 default:
555 llvm_unreachable("Unhandled reduction");
556 }
557 return ScalarOpc;
558 }
559};
560
561
562} // namespace llvm
563
564#endif // LLVM_CODEGEN_GLOBALISEL_GENERICMACHINEINSTRS_H
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
IRTranslator LLVM IR MI
#define I(x, y, z)
Definition: MD5.cpp:58
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:711
Represents overflowing add/sub operations that also consume a carry-in.
static bool classof(const MachineInstr *MI)
Represents overflowing add/sub operations.
static bool classof(const MachineInstr *MI)
Represent a G_ICMP or G_FCMP.
static bool classof(const MachineInstr *MI)
CmpInst::Predicate getCond() const
Register getLHSReg() const
Register getRHSReg() const
Represents any generic load, including sign/zero extending variants.
Register getDstReg() const
Get the definition register of the loaded value.
static bool classof(const MachineInstr *MI)
Represents overflowing binary operations.
MachineOperand & getRHS()
MachineOperand & getLHS()
Register getCarryOutReg() const
Register getDstReg() const
static bool classof(const MachineInstr *MI)
Represents a G_BUILD_VECTOR.
static bool classof(const MachineInstr *MI)
Represents a G_CONCAT_VECTORS.
static bool classof(const MachineInstr *MI)
Represents either a G_SEXTLOAD or G_ZEXTLOAD.
static bool classof(const MachineInstr *MI)
Represent a G_FCMP.
static bool classof(const MachineInstr *MI)
Represent a G_ICMP.
static bool classof(const MachineInstr *MI)
Represents a G_IMPLICIT_DEF.
static bool classof(const MachineInstr *MI)
Represents a G_INDEX_ZEXTLOAD/G_INDEXED_SEXTLOAD.
static bool classof(const MachineInstr *MI)
Represents indexed loads.
static bool classof(const MachineInstr *MI)
Register getOffsetReg() const
Get the offset register of the pointer value.
Register getWritebackReg() const
Get the def register of the writeback value.
Register getDstReg() const
Get the definition register of the loaded value.
Register getBaseReg() const
Get the base register of the pointer value.
Represents a G_SEXTLOAD.
static bool classof(const MachineInstr *MI)
Represents indexed stores.
Register getOffsetReg() const
Get the offset register of the pointer value.
Register getValueReg() const
Get the stored value register.
Register getBaseReg() const
Get the base register of the pointer value.
static bool classof(const MachineInstr *MI)
Register getWritebackReg() const
Get the def register of the writeback value.
Represents a G_ZEXTLOAD.
static bool classof(const MachineInstr *MI)
Represents a call to an intrinsic.
Intrinsic::ID getIntrinsicID() const
bool is(Intrinsic::ID ID) const
static bool classof(const MachineInstr *MI)
bool hasSideEffects() const
Represents any type of generic load or store.
Register getPointerReg() const
Get the source register of the pointer value.
static bool classof(const MachineInstr *MI)
Represents a G_LOAD.
static bool classof(const MachineInstr *MI)
Provides common memory operand functionality.
MachineMemOperand & getMMO() const
Get the MachineMemOperand on this instruction.
bool isUnordered() const
Returns true if this memory operation doesn't have any ordering constraints other than normal aliasin...
bool isAtomic() const
Returns true if the attached MachineMemOperand has the atomic flag set.
bool isVolatile() const
Returns true if the attached MachineMemOpeand as the volatile flag set.
static bool classof(const MachineInstr *MI)
uint64_t getMemSizeInBits() const
Returns the size in bits of the memory access.
bool isSimple() const
Returns true if the memory operation is neither atomic or volatile.
uint64_t getMemSize() const
Returns the size in bytes of the memory access.
Represents G_BUILD_VECTOR, G_CONCAT_VECTORS or G_MERGE_VALUES.
Register getSourceReg(unsigned I) const
Returns the I'th source register.
unsigned getNumSources() const
Returns the number of source registers.
static bool classof(const MachineInstr *MI)
Represents a G_MERGE_VALUES.
static bool classof(const MachineInstr *MI)
Represents a G_PTR_ADD.
Register getOffsetReg() const
static bool classof(const MachineInstr *MI)
Register getBaseReg() const
Represents a G_SEXTLOAD.
static bool classof(const MachineInstr *MI)
Represents a G_SELECT.
Register getCondReg() const
static bool classof(const MachineInstr *MI)
Register getFalseReg() const
Register getTrueReg() const
Represents a G_STORE.
static bool classof(const MachineInstr *MI)
Register getValueReg() const
Get the stored value register.
Represents a G_UNMERGE_VALUES.
unsigned getNumDefs() const
Returns the number of def registers.
static bool classof(const MachineInstr *MI)
Register getSourceReg() const
Get the unmerge source register.
unsigned getScalarOpcForReduction()
Get the opcode for the equivalent scalar operation for this reduction.
static bool classof(const MachineInstr *MI)
Represents a G_ZEXTLOAD.
static bool classof(const MachineInstr *MI)
A base class for all GenericMachineInstrs.
static bool classof(const MachineInstr *MI)
Register getReg(unsigned Idx) const
Access the Idx'th operand as a register and return it.
Representation of each machine instruction.
Definition: MachineInstr.h:68
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:543
unsigned getNumOperands() const
Retuns the total number of operands.
Definition: MachineInstr.h:546
unsigned getNumExplicitDefs() const
Returns the number of non-implicit definitions.
mmo_iterator memoperands_begin() const
Access to memory operands of the instruction.
Definition: MachineInstr.h:774
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:553
A description of a memory reference used in the backend.
bool isUnordered() const
Returns true if this memory operation doesn't have any ordering constraints other than normal aliasin...
bool isAtomic() const
Returns true if this operation has an atomic ordering requirement of unordered or higher,...
uint64_t getSize() const
Return the size in bytes of the memory reference.
uint64_t getSizeInBits() const
Return the size in bits of the memory reference.
MachineOperand class - Representation of each machine instruction operand.
int64_t getImm() const
Register getReg() const
getReg - Returns the register number.
Intrinsic::ID getIntrinsicID() const
unsigned getPredicate() const
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
bool isPreISelGenericOpcode(unsigned Opcode)
Check whether the given Opcode is a generic opcode that is not supposed to appear after ISel.
Definition: TargetOpcodes.h:30