14#ifndef LLVM_CODEGEN_GLOBALISEL_GENERICMACHINEINSTRS_H
15#define LLVM_CODEGEN_GLOBALISEL_GENERICMACHINEINSTRS_H
74 switch (
MI->getOpcode()) {
75 case TargetOpcode::G_LOAD:
76 case TargetOpcode::G_STORE:
77 case TargetOpcode::G_ZEXTLOAD:
78 case TargetOpcode::G_SEXTLOAD:
104 return MI->getOpcode() == TargetOpcode::G_INDEXED_LOAD;
112 return MI->getOpcode() == TargetOpcode::G_INDEXED_SEXTLOAD ||
113 MI->getOpcode() == TargetOpcode::G_INDEXED_ZEXTLOAD;
121 return MI->getOpcode() == TargetOpcode::G_INDEXED_ZEXTLOAD;
129 return MI->getOpcode() == TargetOpcode::G_INDEXED_SEXTLOAD;
149 return MI->getOpcode() == TargetOpcode::G_INDEXED_STORE;
160 switch (
MI->getOpcode()) {
161 case TargetOpcode::G_LOAD:
162 case TargetOpcode::G_ZEXTLOAD:
163 case TargetOpcode::G_SEXTLOAD:
175 return MI->getOpcode() == TargetOpcode::G_LOAD;
183 return MI->getOpcode() == TargetOpcode::G_SEXTLOAD ||
184 MI->getOpcode() == TargetOpcode::G_ZEXTLOAD;
192 return MI->getOpcode() == TargetOpcode::G_SEXTLOAD;
200 return MI->getOpcode() == TargetOpcode::G_ZEXTLOAD;
211 return MI->getOpcode() == TargetOpcode::G_STORE;
224 return MI->getOpcode() == TargetOpcode::G_UNMERGE_VALUES;
239 switch (
MI->getOpcode()) {
240 case TargetOpcode::G_MERGE_VALUES:
241 case TargetOpcode::G_CONCAT_VECTORS:
242 case TargetOpcode::G_BUILD_VECTOR:
254 return MI->getOpcode() == TargetOpcode::G_MERGE_VALUES;
262 return MI->getOpcode() == TargetOpcode::G_CONCAT_VECTORS;
270 return MI->getOpcode() == TargetOpcode::G_BUILD_VECTOR;
281 return MI->getOpcode() == TargetOpcode::G_PTR_ADD;
289 return MI->getOpcode() == TargetOpcode::G_IMPLICIT_DEF;
301 return MI->getOpcode() == TargetOpcode::G_SELECT;
315 return MI->getOpcode() == TargetOpcode::G_ICMP ||
316 MI->getOpcode() == TargetOpcode::G_FCMP;
324 return MI->getOpcode() == TargetOpcode::G_ICMP;
332 return MI->getOpcode() == TargetOpcode::G_FCMP;
349 switch (
MI->getOpcode()) {
350 case TargetOpcode::G_UADDO:
351 case TargetOpcode::G_SADDO:
352 case TargetOpcode::G_USUBO:
353 case TargetOpcode::G_SSUBO:
354 case TargetOpcode::G_UADDE:
355 case TargetOpcode::G_SADDE:
356 case TargetOpcode::G_USUBE:
357 case TargetOpcode::G_SSUBE:
358 case TargetOpcode::G_UMULO:
359 case TargetOpcode::G_SMULO:
376 case TargetOpcode::G_UADDO:
377 case TargetOpcode::G_SADDO:
378 case TargetOpcode::G_UADDE:
379 case TargetOpcode::G_SADDE:
389 case TargetOpcode::G_SADDO:
390 case TargetOpcode::G_SSUBO:
391 case TargetOpcode::G_SADDE:
392 case TargetOpcode::G_SSUBE:
401 switch (
MI->getOpcode()) {
402 case TargetOpcode::G_UADDO:
403 case TargetOpcode::G_SADDO:
404 case TargetOpcode::G_USUBO:
405 case TargetOpcode::G_SSUBO:
406 case TargetOpcode::G_UADDE:
407 case TargetOpcode::G_SADDE:
408 case TargetOpcode::G_USUBE:
409 case TargetOpcode::G_SSUBE:
424 switch (
MI->getOpcode()) {
425 case TargetOpcode::G_UADDE:
426 case TargetOpcode::G_SADDE:
427 case TargetOpcode::G_USUBE:
428 case TargetOpcode::G_SSUBE:
447 case TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS:
448 case TargetOpcode::G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS:
457 case TargetOpcode::G_INTRINSIC_CONVERGENT:
458 case TargetOpcode::G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS:
466 switch (
MI->getOpcode()) {
467 case TargetOpcode::G_INTRINSIC:
468 case TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS:
469 case TargetOpcode::G_INTRINSIC_CONVERGENT:
470 case TargetOpcode::G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS:
482 switch (
MI->getOpcode()) {
483 case TargetOpcode::G_VECREDUCE_FADD:
484 case TargetOpcode::G_VECREDUCE_FMUL:
485 case TargetOpcode::G_VECREDUCE_FMAX:
486 case TargetOpcode::G_VECREDUCE_FMIN:
487 case TargetOpcode::G_VECREDUCE_FMAXIMUM:
488 case TargetOpcode::G_VECREDUCE_FMINIMUM:
489 case TargetOpcode::G_VECREDUCE_ADD:
490 case TargetOpcode::G_VECREDUCE_MUL:
491 case TargetOpcode::G_VECREDUCE_AND:
492 case TargetOpcode::G_VECREDUCE_OR:
493 case TargetOpcode::G_VECREDUCE_XOR:
494 case TargetOpcode::G_VECREDUCE_SMAX:
495 case TargetOpcode::G_VECREDUCE_SMIN:
496 case TargetOpcode::G_VECREDUCE_UMAX:
497 case TargetOpcode::G_VECREDUCE_UMIN:
509 case TargetOpcode::G_VECREDUCE_FADD:
510 ScalarOpc = TargetOpcode::G_FADD;
512 case TargetOpcode::G_VECREDUCE_FMUL:
513 ScalarOpc = TargetOpcode::G_FMUL;
515 case TargetOpcode::G_VECREDUCE_FMAX:
516 ScalarOpc = TargetOpcode::G_FMAXNUM;
518 case TargetOpcode::G_VECREDUCE_FMIN:
519 ScalarOpc = TargetOpcode::G_FMINNUM;
521 case TargetOpcode::G_VECREDUCE_FMAXIMUM:
522 ScalarOpc = TargetOpcode::G_FMAXIMUM;
524 case TargetOpcode::G_VECREDUCE_FMINIMUM:
525 ScalarOpc = TargetOpcode::G_FMINIMUM;
527 case TargetOpcode::G_VECREDUCE_ADD:
528 ScalarOpc = TargetOpcode::G_ADD;
530 case TargetOpcode::G_VECREDUCE_MUL:
531 ScalarOpc = TargetOpcode::G_MUL;
533 case TargetOpcode::G_VECREDUCE_AND:
534 ScalarOpc = TargetOpcode::G_AND;
536 case TargetOpcode::G_VECREDUCE_OR:
537 ScalarOpc = TargetOpcode::G_OR;
539 case TargetOpcode::G_VECREDUCE_XOR:
540 ScalarOpc = TargetOpcode::G_XOR;
542 case TargetOpcode::G_VECREDUCE_SMAX:
543 ScalarOpc = TargetOpcode::G_SMAX;
545 case TargetOpcode::G_VECREDUCE_SMIN:
546 ScalarOpc = TargetOpcode::G_SMIN;
548 case TargetOpcode::G_VECREDUCE_UMAX:
549 ScalarOpc = TargetOpcode::G_UMAX;
551 case TargetOpcode::G_VECREDUCE_UMIN:
552 ScalarOpc = TargetOpcode::G_UMIN;
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Represents overflowing add/sub operations that also consume a carry-in.
Register getCarryInReg() const
static bool classof(const MachineInstr *MI)
Represents overflowing add/sub operations.
static bool classof(const MachineInstr *MI)
Represent a G_ICMP or G_FCMP.
static bool classof(const MachineInstr *MI)
CmpInst::Predicate getCond() const
Register getLHSReg() const
Register getRHSReg() const
Represents any generic load, including sign/zero extending variants.
Register getDstReg() const
Get the definition register of the loaded value.
static bool classof(const MachineInstr *MI)
Represents overflowing binary operations.
MachineOperand & getRHS()
MachineOperand & getLHS()
Register getCarryOutReg() const
Register getDstReg() const
static bool classof(const MachineInstr *MI)
Represents a G_BUILD_VECTOR.
static bool classof(const MachineInstr *MI)
Represents a G_CONCAT_VECTORS.
static bool classof(const MachineInstr *MI)
Represents either a G_SEXTLOAD or G_ZEXTLOAD.
static bool classof(const MachineInstr *MI)
static bool classof(const MachineInstr *MI)
static bool classof(const MachineInstr *MI)
Represents a G_IMPLICIT_DEF.
static bool classof(const MachineInstr *MI)
Represents a G_INDEX_ZEXTLOAD/G_INDEXED_SEXTLOAD.
static bool classof(const MachineInstr *MI)
Represents indexed loads.
static bool classof(const MachineInstr *MI)
Register getOffsetReg() const
Get the offset register of the pointer value.
Register getWritebackReg() const
Get the def register of the writeback value.
Register getDstReg() const
Get the definition register of the loaded value.
Register getBaseReg() const
Get the base register of the pointer value.
static bool classof(const MachineInstr *MI)
Represents indexed stores.
Register getOffsetReg() const
Get the offset register of the pointer value.
Register getValueReg() const
Get the stored value register.
Register getBaseReg() const
Get the base register of the pointer value.
static bool classof(const MachineInstr *MI)
Register getWritebackReg() const
Get the def register of the writeback value.
static bool classof(const MachineInstr *MI)
Represents a call to an intrinsic.
bool isConvergent() const
Intrinsic::ID getIntrinsicID() const
bool is(Intrinsic::ID ID) const
static bool classof(const MachineInstr *MI)
bool hasSideEffects() const
Represents any type of generic load or store.
Register getPointerReg() const
Get the source register of the pointer value.
static bool classof(const MachineInstr *MI)
static bool classof(const MachineInstr *MI)
Provides common memory operand functionality.
MachineMemOperand & getMMO() const
Get the MachineMemOperand on this instruction.
bool isUnordered() const
Returns true if this memory operation doesn't have any ordering constraints other than normal aliasin...
bool isAtomic() const
Returns true if the attached MachineMemOperand has the atomic flag set.
bool isVolatile() const
Returns true if the attached MachineMemOpeand as the volatile flag set.
static bool classof(const MachineInstr *MI)
uint64_t getMemSizeInBits() const
Returns the size in bits of the memory access.
bool isSimple() const
Returns true if the memory operation is neither atomic or volatile.
uint64_t getMemSize() const
Returns the size in bytes of the memory access.
Represents G_BUILD_VECTOR, G_CONCAT_VECTORS or G_MERGE_VALUES.
Register getSourceReg(unsigned I) const
Returns the I'th source register.
unsigned getNumSources() const
Returns the number of source registers.
static bool classof(const MachineInstr *MI)
Represents a G_MERGE_VALUES.
static bool classof(const MachineInstr *MI)
Register getOffsetReg() const
static bool classof(const MachineInstr *MI)
Register getBaseReg() const
static bool classof(const MachineInstr *MI)
Register getCondReg() const
static bool classof(const MachineInstr *MI)
Register getFalseReg() const
Register getTrueReg() const
static bool classof(const MachineInstr *MI)
Register getValueReg() const
Get the stored value register.
Represents a G_UNMERGE_VALUES.
unsigned getNumDefs() const
Returns the number of def registers.
static bool classof(const MachineInstr *MI)
Register getSourceReg() const
Get the unmerge source register.
unsigned getScalarOpcForReduction()
Get the opcode for the equivalent scalar operation for this reduction.
static bool classof(const MachineInstr *MI)
static bool classof(const MachineInstr *MI)
A base class for all GenericMachineInstrs.
static bool classof(const MachineInstr *MI)
Register getReg(unsigned Idx) const
Access the Idx'th operand as a register and return it.
GenericMachineInstr()=delete
Representation of each machine instruction.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
unsigned getNumOperands() const
Retuns the total number of operands.
unsigned getNumExplicitDefs() const
Returns the number of non-implicit definitions.
mmo_iterator memoperands_begin() const
Access to memory operands of the instruction.
const MachineOperand & getOperand(unsigned i) const
A description of a memory reference used in the backend.
bool isUnordered() const
Returns true if this memory operation doesn't have any ordering constraints other than normal aliasin...
bool isAtomic() const
Returns true if this operation has an atomic ordering requirement of unordered or higher,...
uint64_t getSize() const
Return the size in bytes of the memory reference.
uint64_t getSizeInBits() const
Return the size in bits of the memory reference.
MachineOperand class - Representation of each machine instruction operand.
Register getReg() const
getReg - Returns the register number.
Intrinsic::ID getIntrinsicID() const
unsigned getPredicate() const
Wrapper class representing virtual and physical registers.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
This is an optimization pass for GlobalISel generic memory operations.
bool isPreISelGenericOpcode(unsigned Opcode)
Check whether the given Opcode is a generic opcode that is not supposed to appear after ISel.