14#ifndef LLVM_CODEGEN_GLOBALISEL_GENERICMACHINEINSTRS_H
15#define LLVM_CODEGEN_GLOBALISEL_GENERICMACHINEINSTRS_H
74 switch (
MI->getOpcode()) {
75 case TargetOpcode::G_LOAD:
76 case TargetOpcode::G_STORE:
77 case TargetOpcode::G_ZEXTLOAD:
78 case TargetOpcode::G_SEXTLOAD:
104 return MI->getOpcode() == TargetOpcode::G_INDEXED_LOAD;
112 return MI->getOpcode() == TargetOpcode::G_INDEXED_SEXTLOAD ||
113 MI->getOpcode() == TargetOpcode::G_INDEXED_ZEXTLOAD;
121 switch (
MI->getOpcode()) {
122 case TargetOpcode::G_INDEXED_LOAD:
123 case TargetOpcode::G_INDEXED_ZEXTLOAD:
124 case TargetOpcode::G_INDEXED_SEXTLOAD:
136 return MI->getOpcode() == TargetOpcode::G_INDEXED_ZEXTLOAD;
144 return MI->getOpcode() == TargetOpcode::G_INDEXED_SEXTLOAD;
164 return MI->getOpcode() == TargetOpcode::G_INDEXED_STORE;
175 switch (
MI->getOpcode()) {
176 case TargetOpcode::G_LOAD:
177 case TargetOpcode::G_ZEXTLOAD:
178 case TargetOpcode::G_SEXTLOAD:
190 return MI->getOpcode() == TargetOpcode::G_LOAD;
198 return MI->getOpcode() == TargetOpcode::G_SEXTLOAD ||
199 MI->getOpcode() == TargetOpcode::G_ZEXTLOAD;
207 return MI->getOpcode() == TargetOpcode::G_SEXTLOAD;
215 return MI->getOpcode() == TargetOpcode::G_ZEXTLOAD;
226 return MI->getOpcode() == TargetOpcode::G_STORE;
239 return MI->getOpcode() == TargetOpcode::G_UNMERGE_VALUES;
254 switch (
MI->getOpcode()) {
255 case TargetOpcode::G_MERGE_VALUES:
256 case TargetOpcode::G_CONCAT_VECTORS:
257 case TargetOpcode::G_BUILD_VECTOR:
269 return MI->getOpcode() == TargetOpcode::G_MERGE_VALUES;
277 return MI->getOpcode() == TargetOpcode::G_CONCAT_VECTORS;
285 return MI->getOpcode() == TargetOpcode::G_BUILD_VECTOR;
293 return MI->getOpcode() == TargetOpcode::G_BUILD_VECTOR_TRUNC;
304 return MI->getOpcode() == TargetOpcode::G_PTR_ADD;
312 return MI->getOpcode() == TargetOpcode::G_IMPLICIT_DEF;
324 return MI->getOpcode() == TargetOpcode::G_SELECT;
338 return MI->getOpcode() == TargetOpcode::G_ICMP ||
339 MI->getOpcode() == TargetOpcode::G_FCMP;
347 return MI->getOpcode() == TargetOpcode::G_ICMP;
355 return MI->getOpcode() == TargetOpcode::G_FCMP;
374 switch (
MI->getOpcode()) {
375 case TargetOpcode::G_UADDO:
376 case TargetOpcode::G_SADDO:
377 case TargetOpcode::G_USUBO:
378 case TargetOpcode::G_SSUBO:
379 case TargetOpcode::G_UADDE:
380 case TargetOpcode::G_SADDE:
381 case TargetOpcode::G_USUBE:
382 case TargetOpcode::G_SSUBE:
383 case TargetOpcode::G_UMULO:
384 case TargetOpcode::G_SMULO:
401 case TargetOpcode::G_UADDO:
402 case TargetOpcode::G_SADDO:
403 case TargetOpcode::G_UADDE:
404 case TargetOpcode::G_SADDE:
414 case TargetOpcode::G_SADDO:
415 case TargetOpcode::G_SSUBO:
416 case TargetOpcode::G_SADDE:
417 case TargetOpcode::G_SSUBE:
426 switch (
MI->getOpcode()) {
427 case TargetOpcode::G_UADDO:
428 case TargetOpcode::G_SADDO:
429 case TargetOpcode::G_USUBO:
430 case TargetOpcode::G_SSUBO:
431 case TargetOpcode::G_UADDE:
432 case TargetOpcode::G_SADDE:
433 case TargetOpcode::G_USUBE:
434 case TargetOpcode::G_SSUBE:
449 switch (
MI->getOpcode()) {
450 case TargetOpcode::G_UADDO:
451 case TargetOpcode::G_SADDO:
466 switch (
MI->getOpcode()) {
467 case TargetOpcode::G_UADDE:
468 case TargetOpcode::G_SADDE:
469 case TargetOpcode::G_USUBE:
470 case TargetOpcode::G_SSUBE:
489 case TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS:
490 case TargetOpcode::G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS:
499 case TargetOpcode::G_INTRINSIC_CONVERGENT:
500 case TargetOpcode::G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS:
508 switch (
MI->getOpcode()) {
509 case TargetOpcode::G_INTRINSIC:
510 case TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS:
511 case TargetOpcode::G_INTRINSIC_CONVERGENT:
512 case TargetOpcode::G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS:
524 switch (
MI->getOpcode()) {
525 case TargetOpcode::G_VECREDUCE_FADD:
526 case TargetOpcode::G_VECREDUCE_FMUL:
527 case TargetOpcode::G_VECREDUCE_FMAX:
528 case TargetOpcode::G_VECREDUCE_FMIN:
529 case TargetOpcode::G_VECREDUCE_FMAXIMUM:
530 case TargetOpcode::G_VECREDUCE_FMINIMUM:
531 case TargetOpcode::G_VECREDUCE_ADD:
532 case TargetOpcode::G_VECREDUCE_MUL:
533 case TargetOpcode::G_VECREDUCE_AND:
534 case TargetOpcode::G_VECREDUCE_OR:
535 case TargetOpcode::G_VECREDUCE_XOR:
536 case TargetOpcode::G_VECREDUCE_SMAX:
537 case TargetOpcode::G_VECREDUCE_SMIN:
538 case TargetOpcode::G_VECREDUCE_UMAX:
539 case TargetOpcode::G_VECREDUCE_UMIN:
551 case TargetOpcode::G_VECREDUCE_FADD:
552 ScalarOpc = TargetOpcode::G_FADD;
554 case TargetOpcode::G_VECREDUCE_FMUL:
555 ScalarOpc = TargetOpcode::G_FMUL;
557 case TargetOpcode::G_VECREDUCE_FMAX:
558 ScalarOpc = TargetOpcode::G_FMAXNUM;
560 case TargetOpcode::G_VECREDUCE_FMIN:
561 ScalarOpc = TargetOpcode::G_FMINNUM;
563 case TargetOpcode::G_VECREDUCE_FMAXIMUM:
564 ScalarOpc = TargetOpcode::G_FMAXIMUM;
566 case TargetOpcode::G_VECREDUCE_FMINIMUM:
567 ScalarOpc = TargetOpcode::G_FMINIMUM;
569 case TargetOpcode::G_VECREDUCE_ADD:
570 ScalarOpc = TargetOpcode::G_ADD;
572 case TargetOpcode::G_VECREDUCE_MUL:
573 ScalarOpc = TargetOpcode::G_MUL;
575 case TargetOpcode::G_VECREDUCE_AND:
576 ScalarOpc = TargetOpcode::G_AND;
578 case TargetOpcode::G_VECREDUCE_OR:
579 ScalarOpc = TargetOpcode::G_OR;
581 case TargetOpcode::G_VECREDUCE_XOR:
582 ScalarOpc = TargetOpcode::G_XOR;
584 case TargetOpcode::G_VECREDUCE_SMAX:
585 ScalarOpc = TargetOpcode::G_SMAX;
587 case TargetOpcode::G_VECREDUCE_SMIN:
588 ScalarOpc = TargetOpcode::G_SMIN;
590 case TargetOpcode::G_VECREDUCE_UMAX:
591 ScalarOpc = TargetOpcode::G_UMAX;
593 case TargetOpcode::G_VECREDUCE_UMIN:
594 ScalarOpc = TargetOpcode::G_UMIN;
618 return MI->getOpcode() == TargetOpcode::G_PHI;
629 switch (
MI->getOpcode()) {
631 case TargetOpcode::G_ADD:
632 case TargetOpcode::G_SUB:
633 case TargetOpcode::G_MUL:
634 case TargetOpcode::G_SDIV:
635 case TargetOpcode::G_UDIV:
636 case TargetOpcode::G_SREM:
637 case TargetOpcode::G_UREM:
638 case TargetOpcode::G_SMIN:
639 case TargetOpcode::G_SMAX:
640 case TargetOpcode::G_UMIN:
641 case TargetOpcode::G_UMAX:
643 case TargetOpcode::G_FMINNUM:
644 case TargetOpcode::G_FMAXNUM:
645 case TargetOpcode::G_FMINNUM_IEEE:
646 case TargetOpcode::G_FMAXNUM_IEEE:
647 case TargetOpcode::G_FMINIMUM:
648 case TargetOpcode::G_FMAXIMUM:
649 case TargetOpcode::G_FADD:
650 case TargetOpcode::G_FSUB:
651 case TargetOpcode::G_FMUL:
652 case TargetOpcode::G_FDIV:
653 case TargetOpcode::G_FPOW:
655 case TargetOpcode::G_AND:
656 case TargetOpcode::G_OR:
657 case TargetOpcode::G_XOR:
669 switch (
MI->getOpcode()) {
670 case TargetOpcode::G_ADD:
671 case TargetOpcode::G_SUB:
672 case TargetOpcode::G_MUL:
673 case TargetOpcode::G_SDIV:
674 case TargetOpcode::G_UDIV:
675 case TargetOpcode::G_SREM:
676 case TargetOpcode::G_UREM:
677 case TargetOpcode::G_SMIN:
678 case TargetOpcode::G_SMAX:
679 case TargetOpcode::G_UMIN:
680 case TargetOpcode::G_UMAX:
692 switch (
MI->getOpcode()) {
693 case TargetOpcode::G_FMINNUM:
694 case TargetOpcode::G_FMAXNUM:
695 case TargetOpcode::G_FMINNUM_IEEE:
696 case TargetOpcode::G_FMAXNUM_IEEE:
697 case TargetOpcode::G_FMINIMUM:
698 case TargetOpcode::G_FMAXIMUM:
699 case TargetOpcode::G_FADD:
700 case TargetOpcode::G_FSUB:
701 case TargetOpcode::G_FMUL:
702 case TargetOpcode::G_FDIV:
703 case TargetOpcode::G_FPOW:
715 switch (
MI->getOpcode()) {
716 case TargetOpcode::G_AND:
717 case TargetOpcode::G_OR:
718 case TargetOpcode::G_XOR:
730 return MI->getOpcode() == TargetOpcode::G_ADD;
738 return MI->getOpcode() == TargetOpcode::G_AND;
746 return MI->getOpcode() == TargetOpcode::G_OR;
757 return MI->getOpcode() == TargetOpcode::G_EXTRACT_VECTOR_ELT;
769 return MI->getOpcode() == TargetOpcode::G_INSERT_VECTOR_ELT;
779 return MI->getOpcode() == TargetOpcode::G_FREEZE;
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Represents overflowing add operations.
static bool classof(const MachineInstr *MI)
Represents overflowing add/sub operations that also consume a carry-in.
Register getCarryInReg() const
static bool classof(const MachineInstr *MI)
Represents overflowing add/sub operations.
static bool classof(const MachineInstr *MI)
Represents an integer addition.
static bool classof(const MachineInstr *MI)
Represents a logical and.
static bool classof(const MachineInstr *MI)
Represent a G_ICMP or G_FCMP.
static bool classof(const MachineInstr *MI)
CmpInst::Predicate getCond() const
Register getLHSReg() const
Register getRHSReg() const
Represents any generic load, including sign/zero extending variants.
Register getDstReg() const
Get the definition register of the loaded value.
static bool classof(const MachineInstr *MI)
Represents overflowing binary operations.
MachineOperand & getRHS()
MachineOperand & getLHS()
Register getCarryOutReg() const
Register getDstReg() const
static bool classof(const MachineInstr *MI)
Register getRHSReg() const
Register getLHSReg() const
Represents a binary operation, i.e, x = y op z.
Register getLHSReg() const
static bool classof(const MachineInstr *MI)
Register getRHSReg() const
Represents a G_BUILD_VECTOR_TRUNC.
static bool classof(const MachineInstr *MI)
Represents a G_BUILD_VECTOR.
static bool classof(const MachineInstr *MI)
Represents a G_CONCAT_VECTORS.
static bool classof(const MachineInstr *MI)
Represents either a G_SEXTLOAD or G_ZEXTLOAD.
static bool classof(const MachineInstr *MI)
Represents a floating point binary operation.
static bool classof(const MachineInstr *MI)
static bool classof(const MachineInstr *MI)
Register getSourceReg() const
static bool classof(const MachineInstr *MI)
static bool classof(const MachineInstr *MI)
Represents a G_IMPLICIT_DEF.
static bool classof(const MachineInstr *MI)
Represents either G_INDEXED_LOAD, G_INDEXED_ZEXTLOAD or G_INDEXED_SEXTLOAD.
static bool classof(const MachineInstr *MI)
Represents a G_INDEX_ZEXTLOAD/G_INDEXED_SEXTLOAD.
static bool classof(const MachineInstr *MI)
Represents indexed loads.
static bool classof(const MachineInstr *MI)
Register getOffsetReg() const
Get the offset register of the pointer value.
Register getWritebackReg() const
Get the def register of the writeback value.
Register getDstReg() const
Get the definition register of the loaded value.
Register getBaseReg() const
Get the base register of the pointer value.
static bool classof(const MachineInstr *MI)
Represents indexed stores.
Register getOffsetReg() const
Get the offset register of the pointer value.
Register getValueReg() const
Get the stored value register.
Register getBaseReg() const
Get the base register of the pointer value.
static bool classof(const MachineInstr *MI)
Register getWritebackReg() const
Get the def register of the writeback value.
static bool classof(const MachineInstr *MI)
Represents an insert vector element.
Register getVectorReg() const
Register getIndexReg() const
Register getElementReg() const
static bool classof(const MachineInstr *MI)
Represents an integer binary operation.
static bool classof(const MachineInstr *MI)
Represents a call to an intrinsic.
bool isConvergent() const
Intrinsic::ID getIntrinsicID() const
bool is(Intrinsic::ID ID) const
static bool classof(const MachineInstr *MI)
bool hasSideEffects() const
Represents any type of generic load or store.
Register getPointerReg() const
Get the source register of the pointer value.
static bool classof(const MachineInstr *MI)
static bool classof(const MachineInstr *MI)
Represents a logical binary operation.
static bool classof(const MachineInstr *MI)
Provides common memory operand functionality.
MachineMemOperand & getMMO() const
Get the MachineMemOperand on this instruction.
LocationSize getMemSize() const
Returns the size in bytes of the memory access.
bool isUnordered() const
Returns true if this memory operation doesn't have any ordering constraints other than normal aliasin...
bool isAtomic() const
Returns true if the attached MachineMemOperand has the atomic flag set.
bool isVolatile() const
Returns true if the attached MachineMemOpeand as the volatile flag set.
static bool classof(const MachineInstr *MI)
LocationSize getMemSizeInBits() const
Returns the size in bits of the memory access.
bool isSimple() const
Returns true if the memory operation is neither atomic or volatile.
Represents G_BUILD_VECTOR, G_CONCAT_VECTORS or G_MERGE_VALUES.
Register getSourceReg(unsigned I) const
Returns the I'th source register.
unsigned getNumSources() const
Returns the number of source registers.
static bool classof(const MachineInstr *MI)
Represents a G_MERGE_VALUES.
static bool classof(const MachineInstr *MI)
static bool classof(const MachineInstr *MI)
MachineBasicBlock * getIncomingBlock(unsigned I) const
Returns the I'th incoming basic block.
Register getIncomingValue(unsigned I) const
Returns the I'th incoming vreg.
static bool classof(const MachineInstr *MI)
unsigned getNumIncomingValues() const
Returns the number of incoming values.
Register getOffsetReg() const
static bool classof(const MachineInstr *MI)
Register getBaseReg() const
static bool classof(const MachineInstr *MI)
Register getCondReg() const
static bool classof(const MachineInstr *MI)
Register getFalseReg() const
Register getTrueReg() const
static bool classof(const MachineInstr *MI)
Register getValueReg() const
Get the stored value register.
Represents a G_UNMERGE_VALUES.
unsigned getNumDefs() const
Returns the number of def registers.
static bool classof(const MachineInstr *MI)
Register getSourceReg() const
Get the unmerge source register.
unsigned getScalarOpcForReduction()
Get the opcode for the equivalent scalar operation for this reduction.
static bool classof(const MachineInstr *MI)
static bool classof(const MachineInstr *MI)
A base class for all GenericMachineInstrs.
static bool classof(const MachineInstr *MI)
Register getReg(unsigned Idx) const
Access the Idx'th operand as a register and return it.
GenericMachineInstr()=delete
Representation of each machine instruction.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
unsigned getNumOperands() const
Retuns the total number of operands.
unsigned getNumExplicitDefs() const
Returns the number of non-implicit definitions.
mmo_iterator memoperands_begin() const
Access to memory operands of the instruction.
const MachineOperand & getOperand(unsigned i) const
A description of a memory reference used in the backend.
LocationSize getSize() const
Return the size in bytes of the memory reference.
bool isUnordered() const
Returns true if this memory operation doesn't have any ordering constraints other than normal aliasin...
bool isAtomic() const
Returns true if this operation has an atomic ordering requirement of unordered or higher,...
LocationSize getSizeInBits() const
Return the size in bits of the memory reference.
MachineOperand class - Representation of each machine instruction operand.
MachineBasicBlock * getMBB() const
Register getReg() const
getReg - Returns the register number.
Intrinsic::ID getIntrinsicID() const
unsigned getPredicate() const
Wrapper class representing virtual and physical registers.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
This is an optimization pass for GlobalISel generic memory operations.
bool isPreISelGenericOpcode(unsigned Opcode)
Check whether the given Opcode is a generic opcode that is not supposed to appear after ISel.